From 65b9f879983bbd40e8bbb88ea0a3d8f00638a934 Mon Sep 17 00:00:00 2001 From: Sachin Parekh Date: Fri, 9 Apr 2021 16:51:34 +0530 Subject: [PATCH] esp32c3/memprot: Fix incorrect access to DRAM0 split line registers memprot_ll_set_dram0_split_line_* and memprot_ll_get_dram0_split_line_* APIs were accessing incorrect configuration register --- components/hal/esp32c3/include/hal/memprot_ll.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/components/hal/esp32c3/include/hal/memprot_ll.h b/components/hal/esp32c3/include/hal/memprot_ll.h index 5da2b452d3..78c7bcbda2 100644 --- a/components/hal/esp32c3/include/hal/memprot_ll.h +++ b/components/hal/esp32c3/include/hal/memprot_ll.h @@ -381,22 +381,22 @@ static inline void memprot_ll_set_dram0_split_line(const void *line_addr, uint32 static inline void memprot_ll_set_dram0_split_line_D_0(const void *line_addr) { - memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG); + memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG); } static inline void memprot_ll_set_dram0_split_line_D_1(const void *line_addr) { - memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG); + memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG); } static inline void* memprot_ll_get_dram0_split_line_D_0(void) { - return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG), SOC_DIRAM_DRAM_LOW); + return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG), SOC_DIRAM_DRAM_LOW); } static inline void* memprot_ll_get_dram0_split_line_D_1(void) { - return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG), SOC_DIRAM_DRAM_LOW); + return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG), SOC_DIRAM_DRAM_LOW); }