diff --git a/components/soc/esp32h4/register/hw_ver_beta5/soc/pmu_reg.h b/components/soc/esp32h4/register/hw_ver_beta5/soc/pmu_reg.h new file mode 100644 index 0000000000..6838ec3ce5 --- /dev/null +++ b/components/soc/esp32h4/register/hw_ver_beta5/soc/pmu_reg.h @@ -0,0 +1,3766 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PMU_HP_ACTIVE_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_ACTIVE_DIG_POWER_REG (DR_REG_PMU_BASE + 0x0) +/** PMU_HP_ACTIVE_VDD_FLASH_MODE : R/W; bitpos: [21:18]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_VDD_FLASH_MODE 0x0000000FU +#define PMU_HP_ACTIVE_VDD_FLASH_MODE_M (PMU_HP_ACTIVE_VDD_FLASH_MODE_V << PMU_HP_ACTIVE_VDD_FLASH_MODE_S) +#define PMU_HP_ACTIVE_VDD_FLASH_MODE_V 0x0000000FU +#define PMU_HP_ACTIVE_VDD_FLASH_MODE_S 18 +/** PMU_HP_ACTIVE_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_ACTIVE_HP_MEM_DSLP_M (PMU_HP_ACTIVE_HP_MEM_DSLP_V << PMU_HP_ACTIVE_HP_MEM_DSLP_S) +#define PMU_HP_ACTIVE_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_ACTIVE_HP_MEM_DSLP_S 22 +/** PMU_HP_ACTIVE_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_M (PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V << PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_M (PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_ACTIVE_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN (BIT(28)) +#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_M (PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_S 28 +/** PMU_HP_ACTIVE_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_M (PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V << PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_ACTIVE_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN (BIT(30)) +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_M (PMU_HP_ACTIVE_PD_HP_AON_PD_EN_V << PMU_HP_ACTIVE_PD_HP_AON_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_S 30 +/** PMU_HP_ACTIVE_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_M (PMU_HP_ACTIVE_PD_TOP_PD_EN_V << PMU_HP_ACTIVE_PD_TOP_PD_EN_S) +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_S 31 + +/** PMU_HP_ACTIVE_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x4) +/** PMU_HP_ACTIVE_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_M (PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V << PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S) +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_ACTIVE_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x8) +/** PMU_HP_ACTIVE_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_M (PMU_HP_ACTIVE_DIG_ICG_APB_EN_V << PMU_HP_ACTIVE_DIG_ICG_APB_EN_S) +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_ACTIVE_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_MODEM_REG (DR_REG_PMU_BASE + 0xc) +/** PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_M (PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V << PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_ACTIVE_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x10) +/** PMU_HP_ACTIVE_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_M (PMU_HP_ACTIVE_UART_WAKEUP_EN_V << PMU_HP_ACTIVE_UART_WAKEUP_EN_S) +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_S 24 +/** PMU_HP_ACTIVE_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_M (PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S) +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_ACTIVE_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_M (PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S) +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_ACTIVE_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_M (PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V << PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S) +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_ACTIVE_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_M (PMU_HP_ACTIVE_DIG_PAUSE_WDT_V << PMU_HP_ACTIVE_DIG_PAUSE_WDT_S) +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_S 28 +/** PMU_HP_ACTIVE_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_ACTIVE_DIG_CPU_STALL_M (PMU_HP_ACTIVE_DIG_CPU_STALL_V << PMU_HP_ACTIVE_DIG_CPU_STALL_S) +#define PMU_HP_ACTIVE_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_CPU_STALL_S 29 + +/** PMU_HP_ACTIVE_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x14) +/** PMU_HP_ACTIVE_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_I2C_ISO_EN (BIT(26)) +#define PMU_HP_ACTIVE_I2C_ISO_EN_M (PMU_HP_ACTIVE_I2C_ISO_EN_V << PMU_HP_ACTIVE_I2C_ISO_EN_S) +#define PMU_HP_ACTIVE_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_ACTIVE_I2C_ISO_EN_S 26 +/** PMU_HP_ACTIVE_I2C_RETENTION : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_I2C_RETENTION (BIT(27)) +#define PMU_HP_ACTIVE_I2C_RETENTION_M (PMU_HP_ACTIVE_I2C_RETENTION_V << PMU_HP_ACTIVE_I2C_RETENTION_S) +#define PMU_HP_ACTIVE_I2C_RETENTION_V 0x00000001U +#define PMU_HP_ACTIVE_I2C_RETENTION_S 27 +/** PMU_HP_ACTIVE_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BB_I2C (BIT(28)) +#define PMU_HP_ACTIVE_XPD_BB_I2C_M (PMU_HP_ACTIVE_XPD_BB_I2C_V << PMU_HP_ACTIVE_XPD_BB_I2C_S) +#define PMU_HP_ACTIVE_XPD_BB_I2C_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BB_I2C_S 28 +/** PMU_HP_ACTIVE_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C (BIT(29)) +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_M (PMU_HP_ACTIVE_XPD_BBPLL_I2C_V << PMU_HP_ACTIVE_XPD_BBPLL_I2C_S) +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_S 29 +/** PMU_HP_ACTIVE_XPD_BBPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BBPLL (BIT(30)) +#define PMU_HP_ACTIVE_XPD_BBPLL_M (PMU_HP_ACTIVE_XPD_BBPLL_V << PMU_HP_ACTIVE_XPD_BBPLL_S) +#define PMU_HP_ACTIVE_XPD_BBPLL_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BBPLL_S 30 + +/** PMU_HP_ACTIVE_BIAS_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BIAS_REG (DR_REG_PMU_BASE + 0x18) +/** PMU_HP_ACTIVE_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_DCDC_CCM_ENB (BIT(9)) +#define PMU_HP_ACTIVE_DCDC_CCM_ENB_M (PMU_HP_ACTIVE_DCDC_CCM_ENB_V << PMU_HP_ACTIVE_DCDC_CCM_ENB_S) +#define PMU_HP_ACTIVE_DCDC_CCM_ENB_V 0x00000001U +#define PMU_HP_ACTIVE_DCDC_CCM_ENB_S 9 +/** PMU_HP_ACTIVE_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY (BIT(10)) +#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY_M (PMU_HP_ACTIVE_DCDC_CLEAR_RDY_V << PMU_HP_ACTIVE_DCDC_CLEAR_RDY_S) +#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY_V 0x00000001U +#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY_S 10 +/** PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 3; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS 0x00000003U +#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_M (PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_V << PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_S) +#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_V 0x00000003U +#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_S 11 +/** PMU_HP_ACTIVE_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 6; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS 0x0000000FU +#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS_M (PMU_HP_ACTIVE_DIG_PMU_DSFMOS_V << PMU_HP_ACTIVE_DIG_PMU_DSFMOS_S) +#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS_V 0x0000000FU +#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS_S 13 +/** PMU_HP_ACTIVE_DCM_VSET : R/W; bitpos: [21:17]; default: 23; + * need_des + */ +#define PMU_HP_ACTIVE_DCM_VSET 0x0000001FU +#define PMU_HP_ACTIVE_DCM_VSET_M (PMU_HP_ACTIVE_DCM_VSET_V << PMU_HP_ACTIVE_DCM_VSET_S) +#define PMU_HP_ACTIVE_DCM_VSET_V 0x0000001FU +#define PMU_HP_ACTIVE_DCM_VSET_S 17 +/** PMU_HP_ACTIVE_DCM_MODE : R/W; bitpos: [23:22]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DCM_MODE 0x00000003U +#define PMU_HP_ACTIVE_DCM_MODE_M (PMU_HP_ACTIVE_DCM_MODE_V << PMU_HP_ACTIVE_DCM_MODE_S) +#define PMU_HP_ACTIVE_DCM_MODE_V 0x00000003U +#define PMU_HP_ACTIVE_DCM_MODE_S 22 +/** PMU_HP_ACTIVE_XPD_TRX : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_TRX (BIT(24)) +#define PMU_HP_ACTIVE_XPD_TRX_M (PMU_HP_ACTIVE_XPD_TRX_V << PMU_HP_ACTIVE_XPD_TRX_S) +#define PMU_HP_ACTIVE_XPD_TRX_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_TRX_S 24 +/** PMU_HP_ACTIVE_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BIAS (BIT(25)) +#define PMU_HP_ACTIVE_XPD_BIAS_M (PMU_HP_ACTIVE_XPD_BIAS_V << PMU_HP_ACTIVE_XPD_BIAS_S) +#define PMU_HP_ACTIVE_XPD_BIAS_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BIAS_S 25 +/** PMU_HP_ACTIVE_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC (BIT(29)) +#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC_M (PMU_HP_ACTIVE_DISCNNT_DIG_RTC_V << PMU_HP_ACTIVE_DISCNNT_DIG_RTC_S) +#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC_V 0x00000001U +#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC_S 29 +/** PMU_HP_ACTIVE_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_CUR (BIT(30)) +#define PMU_HP_ACTIVE_PD_CUR_M (PMU_HP_ACTIVE_PD_CUR_V << PMU_HP_ACTIVE_PD_CUR_S) +#define PMU_HP_ACTIVE_PD_CUR_V 0x00000001U +#define PMU_HP_ACTIVE_PD_CUR_S 30 +/** PMU_HP_ACTIVE_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_BIAS_SLEEP (BIT(31)) +#define PMU_HP_ACTIVE_BIAS_SLEEP_M (PMU_HP_ACTIVE_BIAS_SLEEP_V << PMU_HP_ACTIVE_BIAS_SLEEP_S) +#define PMU_HP_ACTIVE_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_ACTIVE_BIAS_SLEEP_S 31 + +/** PMU_HP_ACTIVE_BACKUP_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_REG (DR_REG_PMU_BASE + 0x1c) +/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S 4 +/** PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S 6 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S 14 +/** PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S 16 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:18]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE 0x0000001FU +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V 0x0000001FU +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S 18 +/** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [27:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE 0x0000001FU +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V 0x0000001FU +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S 23 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN (BIT(29)) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_M (PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V << PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V 0x00000001U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S 29 +/** PMU_HP_MODEM2ACTIVE_BACKUP_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN (BIT(30)) +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_M (PMU_HP_MODEM2ACTIVE_BACKUP_EN_V << PMU_HP_MODEM2ACTIVE_BACKUP_EN_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_V 0x00000001U +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_S 30 + +/** PMU_HP_ACTIVE_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x20) +/** PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_M (PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V << PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_ACTIVE_SYSCLK_REG register + * need_des + */ +#define PMU_HP_ACTIVE_SYSCLK_REG (DR_REG_PMU_BASE + 0x24) +/** PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_M (PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V << PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_M (PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V << PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_ACTIVE_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_M (PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V << PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S) +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_ACTIVE_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_ACTIVE_ICG_SLP_SEL_M (PMU_HP_ACTIVE_ICG_SLP_SEL_V << PMU_HP_ACTIVE_ICG_SLP_SEL_S) +#define PMU_HP_ACTIVE_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_ICG_SLP_SEL_S 29 +/** PMU_HP_ACTIVE_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_M (PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V << PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_ACTIVE_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x28) +/** PMU_HP_ACTIVE_HP_POWER_DET_BYPASS : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS (BIT(0)) +#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_M (PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V << PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S) +#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V 0x00000001U +#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S 0 +/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 24; + * need_des + */ +#define PMU_LP_DBIAS_VOL 0x0000001FU +#define PMU_LP_DBIAS_VOL_M (PMU_LP_DBIAS_VOL_V << PMU_LP_DBIAS_VOL_S) +#define PMU_LP_DBIAS_VOL_V 0x0000001FU +#define PMU_LP_DBIAS_VOL_S 4 +/** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 24; + * need_des + */ +#define PMU_HP_DBIAS_VOL 0x0000001FU +#define PMU_HP_DBIAS_VOL_M (PMU_HP_DBIAS_VOL_V << PMU_HP_DBIAS_VOL_S) +#define PMU_HP_DBIAS_VOL_V 0x0000001FU +#define PMU_HP_DBIAS_VOL_S 9 +/** PMU_DIG_REGULATOR0_DBIAS_SEL : R/W; bitpos: [14]; default: 1; + * need_des + */ +#define PMU_DIG_REGULATOR0_DBIAS_SEL (BIT(14)) +#define PMU_DIG_REGULATOR0_DBIAS_SEL_M (PMU_DIG_REGULATOR0_DBIAS_SEL_V << PMU_DIG_REGULATOR0_DBIAS_SEL_S) +#define PMU_DIG_REGULATOR0_DBIAS_SEL_V 0x00000001U +#define PMU_DIG_REGULATOR0_DBIAS_SEL_S 14 +/** PMU_DIG_DBIAS_INIT : WT; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_DIG_DBIAS_INIT (BIT(15)) +#define PMU_DIG_DBIAS_INIT_M (PMU_DIG_DBIAS_INIT_V << PMU_DIG_DBIAS_INIT_S) +#define PMU_DIG_DBIAS_INIT_V 0x00000001U +#define PMU_DIG_DBIAS_INIT_S 15 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_ACTIVE_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_S 18 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 8; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 8; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_ACTIVE_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 16; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_ACTIVE_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x2c) +/** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_M (PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V << PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_ACTIVE_XTAL_REG register + * need_des + */ +#define PMU_HP_ACTIVE_XTAL_REG (DR_REG_PMU_BASE + 0x30) +/** PMU_HP_ACTIVE_XPD_XTALX2 : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_XTALX2 (BIT(30)) +#define PMU_HP_ACTIVE_XPD_XTALX2_M (PMU_HP_ACTIVE_XPD_XTALX2_V << PMU_HP_ACTIVE_XPD_XTALX2_S) +#define PMU_HP_ACTIVE_XPD_XTALX2_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_XTALX2_S 30 +/** PMU_HP_ACTIVE_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_XTAL (BIT(31)) +#define PMU_HP_ACTIVE_XPD_XTAL_M (PMU_HP_ACTIVE_XPD_XTAL_V << PMU_HP_ACTIVE_XPD_XTAL_S) +#define PMU_HP_ACTIVE_XPD_XTAL_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_XTAL_S 31 + +/** PMU_HP_SLEEP_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_DIG_POWER_REG (DR_REG_PMU_BASE + 0x68) +/** PMU_HP_SLEEP_VDD_FLASH_MODE : R/W; bitpos: [21:18]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_VDD_FLASH_MODE 0x0000000FU +#define PMU_HP_SLEEP_VDD_FLASH_MODE_M (PMU_HP_SLEEP_VDD_FLASH_MODE_V << PMU_HP_SLEEP_VDD_FLASH_MODE_S) +#define PMU_HP_SLEEP_VDD_FLASH_MODE_V 0x0000000FU +#define PMU_HP_SLEEP_VDD_FLASH_MODE_S 18 +/** PMU_HP_SLEEP_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_SLEEP_HP_MEM_DSLP_M (PMU_HP_SLEEP_HP_MEM_DSLP_V << PMU_HP_SLEEP_HP_MEM_DSLP_S) +#define PMU_HP_SLEEP_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_SLEEP_HP_MEM_DSLP_S 22 +/** PMU_HP_SLEEP_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_M (PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V << PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_SLEEP_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_M (PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V << PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_SLEEP_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN (BIT(28)) +#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_M (PMU_HP_SLEEP_PD_HP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_HP_PERI_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_S 28 +/** PMU_HP_SLEEP_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_M (PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V << PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_SLEEP_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN (BIT(30)) +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_M (PMU_HP_SLEEP_PD_HP_AON_PD_EN_V << PMU_HP_SLEEP_PD_HP_AON_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_S 30 +/** PMU_HP_SLEEP_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_SLEEP_PD_TOP_PD_EN_M (PMU_HP_SLEEP_PD_TOP_PD_EN_V << PMU_HP_SLEEP_PD_TOP_PD_EN_S) +#define PMU_HP_SLEEP_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_TOP_PD_EN_S 31 + +/** PMU_HP_SLEEP_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x6c) +/** PMU_HP_SLEEP_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_M (PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V << PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S) +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_SLEEP_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x70) +/** PMU_HP_SLEEP_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_M (PMU_HP_SLEEP_DIG_ICG_APB_EN_V << PMU_HP_SLEEP_DIG_ICG_APB_EN_S) +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_SLEEP_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x74) +/** PMU_HP_SLEEP_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_M (PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V << PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_SLEEP_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x78) +/** PMU_HP_SLEEP_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_SLEEP_UART_WAKEUP_EN_M (PMU_HP_SLEEP_UART_WAKEUP_EN_V << PMU_HP_SLEEP_UART_WAKEUP_EN_S) +#define PMU_HP_SLEEP_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_SLEEP_UART_WAKEUP_EN_S 24 +/** PMU_HP_SLEEP_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_M (PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S) +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_SLEEP_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_M (PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S) +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_SLEEP_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_M (PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V << PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S) +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_SLEEP_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_M (PMU_HP_SLEEP_DIG_PAUSE_WDT_V << PMU_HP_SLEEP_DIG_PAUSE_WDT_S) +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_S 28 +/** PMU_HP_SLEEP_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_SLEEP_DIG_CPU_STALL_M (PMU_HP_SLEEP_DIG_CPU_STALL_V << PMU_HP_SLEEP_DIG_CPU_STALL_S) +#define PMU_HP_SLEEP_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_SLEEP_DIG_CPU_STALL_S 29 + +/** PMU_HP_SLEEP_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x7c) +/** PMU_HP_SLEEP_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_I2C_ISO_EN (BIT(26)) +#define PMU_HP_SLEEP_I2C_ISO_EN_M (PMU_HP_SLEEP_I2C_ISO_EN_V << PMU_HP_SLEEP_I2C_ISO_EN_S) +#define PMU_HP_SLEEP_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_SLEEP_I2C_ISO_EN_S 26 +/** PMU_HP_SLEEP_I2C_RETENTION : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_I2C_RETENTION (BIT(27)) +#define PMU_HP_SLEEP_I2C_RETENTION_M (PMU_HP_SLEEP_I2C_RETENTION_V << PMU_HP_SLEEP_I2C_RETENTION_S) +#define PMU_HP_SLEEP_I2C_RETENTION_V 0x00000001U +#define PMU_HP_SLEEP_I2C_RETENTION_S 27 +/** PMU_HP_SLEEP_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BB_I2C (BIT(28)) +#define PMU_HP_SLEEP_XPD_BB_I2C_M (PMU_HP_SLEEP_XPD_BB_I2C_V << PMU_HP_SLEEP_XPD_BB_I2C_S) +#define PMU_HP_SLEEP_XPD_BB_I2C_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BB_I2C_S 28 +/** PMU_HP_SLEEP_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BBPLL_I2C (BIT(29)) +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_M (PMU_HP_SLEEP_XPD_BBPLL_I2C_V << PMU_HP_SLEEP_XPD_BBPLL_I2C_S) +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_S 29 +/** PMU_HP_SLEEP_XPD_BBPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BBPLL (BIT(30)) +#define PMU_HP_SLEEP_XPD_BBPLL_M (PMU_HP_SLEEP_XPD_BBPLL_V << PMU_HP_SLEEP_XPD_BBPLL_S) +#define PMU_HP_SLEEP_XPD_BBPLL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BBPLL_S 30 + +/** PMU_HP_SLEEP_BIAS_REG register + * need_des + */ +#define PMU_HP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0x80) +/** PMU_HP_SLEEP_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_DCDC_CCM_ENB (BIT(9)) +#define PMU_HP_SLEEP_DCDC_CCM_ENB_M (PMU_HP_SLEEP_DCDC_CCM_ENB_V << PMU_HP_SLEEP_DCDC_CCM_ENB_S) +#define PMU_HP_SLEEP_DCDC_CCM_ENB_V 0x00000001U +#define PMU_HP_SLEEP_DCDC_CCM_ENB_S 9 +/** PMU_HP_SLEEP_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DCDC_CLEAR_RDY (BIT(10)) +#define PMU_HP_SLEEP_DCDC_CLEAR_RDY_M (PMU_HP_SLEEP_DCDC_CLEAR_RDY_V << PMU_HP_SLEEP_DCDC_CLEAR_RDY_S) +#define PMU_HP_SLEEP_DCDC_CLEAR_RDY_V 0x00000001U +#define PMU_HP_SLEEP_DCDC_CLEAR_RDY_S 10 +/** PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS 0x00000003U +#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_M (PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_V << PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_S) +#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_V 0x00000003U +#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_S 11 +/** PMU_HP_SLEEP_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 4; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PMU_DSFMOS 0x0000000FU +#define PMU_HP_SLEEP_DIG_PMU_DSFMOS_M (PMU_HP_SLEEP_DIG_PMU_DSFMOS_V << PMU_HP_SLEEP_DIG_PMU_DSFMOS_S) +#define PMU_HP_SLEEP_DIG_PMU_DSFMOS_V 0x0000000FU +#define PMU_HP_SLEEP_DIG_PMU_DSFMOS_S 13 +/** PMU_HP_SLEEP_DCM_VSET : R/W; bitpos: [21:17]; default: 23; + * need_des + */ +#define PMU_HP_SLEEP_DCM_VSET 0x0000001FU +#define PMU_HP_SLEEP_DCM_VSET_M (PMU_HP_SLEEP_DCM_VSET_V << PMU_HP_SLEEP_DCM_VSET_S) +#define PMU_HP_SLEEP_DCM_VSET_V 0x0000001FU +#define PMU_HP_SLEEP_DCM_VSET_S 17 +/** PMU_HP_SLEEP_DCM_MODE : R/W; bitpos: [23:22]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DCM_MODE 0x00000003U +#define PMU_HP_SLEEP_DCM_MODE_M (PMU_HP_SLEEP_DCM_MODE_V << PMU_HP_SLEEP_DCM_MODE_S) +#define PMU_HP_SLEEP_DCM_MODE_V 0x00000003U +#define PMU_HP_SLEEP_DCM_MODE_S 22 +/** PMU_HP_SLEEP_XPD_TRX : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_TRX (BIT(24)) +#define PMU_HP_SLEEP_XPD_TRX_M (PMU_HP_SLEEP_XPD_TRX_V << PMU_HP_SLEEP_XPD_TRX_S) +#define PMU_HP_SLEEP_XPD_TRX_V 0x00000001U +#define PMU_HP_SLEEP_XPD_TRX_S 24 +/** PMU_HP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BIAS (BIT(25)) +#define PMU_HP_SLEEP_XPD_BIAS_M (PMU_HP_SLEEP_XPD_BIAS_V << PMU_HP_SLEEP_XPD_BIAS_S) +#define PMU_HP_SLEEP_XPD_BIAS_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BIAS_S 25 +/** PMU_HP_SLEEP_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DISCNNT_DIG_RTC (BIT(29)) +#define PMU_HP_SLEEP_DISCNNT_DIG_RTC_M (PMU_HP_SLEEP_DISCNNT_DIG_RTC_V << PMU_HP_SLEEP_DISCNNT_DIG_RTC_S) +#define PMU_HP_SLEEP_DISCNNT_DIG_RTC_V 0x00000001U +#define PMU_HP_SLEEP_DISCNNT_DIG_RTC_S 29 +/** PMU_HP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_CUR (BIT(30)) +#define PMU_HP_SLEEP_PD_CUR_M (PMU_HP_SLEEP_PD_CUR_V << PMU_HP_SLEEP_PD_CUR_S) +#define PMU_HP_SLEEP_PD_CUR_V 0x00000001U +#define PMU_HP_SLEEP_PD_CUR_S 30 +/** PMU_HP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_BIAS_SLEEP (BIT(31)) +#define PMU_HP_SLEEP_BIAS_SLEEP_M (PMU_HP_SLEEP_BIAS_SLEEP_V << PMU_HP_SLEEP_BIAS_SLEEP_S) +#define PMU_HP_SLEEP_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_SLEEP_BIAS_SLEEP_S 31 + +/** PMU_HP_SLEEP_BACKUP_REG register + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_REG (DR_REG_PMU_BASE + 0x84) +/** PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S 6 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [9:8]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S 8 +/** PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S 16 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [19:18]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S 18 +/** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [24:20]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE 0x0000001FU +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODE_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V 0x0000001FU +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S 20 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [29:25]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE 0x0000001FU +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V 0x0000001FU +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S 25 +/** PMU_HP_MODEM2SLEEP_BACKUP_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_EN (BIT(30)) +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_M (PMU_HP_MODEM2SLEEP_BACKUP_EN_V << PMU_HP_MODEM2SLEEP_BACKUP_EN_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_V 0x00000001U +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_S 30 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN (BIT(31)) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_M (PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V << PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V 0x00000001U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S 31 + +/** PMU_HP_SLEEP_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x88) +/** PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_M (PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V << PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_SLEEP_SYSCLK_REG register + * need_des + */ +#define PMU_HP_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0x8c) +/** PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_M (PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V << PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_SLEEP_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_M (PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V << PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_SLEEP_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_M (PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V << PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S) +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_SLEEP_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_SLEEP_ICG_SLP_SEL_M (PMU_HP_SLEEP_ICG_SLP_SEL_V << PMU_HP_SLEEP_ICG_SLP_SEL_S) +#define PMU_HP_SLEEP_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_ICG_SLP_SEL_S 29 +/** PMU_HP_SLEEP_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_M (PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V << PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S) +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_SLEEP_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x90) +/** PMU_HP_SLEEP_HP_POWER_DET_BYPASS : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS (BIT(0)) +#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_M (PMU_HP_SLEEP_HP_POWER_DET_BYPASS_V << PMU_HP_SLEEP_HP_POWER_DET_BYPASS_S) +#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_V 0x00000001U +#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_S 0 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_SLEEP_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_S 18 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 8; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 8; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_SLEEP_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 16; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_SLEEP_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x94) +/** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: .; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_M (PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S) +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_SLEEP_XTAL_REG register + * need_des + */ +#define PMU_HP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0x98) +/** PMU_HP_SLEEP_XPD_XTALX2 : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_XTALX2 (BIT(30)) +#define PMU_HP_SLEEP_XPD_XTALX2_M (PMU_HP_SLEEP_XPD_XTALX2_V << PMU_HP_SLEEP_XPD_XTALX2_S) +#define PMU_HP_SLEEP_XPD_XTALX2_V 0x00000001U +#define PMU_HP_SLEEP_XPD_XTALX2_S 30 +/** PMU_HP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_XTAL (BIT(31)) +#define PMU_HP_SLEEP_XPD_XTAL_M (PMU_HP_SLEEP_XPD_XTAL_V << PMU_HP_SLEEP_XPD_XTAL_S) +#define PMU_HP_SLEEP_XPD_XTAL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_XTAL_S 31 + +/** PMU_HP_SLEEP_LP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x9c) +/** PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD (BIT(21)) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V 0x00000001U +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S 21 +/** PMU_HP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_XPD (BIT(22)) +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_M (PMU_HP_SLEEP_LP_REGULATOR_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_XPD_S) +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_S 22 +/** PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 8; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 +/** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S) +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_SLEEP_LP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xa0) +/** PMU_HP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_M (PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S) +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S 28 + +/** PMU_HP_SLEEP_LP_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xa8) +/** PMU_HP_SLEEP_VDD_IO_MODE : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_VDD_IO_MODE 0x0000000FU +#define PMU_HP_SLEEP_VDD_IO_MODE_M (PMU_HP_SLEEP_VDD_IO_MODE_V << PMU_HP_SLEEP_VDD_IO_MODE_S) +#define PMU_HP_SLEEP_VDD_IO_MODE_V 0x0000000FU +#define PMU_HP_SLEEP_VDD_IO_MODE_S 23 +/** PMU_HP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_BOD_SOURCE_SEL (BIT(27)) +#define PMU_HP_SLEEP_BOD_SOURCE_SEL_M (PMU_HP_SLEEP_BOD_SOURCE_SEL_V << PMU_HP_SLEEP_BOD_SOURCE_SEL_S) +#define PMU_HP_SLEEP_BOD_SOURCE_SEL_V 0x00000001U +#define PMU_HP_SLEEP_BOD_SOURCE_SEL_S 27 +/** PMU_HP_SLEEP_VDDBAT_MODE : R/W; bitpos: [29:28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_VDDBAT_MODE 0x00000003U +#define PMU_HP_SLEEP_VDDBAT_MODE_M (PMU_HP_SLEEP_VDDBAT_MODE_V << PMU_HP_SLEEP_VDDBAT_MODE_S) +#define PMU_HP_SLEEP_VDDBAT_MODE_V 0x00000003U +#define PMU_HP_SLEEP_VDDBAT_MODE_S 28 +/** PMU_HP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_MEM_DSLP (BIT(30)) +#define PMU_HP_SLEEP_LP_MEM_DSLP_M (PMU_HP_SLEEP_LP_MEM_DSLP_V << PMU_HP_SLEEP_LP_MEM_DSLP_S) +#define PMU_HP_SLEEP_LP_MEM_DSLP_V 0x00000001U +#define PMU_HP_SLEEP_LP_MEM_DSLP_S 30 +/** PMU_HP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN (BIT(31)) +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_M (PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S) +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S 31 + +/** PMU_HP_SLEEP_LP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xac) +/** PMU_HP_SLEEP_XPD_LPPLL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_LPPLL (BIT(27)) +#define PMU_HP_SLEEP_XPD_LPPLL_M (PMU_HP_SLEEP_XPD_LPPLL_V << PMU_HP_SLEEP_XPD_LPPLL_S) +#define PMU_HP_SLEEP_XPD_LPPLL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_LPPLL_S 27 +/** PMU_HP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_XTAL32K (BIT(28)) +#define PMU_HP_SLEEP_XPD_XTAL32K_M (PMU_HP_SLEEP_XPD_XTAL32K_V << PMU_HP_SLEEP_XPD_XTAL32K_S) +#define PMU_HP_SLEEP_XPD_XTAL32K_V 0x00000001U +#define PMU_HP_SLEEP_XPD_XTAL32K_S 28 +/** PMU_HP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_RC32K (BIT(29)) +#define PMU_HP_SLEEP_XPD_RC32K_M (PMU_HP_SLEEP_XPD_RC32K_V << PMU_HP_SLEEP_XPD_RC32K_S) +#define PMU_HP_SLEEP_XPD_RC32K_V 0x00000001U +#define PMU_HP_SLEEP_XPD_RC32K_S 29 +/** PMU_HP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_FOSC_CLK (BIT(30)) +#define PMU_HP_SLEEP_XPD_FOSC_CLK_M (PMU_HP_SLEEP_XPD_FOSC_CLK_V << PMU_HP_SLEEP_XPD_FOSC_CLK_S) +#define PMU_HP_SLEEP_XPD_FOSC_CLK_V 0x00000001U +#define PMU_HP_SLEEP_XPD_FOSC_CLK_S 30 +/** PMU_HP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_OSC_CLK (BIT(31)) +#define PMU_HP_SLEEP_PD_OSC_CLK_M (PMU_HP_SLEEP_PD_OSC_CLK_V << PMU_HP_SLEEP_PD_OSC_CLK_S) +#define PMU_HP_SLEEP_PD_OSC_CLK_V 0x00000001U +#define PMU_HP_SLEEP_PD_OSC_CLK_S 31 + +/** PMU_LP_SLEEP_LP_REGULATOR0_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0xb4) +/** PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD (BIT(21)) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V 0x00000001U +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S 21 +/** PMU_LP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_XPD (BIT(22)) +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_M (PMU_LP_SLEEP_LP_REGULATOR_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_XPD_S) +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_V 0x00000001U +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_S 22 +/** PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 8; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 +/** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S) +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S 27 + +/** PMU_LP_SLEEP_LP_REGULATOR1_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xb8) +/** PMU_LP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:28]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_M (PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S) +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S 28 + +/** PMU_LP_SLEEP_XTAL_REG register + * need_des + */ +#define PMU_LP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0xbc) +/** PMU_LP_SLEEP_XPD_XTALX2 : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_XPD_XTALX2 (BIT(30)) +#define PMU_LP_SLEEP_XPD_XTALX2_M (PMU_LP_SLEEP_XPD_XTALX2_V << PMU_LP_SLEEP_XPD_XTALX2_S) +#define PMU_LP_SLEEP_XPD_XTALX2_V 0x00000001U +#define PMU_LP_SLEEP_XPD_XTALX2_S 30 +/** PMU_LP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_XPD_XTAL (BIT(31)) +#define PMU_LP_SLEEP_XPD_XTAL_M (PMU_LP_SLEEP_XPD_XTAL_V << PMU_LP_SLEEP_XPD_XTAL_S) +#define PMU_LP_SLEEP_XPD_XTAL_V 0x00000001U +#define PMU_LP_SLEEP_XPD_XTAL_S 31 + +/** PMU_LP_SLEEP_LP_DIG_POWER_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xc0) +/** PMU_LP_SLEEP_VDD_IO_MODE : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_VDD_IO_MODE 0x0000000FU +#define PMU_LP_SLEEP_VDD_IO_MODE_M (PMU_LP_SLEEP_VDD_IO_MODE_V << PMU_LP_SLEEP_VDD_IO_MODE_S) +#define PMU_LP_SLEEP_VDD_IO_MODE_V 0x0000000FU +#define PMU_LP_SLEEP_VDD_IO_MODE_S 23 +/** PMU_LP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_BOD_SOURCE_SEL (BIT(27)) +#define PMU_LP_SLEEP_BOD_SOURCE_SEL_M (PMU_LP_SLEEP_BOD_SOURCE_SEL_V << PMU_LP_SLEEP_BOD_SOURCE_SEL_S) +#define PMU_LP_SLEEP_BOD_SOURCE_SEL_V 0x00000001U +#define PMU_LP_SLEEP_BOD_SOURCE_SEL_S 27 +/** PMU_LP_SLEEP_VDDBAT_MODE : R/W; bitpos: [29:28]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_VDDBAT_MODE 0x00000003U +#define PMU_LP_SLEEP_VDDBAT_MODE_M (PMU_LP_SLEEP_VDDBAT_MODE_V << PMU_LP_SLEEP_VDDBAT_MODE_S) +#define PMU_LP_SLEEP_VDDBAT_MODE_V 0x00000003U +#define PMU_LP_SLEEP_VDDBAT_MODE_S 28 +/** PMU_LP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_MEM_DSLP (BIT(30)) +#define PMU_LP_SLEEP_LP_MEM_DSLP_M (PMU_LP_SLEEP_LP_MEM_DSLP_V << PMU_LP_SLEEP_LP_MEM_DSLP_S) +#define PMU_LP_SLEEP_LP_MEM_DSLP_V 0x00000001U +#define PMU_LP_SLEEP_LP_MEM_DSLP_S 30 +/** PMU_LP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN (BIT(31)) +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_M (PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S) +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V 0x00000001U +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S 31 + +/** PMU_LP_SLEEP_LP_CK_POWER_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xc4) +/** PMU_LP_SLEEP_XPD_LPPLL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_LPPLL (BIT(27)) +#define PMU_LP_SLEEP_XPD_LPPLL_M (PMU_LP_SLEEP_XPD_LPPLL_V << PMU_LP_SLEEP_XPD_LPPLL_S) +#define PMU_LP_SLEEP_XPD_LPPLL_V 0x00000001U +#define PMU_LP_SLEEP_XPD_LPPLL_S 27 +/** PMU_LP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_XTAL32K (BIT(28)) +#define PMU_LP_SLEEP_XPD_XTAL32K_M (PMU_LP_SLEEP_XPD_XTAL32K_V << PMU_LP_SLEEP_XPD_XTAL32K_S) +#define PMU_LP_SLEEP_XPD_XTAL32K_V 0x00000001U +#define PMU_LP_SLEEP_XPD_XTAL32K_S 28 +/** PMU_LP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_RC32K (BIT(29)) +#define PMU_LP_SLEEP_XPD_RC32K_M (PMU_LP_SLEEP_XPD_RC32K_V << PMU_LP_SLEEP_XPD_RC32K_S) +#define PMU_LP_SLEEP_XPD_RC32K_V 0x00000001U +#define PMU_LP_SLEEP_XPD_RC32K_S 29 +/** PMU_LP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_XPD_FOSC_CLK (BIT(30)) +#define PMU_LP_SLEEP_XPD_FOSC_CLK_M (PMU_LP_SLEEP_XPD_FOSC_CLK_V << PMU_LP_SLEEP_XPD_FOSC_CLK_S) +#define PMU_LP_SLEEP_XPD_FOSC_CLK_V 0x00000001U +#define PMU_LP_SLEEP_XPD_FOSC_CLK_S 30 +/** PMU_LP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_OSC_CLK (BIT(31)) +#define PMU_LP_SLEEP_PD_OSC_CLK_M (PMU_LP_SLEEP_PD_OSC_CLK_V << PMU_LP_SLEEP_PD_OSC_CLK_S) +#define PMU_LP_SLEEP_PD_OSC_CLK_V 0x00000001U +#define PMU_LP_SLEEP_PD_OSC_CLK_S 31 + +/** PMU_LP_SLEEP_BIAS_REG register + * need_des + */ +#define PMU_LP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0xc8) +/** PMU_LP_SLEEP_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_DCDC_CCM_ENB (BIT(9)) +#define PMU_LP_SLEEP_DCDC_CCM_ENB_M (PMU_LP_SLEEP_DCDC_CCM_ENB_V << PMU_LP_SLEEP_DCDC_CCM_ENB_S) +#define PMU_LP_SLEEP_DCDC_CCM_ENB_V 0x00000001U +#define PMU_LP_SLEEP_DCDC_CCM_ENB_S 9 +/** PMU_LP_SLEEP_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_DCDC_CLEAR_RDY (BIT(10)) +#define PMU_LP_SLEEP_DCDC_CLEAR_RDY_M (PMU_LP_SLEEP_DCDC_CLEAR_RDY_V << PMU_LP_SLEEP_DCDC_CLEAR_RDY_S) +#define PMU_LP_SLEEP_DCDC_CLEAR_RDY_V 0x00000001U +#define PMU_LP_SLEEP_DCDC_CLEAR_RDY_S 10 +/** PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS 0x00000003U +#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_M (PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_V << PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_S) +#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_V 0x00000003U +#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_S 11 +/** PMU_LP_SLEEP_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 4; + * need_des + */ +#define PMU_LP_SLEEP_DIG_PMU_DSFMOS 0x0000000FU +#define PMU_LP_SLEEP_DIG_PMU_DSFMOS_M (PMU_LP_SLEEP_DIG_PMU_DSFMOS_V << PMU_LP_SLEEP_DIG_PMU_DSFMOS_S) +#define PMU_LP_SLEEP_DIG_PMU_DSFMOS_V 0x0000000FU +#define PMU_LP_SLEEP_DIG_PMU_DSFMOS_S 13 +/** PMU_LP_SLEEP_DCM_VSET : R/W; bitpos: [21:17]; default: 23; + * need_des + */ +#define PMU_LP_SLEEP_DCM_VSET 0x0000001FU +#define PMU_LP_SLEEP_DCM_VSET_M (PMU_LP_SLEEP_DCM_VSET_V << PMU_LP_SLEEP_DCM_VSET_S) +#define PMU_LP_SLEEP_DCM_VSET_V 0x0000001FU +#define PMU_LP_SLEEP_DCM_VSET_S 17 +/** PMU_LP_SLEEP_DCM_MODE : R/W; bitpos: [23:22]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_DCM_MODE 0x00000003U +#define PMU_LP_SLEEP_DCM_MODE_M (PMU_LP_SLEEP_DCM_MODE_V << PMU_LP_SLEEP_DCM_MODE_S) +#define PMU_LP_SLEEP_DCM_MODE_V 0x00000003U +#define PMU_LP_SLEEP_DCM_MODE_S 22 +/** PMU_LP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_BIAS (BIT(25)) +#define PMU_LP_SLEEP_XPD_BIAS_M (PMU_LP_SLEEP_XPD_BIAS_V << PMU_LP_SLEEP_XPD_BIAS_S) +#define PMU_LP_SLEEP_XPD_BIAS_V 0x00000001U +#define PMU_LP_SLEEP_XPD_BIAS_S 25 +/** PMU_LP_SLEEP_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_DISCNNT_DIG_RTC (BIT(29)) +#define PMU_LP_SLEEP_DISCNNT_DIG_RTC_M (PMU_LP_SLEEP_DISCNNT_DIG_RTC_V << PMU_LP_SLEEP_DISCNNT_DIG_RTC_S) +#define PMU_LP_SLEEP_DISCNNT_DIG_RTC_V 0x00000001U +#define PMU_LP_SLEEP_DISCNNT_DIG_RTC_S 29 +/** PMU_LP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_CUR (BIT(30)) +#define PMU_LP_SLEEP_PD_CUR_M (PMU_LP_SLEEP_PD_CUR_V << PMU_LP_SLEEP_PD_CUR_S) +#define PMU_LP_SLEEP_PD_CUR_V 0x00000001U +#define PMU_LP_SLEEP_PD_CUR_S 30 +/** PMU_LP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_BIAS_SLEEP (BIT(31)) +#define PMU_LP_SLEEP_BIAS_SLEEP_M (PMU_LP_SLEEP_BIAS_SLEEP_V << PMU_LP_SLEEP_BIAS_SLEEP_S) +#define PMU_LP_SLEEP_BIAS_SLEEP_V 0x00000001U +#define PMU_LP_SLEEP_BIAS_SLEEP_S 31 + +/** PMU_IMM_HP_CK_POWER_REG register + * need_des + */ +#define PMU_IMM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0xcc) +/** PMU_TIE_LOW_GLOBAL_BBPLL_ICG : WT; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG (BIT(0)) +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_M (PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V << PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S) +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S 0 +/** PMU_TIE_LOW_GLOBAL_XTAL_ICG : WT; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG (BIT(1)) +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_M (PMU_TIE_LOW_GLOBAL_XTAL_ICG_V << PMU_TIE_LOW_GLOBAL_XTAL_ICG_S) +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_S 1 +/** PMU_TIE_LOW_I2C_RETENTION : WT; bitpos: [2]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_I2C_RETENTION (BIT(2)) +#define PMU_TIE_LOW_I2C_RETENTION_M (PMU_TIE_LOW_I2C_RETENTION_V << PMU_TIE_LOW_I2C_RETENTION_S) +#define PMU_TIE_LOW_I2C_RETENTION_V 0x00000001U +#define PMU_TIE_LOW_I2C_RETENTION_S 2 +/** PMU_TIE_LOW_XPD_BB_I2C : WT; bitpos: [3]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_BB_I2C (BIT(3)) +#define PMU_TIE_LOW_XPD_BB_I2C_M (PMU_TIE_LOW_XPD_BB_I2C_V << PMU_TIE_LOW_XPD_BB_I2C_S) +#define PMU_TIE_LOW_XPD_BB_I2C_V 0x00000001U +#define PMU_TIE_LOW_XPD_BB_I2C_S 3 +/** PMU_TIE_LOW_XPD_BBPLL_I2C : WT; bitpos: [4]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_BBPLL_I2C (BIT(4)) +#define PMU_TIE_LOW_XPD_BBPLL_I2C_M (PMU_TIE_LOW_XPD_BBPLL_I2C_V << PMU_TIE_LOW_XPD_BBPLL_I2C_S) +#define PMU_TIE_LOW_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_TIE_LOW_XPD_BBPLL_I2C_S 4 +/** PMU_TIE_LOW_XPD_BBPLL : WT; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_BBPLL (BIT(5)) +#define PMU_TIE_LOW_XPD_BBPLL_M (PMU_TIE_LOW_XPD_BBPLL_V << PMU_TIE_LOW_XPD_BBPLL_S) +#define PMU_TIE_LOW_XPD_BBPLL_V 0x00000001U +#define PMU_TIE_LOW_XPD_BBPLL_S 5 +/** PMU_TIE_LOW_XPD_XTAL : WT; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_XTAL (BIT(6)) +#define PMU_TIE_LOW_XPD_XTAL_M (PMU_TIE_LOW_XPD_XTAL_V << PMU_TIE_LOW_XPD_XTAL_S) +#define PMU_TIE_LOW_XPD_XTAL_V 0x00000001U +#define PMU_TIE_LOW_XPD_XTAL_S 6 +/** PMU_TIE_LOW_GLOBAL_XTALX2_ICG : WT; bitpos: [7]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG (BIT(7)) +#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG_M (PMU_TIE_LOW_GLOBAL_XTALX2_ICG_V << PMU_TIE_LOW_GLOBAL_XTALX2_ICG_S) +#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG_S 7 +/** PMU_TIE_LOW_XPD_XTALX2 : WT; bitpos: [8]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_XTALX2 (BIT(8)) +#define PMU_TIE_LOW_XPD_XTALX2_M (PMU_TIE_LOW_XPD_XTALX2_V << PMU_TIE_LOW_XPD_XTALX2_S) +#define PMU_TIE_LOW_XPD_XTALX2_V 0x00000001U +#define PMU_TIE_LOW_XPD_XTALX2_S 8 +/** PMU_TIE_HIGH_XTALX2 : WT; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XTALX2 (BIT(23)) +#define PMU_TIE_HIGH_XTALX2_M (PMU_TIE_HIGH_XTALX2_V << PMU_TIE_HIGH_XTALX2_S) +#define PMU_TIE_HIGH_XTALX2_V 0x00000001U +#define PMU_TIE_HIGH_XTALX2_S 23 +/** PMU_TIE_HIGH_GLOBAL_XTALX2_ICG : WT; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG (BIT(24)) +#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_M (PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_V << PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_S 24 +/** PMU_TIE_HIGH_GLOBAL_BBPLL_ICG : WT; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG (BIT(25)) +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_M (PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S 25 +/** PMU_TIE_HIGH_GLOBAL_XTAL_ICG : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG (BIT(26)) +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_M (PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V << PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S 26 +/** PMU_TIE_HIGH_I2C_RETENTION : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_I2C_RETENTION (BIT(27)) +#define PMU_TIE_HIGH_I2C_RETENTION_M (PMU_TIE_HIGH_I2C_RETENTION_V << PMU_TIE_HIGH_I2C_RETENTION_S) +#define PMU_TIE_HIGH_I2C_RETENTION_V 0x00000001U +#define PMU_TIE_HIGH_I2C_RETENTION_S 27 +/** PMU_TIE_HIGH_XPD_BB_I2C : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_BB_I2C (BIT(28)) +#define PMU_TIE_HIGH_XPD_BB_I2C_M (PMU_TIE_HIGH_XPD_BB_I2C_V << PMU_TIE_HIGH_XPD_BB_I2C_S) +#define PMU_TIE_HIGH_XPD_BB_I2C_V 0x00000001U +#define PMU_TIE_HIGH_XPD_BB_I2C_S 28 +/** PMU_TIE_HIGH_XPD_BBPLL_I2C : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_BBPLL_I2C (BIT(29)) +#define PMU_TIE_HIGH_XPD_BBPLL_I2C_M (PMU_TIE_HIGH_XPD_BBPLL_I2C_V << PMU_TIE_HIGH_XPD_BBPLL_I2C_S) +#define PMU_TIE_HIGH_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_TIE_HIGH_XPD_BBPLL_I2C_S 29 +/** PMU_TIE_HIGH_XPD_BBPLL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_BBPLL (BIT(30)) +#define PMU_TIE_HIGH_XPD_BBPLL_M (PMU_TIE_HIGH_XPD_BBPLL_V << PMU_TIE_HIGH_XPD_BBPLL_S) +#define PMU_TIE_HIGH_XPD_BBPLL_V 0x00000001U +#define PMU_TIE_HIGH_XPD_BBPLL_S 30 +/** PMU_TIE_HIGH_XPD_XTAL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_XTAL (BIT(31)) +#define PMU_TIE_HIGH_XPD_XTAL_M (PMU_TIE_HIGH_XPD_XTAL_V << PMU_TIE_HIGH_XPD_XTAL_S) +#define PMU_TIE_HIGH_XPD_XTAL_V 0x00000001U +#define PMU_TIE_HIGH_XPD_XTAL_S 31 + +/** PMU_IMM_SLEEP_SYSCLK_REG register + * need_des + */ +#define PMU_IMM_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0xd0) +/** PMU_UPDATE_DIG_ICG_SWITCH : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_SWITCH (BIT(28)) +#define PMU_UPDATE_DIG_ICG_SWITCH_M (PMU_UPDATE_DIG_ICG_SWITCH_V << PMU_UPDATE_DIG_ICG_SWITCH_S) +#define PMU_UPDATE_DIG_ICG_SWITCH_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_SWITCH_S 28 +/** PMU_TIE_LOW_ICG_SLP_SEL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_ICG_SLP_SEL (BIT(29)) +#define PMU_TIE_LOW_ICG_SLP_SEL_M (PMU_TIE_LOW_ICG_SLP_SEL_V << PMU_TIE_LOW_ICG_SLP_SEL_S) +#define PMU_TIE_LOW_ICG_SLP_SEL_V 0x00000001U +#define PMU_TIE_LOW_ICG_SLP_SEL_S 29 +/** PMU_TIE_HIGH_ICG_SLP_SEL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_ICG_SLP_SEL (BIT(30)) +#define PMU_TIE_HIGH_ICG_SLP_SEL_M (PMU_TIE_HIGH_ICG_SLP_SEL_V << PMU_TIE_HIGH_ICG_SLP_SEL_S) +#define PMU_TIE_HIGH_ICG_SLP_SEL_V 0x00000001U +#define PMU_TIE_HIGH_ICG_SLP_SEL_S 30 +/** PMU_UPDATE_DIG_SYS_CLK_SEL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_SYS_CLK_SEL (BIT(31)) +#define PMU_UPDATE_DIG_SYS_CLK_SEL_M (PMU_UPDATE_DIG_SYS_CLK_SEL_V << PMU_UPDATE_DIG_SYS_CLK_SEL_S) +#define PMU_UPDATE_DIG_SYS_CLK_SEL_V 0x00000001U +#define PMU_UPDATE_DIG_SYS_CLK_SEL_S 31 + +/** PMU_IMM_HP_FUNC_ICG_REG register + * need_des + */ +#define PMU_IMM_HP_FUNC_ICG_REG (DR_REG_PMU_BASE + 0xd4) +/** PMU_UPDATE_DIG_ICG_FUNC_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_FUNC_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_FUNC_EN_M (PMU_UPDATE_DIG_ICG_FUNC_EN_V << PMU_UPDATE_DIG_ICG_FUNC_EN_S) +#define PMU_UPDATE_DIG_ICG_FUNC_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_FUNC_EN_S 31 + +/** PMU_IMM_HP_APB_ICG_REG register + * need_des + */ +#define PMU_IMM_HP_APB_ICG_REG (DR_REG_PMU_BASE + 0xd8) +/** PMU_UPDATE_DIG_ICG_APB_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_APB_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_APB_EN_M (PMU_UPDATE_DIG_ICG_APB_EN_V << PMU_UPDATE_DIG_ICG_APB_EN_S) +#define PMU_UPDATE_DIG_ICG_APB_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_APB_EN_S 31 + +/** PMU_IMM_MODEM_ICG_REG register + * need_des + */ +#define PMU_IMM_MODEM_ICG_REG (DR_REG_PMU_BASE + 0xdc) +/** PMU_UPDATE_DIG_ICG_MODEM_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_MODEM_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_MODEM_EN_M (PMU_UPDATE_DIG_ICG_MODEM_EN_V << PMU_UPDATE_DIG_ICG_MODEM_EN_S) +#define PMU_UPDATE_DIG_ICG_MODEM_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_MODEM_EN_S 31 + +/** PMU_IMM_LP_ICG_REG register + * need_des + */ +#define PMU_IMM_LP_ICG_REG (DR_REG_PMU_BASE + 0xe0) +/** PMU_TIE_LOW_LP_ROOTCLK_SEL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_LP_ROOTCLK_SEL (BIT(30)) +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_M (PMU_TIE_LOW_LP_ROOTCLK_SEL_V << PMU_TIE_LOW_LP_ROOTCLK_SEL_S) +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_V 0x00000001U +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_S 30 +/** PMU_TIE_HIGH_LP_ROOTCLK_SEL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL (BIT(31)) +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_M (PMU_TIE_HIGH_LP_ROOTCLK_SEL_V << PMU_TIE_HIGH_LP_ROOTCLK_SEL_S) +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_V 0x00000001U +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_S 31 + +/** PMU_IMM_PAD_HOLD_ALL_REG register + * need_des + */ +#define PMU_IMM_PAD_HOLD_ALL_REG (DR_REG_PMU_BASE + 0xe4) +/** PMU_TIE_HIGH_DIG_PAD_SLP_SEL : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL (BIT(26)) +#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL_M (PMU_TIE_HIGH_DIG_PAD_SLP_SEL_V << PMU_TIE_HIGH_DIG_PAD_SLP_SEL_S) +#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL_S 26 +/** PMU_TIE_LOW_DIG_PAD_SLP_SEL : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_TIE_LOW_DIG_PAD_SLP_SEL_M (PMU_TIE_LOW_DIG_PAD_SLP_SEL_V << PMU_TIE_LOW_DIG_PAD_SLP_SEL_S) +#define PMU_TIE_LOW_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_TIE_LOW_DIG_PAD_SLP_SEL_S 27 +/** PMU_TIE_HIGH_LP_PAD_HOLD_ALL : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL (BIT(28)) +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_M (PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S) +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S 28 +/** PMU_TIE_LOW_LP_PAD_HOLD_ALL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL (BIT(29)) +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_M (PMU_TIE_LOW_LP_PAD_HOLD_ALL_V << PMU_TIE_LOW_LP_PAD_HOLD_ALL_S) +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_S 29 +/** PMU_TIE_HIGH_HP_PAD_HOLD_ALL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL (BIT(30)) +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_M (PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S) +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S 30 +/** PMU_TIE_LOW_HP_PAD_HOLD_ALL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL (BIT(31)) +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_M (PMU_TIE_LOW_HP_PAD_HOLD_ALL_V << PMU_TIE_LOW_HP_PAD_HOLD_ALL_S) +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_S 31 + +/** PMU_IMM_I2C_ISO_REG register + * need_des + */ +#define PMU_IMM_I2C_ISO_REG (DR_REG_PMU_BASE + 0xe8) +/** PMU_TIE_HIGH_I2C_ISO_EN : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_I2C_ISO_EN (BIT(30)) +#define PMU_TIE_HIGH_I2C_ISO_EN_M (PMU_TIE_HIGH_I2C_ISO_EN_V << PMU_TIE_HIGH_I2C_ISO_EN_S) +#define PMU_TIE_HIGH_I2C_ISO_EN_V 0x00000001U +#define PMU_TIE_HIGH_I2C_ISO_EN_S 30 +/** PMU_TIE_LOW_I2C_ISO_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_I2C_ISO_EN (BIT(31)) +#define PMU_TIE_LOW_I2C_ISO_EN_M (PMU_TIE_LOW_I2C_ISO_EN_V << PMU_TIE_LOW_I2C_ISO_EN_S) +#define PMU_TIE_LOW_I2C_ISO_EN_V 0x00000001U +#define PMU_TIE_LOW_I2C_ISO_EN_S 31 + +/** PMU_POWER_WAIT_TIMER0_REG register + * need_des + */ +#define PMU_POWER_WAIT_TIMER0_REG (DR_REG_PMU_BASE + 0xec) +/** PMU_DG_HP_POWERDOWN_TIMER : R/W; bitpos: [13:5]; default: 255; + * need_des + */ +#define PMU_DG_HP_POWERDOWN_TIMER 0x000001FFU +#define PMU_DG_HP_POWERDOWN_TIMER_M (PMU_DG_HP_POWERDOWN_TIMER_V << PMU_DG_HP_POWERDOWN_TIMER_S) +#define PMU_DG_HP_POWERDOWN_TIMER_V 0x000001FFU +#define PMU_DG_HP_POWERDOWN_TIMER_S 5 +/** PMU_DG_HP_POWERUP_TIMER : R/W; bitpos: [22:14]; default: 255; + * need_des + */ +#define PMU_DG_HP_POWERUP_TIMER 0x000001FFU +#define PMU_DG_HP_POWERUP_TIMER_M (PMU_DG_HP_POWERUP_TIMER_V << PMU_DG_HP_POWERUP_TIMER_S) +#define PMU_DG_HP_POWERUP_TIMER_V 0x000001FFU +#define PMU_DG_HP_POWERUP_TIMER_S 14 +/** PMU_DG_HP_PD_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; + * need_des + */ +#define PMU_DG_HP_PD_WAIT_TIMER 0x000001FFU +#define PMU_DG_HP_PD_WAIT_TIMER_M (PMU_DG_HP_PD_WAIT_TIMER_V << PMU_DG_HP_PD_WAIT_TIMER_S) +#define PMU_DG_HP_PD_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_HP_PD_WAIT_TIMER_S 23 + +/** PMU_POWER_WAIT_TIMER1_REG register + * need_des + */ +#define PMU_POWER_WAIT_TIMER1_REG (DR_REG_PMU_BASE + 0xf0) +/** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [15:9]; default: 63; + * need_des + */ +#define PMU_DG_LP_POWERDOWN_TIMER 0x0000007FU +#define PMU_DG_LP_POWERDOWN_TIMER_M (PMU_DG_LP_POWERDOWN_TIMER_V << PMU_DG_LP_POWERDOWN_TIMER_S) +#define PMU_DG_LP_POWERDOWN_TIMER_V 0x0000007FU +#define PMU_DG_LP_POWERDOWN_TIMER_S 9 +/** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:16]; default: 63; + * need_des + */ +#define PMU_DG_LP_POWERUP_TIMER 0x0000007FU +#define PMU_DG_LP_POWERUP_TIMER_M (PMU_DG_LP_POWERUP_TIMER_V << PMU_DG_LP_POWERUP_TIMER_S) +#define PMU_DG_LP_POWERUP_TIMER_V 0x0000007FU +#define PMU_DG_LP_POWERUP_TIMER_S 16 +/** PMU_DG_LP_PD_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; + * need_des + */ +#define PMU_DG_LP_PD_WAIT_TIMER 0x000001FFU +#define PMU_DG_LP_PD_WAIT_TIMER_M (PMU_DG_LP_PD_WAIT_TIMER_V << PMU_DG_LP_PD_WAIT_TIMER_S) +#define PMU_DG_LP_PD_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_LP_PD_WAIT_TIMER_S 23 + +/** PMU_POWER_WAIT_TIMER2_REG register + * need_des + */ +#define PMU_POWER_WAIT_TIMER2_REG (DR_REG_PMU_BASE + 0xf4) +/** PMU_DG_LP_ISO_WAIT_TIMER : R/W; bitpos: [7:0]; default: 255; + * need_des + */ +#define PMU_DG_LP_ISO_WAIT_TIMER 0x000000FFU +#define PMU_DG_LP_ISO_WAIT_TIMER_M (PMU_DG_LP_ISO_WAIT_TIMER_V << PMU_DG_LP_ISO_WAIT_TIMER_S) +#define PMU_DG_LP_ISO_WAIT_TIMER_V 0x000000FFU +#define PMU_DG_LP_ISO_WAIT_TIMER_S 0 +/** PMU_DG_LP_RST_WAIT_TIMER : R/W; bitpos: [15:8]; default: 255; + * need_des + */ +#define PMU_DG_LP_RST_WAIT_TIMER 0x000000FFU +#define PMU_DG_LP_RST_WAIT_TIMER_M (PMU_DG_LP_RST_WAIT_TIMER_V << PMU_DG_LP_RST_WAIT_TIMER_S) +#define PMU_DG_LP_RST_WAIT_TIMER_V 0x000000FFU +#define PMU_DG_LP_RST_WAIT_TIMER_S 8 +/** PMU_DG_HP_ISO_WAIT_TIMER : R/W; bitpos: [23:16]; default: 255; + * need_des + */ +#define PMU_DG_HP_ISO_WAIT_TIMER 0x000000FFU +#define PMU_DG_HP_ISO_WAIT_TIMER_M (PMU_DG_HP_ISO_WAIT_TIMER_V << PMU_DG_HP_ISO_WAIT_TIMER_S) +#define PMU_DG_HP_ISO_WAIT_TIMER_V 0x000000FFU +#define PMU_DG_HP_ISO_WAIT_TIMER_S 16 +/** PMU_DG_HP_RST_WAIT_TIMER : R/W; bitpos: [31:24]; default: 255; + * need_des + */ +#define PMU_DG_HP_RST_WAIT_TIMER 0x000000FFU +#define PMU_DG_HP_RST_WAIT_TIMER_M (PMU_DG_HP_RST_WAIT_TIMER_V << PMU_DG_HP_RST_WAIT_TIMER_S) +#define PMU_DG_HP_RST_WAIT_TIMER_V 0x000000FFU +#define PMU_DG_HP_RST_WAIT_TIMER_S 24 + +/** PMU_POWER_PD_TOP_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf8) +/** PMU_FORCE_TOP_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_RESET (BIT(0)) +#define PMU_FORCE_TOP_RESET_M (PMU_FORCE_TOP_RESET_V << PMU_FORCE_TOP_RESET_S) +#define PMU_FORCE_TOP_RESET_V 0x00000001U +#define PMU_FORCE_TOP_RESET_S 0 +/** PMU_FORCE_TOP_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_ISO (BIT(1)) +#define PMU_FORCE_TOP_ISO_M (PMU_FORCE_TOP_ISO_V << PMU_FORCE_TOP_ISO_S) +#define PMU_FORCE_TOP_ISO_V 0x00000001U +#define PMU_FORCE_TOP_ISO_S 1 +/** PMU_FORCE_TOP_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_PU (BIT(2)) +#define PMU_FORCE_TOP_PU_M (PMU_FORCE_TOP_PU_V << PMU_FORCE_TOP_PU_S) +#define PMU_FORCE_TOP_PU_V 0x00000001U +#define PMU_FORCE_TOP_PU_S 2 +/** PMU_FORCE_TOP_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_NO_RESET (BIT(3)) +#define PMU_FORCE_TOP_NO_RESET_M (PMU_FORCE_TOP_NO_RESET_V << PMU_FORCE_TOP_NO_RESET_S) +#define PMU_FORCE_TOP_NO_RESET_V 0x00000001U +#define PMU_FORCE_TOP_NO_RESET_S 3 +/** PMU_FORCE_TOP_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_NO_ISO (BIT(4)) +#define PMU_FORCE_TOP_NO_ISO_M (PMU_FORCE_TOP_NO_ISO_V << PMU_FORCE_TOP_NO_ISO_S) +#define PMU_FORCE_TOP_NO_ISO_V 0x00000001U +#define PMU_FORCE_TOP_NO_ISO_S 4 +/** PMU_FORCE_TOP_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_PD (BIT(5)) +#define PMU_FORCE_TOP_PD_M (PMU_FORCE_TOP_PD_V << PMU_FORCE_TOP_PD_S) +#define PMU_FORCE_TOP_PD_V 0x00000001U +#define PMU_FORCE_TOP_PD_S 5 +/** PMU_PD_TOP_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_TOP_MASK 0x0000001FU +#define PMU_PD_TOP_MASK_M (PMU_PD_TOP_MASK_V << PMU_PD_TOP_MASK_S) +#define PMU_PD_TOP_MASK_V 0x0000001FU +#define PMU_PD_TOP_MASK_S 6 +/** PMU_PD_TOP_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_TOP_PD_MASK 0x0000001FU +#define PMU_PD_TOP_PD_MASK_M (PMU_PD_TOP_PD_MASK_V << PMU_PD_TOP_PD_MASK_S) +#define PMU_PD_TOP_PD_MASK_V 0x0000001FU +#define PMU_PD_TOP_PD_MASK_S 27 + +/** PMU_POWER_PD_HPAON_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPAON_CNTL_REG (DR_REG_PMU_BASE + 0xfc) +/** PMU_FORCE_HP_AON_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_AON_RESET (BIT(0)) +#define PMU_FORCE_HP_AON_RESET_M (PMU_FORCE_HP_AON_RESET_V << PMU_FORCE_HP_AON_RESET_S) +#define PMU_FORCE_HP_AON_RESET_V 0x00000001U +#define PMU_FORCE_HP_AON_RESET_S 0 +/** PMU_FORCE_HP_AON_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_AON_ISO (BIT(1)) +#define PMU_FORCE_HP_AON_ISO_M (PMU_FORCE_HP_AON_ISO_V << PMU_FORCE_HP_AON_ISO_S) +#define PMU_FORCE_HP_AON_ISO_V 0x00000001U +#define PMU_FORCE_HP_AON_ISO_S 1 +/** PMU_FORCE_HP_AON_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_AON_PU (BIT(2)) +#define PMU_FORCE_HP_AON_PU_M (PMU_FORCE_HP_AON_PU_V << PMU_FORCE_HP_AON_PU_S) +#define PMU_FORCE_HP_AON_PU_V 0x00000001U +#define PMU_FORCE_HP_AON_PU_S 2 +/** PMU_FORCE_HP_AON_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_AON_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_AON_NO_RESET_M (PMU_FORCE_HP_AON_NO_RESET_V << PMU_FORCE_HP_AON_NO_RESET_S) +#define PMU_FORCE_HP_AON_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_AON_NO_RESET_S 3 +/** PMU_FORCE_HP_AON_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_AON_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_AON_NO_ISO_M (PMU_FORCE_HP_AON_NO_ISO_V << PMU_FORCE_HP_AON_NO_ISO_S) +#define PMU_FORCE_HP_AON_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_AON_NO_ISO_S 4 +/** PMU_FORCE_HP_AON_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_AON_PD (BIT(5)) +#define PMU_FORCE_HP_AON_PD_M (PMU_FORCE_HP_AON_PD_V << PMU_FORCE_HP_AON_PD_S) +#define PMU_FORCE_HP_AON_PD_V 0x00000001U +#define PMU_FORCE_HP_AON_PD_S 5 +/** PMU_PD_HP_AON_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_AON_MASK 0x0000001FU +#define PMU_PD_HP_AON_MASK_M (PMU_PD_HP_AON_MASK_V << PMU_PD_HP_AON_MASK_S) +#define PMU_PD_HP_AON_MASK_V 0x0000001FU +#define PMU_PD_HP_AON_MASK_S 6 +/** PMU_PD_HP_AON_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_AON_PD_MASK 0x0000001FU +#define PMU_PD_HP_AON_PD_MASK_M (PMU_PD_HP_AON_PD_MASK_V << PMU_PD_HP_AON_PD_MASK_S) +#define PMU_PD_HP_AON_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_AON_PD_MASK_S 27 + +/** PMU_POWER_PD_HPCPU_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPCPU_CNTL_REG (DR_REG_PMU_BASE + 0x100) +/** PMU_FORCE_HP_CPU_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_RESET (BIT(0)) +#define PMU_FORCE_HP_CPU_RESET_M (PMU_FORCE_HP_CPU_RESET_V << PMU_FORCE_HP_CPU_RESET_S) +#define PMU_FORCE_HP_CPU_RESET_V 0x00000001U +#define PMU_FORCE_HP_CPU_RESET_S 0 +/** PMU_FORCE_HP_CPU_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_ISO (BIT(1)) +#define PMU_FORCE_HP_CPU_ISO_M (PMU_FORCE_HP_CPU_ISO_V << PMU_FORCE_HP_CPU_ISO_S) +#define PMU_FORCE_HP_CPU_ISO_V 0x00000001U +#define PMU_FORCE_HP_CPU_ISO_S 1 +/** PMU_FORCE_HP_CPU_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_PU (BIT(2)) +#define PMU_FORCE_HP_CPU_PU_M (PMU_FORCE_HP_CPU_PU_V << PMU_FORCE_HP_CPU_PU_S) +#define PMU_FORCE_HP_CPU_PU_V 0x00000001U +#define PMU_FORCE_HP_CPU_PU_S 2 +/** PMU_FORCE_HP_CPU_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_CPU_NO_RESET_M (PMU_FORCE_HP_CPU_NO_RESET_V << PMU_FORCE_HP_CPU_NO_RESET_S) +#define PMU_FORCE_HP_CPU_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_CPU_NO_RESET_S 3 +/** PMU_FORCE_HP_CPU_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_CPU_NO_ISO_M (PMU_FORCE_HP_CPU_NO_ISO_V << PMU_FORCE_HP_CPU_NO_ISO_S) +#define PMU_FORCE_HP_CPU_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_CPU_NO_ISO_S 4 +/** PMU_FORCE_HP_CPU_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_PD (BIT(5)) +#define PMU_FORCE_HP_CPU_PD_M (PMU_FORCE_HP_CPU_PD_V << PMU_FORCE_HP_CPU_PD_S) +#define PMU_FORCE_HP_CPU_PD_V 0x00000001U +#define PMU_FORCE_HP_CPU_PD_S 5 +/** PMU_PD_HP_CPU_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_CPU_MASK 0x0000001FU +#define PMU_PD_HP_CPU_MASK_M (PMU_PD_HP_CPU_MASK_V << PMU_PD_HP_CPU_MASK_S) +#define PMU_PD_HP_CPU_MASK_V 0x0000001FU +#define PMU_PD_HP_CPU_MASK_S 6 +/** PMU_PD_HP_CPU_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_CPU_PD_MASK 0x0000001FU +#define PMU_PD_HP_CPU_PD_MASK_M (PMU_PD_HP_CPU_PD_MASK_V << PMU_PD_HP_CPU_PD_MASK_S) +#define PMU_PD_HP_CPU_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_CPU_PD_MASK_S 27 + +/** PMU_POWER_PD_HPPERI_RESERVE_REG register + * need_des + */ +#define PMU_POWER_PD_HPPERI_RESERVE_REG (DR_REG_PMU_BASE + 0x104) +/** PMU_FORCE_HP_PERI_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PERI_RESET (BIT(0)) +#define PMU_FORCE_HP_PERI_RESET_M (PMU_FORCE_HP_PERI_RESET_V << PMU_FORCE_HP_PERI_RESET_S) +#define PMU_FORCE_HP_PERI_RESET_V 0x00000001U +#define PMU_FORCE_HP_PERI_RESET_S 0 +/** PMU_FORCE_HP_PERI_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PERI_ISO (BIT(1)) +#define PMU_FORCE_HP_PERI_ISO_M (PMU_FORCE_HP_PERI_ISO_V << PMU_FORCE_HP_PERI_ISO_S) +#define PMU_FORCE_HP_PERI_ISO_V 0x00000001U +#define PMU_FORCE_HP_PERI_ISO_S 1 +/** PMU_FORCE_HP_PERI_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_PERI_PU (BIT(2)) +#define PMU_FORCE_HP_PERI_PU_M (PMU_FORCE_HP_PERI_PU_V << PMU_FORCE_HP_PERI_PU_S) +#define PMU_FORCE_HP_PERI_PU_V 0x00000001U +#define PMU_FORCE_HP_PERI_PU_S 2 +/** PMU_FORCE_HP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_PERI_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_PERI_NO_RESET_M (PMU_FORCE_HP_PERI_NO_RESET_V << PMU_FORCE_HP_PERI_NO_RESET_S) +#define PMU_FORCE_HP_PERI_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_PERI_NO_RESET_S 3 +/** PMU_FORCE_HP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_PERI_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_PERI_NO_ISO_M (PMU_FORCE_HP_PERI_NO_ISO_V << PMU_FORCE_HP_PERI_NO_ISO_S) +#define PMU_FORCE_HP_PERI_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_PERI_NO_ISO_S 4 +/** PMU_FORCE_HP_PERI_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PERI_PD (BIT(5)) +#define PMU_FORCE_HP_PERI_PD_M (PMU_FORCE_HP_PERI_PD_V << PMU_FORCE_HP_PERI_PD_S) +#define PMU_FORCE_HP_PERI_PD_V 0x00000001U +#define PMU_FORCE_HP_PERI_PD_S 5 +/** PMU_PD_HP_PERI_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_PERI_MASK 0x0000001FU +#define PMU_PD_HP_PERI_MASK_M (PMU_PD_HP_PERI_MASK_V << PMU_PD_HP_PERI_MASK_S) +#define PMU_PD_HP_PERI_MASK_V 0x0000001FU +#define PMU_PD_HP_PERI_MASK_S 6 +/** PMU_PD_HP_PERI_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_PERI_PD_MASK 0x0000001FU +#define PMU_PD_HP_PERI_PD_MASK_M (PMU_PD_HP_PERI_PD_MASK_V << PMU_PD_HP_PERI_PD_MASK_S) +#define PMU_PD_HP_PERI_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_PERI_PD_MASK_S 27 + +/** PMU_POWER_PD_HPWIFI_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPWIFI_CNTL_REG (DR_REG_PMU_BASE + 0x108) +/** PMU_FORCE_HP_WIFI_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_WIFI_RESET (BIT(0)) +#define PMU_FORCE_HP_WIFI_RESET_M (PMU_FORCE_HP_WIFI_RESET_V << PMU_FORCE_HP_WIFI_RESET_S) +#define PMU_FORCE_HP_WIFI_RESET_V 0x00000001U +#define PMU_FORCE_HP_WIFI_RESET_S 0 +/** PMU_FORCE_HP_WIFI_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_WIFI_ISO (BIT(1)) +#define PMU_FORCE_HP_WIFI_ISO_M (PMU_FORCE_HP_WIFI_ISO_V << PMU_FORCE_HP_WIFI_ISO_S) +#define PMU_FORCE_HP_WIFI_ISO_V 0x00000001U +#define PMU_FORCE_HP_WIFI_ISO_S 1 +/** PMU_FORCE_HP_WIFI_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_WIFI_PU (BIT(2)) +#define PMU_FORCE_HP_WIFI_PU_M (PMU_FORCE_HP_WIFI_PU_V << PMU_FORCE_HP_WIFI_PU_S) +#define PMU_FORCE_HP_WIFI_PU_V 0x00000001U +#define PMU_FORCE_HP_WIFI_PU_S 2 +/** PMU_FORCE_HP_WIFI_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_WIFI_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_WIFI_NO_RESET_M (PMU_FORCE_HP_WIFI_NO_RESET_V << PMU_FORCE_HP_WIFI_NO_RESET_S) +#define PMU_FORCE_HP_WIFI_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_WIFI_NO_RESET_S 3 +/** PMU_FORCE_HP_WIFI_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_WIFI_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_WIFI_NO_ISO_M (PMU_FORCE_HP_WIFI_NO_ISO_V << PMU_FORCE_HP_WIFI_NO_ISO_S) +#define PMU_FORCE_HP_WIFI_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_WIFI_NO_ISO_S 4 +/** PMU_FORCE_HP_WIFI_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_WIFI_PD (BIT(5)) +#define PMU_FORCE_HP_WIFI_PD_M (PMU_FORCE_HP_WIFI_PD_V << PMU_FORCE_HP_WIFI_PD_S) +#define PMU_FORCE_HP_WIFI_PD_V 0x00000001U +#define PMU_FORCE_HP_WIFI_PD_S 5 +/** PMU_PD_HP_WIFI_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_WIFI_MASK 0x0000001FU +#define PMU_PD_HP_WIFI_MASK_M (PMU_PD_HP_WIFI_MASK_V << PMU_PD_HP_WIFI_MASK_S) +#define PMU_PD_HP_WIFI_MASK_V 0x0000001FU +#define PMU_PD_HP_WIFI_MASK_S 6 +/** PMU_PD_HP_WIFI_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_WIFI_PD_MASK 0x0000001FU +#define PMU_PD_HP_WIFI_PD_MASK_M (PMU_PD_HP_WIFI_PD_MASK_V << PMU_PD_HP_WIFI_PD_MASK_S) +#define PMU_PD_HP_WIFI_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_WIFI_PD_MASK_S 27 + +/** PMU_POWER_PD_LPPERI_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x10c) +/** PMU_FORCE_LP_PERI_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_RESET (BIT(0)) +#define PMU_FORCE_LP_PERI_RESET_M (PMU_FORCE_LP_PERI_RESET_V << PMU_FORCE_LP_PERI_RESET_S) +#define PMU_FORCE_LP_PERI_RESET_V 0x00000001U +#define PMU_FORCE_LP_PERI_RESET_S 0 +/** PMU_FORCE_LP_PERI_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_ISO (BIT(1)) +#define PMU_FORCE_LP_PERI_ISO_M (PMU_FORCE_LP_PERI_ISO_V << PMU_FORCE_LP_PERI_ISO_S) +#define PMU_FORCE_LP_PERI_ISO_V 0x00000001U +#define PMU_FORCE_LP_PERI_ISO_S 1 +/** PMU_FORCE_LP_PERI_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_PU (BIT(2)) +#define PMU_FORCE_LP_PERI_PU_M (PMU_FORCE_LP_PERI_PU_V << PMU_FORCE_LP_PERI_PU_S) +#define PMU_FORCE_LP_PERI_PU_V 0x00000001U +#define PMU_FORCE_LP_PERI_PU_S 2 +/** PMU_FORCE_LP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_NO_RESET (BIT(3)) +#define PMU_FORCE_LP_PERI_NO_RESET_M (PMU_FORCE_LP_PERI_NO_RESET_V << PMU_FORCE_LP_PERI_NO_RESET_S) +#define PMU_FORCE_LP_PERI_NO_RESET_V 0x00000001U +#define PMU_FORCE_LP_PERI_NO_RESET_S 3 +/** PMU_FORCE_LP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_NO_ISO (BIT(4)) +#define PMU_FORCE_LP_PERI_NO_ISO_M (PMU_FORCE_LP_PERI_NO_ISO_V << PMU_FORCE_LP_PERI_NO_ISO_S) +#define PMU_FORCE_LP_PERI_NO_ISO_V 0x00000001U +#define PMU_FORCE_LP_PERI_NO_ISO_S 4 +/** PMU_FORCE_LP_PERI_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_PD (BIT(5)) +#define PMU_FORCE_LP_PERI_PD_M (PMU_FORCE_LP_PERI_PD_V << PMU_FORCE_LP_PERI_PD_S) +#define PMU_FORCE_LP_PERI_PD_V 0x00000001U +#define PMU_FORCE_LP_PERI_PD_S 5 + +/** PMU_POWER_PD_MEM_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_MEM_CNTL_REG (DR_REG_PMU_BASE + 0x110) +/** PMU_FORCE_HP_MEM_ISO : R/W; bitpos: [3:0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_MEM_ISO 0x0000000FU +#define PMU_FORCE_HP_MEM_ISO_M (PMU_FORCE_HP_MEM_ISO_V << PMU_FORCE_HP_MEM_ISO_S) +#define PMU_FORCE_HP_MEM_ISO_V 0x0000000FU +#define PMU_FORCE_HP_MEM_ISO_S 0 +/** PMU_FORCE_HP_MEM_PD : R/W; bitpos: [7:4]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_MEM_PD 0x0000000FU +#define PMU_FORCE_HP_MEM_PD_M (PMU_FORCE_HP_MEM_PD_V << PMU_FORCE_HP_MEM_PD_S) +#define PMU_FORCE_HP_MEM_PD_V 0x0000000FU +#define PMU_FORCE_HP_MEM_PD_S 4 +/** PMU_FORCE_HP_MEM_NO_ISO : R/W; bitpos: [27:24]; default: 15; + * need_des + */ +#define PMU_FORCE_HP_MEM_NO_ISO 0x0000000FU +#define PMU_FORCE_HP_MEM_NO_ISO_M (PMU_FORCE_HP_MEM_NO_ISO_V << PMU_FORCE_HP_MEM_NO_ISO_S) +#define PMU_FORCE_HP_MEM_NO_ISO_V 0x0000000FU +#define PMU_FORCE_HP_MEM_NO_ISO_S 24 +/** PMU_FORCE_HP_MEM_PU : R/W; bitpos: [31:28]; default: 15; + * need_des + */ +#define PMU_FORCE_HP_MEM_PU 0x0000000FU +#define PMU_FORCE_HP_MEM_PU_M (PMU_FORCE_HP_MEM_PU_V << PMU_FORCE_HP_MEM_PU_S) +#define PMU_FORCE_HP_MEM_PU_V 0x0000000FU +#define PMU_FORCE_HP_MEM_PU_S 28 + +/** PMU_POWER_PD_MEM_MASK_REG register + * need_des + */ +#define PMU_POWER_PD_MEM_MASK_REG (DR_REG_PMU_BASE + 0x114) +/** PMU_PD_HP_MEM2_PD_MASK : R/W; bitpos: [4:0]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM2_PD_MASK 0x0000001FU +#define PMU_PD_HP_MEM2_PD_MASK_M (PMU_PD_HP_MEM2_PD_MASK_V << PMU_PD_HP_MEM2_PD_MASK_S) +#define PMU_PD_HP_MEM2_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM2_PD_MASK_S 0 +/** PMU_PD_HP_MEM1_PD_MASK : R/W; bitpos: [9:5]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM1_PD_MASK 0x0000001FU +#define PMU_PD_HP_MEM1_PD_MASK_M (PMU_PD_HP_MEM1_PD_MASK_V << PMU_PD_HP_MEM1_PD_MASK_S) +#define PMU_PD_HP_MEM1_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM1_PD_MASK_S 5 +/** PMU_PD_HP_MEM0_PD_MASK : R/W; bitpos: [14:10]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM0_PD_MASK 0x0000001FU +#define PMU_PD_HP_MEM0_PD_MASK_M (PMU_PD_HP_MEM0_PD_MASK_V << PMU_PD_HP_MEM0_PD_MASK_S) +#define PMU_PD_HP_MEM0_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM0_PD_MASK_S 10 +/** PMU_PD_HP_MEM2_MASK : R/W; bitpos: [21:17]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM2_MASK 0x0000001FU +#define PMU_PD_HP_MEM2_MASK_M (PMU_PD_HP_MEM2_MASK_V << PMU_PD_HP_MEM2_MASK_S) +#define PMU_PD_HP_MEM2_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM2_MASK_S 17 +/** PMU_PD_HP_MEM1_MASK : R/W; bitpos: [26:22]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM1_MASK 0x0000001FU +#define PMU_PD_HP_MEM1_MASK_M (PMU_PD_HP_MEM1_MASK_V << PMU_PD_HP_MEM1_MASK_S) +#define PMU_PD_HP_MEM1_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM1_MASK_S 22 +/** PMU_PD_HP_MEM0_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM0_MASK 0x0000001FU +#define PMU_PD_HP_MEM0_MASK_M (PMU_PD_HP_MEM0_MASK_V << PMU_PD_HP_MEM0_MASK_S) +#define PMU_PD_HP_MEM0_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM0_MASK_S 27 + +/** PMU_POWER_HP_PAD_REG register + * need_des + */ +#define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x118) +/** PMU_FORCE_HP_PAD_NO_ISO_ALL : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PAD_NO_ISO_ALL (BIT(0)) +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_M (PMU_FORCE_HP_PAD_NO_ISO_ALL_V << PMU_FORCE_HP_PAD_NO_ISO_ALL_S) +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_V 0x00000001U +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_S 0 +/** PMU_FORCE_HP_PAD_ISO_ALL : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PAD_ISO_ALL (BIT(1)) +#define PMU_FORCE_HP_PAD_ISO_ALL_M (PMU_FORCE_HP_PAD_ISO_ALL_V << PMU_FORCE_HP_PAD_ISO_ALL_S) +#define PMU_FORCE_HP_PAD_ISO_ALL_V 0x00000001U +#define PMU_FORCE_HP_PAD_ISO_ALL_S 1 + +/** PMU_POWER_FLASH1P8_LDO_REG register + * need_des + */ +#define PMU_POWER_FLASH1P8_LDO_REG (DR_REG_PMU_BASE + 0x11c) +/** PMU_FLASH1P8_LDO_RDY : RO; bitpos: [0]; default: 1; + * need_des + */ +#define PMU_FLASH1P8_LDO_RDY (BIT(0)) +#define PMU_FLASH1P8_LDO_RDY_M (PMU_FLASH1P8_LDO_RDY_V << PMU_FLASH1P8_LDO_RDY_S) +#define PMU_FLASH1P8_LDO_RDY_V 0x00000001U +#define PMU_FLASH1P8_LDO_RDY_S 0 +/** PMU_FLASH1P8_SW_EN_XPD : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_SW_EN_XPD (BIT(1)) +#define PMU_FLASH1P8_SW_EN_XPD_M (PMU_FLASH1P8_SW_EN_XPD_V << PMU_FLASH1P8_SW_EN_XPD_S) +#define PMU_FLASH1P8_SW_EN_XPD_V 0x00000001U +#define PMU_FLASH1P8_SW_EN_XPD_S 1 +/** PMU_FLASH1P8_SW_EN_THRU : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_SW_EN_THRU (BIT(2)) +#define PMU_FLASH1P8_SW_EN_THRU_M (PMU_FLASH1P8_SW_EN_THRU_V << PMU_FLASH1P8_SW_EN_THRU_S) +#define PMU_FLASH1P8_SW_EN_THRU_V 0x00000001U +#define PMU_FLASH1P8_SW_EN_THRU_S 2 +/** PMU_FLASH1P8_SW_EN_STANDBY : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_SW_EN_STANDBY (BIT(3)) +#define PMU_FLASH1P8_SW_EN_STANDBY_M (PMU_FLASH1P8_SW_EN_STANDBY_V << PMU_FLASH1P8_SW_EN_STANDBY_S) +#define PMU_FLASH1P8_SW_EN_STANDBY_V 0x00000001U +#define PMU_FLASH1P8_SW_EN_STANDBY_S 3 +/** PMU_FLASH1P8_SW_EN_POWER_ADJUST : R/W; bitpos: [4]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_SW_EN_POWER_ADJUST (BIT(4)) +#define PMU_FLASH1P8_SW_EN_POWER_ADJUST_M (PMU_FLASH1P8_SW_EN_POWER_ADJUST_V << PMU_FLASH1P8_SW_EN_POWER_ADJUST_S) +#define PMU_FLASH1P8_SW_EN_POWER_ADJUST_V 0x00000001U +#define PMU_FLASH1P8_SW_EN_POWER_ADJUST_S 4 +/** PMU_FLASH1P8_SW_EN_ENDET : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_SW_EN_ENDET (BIT(5)) +#define PMU_FLASH1P8_SW_EN_ENDET_M (PMU_FLASH1P8_SW_EN_ENDET_V << PMU_FLASH1P8_SW_EN_ENDET_S) +#define PMU_FLASH1P8_SW_EN_ENDET_V 0x00000001U +#define PMU_FLASH1P8_SW_EN_ENDET_S 5 +/** PMU_FLASH1P8_BYPASS_LDO_RDY : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_BYPASS_LDO_RDY (BIT(22)) +#define PMU_FLASH1P8_BYPASS_LDO_RDY_M (PMU_FLASH1P8_BYPASS_LDO_RDY_V << PMU_FLASH1P8_BYPASS_LDO_RDY_S) +#define PMU_FLASH1P8_BYPASS_LDO_RDY_V 0x00000001U +#define PMU_FLASH1P8_BYPASS_LDO_RDY_S 22 +/** PMU_FLASH1P8_XPD : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_XPD (BIT(23)) +#define PMU_FLASH1P8_XPD_M (PMU_FLASH1P8_XPD_V << PMU_FLASH1P8_XPD_S) +#define PMU_FLASH1P8_XPD_V 0x00000001U +#define PMU_FLASH1P8_XPD_S 23 +/** PMU_FLASH1P8_THRU : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define PMU_FLASH1P8_THRU (BIT(24)) +#define PMU_FLASH1P8_THRU_M (PMU_FLASH1P8_THRU_V << PMU_FLASH1P8_THRU_S) +#define PMU_FLASH1P8_THRU_V 0x00000001U +#define PMU_FLASH1P8_THRU_S 24 +/** PMU_FLASH1P8_STANDBY : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_STANDBY (BIT(25)) +#define PMU_FLASH1P8_STANDBY_M (PMU_FLASH1P8_STANDBY_V << PMU_FLASH1P8_STANDBY_S) +#define PMU_FLASH1P8_STANDBY_V 0x00000001U +#define PMU_FLASH1P8_STANDBY_S 25 +/** PMU_FLASH1P8_POWER_ADJUST : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_POWER_ADJUST 0x0000000FU +#define PMU_FLASH1P8_POWER_ADJUST_M (PMU_FLASH1P8_POWER_ADJUST_V << PMU_FLASH1P8_POWER_ADJUST_S) +#define PMU_FLASH1P8_POWER_ADJUST_V 0x0000000FU +#define PMU_FLASH1P8_POWER_ADJUST_S 26 +/** PMU_FLASH1P8_ENDET : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_ENDET (BIT(31)) +#define PMU_FLASH1P8_ENDET_M (PMU_FLASH1P8_ENDET_V << PMU_FLASH1P8_ENDET_S) +#define PMU_FLASH1P8_ENDET_V 0x00000001U +#define PMU_FLASH1P8_ENDET_S 31 + +/** PMU_POWER_FLASH1P2_LDO_REG register + * need_des + */ +#define PMU_POWER_FLASH1P2_LDO_REG (DR_REG_PMU_BASE + 0x120) +/** PMU_FLASH1P2_LDO_RDY : RO; bitpos: [0]; default: 1; + * need_des + */ +#define PMU_FLASH1P2_LDO_RDY (BIT(0)) +#define PMU_FLASH1P2_LDO_RDY_M (PMU_FLASH1P2_LDO_RDY_V << PMU_FLASH1P2_LDO_RDY_S) +#define PMU_FLASH1P2_LDO_RDY_V 0x00000001U +#define PMU_FLASH1P2_LDO_RDY_S 0 +/** PMU_FLASH1P2_SW_EN_XPD : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_SW_EN_XPD (BIT(1)) +#define PMU_FLASH1P2_SW_EN_XPD_M (PMU_FLASH1P2_SW_EN_XPD_V << PMU_FLASH1P2_SW_EN_XPD_S) +#define PMU_FLASH1P2_SW_EN_XPD_V 0x00000001U +#define PMU_FLASH1P2_SW_EN_XPD_S 1 +/** PMU_FLASH1P2_SW_EN_THRU : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_SW_EN_THRU (BIT(2)) +#define PMU_FLASH1P2_SW_EN_THRU_M (PMU_FLASH1P2_SW_EN_THRU_V << PMU_FLASH1P2_SW_EN_THRU_S) +#define PMU_FLASH1P2_SW_EN_THRU_V 0x00000001U +#define PMU_FLASH1P2_SW_EN_THRU_S 2 +/** PMU_FLASH1P2_SW_EN_STANDBY : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_SW_EN_STANDBY (BIT(3)) +#define PMU_FLASH1P2_SW_EN_STANDBY_M (PMU_FLASH1P2_SW_EN_STANDBY_V << PMU_FLASH1P2_SW_EN_STANDBY_S) +#define PMU_FLASH1P2_SW_EN_STANDBY_V 0x00000001U +#define PMU_FLASH1P2_SW_EN_STANDBY_S 3 +/** PMU_FLASH1P2_SW_EN_POWER_ADJUST : R/W; bitpos: [4]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_SW_EN_POWER_ADJUST (BIT(4)) +#define PMU_FLASH1P2_SW_EN_POWER_ADJUST_M (PMU_FLASH1P2_SW_EN_POWER_ADJUST_V << PMU_FLASH1P2_SW_EN_POWER_ADJUST_S) +#define PMU_FLASH1P2_SW_EN_POWER_ADJUST_V 0x00000001U +#define PMU_FLASH1P2_SW_EN_POWER_ADJUST_S 4 +/** PMU_FLASH1P2_SW_EN_ENDET : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_SW_EN_ENDET (BIT(5)) +#define PMU_FLASH1P2_SW_EN_ENDET_M (PMU_FLASH1P2_SW_EN_ENDET_V << PMU_FLASH1P2_SW_EN_ENDET_S) +#define PMU_FLASH1P2_SW_EN_ENDET_V 0x00000001U +#define PMU_FLASH1P2_SW_EN_ENDET_S 5 +/** PMU_FLASH1P2_BYPASS_LDO_RDY : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_BYPASS_LDO_RDY (BIT(22)) +#define PMU_FLASH1P2_BYPASS_LDO_RDY_M (PMU_FLASH1P2_BYPASS_LDO_RDY_V << PMU_FLASH1P2_BYPASS_LDO_RDY_S) +#define PMU_FLASH1P2_BYPASS_LDO_RDY_V 0x00000001U +#define PMU_FLASH1P2_BYPASS_LDO_RDY_S 22 +/** PMU_FLASH1P2_XPD : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_XPD (BIT(23)) +#define PMU_FLASH1P2_XPD_M (PMU_FLASH1P2_XPD_V << PMU_FLASH1P2_XPD_S) +#define PMU_FLASH1P2_XPD_V 0x00000001U +#define PMU_FLASH1P2_XPD_S 23 +/** PMU_FLASH1P2_THRU : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define PMU_FLASH1P2_THRU (BIT(24)) +#define PMU_FLASH1P2_THRU_M (PMU_FLASH1P2_THRU_V << PMU_FLASH1P2_THRU_S) +#define PMU_FLASH1P2_THRU_V 0x00000001U +#define PMU_FLASH1P2_THRU_S 24 +/** PMU_FLASH1P2_STANDBY : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_STANDBY (BIT(25)) +#define PMU_FLASH1P2_STANDBY_M (PMU_FLASH1P2_STANDBY_V << PMU_FLASH1P2_STANDBY_S) +#define PMU_FLASH1P2_STANDBY_V 0x00000001U +#define PMU_FLASH1P2_STANDBY_S 25 +/** PMU_FLASH1P2_POWER_ADJUST : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_POWER_ADJUST 0x0000000FU +#define PMU_FLASH1P2_POWER_ADJUST_M (PMU_FLASH1P2_POWER_ADJUST_V << PMU_FLASH1P2_POWER_ADJUST_S) +#define PMU_FLASH1P2_POWER_ADJUST_V 0x0000000FU +#define PMU_FLASH1P2_POWER_ADJUST_S 26 +/** PMU_FLASH1P2_ENDET : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_ENDET (BIT(31)) +#define PMU_FLASH1P2_ENDET_M (PMU_FLASH1P2_ENDET_V << PMU_FLASH1P2_ENDET_S) +#define PMU_FLASH1P2_ENDET_V 0x00000001U +#define PMU_FLASH1P2_ENDET_S 31 + +/** PMU_POWER_VDD_FLASH_REG register + * need_des + */ +#define PMU_POWER_VDD_FLASH_REG (DR_REG_PMU_BASE + 0x124) +/** PMU_FLASH_LDO_SW_EN_TIEL : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_FLASH_LDO_SW_EN_TIEL (BIT(22)) +#define PMU_FLASH_LDO_SW_EN_TIEL_M (PMU_FLASH_LDO_SW_EN_TIEL_V << PMU_FLASH_LDO_SW_EN_TIEL_S) +#define PMU_FLASH_LDO_SW_EN_TIEL_V 0x00000001U +#define PMU_FLASH_LDO_SW_EN_TIEL_S 22 +/** PMU_FLASH_LDO_POWER_SEL : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_FLASH_LDO_POWER_SEL (BIT(23)) +#define PMU_FLASH_LDO_POWER_SEL_M (PMU_FLASH_LDO_POWER_SEL_V << PMU_FLASH_LDO_POWER_SEL_S) +#define PMU_FLASH_LDO_POWER_SEL_V 0x00000001U +#define PMU_FLASH_LDO_POWER_SEL_S 23 +/** PMU_FLASH_LDO_SW_EN_POWER_SEL : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_FLASH_LDO_SW_EN_POWER_SEL (BIT(24)) +#define PMU_FLASH_LDO_SW_EN_POWER_SEL_M (PMU_FLASH_LDO_SW_EN_POWER_SEL_V << PMU_FLASH_LDO_SW_EN_POWER_SEL_S) +#define PMU_FLASH_LDO_SW_EN_POWER_SEL_V 0x00000001U +#define PMU_FLASH_LDO_SW_EN_POWER_SEL_S 24 +/** PMU_FLASH_LDO_WAIT_TARGET : R/W; bitpos: [28:25]; default: 15; + * need_des + */ +#define PMU_FLASH_LDO_WAIT_TARGET 0x0000000FU +#define PMU_FLASH_LDO_WAIT_TARGET_M (PMU_FLASH_LDO_WAIT_TARGET_V << PMU_FLASH_LDO_WAIT_TARGET_S) +#define PMU_FLASH_LDO_WAIT_TARGET_V 0x0000000FU +#define PMU_FLASH_LDO_WAIT_TARGET_S 25 +/** PMU_FLASH_LDO_TIEL_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_FLASH_LDO_TIEL_EN (BIT(29)) +#define PMU_FLASH_LDO_TIEL_EN_M (PMU_FLASH_LDO_TIEL_EN_V << PMU_FLASH_LDO_TIEL_EN_S) +#define PMU_FLASH_LDO_TIEL_EN_V 0x00000001U +#define PMU_FLASH_LDO_TIEL_EN_S 29 +/** PMU_FLASH_LDO_TIEL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_FLASH_LDO_TIEL (BIT(30)) +#define PMU_FLASH_LDO_TIEL_M (PMU_FLASH_LDO_TIEL_V << PMU_FLASH_LDO_TIEL_S) +#define PMU_FLASH_LDO_TIEL_V 0x00000001U +#define PMU_FLASH_LDO_TIEL_S 30 +/** PMU_FLASH_LDO_SW_UPDATE : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_FLASH_LDO_SW_UPDATE (BIT(31)) +#define PMU_FLASH_LDO_SW_UPDATE_M (PMU_FLASH_LDO_SW_UPDATE_V << PMU_FLASH_LDO_SW_UPDATE_S) +#define PMU_FLASH_LDO_SW_UPDATE_V 0x00000001U +#define PMU_FLASH_LDO_SW_UPDATE_S 31 + +/** PMU_POWER_IO_LDO_REG register + * need_des + */ +#define PMU_POWER_IO_LDO_REG (DR_REG_PMU_BASE + 0x128) +/** PMU_IO_LDO_RDY : RO; bitpos: [0]; default: 1; + * need_des + */ +#define PMU_IO_LDO_RDY (BIT(0)) +#define PMU_IO_LDO_RDY_M (PMU_IO_LDO_RDY_V << PMU_IO_LDO_RDY_S) +#define PMU_IO_LDO_RDY_V 0x00000001U +#define PMU_IO_LDO_RDY_S 0 +/** PMU_IO_SW_EN_XPD : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_IO_SW_EN_XPD (BIT(1)) +#define PMU_IO_SW_EN_XPD_M (PMU_IO_SW_EN_XPD_V << PMU_IO_SW_EN_XPD_S) +#define PMU_IO_SW_EN_XPD_V 0x00000001U +#define PMU_IO_SW_EN_XPD_S 1 +/** PMU_IO_SW_EN_THRU : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define PMU_IO_SW_EN_THRU (BIT(3)) +#define PMU_IO_SW_EN_THRU_M (PMU_IO_SW_EN_THRU_V << PMU_IO_SW_EN_THRU_S) +#define PMU_IO_SW_EN_THRU_V 0x00000001U +#define PMU_IO_SW_EN_THRU_S 3 +/** PMU_IO_SW_EN_STANDBY : R/W; bitpos: [4]; default: 0; + * need_des + */ +#define PMU_IO_SW_EN_STANDBY (BIT(4)) +#define PMU_IO_SW_EN_STANDBY_M (PMU_IO_SW_EN_STANDBY_V << PMU_IO_SW_EN_STANDBY_S) +#define PMU_IO_SW_EN_STANDBY_V 0x00000001U +#define PMU_IO_SW_EN_STANDBY_S 4 +/** PMU_IO_SW_EN_POWER_ADJUST : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_IO_SW_EN_POWER_ADJUST (BIT(5)) +#define PMU_IO_SW_EN_POWER_ADJUST_M (PMU_IO_SW_EN_POWER_ADJUST_V << PMU_IO_SW_EN_POWER_ADJUST_S) +#define PMU_IO_SW_EN_POWER_ADJUST_V 0x00000001U +#define PMU_IO_SW_EN_POWER_ADJUST_S 5 +/** PMU_IO_SW_EN_ENDET : R/W; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_IO_SW_EN_ENDET (BIT(6)) +#define PMU_IO_SW_EN_ENDET_M (PMU_IO_SW_EN_ENDET_V << PMU_IO_SW_EN_ENDET_S) +#define PMU_IO_SW_EN_ENDET_V 0x00000001U +#define PMU_IO_SW_EN_ENDET_S 6 +/** PMU_IO_BYPASS_LDO_RDY : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_IO_BYPASS_LDO_RDY (BIT(22)) +#define PMU_IO_BYPASS_LDO_RDY_M (PMU_IO_BYPASS_LDO_RDY_V << PMU_IO_BYPASS_LDO_RDY_S) +#define PMU_IO_BYPASS_LDO_RDY_V 0x00000001U +#define PMU_IO_BYPASS_LDO_RDY_S 22 +/** PMU_IO_XPD : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_IO_XPD (BIT(23)) +#define PMU_IO_XPD_M (PMU_IO_XPD_V << PMU_IO_XPD_S) +#define PMU_IO_XPD_V 0x00000001U +#define PMU_IO_XPD_S 23 +/** PMU_IO_THRU : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define PMU_IO_THRU (BIT(24)) +#define PMU_IO_THRU_M (PMU_IO_THRU_V << PMU_IO_THRU_S) +#define PMU_IO_THRU_V 0x00000001U +#define PMU_IO_THRU_S 24 +/** PMU_IO_STANDBY : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_IO_STANDBY (BIT(25)) +#define PMU_IO_STANDBY_M (PMU_IO_STANDBY_V << PMU_IO_STANDBY_S) +#define PMU_IO_STANDBY_V 0x00000001U +#define PMU_IO_STANDBY_S 25 +/** PMU_IO_POWER_ADJUST : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_IO_POWER_ADJUST 0x0000000FU +#define PMU_IO_POWER_ADJUST_M (PMU_IO_POWER_ADJUST_V << PMU_IO_POWER_ADJUST_S) +#define PMU_IO_POWER_ADJUST_V 0x0000000FU +#define PMU_IO_POWER_ADJUST_S 26 +/** PMU_IO_ENDET : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_IO_ENDET (BIT(31)) +#define PMU_IO_ENDET_M (PMU_IO_ENDET_V << PMU_IO_ENDET_S) +#define PMU_IO_ENDET_V 0x00000001U +#define PMU_IO_ENDET_S 31 + +/** PMU_POWER_VDD_IO_REG register + * need_des + */ +#define PMU_POWER_VDD_IO_REG (DR_REG_PMU_BASE + 0x12c) +/** PMU_IO_LDO_POWER_SEL : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_IO_LDO_POWER_SEL (BIT(23)) +#define PMU_IO_LDO_POWER_SEL_M (PMU_IO_LDO_POWER_SEL_V << PMU_IO_LDO_POWER_SEL_S) +#define PMU_IO_LDO_POWER_SEL_V 0x00000001U +#define PMU_IO_LDO_POWER_SEL_S 23 +/** PMU_IO_LDO_SW_EN_POWER_SEL : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_IO_LDO_SW_EN_POWER_SEL (BIT(24)) +#define PMU_IO_LDO_SW_EN_POWER_SEL_M (PMU_IO_LDO_SW_EN_POWER_SEL_V << PMU_IO_LDO_SW_EN_POWER_SEL_S) +#define PMU_IO_LDO_SW_EN_POWER_SEL_V 0x00000001U +#define PMU_IO_LDO_SW_EN_POWER_SEL_S 24 + +/** PMU_POWER_CK_WAIT_CNTL_REG register + * need_des + */ +#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x130) +/** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256; + * need_des + */ +#define PMU_WAIT_XTL_STABLE 0x0000FFFFU +#define PMU_WAIT_XTL_STABLE_M (PMU_WAIT_XTL_STABLE_V << PMU_WAIT_XTL_STABLE_S) +#define PMU_WAIT_XTL_STABLE_V 0x0000FFFFU +#define PMU_WAIT_XTL_STABLE_S 0 +/** PMU_WAIT_PLL_STABLE : R/W; bitpos: [31:16]; default: 256; + * need_des + */ +#define PMU_WAIT_PLL_STABLE 0x0000FFFFU +#define PMU_WAIT_PLL_STABLE_M (PMU_WAIT_PLL_STABLE_V << PMU_WAIT_PLL_STABLE_S) +#define PMU_WAIT_PLL_STABLE_V 0x0000FFFFU +#define PMU_WAIT_PLL_STABLE_S 16 + +/** PMU_SLP_WAKEUP_CNTL0_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x134) +/** PMU_SLEEP_REQ : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLEEP_REQ (BIT(31)) +#define PMU_SLEEP_REQ_M (PMU_SLEEP_REQ_V << PMU_SLEEP_REQ_S) +#define PMU_SLEEP_REQ_V 0x00000001U +#define PMU_SLEEP_REQ_S 31 + +/** PMU_SLP_WAKEUP_CNTL1_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x138) +/** PMU_SLEEP_REJECT_ENA : R/W; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_SLEEP_REJECT_ENA 0x7FFFFFFFU +#define PMU_SLEEP_REJECT_ENA_M (PMU_SLEEP_REJECT_ENA_V << PMU_SLEEP_REJECT_ENA_S) +#define PMU_SLEEP_REJECT_ENA_V 0x7FFFFFFFU +#define PMU_SLEEP_REJECT_ENA_S 0 +/** PMU_SLP_REJECT_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLP_REJECT_EN (BIT(31)) +#define PMU_SLP_REJECT_EN_M (PMU_SLP_REJECT_EN_V << PMU_SLP_REJECT_EN_S) +#define PMU_SLP_REJECT_EN_V 0x00000001U +#define PMU_SLP_REJECT_EN_S 31 + +/** PMU_SLP_WAKEUP_CNTL2_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x13c) +/** PMU_WAKEUP_ENA : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_WAKEUP_ENA 0xFFFFFFFFU +#define PMU_WAKEUP_ENA_M (PMU_WAKEUP_ENA_V << PMU_WAKEUP_ENA_S) +#define PMU_WAKEUP_ENA_V 0xFFFFFFFFU +#define PMU_WAKEUP_ENA_S 0 + +/** PMU_SLP_WAKEUP_CNTL3_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x140) +/** PMU_LP_MIN_SLP_VAL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define PMU_LP_MIN_SLP_VAL 0x000000FFU +#define PMU_LP_MIN_SLP_VAL_M (PMU_LP_MIN_SLP_VAL_V << PMU_LP_MIN_SLP_VAL_S) +#define PMU_LP_MIN_SLP_VAL_V 0x000000FFU +#define PMU_LP_MIN_SLP_VAL_S 0 +/** PMU_HP_MIN_SLP_VAL : R/W; bitpos: [15:8]; default: 0; + * need_des + */ +#define PMU_HP_MIN_SLP_VAL 0x000000FFU +#define PMU_HP_MIN_SLP_VAL_M (PMU_HP_MIN_SLP_VAL_V << PMU_HP_MIN_SLP_VAL_S) +#define PMU_HP_MIN_SLP_VAL_V 0x000000FFU +#define PMU_HP_MIN_SLP_VAL_S 8 +/** PMU_SLEEP_PRT_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_SLEEP_PRT_SEL 0x00000003U +#define PMU_SLEEP_PRT_SEL_M (PMU_SLEEP_PRT_SEL_V << PMU_SLEEP_PRT_SEL_S) +#define PMU_SLEEP_PRT_SEL_V 0x00000003U +#define PMU_SLEEP_PRT_SEL_S 16 + +/** PMU_SLP_WAKEUP_CNTL4_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x144) +/** PMU_SLP_REJECT_CAUSE_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLP_REJECT_CAUSE_CLR (BIT(31)) +#define PMU_SLP_REJECT_CAUSE_CLR_M (PMU_SLP_REJECT_CAUSE_CLR_V << PMU_SLP_REJECT_CAUSE_CLR_S) +#define PMU_SLP_REJECT_CAUSE_CLR_V 0x00000001U +#define PMU_SLP_REJECT_CAUSE_CLR_S 31 + +/** PMU_SLP_WAKEUP_CNTL5_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x148) +/** PMU_MODEM_WAIT_TARGET : R/W; bitpos: [19:0]; default: 128; + * need_des + */ +#define PMU_MODEM_WAIT_TARGET 0x000FFFFFU +#define PMU_MODEM_WAIT_TARGET_M (PMU_MODEM_WAIT_TARGET_V << PMU_MODEM_WAIT_TARGET_S) +#define PMU_MODEM_WAIT_TARGET_V 0x000FFFFFU +#define PMU_MODEM_WAIT_TARGET_S 0 +/** PMU_LP_ANA_WAIT_TARGET : R/W; bitpos: [31:24]; default: 1; + * need_des + */ +#define PMU_LP_ANA_WAIT_TARGET 0x000000FFU +#define PMU_LP_ANA_WAIT_TARGET_M (PMU_LP_ANA_WAIT_TARGET_V << PMU_LP_ANA_WAIT_TARGET_S) +#define PMU_LP_ANA_WAIT_TARGET_V 0x000000FFU +#define PMU_LP_ANA_WAIT_TARGET_S 24 + +/** PMU_SLP_WAKEUP_CNTL6_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x14c) +/** PMU_SOC_WAKEUP_WAIT : R/W; bitpos: [19:0]; default: 128; + * need_des + */ +#define PMU_SOC_WAKEUP_WAIT 0x000FFFFFU +#define PMU_SOC_WAKEUP_WAIT_M (PMU_SOC_WAKEUP_WAIT_V << PMU_SOC_WAKEUP_WAIT_S) +#define PMU_SOC_WAKEUP_WAIT_V 0x000FFFFFU +#define PMU_SOC_WAKEUP_WAIT_S 0 +/** PMU_SOC_WAKEUP_WAIT_CFG : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_WAIT_CFG 0x00000003U +#define PMU_SOC_WAKEUP_WAIT_CFG_M (PMU_SOC_WAKEUP_WAIT_CFG_V << PMU_SOC_WAKEUP_WAIT_CFG_S) +#define PMU_SOC_WAKEUP_WAIT_CFG_V 0x00000003U +#define PMU_SOC_WAKEUP_WAIT_CFG_S 30 + +/** PMU_SLP_WAKEUP_CNTL7_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x150) +/** PMU_ANA_WAIT_CLK_SEL : R/W; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_ANA_WAIT_CLK_SEL (BIT(15)) +#define PMU_ANA_WAIT_CLK_SEL_M (PMU_ANA_WAIT_CLK_SEL_V << PMU_ANA_WAIT_CLK_SEL_S) +#define PMU_ANA_WAIT_CLK_SEL_V 0x00000001U +#define PMU_ANA_WAIT_CLK_SEL_S 15 +/** PMU_ANA_WAIT_TARGET : R/W; bitpos: [31:16]; default: 1; + * need_des + */ +#define PMU_ANA_WAIT_TARGET 0x0000FFFFU +#define PMU_ANA_WAIT_TARGET_M (PMU_ANA_WAIT_TARGET_V << PMU_ANA_WAIT_TARGET_S) +#define PMU_ANA_WAIT_TARGET_V 0x0000FFFFU +#define PMU_ANA_WAIT_TARGET_S 16 + +/** PMU_SLP_WAKEUP_STATUS0_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x154) +/** PMU_WAKEUP_CAUSE : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_WAKEUP_CAUSE 0xFFFFFFFFU +#define PMU_WAKEUP_CAUSE_M (PMU_WAKEUP_CAUSE_V << PMU_WAKEUP_CAUSE_S) +#define PMU_WAKEUP_CAUSE_V 0xFFFFFFFFU +#define PMU_WAKEUP_CAUSE_S 0 + +/** PMU_SLP_WAKEUP_STATUS1_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x158) +/** PMU_REJECT_CAUSE : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_REJECT_CAUSE 0xFFFFFFFFU +#define PMU_REJECT_CAUSE_M (PMU_REJECT_CAUSE_V << PMU_REJECT_CAUSE_S) +#define PMU_REJECT_CAUSE_V 0xFFFFFFFFU +#define PMU_REJECT_CAUSE_S 0 + +/** PMU_HP_CK_POWERON_REG register + * need_des + */ +#define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x15c) +/** PMU_I2C_POR_WAIT_TARGET : R/W; bitpos: [7:0]; default: 50; + * need_des + */ +#define PMU_I2C_POR_WAIT_TARGET 0x000000FFU +#define PMU_I2C_POR_WAIT_TARGET_M (PMU_I2C_POR_WAIT_TARGET_V << PMU_I2C_POR_WAIT_TARGET_S) +#define PMU_I2C_POR_WAIT_TARGET_V 0x000000FFU +#define PMU_I2C_POR_WAIT_TARGET_S 0 + +/** PMU_HP_CK_CNTL_REG register + * need_des + */ +#define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x160) +/** PMU_MODIFY_ICG_CNTL_WAIT : R/W; bitpos: [7:0]; default: 10; + * need_des + */ +#define PMU_MODIFY_ICG_CNTL_WAIT 0x000000FFU +#define PMU_MODIFY_ICG_CNTL_WAIT_M (PMU_MODIFY_ICG_CNTL_WAIT_V << PMU_MODIFY_ICG_CNTL_WAIT_S) +#define PMU_MODIFY_ICG_CNTL_WAIT_V 0x000000FFU +#define PMU_MODIFY_ICG_CNTL_WAIT_S 0 +/** PMU_SWITCH_ICG_CNTL_WAIT : R/W; bitpos: [15:8]; default: 10; + * need_des + */ +#define PMU_SWITCH_ICG_CNTL_WAIT 0x000000FFU +#define PMU_SWITCH_ICG_CNTL_WAIT_M (PMU_SWITCH_ICG_CNTL_WAIT_V << PMU_SWITCH_ICG_CNTL_WAIT_S) +#define PMU_SWITCH_ICG_CNTL_WAIT_V 0x000000FFU +#define PMU_SWITCH_ICG_CNTL_WAIT_S 8 + +/** PMU_POR_STATUS_REG register + * need_des + */ +#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x164) +/** PMU_POR_DONE : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_POR_DONE (BIT(31)) +#define PMU_POR_DONE_M (PMU_POR_DONE_V << PMU_POR_DONE_S) +#define PMU_POR_DONE_V 0x00000001U +#define PMU_POR_DONE_S 31 + +/** PMU_RF_PWC_REG register + * need_des + */ +#define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x168) +/** PMU_XPD_FORCE_RFTX : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_XPD_FORCE_RFTX (BIT(26)) +#define PMU_XPD_FORCE_RFTX_M (PMU_XPD_FORCE_RFTX_V << PMU_XPD_FORCE_RFTX_S) +#define PMU_XPD_FORCE_RFTX_V 0x00000001U +#define PMU_XPD_FORCE_RFTX_S 26 +/** PMU_XPD_PERIF_I2C : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define PMU_XPD_PERIF_I2C (BIT(27)) +#define PMU_XPD_PERIF_I2C_M (PMU_XPD_PERIF_I2C_V << PMU_XPD_PERIF_I2C_S) +#define PMU_XPD_PERIF_I2C_V 0x00000001U +#define PMU_XPD_PERIF_I2C_S 27 +/** PMU_XPD_RFTX_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_XPD_RFTX_I2C (BIT(28)) +#define PMU_XPD_RFTX_I2C_M (PMU_XPD_RFTX_I2C_V << PMU_XPD_RFTX_I2C_S) +#define PMU_XPD_RFTX_I2C_V 0x00000001U +#define PMU_XPD_RFTX_I2C_S 28 +/** PMU_XPD_RFRX_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_XPD_RFRX_I2C (BIT(29)) +#define PMU_XPD_RFRX_I2C_M (PMU_XPD_RFRX_I2C_V << PMU_XPD_RFRX_I2C_S) +#define PMU_XPD_RFRX_I2C_V 0x00000001U +#define PMU_XPD_RFRX_I2C_S 29 +/** PMU_XPD_RFPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_XPD_RFPLL (BIT(30)) +#define PMU_XPD_RFPLL_M (PMU_XPD_RFPLL_V << PMU_XPD_RFPLL_S) +#define PMU_XPD_RFPLL_V 0x00000001U +#define PMU_XPD_RFPLL_S 30 +/** PMU_XPD_FORCE_RFPLL : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_XPD_FORCE_RFPLL (BIT(31)) +#define PMU_XPD_FORCE_RFPLL_M (PMU_XPD_FORCE_RFPLL_V << PMU_XPD_FORCE_RFPLL_S) +#define PMU_XPD_FORCE_RFPLL_V 0x00000001U +#define PMU_XPD_FORCE_RFPLL_S 31 + +/** PMU_VDDBAT_CFG_REG register + * need_des + */ +#define PMU_VDDBAT_CFG_REG (DR_REG_PMU_BASE + 0x16c) +/** PMU_VDDBAT_MODE : RO; bitpos: [1:0]; default: 0; + * need_des + */ +#define PMU_VDDBAT_MODE 0x00000003U +#define PMU_VDDBAT_MODE_M (PMU_VDDBAT_MODE_V << PMU_VDDBAT_MODE_S) +#define PMU_VDDBAT_MODE_V 0x00000003U +#define PMU_VDDBAT_MODE_S 0 +/** PMU_VDDBAT_SW_UPDATE : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_VDDBAT_SW_UPDATE (BIT(31)) +#define PMU_VDDBAT_SW_UPDATE_M (PMU_VDDBAT_SW_UPDATE_V << PMU_VDDBAT_SW_UPDATE_S) +#define PMU_VDDBAT_SW_UPDATE_V 0x00000001U +#define PMU_VDDBAT_SW_UPDATE_S 31 + +/** PMU_BACKUP_CFG_REG register + * need_des + */ +#define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x170) +/** PMU_BACKUP_SYS_CLK_NO_DIV : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_BACKUP_SYS_CLK_NO_DIV (BIT(31)) +#define PMU_BACKUP_SYS_CLK_NO_DIV_M (PMU_BACKUP_SYS_CLK_NO_DIV_V << PMU_BACKUP_SYS_CLK_NO_DIV_S) +#define PMU_BACKUP_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_BACKUP_SYS_CLK_NO_DIV_S 31 + +/** PMU_INT_RAW_REG register + * need_des + */ +#define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x174) +/** PMU_LP_CPU_EXC_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_RAW (BIT(27)) +#define PMU_LP_CPU_EXC_INT_RAW_M (PMU_LP_CPU_EXC_INT_RAW_V << PMU_LP_CPU_EXC_INT_RAW_S) +#define PMU_LP_CPU_EXC_INT_RAW_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_RAW_S 27 +/** PMU_SDIO_IDLE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_RAW (BIT(28)) +#define PMU_SDIO_IDLE_INT_RAW_M (PMU_SDIO_IDLE_INT_RAW_V << PMU_SDIO_IDLE_INT_RAW_S) +#define PMU_SDIO_IDLE_INT_RAW_V 0x00000001U +#define PMU_SDIO_IDLE_INT_RAW_S 28 +/** PMU_SW_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_RAW (BIT(29)) +#define PMU_SW_INT_RAW_M (PMU_SW_INT_RAW_V << PMU_SW_INT_RAW_S) +#define PMU_SW_INT_RAW_V 0x00000001U +#define PMU_SW_INT_RAW_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_RAW (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_RAW_M (PMU_SOC_SLEEP_REJECT_INT_RAW_V << PMU_SOC_SLEEP_REJECT_INT_RAW_S) +#define PMU_SOC_SLEEP_REJECT_INT_RAW_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_RAW_S 30 +/** PMU_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_RAW (BIT(31)) +#define PMU_SOC_WAKEUP_INT_RAW_M (PMU_SOC_WAKEUP_INT_RAW_V << PMU_SOC_WAKEUP_INT_RAW_S) +#define PMU_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_RAW_S 31 + +/** PMU_HP_INT_ST_REG register + * need_des + */ +#define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x178) +/** PMU_LP_CPU_EXC_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_ST (BIT(27)) +#define PMU_LP_CPU_EXC_INT_ST_M (PMU_LP_CPU_EXC_INT_ST_V << PMU_LP_CPU_EXC_INT_ST_S) +#define PMU_LP_CPU_EXC_INT_ST_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_ST_S 27 +/** PMU_SDIO_IDLE_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_ST (BIT(28)) +#define PMU_SDIO_IDLE_INT_ST_M (PMU_SDIO_IDLE_INT_ST_V << PMU_SDIO_IDLE_INT_ST_S) +#define PMU_SDIO_IDLE_INT_ST_V 0x00000001U +#define PMU_SDIO_IDLE_INT_ST_S 28 +/** PMU_SW_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_ST (BIT(29)) +#define PMU_SW_INT_ST_M (PMU_SW_INT_ST_V << PMU_SW_INT_ST_S) +#define PMU_SW_INT_ST_V 0x00000001U +#define PMU_SW_INT_ST_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_ST (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_ST_M (PMU_SOC_SLEEP_REJECT_INT_ST_V << PMU_SOC_SLEEP_REJECT_INT_ST_S) +#define PMU_SOC_SLEEP_REJECT_INT_ST_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_ST_S 30 +/** PMU_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_ST (BIT(31)) +#define PMU_SOC_WAKEUP_INT_ST_M (PMU_SOC_WAKEUP_INT_ST_V << PMU_SOC_WAKEUP_INT_ST_S) +#define PMU_SOC_WAKEUP_INT_ST_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_ST_S 31 + +/** PMU_HP_INT_ENA_REG register + * need_des + */ +#define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x17c) +/** PMU_LP_CPU_EXC_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_ENA (BIT(27)) +#define PMU_LP_CPU_EXC_INT_ENA_M (PMU_LP_CPU_EXC_INT_ENA_V << PMU_LP_CPU_EXC_INT_ENA_S) +#define PMU_LP_CPU_EXC_INT_ENA_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_ENA_S 27 +/** PMU_SDIO_IDLE_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_ENA (BIT(28)) +#define PMU_SDIO_IDLE_INT_ENA_M (PMU_SDIO_IDLE_INT_ENA_V << PMU_SDIO_IDLE_INT_ENA_S) +#define PMU_SDIO_IDLE_INT_ENA_V 0x00000001U +#define PMU_SDIO_IDLE_INT_ENA_S 28 +/** PMU_SW_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_ENA (BIT(29)) +#define PMU_SW_INT_ENA_M (PMU_SW_INT_ENA_V << PMU_SW_INT_ENA_S) +#define PMU_SW_INT_ENA_V 0x00000001U +#define PMU_SW_INT_ENA_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_ENA (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_ENA_M (PMU_SOC_SLEEP_REJECT_INT_ENA_V << PMU_SOC_SLEEP_REJECT_INT_ENA_S) +#define PMU_SOC_SLEEP_REJECT_INT_ENA_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_ENA_S 30 +/** PMU_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_ENA (BIT(31)) +#define PMU_SOC_WAKEUP_INT_ENA_M (PMU_SOC_WAKEUP_INT_ENA_V << PMU_SOC_WAKEUP_INT_ENA_S) +#define PMU_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_ENA_S 31 + +/** PMU_HP_INT_CLR_REG register + * need_des + */ +#define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x180) +/** PMU_LP_CPU_EXC_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_CLR (BIT(27)) +#define PMU_LP_CPU_EXC_INT_CLR_M (PMU_LP_CPU_EXC_INT_CLR_V << PMU_LP_CPU_EXC_INT_CLR_S) +#define PMU_LP_CPU_EXC_INT_CLR_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_CLR_S 27 +/** PMU_SDIO_IDLE_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_CLR (BIT(28)) +#define PMU_SDIO_IDLE_INT_CLR_M (PMU_SDIO_IDLE_INT_CLR_V << PMU_SDIO_IDLE_INT_CLR_S) +#define PMU_SDIO_IDLE_INT_CLR_V 0x00000001U +#define PMU_SDIO_IDLE_INT_CLR_S 28 +/** PMU_SW_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_CLR (BIT(29)) +#define PMU_SW_INT_CLR_M (PMU_SW_INT_CLR_V << PMU_SW_INT_CLR_S) +#define PMU_SW_INT_CLR_V 0x00000001U +#define PMU_SW_INT_CLR_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_CLR (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_CLR_M (PMU_SOC_SLEEP_REJECT_INT_CLR_V << PMU_SOC_SLEEP_REJECT_INT_CLR_S) +#define PMU_SOC_SLEEP_REJECT_INT_CLR_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_CLR_S 30 +/** PMU_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_CLR (BIT(31)) +#define PMU_SOC_WAKEUP_INT_CLR_M (PMU_SOC_WAKEUP_INT_CLR_V << PMU_SOC_WAKEUP_INT_CLR_S) +#define PMU_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_CLR_S 31 + +/** PMU_LP_INT_RAW_REG register + * need_des + */ +#define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x184) +/** PMU_LP_CPU_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_RAW (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_RAW_M (PMU_LP_CPU_WAKEUP_INT_RAW_V << PMU_LP_CPU_WAKEUP_INT_RAW_S) +#define PMU_LP_CPU_WAKEUP_INT_RAW_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_RAW_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_M (PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_V << PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_M (PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_V << PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_M (PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_V << PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_M (PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_V << PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S 30 +/** PMU_HP_SW_TRIGGER_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_RAW (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_RAW_M (PMU_HP_SW_TRIGGER_INT_RAW_V << PMU_HP_SW_TRIGGER_INT_RAW_S) +#define PMU_HP_SW_TRIGGER_INT_RAW_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_RAW_S 31 + +/** PMU_LP_INT_ST_REG register + * need_des + */ +#define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x188) +/** PMU_LP_CPU_WAKEUP_INT_ST : RO; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_ST (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_ST_M (PMU_LP_CPU_WAKEUP_INT_ST_V << PMU_LP_CPU_WAKEUP_INT_ST_S) +#define PMU_LP_CPU_WAKEUP_INT_ST_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_ST_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_ST : RO; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_M (PMU_SLEEP_SWITCH_MODEM_END_INT_ST_V << PMU_SLEEP_SWITCH_MODEM_END_INT_ST_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_M (PMU_MODEM_SWITCH_SLEEP_END_INT_ST_V << PMU_MODEM_SWITCH_SLEEP_END_INT_ST_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_M (PMU_SLEEP_SWITCH_MODEM_START_INT_ST_V << PMU_SLEEP_SWITCH_MODEM_START_INT_ST_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_M (PMU_MODEM_SWITCH_SLEEP_START_INT_ST_V << PMU_MODEM_SWITCH_SLEEP_START_INT_ST_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S 30 +/** PMU_HP_SW_TRIGGER_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_ST (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_ST_M (PMU_HP_SW_TRIGGER_INT_ST_V << PMU_HP_SW_TRIGGER_INT_ST_S) +#define PMU_HP_SW_TRIGGER_INT_ST_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_ST_S 31 + +/** PMU_LP_INT_ENA_REG register + * need_des + */ +#define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x18c) +/** PMU_LP_CPU_WAKEUP_INT_ENA : R/W; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_ENA (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_ENA_M (PMU_LP_CPU_WAKEUP_INT_ENA_V << PMU_LP_CPU_WAKEUP_INT_ENA_S) +#define PMU_LP_CPU_WAKEUP_INT_ENA_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_ENA_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_ENA : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_M (PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_V << PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_M (PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_V << PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_M (PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_V << PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_M (PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_V << PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S 30 +/** PMU_HP_SW_TRIGGER_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_ENA (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_ENA_M (PMU_HP_SW_TRIGGER_INT_ENA_V << PMU_HP_SW_TRIGGER_INT_ENA_S) +#define PMU_HP_SW_TRIGGER_INT_ENA_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_ENA_S 31 + +/** PMU_LP_INT_CLR_REG register + * need_des + */ +#define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x190) +/** PMU_LP_CPU_WAKEUP_INT_CLR : WT; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_CLR (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_CLR_M (PMU_LP_CPU_WAKEUP_INT_CLR_V << PMU_LP_CPU_WAKEUP_INT_CLR_S) +#define PMU_LP_CPU_WAKEUP_INT_CLR_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_CLR_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_CLR : WT; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_M (PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_V << PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_M (PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_V << PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_M (PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_V << PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_M (PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_V << PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S 30 +/** PMU_HP_SW_TRIGGER_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_CLR (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_CLR_M (PMU_HP_SW_TRIGGER_INT_CLR_V << PMU_HP_SW_TRIGGER_INT_CLR_S) +#define PMU_HP_SW_TRIGGER_INT_CLR_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_CLR_S 31 + +/** PMU_LP_CPU_PWR0_REG register + * need_des + */ +#define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x194) +/** PMU_LP_CPU_WAITI_RDY : RO; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAITI_RDY (BIT(0)) +#define PMU_LP_CPU_WAITI_RDY_M (PMU_LP_CPU_WAITI_RDY_V << PMU_LP_CPU_WAITI_RDY_S) +#define PMU_LP_CPU_WAITI_RDY_V 0x00000001U +#define PMU_LP_CPU_WAITI_RDY_S 0 +/** PMU_LP_CPU_STALL_RDY : RO; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_LP_CPU_STALL_RDY (BIT(1)) +#define PMU_LP_CPU_STALL_RDY_M (PMU_LP_CPU_STALL_RDY_V << PMU_LP_CPU_STALL_RDY_S) +#define PMU_LP_CPU_STALL_RDY_V 0x00000001U +#define PMU_LP_CPU_STALL_RDY_S 1 +/** PMU_LP_CPU_FORCE_STALL : R/W; bitpos: [18]; default: 0; + * need_des + */ +#define PMU_LP_CPU_FORCE_STALL (BIT(18)) +#define PMU_LP_CPU_FORCE_STALL_M (PMU_LP_CPU_FORCE_STALL_V << PMU_LP_CPU_FORCE_STALL_S) +#define PMU_LP_CPU_FORCE_STALL_V 0x00000001U +#define PMU_LP_CPU_FORCE_STALL_S 18 +/** PMU_LP_CPU_SLP_WAITI_FLAG_EN : R/W; bitpos: [19]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN (BIT(19)) +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_M (PMU_LP_CPU_SLP_WAITI_FLAG_EN_V << PMU_LP_CPU_SLP_WAITI_FLAG_EN_S) +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_S 19 +/** PMU_LP_CPU_SLP_STALL_FLAG_EN : R/W; bitpos: [20]; default: 1; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_FLAG_EN (BIT(20)) +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_M (PMU_LP_CPU_SLP_STALL_FLAG_EN_V << PMU_LP_CPU_SLP_STALL_FLAG_EN_S) +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_S 20 +/** PMU_LP_CPU_SLP_STALL_WAIT : R/W; bitpos: [28:21]; default: 255; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_WAIT 0x000000FFU +#define PMU_LP_CPU_SLP_STALL_WAIT_M (PMU_LP_CPU_SLP_STALL_WAIT_V << PMU_LP_CPU_SLP_STALL_WAIT_S) +#define PMU_LP_CPU_SLP_STALL_WAIT_V 0x000000FFU +#define PMU_LP_CPU_SLP_STALL_WAIT_S 21 +/** PMU_LP_CPU_SLP_STALL_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_EN (BIT(29)) +#define PMU_LP_CPU_SLP_STALL_EN_M (PMU_LP_CPU_SLP_STALL_EN_V << PMU_LP_CPU_SLP_STALL_EN_S) +#define PMU_LP_CPU_SLP_STALL_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_STALL_EN_S 29 +/** PMU_LP_CPU_SLP_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_RESET_EN (BIT(30)) +#define PMU_LP_CPU_SLP_RESET_EN_M (PMU_LP_CPU_SLP_RESET_EN_V << PMU_LP_CPU_SLP_RESET_EN_S) +#define PMU_LP_CPU_SLP_RESET_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_RESET_EN_S 30 +/** PMU_LP_CPU_SLP_BYPASS_INTR_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN (BIT(31)) +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_M (PMU_LP_CPU_SLP_BYPASS_INTR_EN_V << PMU_LP_CPU_SLP_BYPASS_INTR_EN_S) +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_S 31 + +/** PMU_LP_CPU_PWR1_REG register + * need_des + */ +#define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x198) +/** PMU_LP_CPU_WAKEUP_EN : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_EN 0x0000FFFFU +#define PMU_LP_CPU_WAKEUP_EN_M (PMU_LP_CPU_WAKEUP_EN_V << PMU_LP_CPU_WAKEUP_EN_S) +#define PMU_LP_CPU_WAKEUP_EN_V 0x0000FFFFU +#define PMU_LP_CPU_WAKEUP_EN_S 0 +/** PMU_LP_CPU_SLEEP_REQ : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLEEP_REQ (BIT(31)) +#define PMU_LP_CPU_SLEEP_REQ_M (PMU_LP_CPU_SLEEP_REQ_V << PMU_LP_CPU_SLEEP_REQ_S) +#define PMU_LP_CPU_SLEEP_REQ_V 0x00000001U +#define PMU_LP_CPU_SLEEP_REQ_S 31 + +/** PMU_HP_LP_CPU_COMM_REG register + * need_des + */ +#define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x19c) +/** PMU_LP_TRIGGER_HP : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_TRIGGER_HP (BIT(30)) +#define PMU_LP_TRIGGER_HP_M (PMU_LP_TRIGGER_HP_V << PMU_LP_TRIGGER_HP_S) +#define PMU_LP_TRIGGER_HP_V 0x00000001U +#define PMU_LP_TRIGGER_HP_S 30 +/** PMU_HP_TRIGGER_LP : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_TRIGGER_LP (BIT(31)) +#define PMU_HP_TRIGGER_LP_M (PMU_HP_TRIGGER_LP_V << PMU_HP_TRIGGER_LP_S) +#define PMU_HP_TRIGGER_LP_V 0x00000001U +#define PMU_HP_TRIGGER_LP_S 31 + +/** PMU_HP_REGULATOR_CFG_REG register + * need_des + */ +#define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x1a0) +/** PMU_DIG_REGULATOR_EN_CAL : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_DIG_REGULATOR_EN_CAL (BIT(31)) +#define PMU_DIG_REGULATOR_EN_CAL_M (PMU_DIG_REGULATOR_EN_CAL_V << PMU_DIG_REGULATOR_EN_CAL_S) +#define PMU_DIG_REGULATOR_EN_CAL_V 0x00000001U +#define PMU_DIG_REGULATOR_EN_CAL_S 31 + +/** PMU_MAIN_STATE_REG register + * need_des + */ +#define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x1a4) +/** PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 256; + * need_des + */ +#define PMU_MAIN_LAST_ST_STATE 0x0000007FU +#define PMU_MAIN_LAST_ST_STATE_M (PMU_MAIN_LAST_ST_STATE_V << PMU_MAIN_LAST_ST_STATE_S) +#define PMU_MAIN_LAST_ST_STATE_V 0x0000007FU +#define PMU_MAIN_LAST_ST_STATE_S 11 +/** PMU_MAIN_TAR_ST_STATE : RO; bitpos: [24:18]; default: 4; + * need_des + */ +#define PMU_MAIN_TAR_ST_STATE 0x0000007FU +#define PMU_MAIN_TAR_ST_STATE_M (PMU_MAIN_TAR_ST_STATE_V << PMU_MAIN_TAR_ST_STATE_S) +#define PMU_MAIN_TAR_ST_STATE_V 0x0000007FU +#define PMU_MAIN_TAR_ST_STATE_S 18 +/** PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 1; + * need_des + */ +#define PMU_MAIN_CUR_ST_STATE 0x0000007FU +#define PMU_MAIN_CUR_ST_STATE_M (PMU_MAIN_CUR_ST_STATE_V << PMU_MAIN_CUR_ST_STATE_S) +#define PMU_MAIN_CUR_ST_STATE_V 0x0000007FU +#define PMU_MAIN_CUR_ST_STATE_S 25 + +/** PMU_PWR_STATE_REG register + * need_des + */ +#define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x1a8) +/** PMU_BACKUP_ST_STATE : RO; bitpos: [17:13]; default: 1; + * need_des + */ +#define PMU_BACKUP_ST_STATE 0x0000001FU +#define PMU_BACKUP_ST_STATE_M (PMU_BACKUP_ST_STATE_V << PMU_BACKUP_ST_STATE_S) +#define PMU_BACKUP_ST_STATE_V 0x0000001FU +#define PMU_BACKUP_ST_STATE_S 13 +/** PMU_LP_PWR_ST_STATE : RO; bitpos: [22:18]; default: 0; + * need_des + */ +#define PMU_LP_PWR_ST_STATE 0x0000001FU +#define PMU_LP_PWR_ST_STATE_M (PMU_LP_PWR_ST_STATE_V << PMU_LP_PWR_ST_STATE_S) +#define PMU_LP_PWR_ST_STATE_V 0x0000001FU +#define PMU_LP_PWR_ST_STATE_S 18 +/** PMU_HP_PWR_ST_STATE : RO; bitpos: [31:23]; default: 1; + * need_des + */ +#define PMU_HP_PWR_ST_STATE 0x000001FFU +#define PMU_HP_PWR_ST_STATE_M (PMU_HP_PWR_ST_STATE_V << PMU_HP_PWR_ST_STATE_S) +#define PMU_HP_PWR_ST_STATE_V 0x000001FFU +#define PMU_HP_PWR_ST_STATE_S 23 + +/** PMU_CLK_STATE0_REG register + * need_des + */ +#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x1ac) +/** PMU_STABLE_XPD_BBPLL_STATE : RO; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_STABLE_XPD_BBPLL_STATE (BIT(0)) +#define PMU_STABLE_XPD_BBPLL_STATE_M (PMU_STABLE_XPD_BBPLL_STATE_V << PMU_STABLE_XPD_BBPLL_STATE_S) +#define PMU_STABLE_XPD_BBPLL_STATE_V 0x00000001U +#define PMU_STABLE_XPD_BBPLL_STATE_S 0 +/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_STABLE_XPD_XTAL_STATE (BIT(1)) +#define PMU_STABLE_XPD_XTAL_STATE_M (PMU_STABLE_XPD_XTAL_STATE_V << PMU_STABLE_XPD_XTAL_STATE_S) +#define PMU_STABLE_XPD_XTAL_STATE_V 0x00000001U +#define PMU_STABLE_XPD_XTAL_STATE_S 1 +/** PMU_SYS_CLK_SLP_SEL_STATE : RO; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_SYS_CLK_SLP_SEL_STATE (BIT(15)) +#define PMU_SYS_CLK_SLP_SEL_STATE_M (PMU_SYS_CLK_SLP_SEL_STATE_V << PMU_SYS_CLK_SLP_SEL_STATE_S) +#define PMU_SYS_CLK_SLP_SEL_STATE_V 0x00000001U +#define PMU_SYS_CLK_SLP_SEL_STATE_S 15 +/** PMU_SYS_CLK_SEL_STATE : RO; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_SYS_CLK_SEL_STATE 0x00000003U +#define PMU_SYS_CLK_SEL_STATE_M (PMU_SYS_CLK_SEL_STATE_V << PMU_SYS_CLK_SEL_STATE_S) +#define PMU_SYS_CLK_SEL_STATE_V 0x00000003U +#define PMU_SYS_CLK_SEL_STATE_S 16 +/** PMU_SYS_CLK_NO_DIV_STATE : RO; bitpos: [18]; default: 0; + * need_des + */ +#define PMU_SYS_CLK_NO_DIV_STATE (BIT(18)) +#define PMU_SYS_CLK_NO_DIV_STATE_M (PMU_SYS_CLK_NO_DIV_STATE_V << PMU_SYS_CLK_NO_DIV_STATE_S) +#define PMU_SYS_CLK_NO_DIV_STATE_V 0x00000001U +#define PMU_SYS_CLK_NO_DIV_STATE_S 18 +/** PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [19]; default: 1; + * need_des + */ +#define PMU_ICG_SYS_CLK_EN_STATE (BIT(19)) +#define PMU_ICG_SYS_CLK_EN_STATE_M (PMU_ICG_SYS_CLK_EN_STATE_V << PMU_ICG_SYS_CLK_EN_STATE_S) +#define PMU_ICG_SYS_CLK_EN_STATE_V 0x00000001U +#define PMU_ICG_SYS_CLK_EN_STATE_S 19 +/** PMU_ICG_MODEM_SWITCH_STATE : RO; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_ICG_MODEM_SWITCH_STATE (BIT(20)) +#define PMU_ICG_MODEM_SWITCH_STATE_M (PMU_ICG_MODEM_SWITCH_STATE_V << PMU_ICG_MODEM_SWITCH_STATE_S) +#define PMU_ICG_MODEM_SWITCH_STATE_V 0x00000001U +#define PMU_ICG_MODEM_SWITCH_STATE_S 20 +/** PMU_ICG_MODEM_CODE_STATE : RO; bitpos: [22:21]; default: 0; + * need_des + */ +#define PMU_ICG_MODEM_CODE_STATE 0x00000003U +#define PMU_ICG_MODEM_CODE_STATE_M (PMU_ICG_MODEM_CODE_STATE_V << PMU_ICG_MODEM_CODE_STATE_S) +#define PMU_ICG_MODEM_CODE_STATE_V 0x00000003U +#define PMU_ICG_MODEM_CODE_STATE_S 21 +/** PMU_ICG_SLP_SEL_STATE : RO; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_ICG_SLP_SEL_STATE (BIT(23)) +#define PMU_ICG_SLP_SEL_STATE_M (PMU_ICG_SLP_SEL_STATE_V << PMU_ICG_SLP_SEL_STATE_S) +#define PMU_ICG_SLP_SEL_STATE_V 0x00000001U +#define PMU_ICG_SLP_SEL_STATE_S 23 +/** PMU_ICG_GLOBAL_XTAL_STATE : RO; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_ICG_GLOBAL_XTAL_STATE (BIT(24)) +#define PMU_ICG_GLOBAL_XTAL_STATE_M (PMU_ICG_GLOBAL_XTAL_STATE_V << PMU_ICG_GLOBAL_XTAL_STATE_S) +#define PMU_ICG_GLOBAL_XTAL_STATE_V 0x00000001U +#define PMU_ICG_GLOBAL_XTAL_STATE_S 24 +/** PMU_ICG_GLOBAL_PLL_STATE : RO; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ICG_GLOBAL_PLL_STATE (BIT(25)) +#define PMU_ICG_GLOBAL_PLL_STATE_M (PMU_ICG_GLOBAL_PLL_STATE_V << PMU_ICG_GLOBAL_PLL_STATE_S) +#define PMU_ICG_GLOBAL_PLL_STATE_V 0x00000001U +#define PMU_ICG_GLOBAL_PLL_STATE_S 25 +/** PMU_ANA_I2C_ISO_EN_STATE : RO; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_ANA_I2C_ISO_EN_STATE (BIT(26)) +#define PMU_ANA_I2C_ISO_EN_STATE_M (PMU_ANA_I2C_ISO_EN_STATE_V << PMU_ANA_I2C_ISO_EN_STATE_S) +#define PMU_ANA_I2C_ISO_EN_STATE_V 0x00000001U +#define PMU_ANA_I2C_ISO_EN_STATE_S 26 +/** PMU_ANA_I2C_RETENTION_STATE : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_ANA_I2C_RETENTION_STATE (BIT(27)) +#define PMU_ANA_I2C_RETENTION_STATE_M (PMU_ANA_I2C_RETENTION_STATE_V << PMU_ANA_I2C_RETENTION_STATE_S) +#define PMU_ANA_I2C_RETENTION_STATE_V 0x00000001U +#define PMU_ANA_I2C_RETENTION_STATE_S 27 +/** PMU_ANA_XPD_BB_I2C_STATE : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_BB_I2C_STATE (BIT(28)) +#define PMU_ANA_XPD_BB_I2C_STATE_M (PMU_ANA_XPD_BB_I2C_STATE_V << PMU_ANA_XPD_BB_I2C_STATE_S) +#define PMU_ANA_XPD_BB_I2C_STATE_V 0x00000001U +#define PMU_ANA_XPD_BB_I2C_STATE_S 28 +/** PMU_ANA_XPD_BBPLL_I2C_STATE : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_BBPLL_I2C_STATE (BIT(29)) +#define PMU_ANA_XPD_BBPLL_I2C_STATE_M (PMU_ANA_XPD_BBPLL_I2C_STATE_V << PMU_ANA_XPD_BBPLL_I2C_STATE_S) +#define PMU_ANA_XPD_BBPLL_I2C_STATE_V 0x00000001U +#define PMU_ANA_XPD_BBPLL_I2C_STATE_S 29 +/** PMU_ANA_XPD_BBPLL_STATE : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_BBPLL_STATE (BIT(30)) +#define PMU_ANA_XPD_BBPLL_STATE_M (PMU_ANA_XPD_BBPLL_STATE_V << PMU_ANA_XPD_BBPLL_STATE_S) +#define PMU_ANA_XPD_BBPLL_STATE_V 0x00000001U +#define PMU_ANA_XPD_BBPLL_STATE_S 30 +/** PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_ANA_XPD_XTAL_STATE (BIT(31)) +#define PMU_ANA_XPD_XTAL_STATE_M (PMU_ANA_XPD_XTAL_STATE_V << PMU_ANA_XPD_XTAL_STATE_S) +#define PMU_ANA_XPD_XTAL_STATE_V 0x00000001U +#define PMU_ANA_XPD_XTAL_STATE_S 31 + +/** PMU_CLK_STATE1_REG register + * need_des + */ +#define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x1b0) +/** PMU_ICG_FUNC_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_ICG_FUNC_EN_STATE 0xFFFFFFFFU +#define PMU_ICG_FUNC_EN_STATE_M (PMU_ICG_FUNC_EN_STATE_V << PMU_ICG_FUNC_EN_STATE_S) +#define PMU_ICG_FUNC_EN_STATE_V 0xFFFFFFFFU +#define PMU_ICG_FUNC_EN_STATE_S 0 + +/** PMU_CLK_STATE2_REG register + * need_des + */ +#define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x1b4) +/** PMU_ICG_APB_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_ICG_APB_EN_STATE 0xFFFFFFFFU +#define PMU_ICG_APB_EN_STATE_M (PMU_ICG_APB_EN_STATE_V << PMU_ICG_APB_EN_STATE_S) +#define PMU_ICG_APB_EN_STATE_V 0xFFFFFFFFU +#define PMU_ICG_APB_EN_STATE_S 0 + +/** PMU_DCM_CTRL_REG register + * need_des + */ +#define PMU_DCM_CTRL_REG (DR_REG_PMU_BASE + 0x1b8) +/** PMU_DSFMOS_USE_POR : R/W; bitpos: [0]; default: 1; + * need_des + */ +#define PMU_DSFMOS_USE_POR (BIT(0)) +#define PMU_DSFMOS_USE_POR_M (PMU_DSFMOS_USE_POR_V << PMU_DSFMOS_USE_POR_S) +#define PMU_DSFMOS_USE_POR_V 0x00000001U +#define PMU_DSFMOS_USE_POR_S 0 +/** PMU_DCDC_DCM_UPDATE : WT; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_DCDC_DCM_UPDATE (BIT(22)) +#define PMU_DCDC_DCM_UPDATE_M (PMU_DCDC_DCM_UPDATE_V << PMU_DCDC_DCM_UPDATE_S) +#define PMU_DCDC_DCM_UPDATE_V 0x00000001U +#define PMU_DCDC_DCM_UPDATE_S 22 +/** PMU_DCDC_PCUR_LIMIT : R/W; bitpos: [25:23]; default: 1; + * need_des + */ +#define PMU_DCDC_PCUR_LIMIT 0x00000007U +#define PMU_DCDC_PCUR_LIMIT_M (PMU_DCDC_PCUR_LIMIT_V << PMU_DCDC_PCUR_LIMIT_S) +#define PMU_DCDC_PCUR_LIMIT_V 0x00000007U +#define PMU_DCDC_PCUR_LIMIT_S 23 +/** PMU_DCDC_BIAS_CAL_DONE : RO; bitpos: [26]; default: 1; + * need_des + */ +#define PMU_DCDC_BIAS_CAL_DONE (BIT(26)) +#define PMU_DCDC_BIAS_CAL_DONE_M (PMU_DCDC_BIAS_CAL_DONE_V << PMU_DCDC_BIAS_CAL_DONE_S) +#define PMU_DCDC_BIAS_CAL_DONE_V 0x00000001U +#define PMU_DCDC_BIAS_CAL_DONE_S 26 +/** PMU_DCDC_CCM_SW_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_DCDC_CCM_SW_EN (BIT(27)) +#define PMU_DCDC_CCM_SW_EN_M (PMU_DCDC_CCM_SW_EN_V << PMU_DCDC_CCM_SW_EN_S) +#define PMU_DCDC_CCM_SW_EN_V 0x00000001U +#define PMU_DCDC_CCM_SW_EN_S 27 +/** PMU_DCDC_VCM_ENB : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_DCDC_VCM_ENB (BIT(28)) +#define PMU_DCDC_VCM_ENB_M (PMU_DCDC_VCM_ENB_V << PMU_DCDC_VCM_ENB_S) +#define PMU_DCDC_VCM_ENB_V 0x00000001U +#define PMU_DCDC_VCM_ENB_S 28 +/** PMU_DCDC_CCM_RDY : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_DCDC_CCM_RDY (BIT(29)) +#define PMU_DCDC_CCM_RDY_M (PMU_DCDC_CCM_RDY_V << PMU_DCDC_CCM_RDY_S) +#define PMU_DCDC_CCM_RDY_V 0x00000001U +#define PMU_DCDC_CCM_RDY_S 29 +/** PMU_DCDC_VCM_RDY : RO; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_DCDC_VCM_RDY (BIT(30)) +#define PMU_DCDC_VCM_RDY_M (PMU_DCDC_VCM_RDY_V << PMU_DCDC_VCM_RDY_S) +#define PMU_DCDC_VCM_RDY_V 0x00000001U +#define PMU_DCDC_VCM_RDY_S 30 +/** PMU_DCDC_RDY_CLR : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_DCDC_RDY_CLR (BIT(31)) +#define PMU_DCDC_RDY_CLR_M (PMU_DCDC_RDY_CLR_V << PMU_DCDC_RDY_CLR_S) +#define PMU_DCDC_RDY_CLR_V 0x00000001U +#define PMU_DCDC_RDY_CLR_S 31 + +/** PMU_DCM_BOOST_CTRL_REG register + * need_des + */ +#define PMU_DCM_BOOST_CTRL_REG (DR_REG_PMU_BASE + 0x1bc) +/** PMU_DCDC_BOOST_CCM_CTRLEN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_DCDC_BOOST_CCM_CTRLEN (BIT(24)) +#define PMU_DCDC_BOOST_CCM_CTRLEN_M (PMU_DCDC_BOOST_CCM_CTRLEN_V << PMU_DCDC_BOOST_CCM_CTRLEN_S) +#define PMU_DCDC_BOOST_CCM_CTRLEN_V 0x00000001U +#define PMU_DCDC_BOOST_CCM_CTRLEN_S 24 +/** PMU_DCDC_BOOST_CCM_ENB : R/W; bitpos: [25]; default: 1; + * need_des + */ +#define PMU_DCDC_BOOST_CCM_ENB (BIT(25)) +#define PMU_DCDC_BOOST_CCM_ENB_M (PMU_DCDC_BOOST_CCM_ENB_V << PMU_DCDC_BOOST_CCM_ENB_S) +#define PMU_DCDC_BOOST_CCM_ENB_V 0x00000001U +#define PMU_DCDC_BOOST_CCM_ENB_S 25 +/** PMU_DCDC_BOOST_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_DCDC_BOOST_EN (BIT(26)) +#define PMU_DCDC_BOOST_EN_M (PMU_DCDC_BOOST_EN_V << PMU_DCDC_BOOST_EN_S) +#define PMU_DCDC_BOOST_EN_V 0x00000001U +#define PMU_DCDC_BOOST_EN_S 26 +/** PMU_DCDC_BOOST_DREG : R/W; bitpos: [31:27]; default: 23; + * need_des + */ +#define PMU_DCDC_BOOST_DREG 0x0000001FU +#define PMU_DCDC_BOOST_DREG_M (PMU_DCDC_BOOST_DREG_V << PMU_DCDC_BOOST_DREG_S) +#define PMU_DCDC_BOOST_DREG_V 0x0000001FU +#define PMU_DCDC_BOOST_DREG_S 27 + +/** PMU_TOUCH_PWR_CTRL_REG register + * need_des + */ +#define PMU_TOUCH_PWR_CTRL_REG (DR_REG_PMU_BASE + 0x1c0) +/** PMU_TOUCH_SLEEP_CYCLES : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define PMU_TOUCH_SLEEP_CYCLES 0x0000FFFFU +#define PMU_TOUCH_SLEEP_CYCLES_M (PMU_TOUCH_SLEEP_CYCLES_V << PMU_TOUCH_SLEEP_CYCLES_S) +#define PMU_TOUCH_SLEEP_CYCLES_V 0x0000FFFFU +#define PMU_TOUCH_SLEEP_CYCLES_S 0 +/** PMU_TOUCH_WAIT_CYCLES : R/W; bitpos: [29:21]; default: 0; + * need_des + */ +#define PMU_TOUCH_WAIT_CYCLES 0x000001FFU +#define PMU_TOUCH_WAIT_CYCLES_M (PMU_TOUCH_WAIT_CYCLES_V << PMU_TOUCH_WAIT_CYCLES_S) +#define PMU_TOUCH_WAIT_CYCLES_V 0x000001FFU +#define PMU_TOUCH_WAIT_CYCLES_S 21 +/** PMU_TOUCH_SLEEP_TIMER_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TOUCH_SLEEP_TIMER_EN (BIT(30)) +#define PMU_TOUCH_SLEEP_TIMER_EN_M (PMU_TOUCH_SLEEP_TIMER_EN_V << PMU_TOUCH_SLEEP_TIMER_EN_S) +#define PMU_TOUCH_SLEEP_TIMER_EN_V 0x00000001U +#define PMU_TOUCH_SLEEP_TIMER_EN_S 30 +/** PMU_TOUCH_FORCE_DONE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TOUCH_FORCE_DONE (BIT(31)) +#define PMU_TOUCH_FORCE_DONE_M (PMU_TOUCH_FORCE_DONE_V << PMU_TOUCH_FORCE_DONE_S) +#define PMU_TOUCH_FORCE_DONE_V 0x00000001U +#define PMU_TOUCH_FORCE_DONE_S 31 + +/** PMU_DATE_REG register + * need_des + */ +#define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc) +/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 37818464; + * need_des + */ +#define PMU_PMU_DATE 0x7FFFFFFFU +#define PMU_PMU_DATE_M (PMU_PMU_DATE_V << PMU_PMU_DATE_S) +#define PMU_PMU_DATE_V 0x7FFFFFFFU +#define PMU_PMU_DATE_S 0 +/** PMU_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_CLK_EN (BIT(31)) +#define PMU_CLK_EN_M (PMU_CLK_EN_V << PMU_CLK_EN_S) +#define PMU_CLK_EN_V 0x00000001U +#define PMU_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/pmu_struct.h b/components/soc/esp32h4/register/hw_ver_beta5/soc/pmu_struct.h similarity index 100% rename from components/soc/esp32h4/register/soc/pmu_struct.h rename to components/soc/esp32h4/register/hw_ver_beta5/soc/pmu_struct.h diff --git a/components/soc/esp32h4/register/hw_ver_mp/soc/interrupt_matrix_reg.h b/components/soc/esp32h4/register/hw_ver_mp/soc/interrupt_matrix_reg.h index 3271b064d8..3d569560d7 100644 --- a/components/soc/esp32h4/register/hw_ver_mp/soc/interrupt_matrix_reg.h +++ b/components/soc/esp32h4/register/hw_ver_mp/soc/interrupt_matrix_reg.h @@ -10,10 +10,12 @@ extern "C" { #endif +#define DR_REG_INTERRUPT_BASE(i) (DR_REG_INTMTX0_BASE + (i) * 0x1000) + /** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG register * WIFI_MAC_INTR mapping register */ -#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0) +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x0) /** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -32,7 +34,7 @@ extern "C" { /** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG register * WIFI_MAC_NMI mapping register */ -#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4) +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x4) /** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -51,7 +53,7 @@ extern "C" { /** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG register * WIFI_PWR_INTR mapping register */ -#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8) +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x8) /** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -70,7 +72,7 @@ extern "C" { /** INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG register * WIFI_BB_INTR mapping register */ -#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc) +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xc) /** INTERRUPT_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -89,7 +91,7 @@ extern "C" { /** INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG register * BT_MAC_INTR mapping register */ -#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10) +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x10) /** INTERRUPT_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -108,7 +110,7 @@ extern "C" { /** INTERRUPT_CORE0_BT_BB_INTR_MAP_REG register * BT_BB_INTR mapping register */ -#define INTERRUPT_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14) +#define INTERRUPT_CORE0_BT_BB_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x14) /** INTERRUPT_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -127,7 +129,7 @@ extern "C" { /** INTERRUPT_CORE0_BT_BB_NMI_MAP_REG register * BT_BB_NMI mapping register */ -#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18) +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x18) /** INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -146,7 +148,7 @@ extern "C" { /** INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG register * LP_TIMER_INTR mapping register */ -#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c) +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x1c) /** INTERRUPT_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -165,7 +167,7 @@ extern "C" { /** INTERRUPT_CORE0_COEX_INTR_MAP_REG register * COEX_INTR mapping register */ -#define INTERRUPT_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20) +#define INTERRUPT_CORE0_COEX_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x20) /** INTERRUPT_CORE0_COEX_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -184,7 +186,7 @@ extern "C" { /** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG register * BLE_TIMER_INTR mapping register */ -#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24) +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x24) /** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -203,7 +205,7 @@ extern "C" { /** INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG register * BLE_SEC_INTR mapping register */ -#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28) +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x28) /** INTERRUPT_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -222,7 +224,7 @@ extern "C" { /** INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG register * I2C_MST_INTR mapping register */ -#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c) +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x2c) /** INTERRUPT_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -241,7 +243,7 @@ extern "C" { /** INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG register * ZB_MAC_INTR mapping register */ -#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30) +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x30) /** INTERRUPT_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -260,7 +262,7 @@ extern "C" { /** INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_REG register * MODEM_APB_TIMEOUT_INTR mapping register */ -#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34) +#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x34) /** INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -279,7 +281,7 @@ extern "C" { /** INTERRUPT_CORE0_BT_MAC_INT1_MAP_REG register * BT_MAC_INT1 mapping register */ -#define INTERRUPT_CORE0_BT_MAC_INT1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38) +#define INTERRUPT_CORE0_BT_MAC_INT1_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x38) /** INTERRUPT_CORE0_BT_MAC_INT1_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -298,7 +300,7 @@ extern "C" { /** INTERRUPT_CORE0_PMU_INTR_MAP_REG register * PMU_INTR mapping register */ -#define INTERRUPT_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3c) +#define INTERRUPT_CORE0_PMU_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x3c) /** INTERRUPT_CORE0_PMU_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -317,7 +319,7 @@ extern "C" { /** INTERRUPT_CORE0_EFUSE_INTR_MAP_REG register * EFUSE_INTR mapping register */ -#define INTERRUPT_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40) +#define INTERRUPT_CORE0_EFUSE_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x40) /** INTERRUPT_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -336,7 +338,7 @@ extern "C" { /** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG register * LP_RTC_TIMER_INTR mapping register */ -#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44) +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x44) /** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -355,7 +357,7 @@ extern "C" { /** INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_REG register * LP_RTC_BLE_TIMER_INTR mapping register */ -#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48) +#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x48) /** INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -374,7 +376,7 @@ extern "C" { /** INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG register * LP_WDT_INTR mapping register */ -#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4c) +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x4c) /** INTERRUPT_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -393,7 +395,7 @@ extern "C" { /** INTERRUPT_CORE0_TOUCH_INTR_MAP_REG register * TOUCH_INTR mapping register */ -#define INTERRUPT_CORE0_TOUCH_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50) +#define INTERRUPT_CORE0_TOUCH_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x50) /** INTERRUPT_CORE0_TOUCH_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -412,7 +414,7 @@ extern "C" { /** INTERRUPT_CORE0_HUK_INTR_MAP_REG register * HUK_INTR mapping register */ -#define INTERRUPT_CORE0_HUK_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54) +#define INTERRUPT_CORE0_HUK_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x54) /** INTERRUPT_CORE0_HUK_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -431,7 +433,7 @@ extern "C" { /** INTERRUPT_CORE0_LP_PERI_PMS_INTR_MAP_REG register * LP_PERI_PMS_INTR mapping register */ -#define INTERRUPT_CORE0_LP_PERI_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58) +#define INTERRUPT_CORE0_LP_PERI_PMS_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x58) /** INTERRUPT_CORE0_LP_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -450,7 +452,7 @@ extern "C" { /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register * CPU_INTR_FROM_CPU_0 mapping register */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5c) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x5c) /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -469,7 +471,7 @@ extern "C" { /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register * CPU_INTR_FROM_CPU_1 mapping register */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x60) /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -488,7 +490,7 @@ extern "C" { /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register * CPU_INTR_FROM_CPU_2 mapping register */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x64) /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -507,7 +509,7 @@ extern "C" { /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register * CPU_INTR_FROM_CPU_3 mapping register */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x68) /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -526,7 +528,7 @@ extern "C" { /** INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_REG register * BUS_MONITOR_INTR mapping register */ -#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c) +#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x6c) /** INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -545,7 +547,7 @@ extern "C" { /** INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_REG register * CORE0_TRACE_INTR mapping register */ -#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70) +#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x70) /** INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -564,7 +566,7 @@ extern "C" { /** INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_REG register * CORE1_TRACE_INTR mapping register */ -#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74) +#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x74) /** INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -583,7 +585,7 @@ extern "C" { /** INTERRUPT_CORE0_CACHE_INTR_MAP_REG register * CACHE_INTR mapping register */ -#define INTERRUPT_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78) +#define INTERRUPT_CORE0_CACHE_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x78) /** INTERRUPT_CORE0_CACHE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -602,7 +604,7 @@ extern "C" { /** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register * CPU_PERI_TIMEOUT_INTR mapping register */ -#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7c) +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x7c) /** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -621,7 +623,7 @@ extern "C" { /** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register * GPIO_INTERRUPT_PRO mapping register */ -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x80) /** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -640,7 +642,7 @@ extern "C" { /** INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_REG register * GPIO_INTERRUPT_2 mapping register */ -#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x84) /** INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -659,7 +661,7 @@ extern "C" { /** INTERRUPT_CORE0_PAU_INTR_MAP_REG register * PAU_INTR mapping register */ -#define INTERRUPT_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88) +#define INTERRUPT_CORE0_PAU_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x88) /** INTERRUPT_CORE0_PAU_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -678,7 +680,7 @@ extern "C" { /** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register * HP_PERI_TIMEOUT_INTR mapping register */ -#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c) +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x8c) /** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -697,7 +699,7 @@ extern "C" { /** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG register * HP_APM_M0_INTR mapping register */ -#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90) +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x90) /** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -716,7 +718,7 @@ extern "C" { /** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG register * HP_APM_M1_INTR mapping register */ -#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94) +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x94) /** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -735,7 +737,7 @@ extern "C" { /** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG register * HP_APM_M2_INTR mapping register */ -#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98) +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x98) /** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -754,7 +756,7 @@ extern "C" { /** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG register * HP_APM_M3_INTR mapping register */ -#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c) +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x9c) /** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -773,7 +775,7 @@ extern "C" { /** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG register * HP_APM_M4_INTR mapping register */ -#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0) +#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xa0) /** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -792,7 +794,7 @@ extern "C" { /** INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_REG register * HP_MEM_APM_M0_INTR mapping register */ -#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa4) +#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xa4) /** INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -811,7 +813,7 @@ extern "C" { /** INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_REG register * HP_MEM_APM_M1_INTR mapping register */ -#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa8) +#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xa8) /** INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -830,7 +832,7 @@ extern "C" { /** INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_REG register * HP_MEM_APM_M2_INTR mapping register */ -#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac) +#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xac) /** INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -849,7 +851,7 @@ extern "C" { /** INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_REG register * HP_MEM_APM_M3_INTR mapping register */ -#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb0) +#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xb0) /** INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -868,7 +870,7 @@ extern "C" { /** INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG register * CPU_APM_M0_INTR mapping register */ -#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb4) +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xb4) /** INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -887,7 +889,7 @@ extern "C" { /** INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG register * CPU_APM_M1_INTR mapping register */ -#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb8) +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xb8) /** INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -906,7 +908,7 @@ extern "C" { /** INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_REG register * CPU_APM_M2_INTR mapping register */ -#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xbc) +#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xbc) /** INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -925,7 +927,7 @@ extern "C" { /** INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_REG register * CPU_APM_M3_INTR mapping register */ -#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0) +#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xc0) /** INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -944,7 +946,7 @@ extern "C" { /** INTERRUPT_CORE0_HP_PERI_PMS_INTR_MAP_REG register * HP_PERI_PMS_INTR mapping register */ -#define INTERRUPT_CORE0_HP_PERI_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4) +#define INTERRUPT_CORE0_HP_PERI_PMS_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xc4) /** INTERRUPT_CORE0_HP_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -963,7 +965,7 @@ extern "C" { /** INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_MAP_REG register * MODEM_PERI_PMS_INTR mapping register */ -#define INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8) +#define INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xc8) /** INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -982,7 +984,7 @@ extern "C" { /** INTERRUPT_CORE0_CPU_PERI_PMS_INTR_MAP_REG register * CPU_PERI_PMS_INTR mapping register */ -#define INTERRUPT_CORE0_CPU_PERI_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc) +#define INTERRUPT_CORE0_CPU_PERI_PMS_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xcc) /** INTERRUPT_CORE0_CPU_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1001,7 +1003,7 @@ extern "C" { /** INTERRUPT_CORE0_MSPI_INTR_MAP_REG register * MSPI_INTR mapping register */ -#define INTERRUPT_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0) +#define INTERRUPT_CORE0_MSPI_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xd0) /** INTERRUPT_CORE0_MSPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1020,7 +1022,7 @@ extern "C" { /** INTERRUPT_CORE0_I2S_INTR_MAP_REG register * I2S_INTR mapping register */ -#define INTERRUPT_CORE0_I2S_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4) +#define INTERRUPT_CORE0_I2S_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xd4) /** INTERRUPT_CORE0_I2S_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1039,7 +1041,7 @@ extern "C" { /** INTERRUPT_CORE0_UHCI0_INTR_MAP_REG register * UHCI0_INTR mapping register */ -#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8) +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xd8) /** INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1058,7 +1060,7 @@ extern "C" { /** INTERRUPT_CORE0_UART0_INTR_MAP_REG register * UART0_INTR mapping register */ -#define INTERRUPT_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc) +#define INTERRUPT_CORE0_UART0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xdc) /** INTERRUPT_CORE0_UART0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1077,7 +1079,7 @@ extern "C" { /** INTERRUPT_CORE0_UART1_INTR_MAP_REG register * UART1_INTR mapping register */ -#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0) +#define INTERRUPT_CORE0_UART1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xe0) /** INTERRUPT_CORE0_UART1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1096,7 +1098,7 @@ extern "C" { /** INTERRUPT_CORE0_LEDC_INTR_MAP_REG register * LEDC_INTR mapping register */ -#define INTERRUPT_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4) +#define INTERRUPT_CORE0_LEDC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xe4) /** INTERRUPT_CORE0_LEDC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1115,7 +1117,7 @@ extern "C" { /** INTERRUPT_CORE0_CAN0_INTR_MAP_REG register * CAN0_INTR mapping register */ -#define INTERRUPT_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe8) +#define INTERRUPT_CORE0_CAN0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xe8) /** INTERRUPT_CORE0_CAN0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1134,7 +1136,7 @@ extern "C" { /** INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_REG register * CAN0_TIMER_INTR mapping register */ -#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xec) +#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xec) /** INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1153,7 +1155,7 @@ extern "C" { /** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG register * USB_SERIAL_JTAG_INTR mapping register */ -#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf0) +#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xf0) /** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1172,7 +1174,7 @@ extern "C" { /** INTERRUPT_CORE0_RMT_INTR_MAP_REG register * RMT_INTR mapping register */ -#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf4) +#define INTERRUPT_CORE0_RMT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xf4) /** INTERRUPT_CORE0_RMT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1191,7 +1193,7 @@ extern "C" { /** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG register * I2C_EXT0_INTR mapping register */ -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf8) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xf8) /** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1210,7 +1212,7 @@ extern "C" { /** INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_REG register * I2C_EXT1_INTR mapping register */ -#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xfc) +#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xfc) /** INTERRUPT_CORE0_I2C_EXT1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1229,7 +1231,7 @@ extern "C" { /** INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG register * TG0_T0_INTR mapping register */ -#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x100) /** INTERRUPT_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1248,7 +1250,7 @@ extern "C" { /** INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG register * TG0_WDT_INTR mapping register */ -#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104) +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x104) /** INTERRUPT_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1267,7 +1269,7 @@ extern "C" { /** INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG register * TG1_T0_INTR mapping register */ -#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108) +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x108) /** INTERRUPT_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1286,7 +1288,7 @@ extern "C" { /** INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG register * TG1_WDT_INTR mapping register */ -#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10c) +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x10c) /** INTERRUPT_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1305,7 +1307,7 @@ extern "C" { /** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register * SYSTIMER_TARGET0_INTR mapping register */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x110) /** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1324,7 +1326,7 @@ extern "C" { /** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register * SYSTIMER_TARGET1_INTR mapping register */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x114) /** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1343,7 +1345,7 @@ extern "C" { /** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register * SYSTIMER_TARGET2_INTR mapping register */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x118) /** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1362,7 +1364,7 @@ extern "C" { /** INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG register * APB_ADC_INTR mapping register */ -#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11c) +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x11c) /** INTERRUPT_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1381,7 +1383,7 @@ extern "C" { /** INTERRUPT_CORE0_PWM0_INTR_MAP_REG register * PWM0_INTR mapping register */ -#define INTERRUPT_CORE0_PWM0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120) +#define INTERRUPT_CORE0_PWM0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x120) /** INTERRUPT_CORE0_PWM0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1400,7 +1402,7 @@ extern "C" { /** INTERRUPT_CORE0_PWM1_INTR_MAP_REG register * PWM1_INTR mapping register */ -#define INTERRUPT_CORE0_PWM1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124) +#define INTERRUPT_CORE0_PWM1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x124) /** INTERRUPT_CORE0_PWM1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1419,7 +1421,7 @@ extern "C" { /** INTERRUPT_CORE0_PCNT_INTR_MAP_REG register * PCNT_INTR mapping register */ -#define INTERRUPT_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128) +#define INTERRUPT_CORE0_PCNT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x128) /** INTERRUPT_CORE0_PCNT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1438,7 +1440,7 @@ extern "C" { /** INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG register * PARL_IO_TX_INTR mapping register */ -#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12c) +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x12c) /** INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1457,7 +1459,7 @@ extern "C" { /** INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG register * PARL_IO_RX_INTR mapping register */ -#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130) +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x130) /** INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1476,7 +1478,7 @@ extern "C" { /** INTERRUPT_CORE0_USB_OTG11_INTR_MAP_REG register * USB_OTG11_INTR mapping register */ -#define INTERRUPT_CORE0_USB_OTG11_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134) +#define INTERRUPT_CORE0_USB_OTG11_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x134) /** INTERRUPT_CORE0_USB_OTG11_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1495,7 +1497,7 @@ extern "C" { /** INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_REG register * ASRC_CHNL0_INTR mapping register */ -#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138) +#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x138) /** INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1514,7 +1516,7 @@ extern "C" { /** INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_REG register * ASRC_CHNL1_INTR mapping register */ -#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13c) +#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x13c) /** INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1533,7 +1535,7 @@ extern "C" { /** INTERRUPT_CORE0_ZERO_DET_INTR_MAP_REG register * ZERO_DET_INTR mapping register */ -#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140) +#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x140) /** INTERRUPT_CORE0_ZERO_DET_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1552,7 +1554,7 @@ extern "C" { /** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG register * DMA_IN_CH0_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144) +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x144) /** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1571,7 +1573,7 @@ extern "C" { /** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG register * DMA_IN_CH1_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148) +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x148) /** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1590,7 +1592,7 @@ extern "C" { /** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG register * DMA_IN_CH2_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14c) +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x14c) /** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1609,7 +1611,7 @@ extern "C" { /** INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_REG register * DMA_IN_CH3_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150) +#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x150) /** INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1628,7 +1630,7 @@ extern "C" { /** INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_REG register * DMA_IN_CH4_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154) +#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x154) /** INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1647,7 +1649,7 @@ extern "C" { /** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG register * DMA_OUT_CH0_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158) +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x158) /** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1666,7 +1668,7 @@ extern "C" { /** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG register * DMA_OUT_CH1_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15c) +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x15c) /** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1685,7 +1687,7 @@ extern "C" { /** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG register * DMA_OUT_CH2_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160) +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x160) /** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1704,7 +1706,7 @@ extern "C" { /** INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_REG register * DMA_OUT_CH3_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164) +#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x164) /** INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1723,7 +1725,7 @@ extern "C" { /** INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_REG register * DMA_OUT_CH4_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168) +#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x168) /** INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1742,7 +1744,7 @@ extern "C" { /** INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG register * GPSPI2_INTR mapping register */ -#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16c) +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x16c) /** INTERRUPT_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1761,7 +1763,7 @@ extern "C" { /** INTERRUPT_CORE0_GPSPI3_INTR_MAP_REG register * GPSPI3_INTR mapping register */ -#define INTERRUPT_CORE0_GPSPI3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170) +#define INTERRUPT_CORE0_GPSPI3_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x170) /** INTERRUPT_CORE0_GPSPI3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1780,7 +1782,7 @@ extern "C" { /** INTERRUPT_CORE0_AES_INTR_MAP_REG register * AES_INTR mapping register */ -#define INTERRUPT_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174) +#define INTERRUPT_CORE0_AES_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x174) /** INTERRUPT_CORE0_AES_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1799,7 +1801,7 @@ extern "C" { /** INTERRUPT_CORE0_SHA_INTR_MAP_REG register * SHA_INTR mapping register */ -#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178) +#define INTERRUPT_CORE0_SHA_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x178) /** INTERRUPT_CORE0_SHA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1818,7 +1820,7 @@ extern "C" { /** INTERRUPT_CORE0_ECC_INTR_MAP_REG register * ECC_INTR mapping register */ -#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17c) +#define INTERRUPT_CORE0_ECC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x17c) /** INTERRUPT_CORE0_ECC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1837,7 +1839,7 @@ extern "C" { /** INTERRUPT_CORE0_ECDSA_INTR_MAP_REG register * ECDSA_INTR mapping register */ -#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180) +#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x180) /** INTERRUPT_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1856,7 +1858,7 @@ extern "C" { /** INTERRUPT_CORE0_KM_INTR_MAP_REG register * KM_INTR mapping register */ -#define INTERRUPT_CORE0_KM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184) +#define INTERRUPT_CORE0_KM_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x184) /** INTERRUPT_CORE0_KM_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -1875,7 +1877,7 @@ extern "C" { /** INTERRUPT_CORE0_INT_STATUS_REG_0_REG register * Status register for interrupt sources 0 ~ 31 */ -#define INTERRUPT_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188) +#define INTERRUPT_CORE0_INT_STATUS_REG_0_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x188) /** INTERRUPT_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0; * Represents the status of the interrupt sources within interrupt-index-range 0 ~ 31. * Each bit corresponds to one interrupt source @@ -1890,7 +1892,7 @@ extern "C" { /** INTERRUPT_CORE0_INT_STATUS_REG_1_REG register * Status register for interrupt sources 32 ~ 63 */ -#define INTERRUPT_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18c) +#define INTERRUPT_CORE0_INT_STATUS_REG_1_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x18c) /** INTERRUPT_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0; * Represents the status of the interrupt sources within interrupt-index-range 32 ~ * 63. Each bit corresponds to one interrupt source @@ -1905,7 +1907,7 @@ extern "C" { /** INTERRUPT_CORE0_INT_STATUS_REG_2_REG register * Status register for interrupt sources 64 ~ 95 */ -#define INTERRUPT_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190) +#define INTERRUPT_CORE0_INT_STATUS_REG_2_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x190) /** INTERRUPT_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0; * Represents the status of the interrupt sources within interrupt-index-range 64 ~ * 95. Each bit corresponds to one interrupt source @@ -1920,7 +1922,7 @@ extern "C" { /** INTERRUPT_CORE0_INT_STATUS_REG_3_REG register * Status register for interrupt sources 96 ~ 97 */ -#define INTERRUPT_CORE0_INT_STATUS_REG_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194) +#define INTERRUPT_CORE0_INT_STATUS_REG_3_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x194) /** INTERRUPT_CORE0_INT_STATUS_3 : RO; bitpos: [1:0]; default: 0; * Represents the status of the interrupt sources within interrupt-index-range 96 ~ * 97. Each bit corresponds to one interrupt source @@ -1935,7 +1937,7 @@ extern "C" { /** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_0_REG register * PASS_IN_SEC status register for interrupt sources 0 ~ 31 */ -#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x198) +#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_0_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x198) /** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0 : RO; bitpos: [31:0]; default: 0; * Represents the PASS_IN_SEC status of the interrupt sources within * interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source @@ -1950,7 +1952,7 @@ extern "C" { /** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_1_REG register * PASS_IN_SEC status register for interrupt sources 32 ~ 63 */ -#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x19c) +#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_1_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x19c) /** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1 : RO; bitpos: [31:0]; default: 0; * Represents the PASS_IN_SEC status of the interrupt sources within * interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source @@ -1965,7 +1967,7 @@ extern "C" { /** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_2_REG register * PASS_IN_SEC status register for interrupt sources 64 ~ 95 */ -#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a0) +#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_2_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x1a0) /** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2 : RO; bitpos: [31:0]; default: 0; * Represents the PASS_IN_SEC status of the interrupt sources within * interrupt-index-range 64 ~ 95. Each bit corresponds to one interrupt source @@ -1980,7 +1982,7 @@ extern "C" { /** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_3_REG register * PASS_IN_SEC status register for interrupt sources 96 ~ 97 */ -#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a4) +#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_3_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x1a4) /** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_3 : RO; bitpos: [1:0]; default: 0; * Represents the PASS_IN_SEC status of the interrupt sources with * interrupt-index-range 96 ~ 97. Each bit corresponds to one interrupt source @@ -1995,7 +1997,7 @@ extern "C" { /** INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG register * reserved */ -#define INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a8) +#define INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x1a8) /** INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC : R/W; bitpos: [5:0]; default: 0; * reserved */ @@ -2007,7 +2009,7 @@ extern "C" { /** INTERRUPT_CORE0_SECURE_STATUS_REG register * reserved */ -#define INTERRUPT_CORE0_SECURE_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1ac) +#define INTERRUPT_CORE0_SECURE_STATUS_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x1ac) /** INTERRUPT_CORE0_INT_SECURE_STATUS : RO; bitpos: [31:0]; default: 0; * reserved */ @@ -2019,7 +2021,7 @@ extern "C" { /** INTERRUPT_CORE0_CLOCK_GATE_REG register * Interrupt clock gating configure register */ -#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b0) +#define INTERRUPT_CORE0_CLOCK_GATE_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x1b0) /** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 0; * Interrupt clock gating configure register */ @@ -2031,7 +2033,7 @@ extern "C" { /** INTERRUPT_CORE0_INTERRUPT_DATE_REG register * Version control register */ -#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7fc) +#define INTERRUPT_CORE0_INTERRUPT_DATE_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x7fc) /** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 38813760; * Version control register */ diff --git a/components/soc/esp32h4/register/soc/pmu_reg.h b/components/soc/esp32h4/register/hw_ver_mp/soc/pmu_reg.h similarity index 100% rename from components/soc/esp32h4/register/soc/pmu_reg.h rename to components/soc/esp32h4/register/hw_ver_mp/soc/pmu_reg.h diff --git a/components/soc/esp32h4/register/hw_ver_mp/soc/pmu_struct.h b/components/soc/esp32h4/register/hw_ver_mp/soc/pmu_struct.h new file mode 100644 index 0000000000..59b5ccdd2b --- /dev/null +++ b/components/soc/esp32h4/register/hw_ver_mp/soc/pmu_struct.h @@ -0,0 +1,929 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef union { + struct { + uint32_t reserved0 : 18; + uint32_t vdd_flash_mode: 4; + uint32_t mem_dslp : 1; + uint32_t mem_pd_en : 4; + uint32_t wifi_pd_en : 1; + uint32_t peri_pd_en : 1; + uint32_t cpu_pd_en : 1; + uint32_t aon_pd_en : 1; + uint32_t top_pd_en : 1; + }; + uint32_t val; +} pmu_hp_dig_power_reg_t; + +typedef union { + struct { + uint32_t reserved0: 30; + uint32_t code : 2; + }; + uint32_t val; +} pmu_hp_icg_modem_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 24; + uint32_t uart_wakeup_en : 1; + uint32_t lp_pad_hold_all: 1; + uint32_t hp_pad_hold_all: 1; + uint32_t dig_pad_slp_sel: 1; + uint32_t dig_pause_wdt : 1; + uint32_t dig_cpu_stall : 1; + uint32_t reserved1 : 2; + }; + uint32_t val; +} pmu_hp_sys_cntl_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 26; + uint32_t i2c_iso_en : 1; + uint32_t i2c_retention: 1; + uint32_t xpd_bb_i2c : 1; + uint32_t xpd_bbpll_i2c: 1; + uint32_t xpd_bbpll : 1; + uint32_t reserved1 : 1; + }; + uint32_t val; +} pmu_hp_clk_power_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 9; + uint32_t dcdc_ccm_enb : 1; + uint32_t dcdc_clear_rdy : 1; + uint32_t dig_reg_dpcur_bias: 2; + uint32_t dig_reg_dsfmos : 4; + uint32_t dcm_vset : 5; + uint32_t dcm_mode : 2; + uint32_t xpd_trx : 1; + uint32_t xpd_bias : 1; + uint32_t reserved1 : 3; + uint32_t discnnt_dig_rtc : 1; + uint32_t pd_cur : 1; + uint32_t bias_sleep : 1; + }; + uint32_t val; +} pmu_hp_bias_reg_t; + +typedef union { + struct { /* HP: Active State */ + uint32_t reserved0 : 4; + uint32_t hp_sleep2active_backup_modem_clk_code: 2; + uint32_t hp_modem2active_backup_modem_clk_code: 2; + uint32_t reserved1 : 6; + uint32_t hp_sleep2active_backup_clk_sel : 2; + uint32_t hp_modem2active_backup_clk_sel : 2; + uint32_t hp_sleep2active_backup_mode : 5; + uint32_t hp_modem2active_backup_mode : 5; + uint32_t reserved3 : 1; + uint32_t hp_sleep2active_backup_en : 1; + uint32_t hp_modem2active_backup_en : 1; + uint32_t reserved4 : 1; + }; + struct { /* HP: Modem State */ + uint32_t reserved5 : 4; + uint32_t hp_sleep2modem_backup_modem_clk_code : 2; + uint32_t reserved6 : 8; + uint32_t hp_sleep2modem_backup_clk_sel : 2; + uint32_t reserved8 : 4; + uint32_t hp_sleep2modem_backup_mode : 5; + uint32_t reserved9 : 4; + uint32_t hp_sleep2modem_backup_en : 1; + uint32_t reserved10 : 2; + }; + struct { /* HP: Sleep State */ + uint32_t reserved11 : 6; + uint32_t hp_modem2sleep_backup_modem_clk_code : 2; + uint32_t hp_active2sleep_backup_modem_clk_code: 2; + uint32_t reserved12 : 6; + uint32_t hp_modem2sleep_backup_clk_sel : 2; + uint32_t hp_active2sleep_backup_clk_sel : 2; + uint32_t hp_modem2sleep_backup_mode : 5; + uint32_t hp_active2sleep_backup_mode : 5; + uint32_t hp_modem2sleep_backup_en : 1; + uint32_t hp_active2sleep_backup_en : 1; + }; + uint32_t val; +} pmu_hp_backup_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 26; + uint32_t dig_sysclk_nodiv: 1; + uint32_t icg_sysclk_en : 1; + uint32_t sysclk_slp_sel : 1; + uint32_t icg_slp_sel : 1; + uint32_t dig_sysclk_sel : 2; + }; + uint32_t val; +} pmu_hp_sysclk_reg_t; + +typedef union { + struct { + uint32_t power_det_bypass: 1; + uint32_t reserved0 : 3; + uint32_t lp_dbias_vol : 5; /* Only HP_ACTIVE mode under hp system is valid */ + uint32_t hp_dbias_vol : 5; /* Only HP_ACTIVE mode under hp system is valid */ + uint32_t dbias_sel : 1; /* Only HP_ACTIVE mode under hp system is valid */ + uint32_t dbias_init : 1; /* Only HP_ACTIVE mode under hp system is valid */ + uint32_t slp_mem_xpd : 1; + uint32_t slp_logic_xpd : 1; + uint32_t xpd : 1; + uint32_t slp_mem_dbias : 4; + uint32_t slp_logic_dbias : 4; + uint32_t dbias : 5; + }; + uint32_t val; +} pmu_hp_regulator0_reg_t; + +typedef union { + struct { + uint32_t reserved0: 8; + uint32_t drv_b : 24; + }; + uint32_t val; +} pmu_hp_regulator1_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 30; + uint32_t xpd_xtalx2: 1; + uint32_t xpd_xtal : 1; + }; + uint32_t val; +} pmu_hp_xtal_reg_t; + +typedef struct pmu_hp_hw_regmap { + pmu_hp_dig_power_reg_t dig_power; + uint32_t icg_func; + uint32_t icg_apb; + pmu_hp_icg_modem_reg_t icg_modem; + pmu_hp_sys_cntl_reg_t syscntl; + pmu_hp_clk_power_reg_t clk_power; + pmu_hp_bias_reg_t bias; + pmu_hp_backup_reg_t backup; + uint32_t backup_clk; + pmu_hp_sysclk_reg_t sysclk; + pmu_hp_regulator0_reg_t regulator0; + pmu_hp_regulator1_reg_t regulator1; + pmu_hp_xtal_reg_t xtal; +} pmu_hp_hw_regmap_t; + +typedef union { + struct { + uint32_t reserved0: 21; + uint32_t slp_xpd : 1; + uint32_t xpd : 1; + uint32_t slp_dbias: 4; + uint32_t dbias : 5; + }; + uint32_t val; +} pmu_lp_regulator0_reg_t; + +typedef union { + struct { + uint32_t reserved0: 28; + uint32_t drv_b : 4; + }; + uint32_t val; +} pmu_lp_regulator1_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 30; + uint32_t xpd_xtalx2: 1; + uint32_t xpd_xtal : 1; + }; + uint32_t val; +} pmu_lp_xtal_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 23; + uint32_t vdd_io_mode : 4; + uint32_t bod_source_sel: 1; + uint32_t vddbat_mode : 2; + uint32_t mem_dslp : 1; + uint32_t peri_pd_en : 1; + }; + uint32_t val; +} pmu_lp_dig_power_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 27; + uint32_t xpd_lppll : 1; + uint32_t xpd_xtal32k: 1; + uint32_t xpd_rc32k : 1; + uint32_t xpd_fosc : 1; + uint32_t pd_osc : 1; + }; + uint32_t val; +} pmu_lp_clk_power_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 9; + uint32_t dcdc_ccm_enb : 1; + uint32_t dcdc_clear_rdy : 1; + uint32_t dig_reg_dpcur_bias: 2; + uint32_t dig_reg_dsfmos : 4; + uint32_t dcm_vset : 5; + uint32_t dcm_mode : 2; + uint32_t reserved1 : 1; + uint32_t xpd_bias : 1; + uint32_t reserved2 : 3; + uint32_t discnnt_dig_rtc : 1; + uint32_t pd_cur : 1; + uint32_t bias_sleep : 1; + }; + uint32_t val; +} pmu_lp_bias_reg_t; + +typedef struct pmu_lp_hw_regmap { + pmu_lp_regulator0_reg_t regulator0; + pmu_lp_regulator1_reg_t regulator1; + pmu_lp_xtal_reg_t xtal; /* Only LP_SLEEP mode under lp system, xtal is valid */ + pmu_lp_dig_power_reg_t dig_power; + pmu_lp_clk_power_reg_t clk_power; + pmu_lp_bias_reg_t bias; /* Only LP_SLEEP mode under lp system, bias is valid */ +} pmu_lp_hw_regmap_t; + +typedef union { + struct { + uint32_t tie_low_global_bbpll_icg : 1; + uint32_t tie_low_global_xtal_icg : 1; + uint32_t tie_low_i2c_retention : 1; + uint32_t tie_low_xpd_bb_i2c : 1; + uint32_t tie_low_xpd_bbpll_i2c : 1; + uint32_t tie_low_xpd_bbpll : 1; + uint32_t tie_low_xpd_xtal : 1; + uint32_t tie_low_global_xtalx2_icg : 1; + uint32_t tie_low_xpd_xtalx2 : 1; + uint32_t reserved0 : 14; + uint32_t tie_high_xtalx2 : 1; + uint32_t tie_high_global_xtalx2_icg: 1; + uint32_t tie_high_global_bbpll_icg : 1; + uint32_t tie_high_global_xtal_icg : 1; + uint32_t tie_high_i2c_retention : 1; + uint32_t tie_high_xpd_bb_i2c : 1; + uint32_t tie_high_xpd_bbpll_i2c : 1; + uint32_t tie_high_xpd_bbpll : 1; + uint32_t tie_high_xpd_xtal : 1; + }; + uint32_t val; +} pmu_imm_hp_clk_power_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 28; + uint32_t update_dig_icg_switch: 1; + uint32_t tie_low_icg_slp_sel : 1; + uint32_t tie_high_icg_slp_sel : 1; + uint32_t update_dig_sysclk_sel: 1; + }; + uint32_t val; +} pmu_imm_sleep_sysclk_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 31; + uint32_t update_dig_icg_func_en: 1; + }; + uint32_t val; +} pmu_imm_hp_func_icg_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 31; + uint32_t update_dig_icg_apb_en: 1; + }; + uint32_t val; +} pmu_imm_hp_apb_icg_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 31; + uint32_t update_dig_icg_modem_en: 1; + }; + uint32_t val; +} pmu_imm_modem_icg_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 30; + uint32_t tie_low_lp_rootclk_sel : 1; + uint32_t tie_high_lp_rootclk_sel: 1; + }; + uint32_t val; +} pmu_imm_lp_icg_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 26; + uint32_t tie_high_dig_pad_slp_sel: 1; + uint32_t tie_low_dig_pad_slp_sel : 1; + uint32_t tie_high_lp_pad_hold_all: 1; + uint32_t tie_low_lp_pad_hold_all : 1; + uint32_t tie_high_hp_pad_hold_all: 1; + uint32_t tie_low_hp_pad_hold_all : 1; + }; + uint32_t val; +} pmu_imm_pad_hold_all_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 30; + uint32_t tie_high_i2c_iso_en: 1; + uint32_t tie_low_i2c_iso_en : 1; + }; + uint32_t val; +} pmu_imm_i2c_isolate_reg_t; + +typedef struct pmu_imm_hw_regmap { + pmu_imm_hp_clk_power_reg_t clk_power; + pmu_imm_sleep_sysclk_reg_t sleep_sysclk; + pmu_imm_hp_func_icg_reg_t hp_func_icg; + pmu_imm_hp_apb_icg_reg_t hp_apb_icg; + pmu_imm_modem_icg_reg_t modem_icg; + pmu_imm_lp_icg_reg_t lp_icg; + pmu_imm_pad_hold_all_reg_t pad_hold_all; + pmu_imm_i2c_isolate_reg_t i2c_iso; +} pmu_imm_hw_regmap_t; + +typedef union { + struct { + uint32_t reserved0 : 5; + uint32_t hp_powerdown_timer: 9; + uint32_t hp_powerup_timer : 9; + uint32_t hp_wait_timer : 9; + }; + uint32_t val; +} pmu_power_wait_timer0_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 9; + uint32_t lp_powerdown_timer: 7; + uint32_t lp_powerup_timer : 7; + uint32_t lp_wait_timer : 9; + }; + uint32_t val; +} pmu_power_wait_timer1_reg_t; + +typedef union { + struct { + uint32_t lp_iso_wait_timer: 8; + uint32_t lp_rst_wait_timer: 8; + uint32_t hp_iso_wait_timer: 8; + uint32_t hp_rst_wait_timer: 8; + }; + uint32_t val; +} pmu_power_wait_timer2_reg_t; + +typedef union { + struct { + uint32_t force_reset : 1; + uint32_t force_iso : 1; + uint32_t force_pu : 1; + uint32_t force_no_reset: 1; + uint32_t force_no_iso : 1; + uint32_t force_pd : 1; + uint32_t mask : 5; /* Invalid of lp peripherals */ + uint32_t reserved0 : 16; /* Invalid of lp peripherals */ + uint32_t pd_mask : 5; /* Invalid of lp peripherals */ + }; + uint32_t val; +} pmu_power_domain_cntl_reg_t; + +typedef union { + struct { + uint32_t force_hp_mem_iso : 4; + uint32_t force_hp_mem_pd : 4; + uint32_t reserved0 : 16; + uint32_t force_hp_mem_no_iso: 4; + uint32_t force_hp_mem_pu : 4; + }; + uint32_t val; +} pmu_power_memory_cntl_reg_t; + +typedef union { + struct { + uint32_t mem2_pd_mask : 5; + uint32_t mem1_pd_mask : 5; + uint32_t mem0_pd_mask : 5; + uint32_t reserved0 : 2; + uint32_t mem2_mask : 5; + uint32_t mem1_mask : 5; + uint32_t mem0_mask : 5; + }; + uint32_t val; +} pmu_power_memory_mask_reg_t; + +typedef union { + struct { + uint32_t force_hp_pad_no_iso_all: 1; + uint32_t force_hp_pad_iso_all : 1; + uint32_t reserved0 : 30; + }; + uint32_t val; +} pmu_power_hp_pad_reg_t; + +typedef union { + struct { + uint32_t ldo_rdy : 1; + uint32_t sw_en_xpd : 1; + uint32_t sw_en_thru : 1; + uint32_t sw_en_standby : 1; + uint32_t sw_en_power_adjust: 1; + uint32_t sw_en_endet : 1; + uint32_t reserved0 : 16; + uint32_t bypass_ldo_rdy : 1; + uint32_t xpd : 1; + uint32_t thru : 1; + uint32_t standby : 1; + uint32_t power_adjust : 4; + uint32_t reserved1 : 1; + uint32_t endet : 1; + }; + uint32_t val; +} pmu_power_flash_ldo_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 22; + uint32_t ldo_sw_en_tiel : 1; + uint32_t ldo_power_sel : 1; + uint32_t ldo_sw_en_power_sel: 1; + uint32_t ldo_wait_target : 4; + uint32_t ldo_tiel_en : 1; + uint32_t ldo_tiel : 1; + uint32_t ldo_sw_update : 1; + }; + uint32_t val; +} pmu_power_vdd_flash_reg_t; + +typedef union { + struct { + uint32_t ldo_rdy : 1; + uint32_t sw_en_xpd : 1; + uint32_t reserved0 : 1; + uint32_t sw_en_thru : 1; + uint32_t sw_en_standby : 1; + uint32_t sw_en_power_adjust: 1; + uint32_t sw_en_endet : 1; + uint32_t reserved1 : 15; + uint32_t bypass_ldo_rdy : 1; + uint32_t xpd : 1; + uint32_t thru : 1; + uint32_t standby : 1; + uint32_t power_adjust : 4; + uint32_t reserved2 : 1; + uint32_t endet : 1; + }; + uint32_t val; +} pmu_power_io_ldo_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 23; + uint32_t ldo_power_sel : 1; + uint32_t ldo_sw_en_power_sel: 1; + uint32_t reserved1 : 7; + }; + uint32_t val; +} pmu_power_vdd_io_reg_t; + +typedef union { + struct { + uint32_t wait_xtal_stable: 16; + uint32_t wait_pll_stable : 16; + }; + uint32_t val; +} pmu_power_clk_wait_cntl_reg_t; + +typedef struct pmu_power_hw_regmap { + pmu_power_wait_timer0_reg_t wait_timer0; + pmu_power_wait_timer1_reg_t wait_timer1; + pmu_power_wait_timer2_reg_t wait_timer2; + pmu_power_domain_cntl_reg_t hp_pd[5]; /* Include TOP, HPAON, HPCPU, HPPERI and MODEM power domain */ + pmu_power_domain_cntl_reg_t lp_peri; + pmu_power_memory_cntl_reg_t mem_cntl; + pmu_power_memory_mask_reg_t mem_mask; + pmu_power_hp_pad_reg_t hp_pad; + pmu_power_flash_ldo_reg_t flash_ldo[2]; /* Include Flash 1p8 and 1p2 LDO */ + pmu_power_vdd_flash_reg_t vdd_flash; + pmu_power_io_ldo_reg_t io_ldo; + pmu_power_vdd_io_reg_t vdd_io; + pmu_power_clk_wait_cntl_reg_t clk_wait; +} pmu_power_hw_regmap_t; + +typedef union { + struct { + uint32_t reserved0: 31; + uint32_t sleep_req: 1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl0_reg_t; + +typedef union { + struct { + uint32_t sleep_reject_ena: 31; + uint32_t slp_reject_en : 1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl1_reg_t; + +typedef union { + struct { + uint32_t lp_min_slp_val: 8; + uint32_t hp_min_slp_val: 8; + uint32_t sleep_prt_sel : 2; + uint32_t reserved0 : 14; + }; + uint32_t val; +} pmu_slp_wakeup_cntl3_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 31; + uint32_t slp_reject_cause_clr: 1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl4_reg_t; + +typedef union { + struct { + uint32_t modem_wait_target : 20; + uint32_t reserved0 : 4; + uint32_t lp_ana_wait_target: 8; + }; + uint32_t val; +} pmu_slp_wakeup_cntl5_reg_t; + +typedef union { + struct { + uint32_t soc_wakeup_wait : 20; + uint32_t reserved0 : 10; + uint32_t soc_wakeup_wait_cfg: 2; + }; + uint32_t val; +} pmu_slp_wakeup_cntl6_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 15; + uint32_t ana_wait_clk_sel: 1; + uint32_t ana_wait_target : 16; + }; + uint32_t val; +} pmu_slp_wakeup_cntl7_reg_t; + +typedef union { + struct { + uint32_t wakeup_cause: 32; + }; + uint32_t val; +} pmu_slp_wakeup_status0_reg_t; + +typedef union { + struct { + uint32_t reject_cause: 32; + }; + uint32_t val; +} pmu_slp_wakeup_status1_reg_t; + +typedef struct pmu_wakeup_hw_regmap { + pmu_slp_wakeup_cntl0_reg_t cntl0; + pmu_slp_wakeup_cntl1_reg_t cntl1; + uint32_t cntl2; + pmu_slp_wakeup_cntl3_reg_t cntl3; + pmu_slp_wakeup_cntl4_reg_t cntl4; + pmu_slp_wakeup_cntl5_reg_t cntl5; + pmu_slp_wakeup_cntl6_reg_t cntl6; + pmu_slp_wakeup_cntl7_reg_t cntl7; + pmu_slp_wakeup_status0_reg_t status0; + pmu_slp_wakeup_status1_reg_t status1; +} pmu_wakeup_hw_regmap_t; + +typedef union { + struct { + uint32_t i2c_por_wait_target: 8; + uint32_t reserved0 : 24; + }; + uint32_t val; +} pmu_hp_clk_poweron_reg_t; + +typedef union { + struct { + uint32_t modify_icg_cntl_wait: 8; + uint32_t switch_icg_cntl_wait: 8; + uint32_t reserved0 : 16; + }; + uint32_t val; +} pmu_hp_clk_cntl_reg_t; + +typedef union { + struct { + uint32_t reserved0: 31; + uint32_t por_done : 1; + }; + uint32_t val; +} pmu_por_status_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 26; + uint32_t xpd_force_rftx : 1; + uint32_t xpd_perif_i2c : 1; + uint32_t xpd_rftx_i2c : 1; + uint32_t xpd_rfrx_i2c : 1; + uint32_t xpd_rfpll : 1; + uint32_t xpd_force_rfpll: 1; + }; + uint32_t val; +} pmu_rf_pwc_reg_t; + +typedef union { + struct { + uint32_t vddbat_mode : 2; + uint32_t reserved0 : 29; + uint32_t vddbat_sw_update: 1; + }; + uint32_t val; +} pmu_vddbat_cfg_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 31; + uint32_t backup_sysclk_nodiv: 1; + }; + uint32_t val; +} pmu_backup_cfg_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 27; + uint32_t lp_cpu_exc : 1; + uint32_t sdio_idle : 1; + uint32_t sw : 1; + uint32_t soc_sleep_reject: 1; + uint32_t soc_wakeup : 1; + }; + uint32_t val; +} pmu_hp_intr_reg_t; + +typedef struct pmu_hp_ext_hw_regmap { + pmu_hp_clk_poweron_reg_t clk_poweron; + pmu_hp_clk_cntl_reg_t clk_cntl; + pmu_por_status_reg_t por_status; + pmu_rf_pwc_reg_t rf_pwc; + pmu_vddbat_cfg_reg_t vddbat_cfg; + pmu_backup_cfg_reg_t backup_cfg; + pmu_hp_intr_reg_t int_raw; + pmu_hp_intr_reg_t int_st; + pmu_hp_intr_reg_t int_ena; + pmu_hp_intr_reg_t int_clr; +} pmu_hp_ext_hw_regmap_t; + +typedef union { + struct { + uint32_t reserved0 : 20; + uint32_t lp_cpu_wakeup : 1; + uint32_t modem_switch_active_end : 1; + uint32_t sleep_switch_active_end : 1; + uint32_t sleep_switch_modem_end : 1; + uint32_t modem_switch_sleep_end : 1; + uint32_t active_switch_sleep_end : 1; + uint32_t modem_switch_active_start: 1; + uint32_t sleep_switch_active_start: 1; + uint32_t sleep_switch_modem_start : 1; + uint32_t modem_switch_sleep_start : 1; + uint32_t active_switch_sleep_start: 1; + uint32_t hp_sw_trigger : 1; + }; + uint32_t val; +} pmu_lp_intr_reg_t; + +typedef union { + struct { + uint32_t waiti_rdy : 1; + uint32_t stall_rdy : 1; + uint32_t reserved0 : 16; + uint32_t force_stall : 1; + uint32_t slp_waiti_flag_en : 1; + uint32_t slp_stall_flag_en : 1; + uint32_t slp_stall_wait : 8; + uint32_t slp_stall_en : 1; + uint32_t slp_reset_en : 1; + uint32_t slp_bypass_intr_en: 1; + }; + uint32_t val; +} pmu_lp_cpu_pwr0_reg_t; + +typedef union { + struct { + uint32_t wakeup_en: 16; + uint32_t reserved0: 15; + uint32_t sleep_req: 1; + }; + uint32_t val; +} pmu_lp_cpu_pwr1_reg_t; + +typedef struct pmu_lp_ext_hw_regmap { + pmu_lp_intr_reg_t int_raw; + pmu_lp_intr_reg_t int_st; + pmu_lp_intr_reg_t int_ena; + pmu_lp_intr_reg_t int_clr; + pmu_lp_cpu_pwr0_reg_t pwr0; + pmu_lp_cpu_pwr1_reg_t pwr1; +} pmu_lp_ext_hw_regmap_t; + + +typedef union { + struct { + uint32_t reserved0 : 30; + uint32_t lp_trigger_hp: 1; + uint32_t hp_trigger_lp: 1; + }; + uint32_t val; +} pmu_hp_lp_cpu_comm_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 31; + uint32_t dig_regulator_en_cal: 1; + }; + uint32_t val; +} pmu_hp_regulator_cfg_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 11; + uint32_t main_last_st_state: 7; + uint32_t main_tar_st_state : 7; + uint32_t main_cur_st_state : 7; + }; + uint32_t val; +} pmu_main_state_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 13; + uint32_t backup_st_state: 5; + uint32_t lp_pwr_st_state: 5; + uint32_t hp_pwr_st_state: 9; + }; + uint32_t val; +} pmu_pwr_state_reg_t; + +typedef union { + struct { + uint32_t stable_xpd_bbpll_state : 1; + uint32_t stable_xpd_xtal_state : 1; + uint32_t reserved0 : 13; + uint32_t sysclk_slp_sel_state : 1; + uint32_t sysclk_sel_state : 2; + uint32_t sysclk_nodiv_state : 1; + uint32_t icg_sysclk_en_state : 1; + uint32_t icg_modem_switch_state : 1; + uint32_t icg_modem_code_state : 2; + uint32_t icg_slp_sel_state : 1; + uint32_t icg_global_xtal_state : 1; + uint32_t icg_global_pll_state : 1; + uint32_t ana_i2c_iso_en_state : 1; + uint32_t ana_i2c_retention_state: 1; + uint32_t ana_xpd_bb_i2c_state : 1; + uint32_t ana_xpd_bbpll_i2c_state: 1; + uint32_t ana_xpd_bbpll_state : 1; + uint32_t ana_xpd_xtal_state : 1; + }; + uint32_t val; +} pmu_clk_state0_reg_t; + +typedef union { + struct { + uint32_t icg_func_en_state: 32; + }; + uint32_t val; +} pmu_clk_state1_reg_t; + +typedef union { + struct { + uint32_t icg_apb_en_state: 32; + }; + uint32_t val; +} pmu_clk_state2_reg_t; + +typedef union { + struct { + uint32_t dsfmos_use_por : 1; + uint32_t reserved0 : 21; + uint32_t dcdc_dcm_update : 1; + uint32_t dcdc_pcur_limit : 3; + uint32_t dcdc_bias_cal_done: 1; + uint32_t dcdc_ccm_sw_en : 1; + uint32_t dcdc_vcm_enb : 1; + uint32_t dcdc_ccm_rdy : 1; + uint32_t dcdc_vcm_rdy : 1; + uint32_t dcdc_rdy_clr : 1; + }; + uint32_t val; +} pmu_dcm_ctrl_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 24; + uint32_t dcdc_boost_ccm_ctrlen: 1; + uint32_t dcdc_boost_ccm_enb : 1; + uint32_t dcdc_boost_en : 1; + uint32_t dcdc_boost_dreg : 5; + }; + uint32_t val; +} pmu_dcm_boost_ctrl_reg_t; + +typedef union { + struct { + uint32_t touch_sleep_cycles : 16; + uint32_t reserved0 : 5; + uint32_t touch_wait_cycles : 9; + uint32_t touch_sleep_timer_en: 1; + uint32_t touch_force_done : 1; + }; + uint32_t val; +} pmu_touch_pwr_ctrl_reg_t; + +typedef union { + struct { + uint32_t reserved_0:23; + /** ext_ocode : R/W; bitpos: [30:23]; default: 120; + * need_des + */ + uint32_t ext_ocode:8; + /** ext_force_ocode : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ext_force_ocode:1; + }; + uint32_t val; +} pmu_ble_bandgap_ctrl_reg_t; + +typedef struct pmu_dev { + volatile pmu_hp_hw_regmap_t hp_sys[3]; + volatile pmu_lp_hw_regmap_t lp_sys[2]; + volatile pmu_imm_hw_regmap_t imm; + volatile pmu_power_hw_regmap_t power; + volatile pmu_wakeup_hw_regmap_t wakeup; + volatile pmu_hp_ext_hw_regmap_t hp_ext; + volatile pmu_lp_ext_hw_regmap_t lp_ext; + + volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_common; + volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg; + + volatile pmu_main_state_reg_t main_state; + volatile pmu_pwr_state_reg_t pwr_state; + volatile pmu_clk_state0_reg_t clk_state0; + volatile pmu_clk_state1_reg_t clk_state1; + volatile pmu_clk_state2_reg_t clk_state2; + + volatile pmu_dcm_ctrl_reg_t dcm_ctrl; + volatile pmu_dcm_boost_ctrl_reg_t dcm_boost_ctrl; + volatile pmu_touch_pwr_ctrl_reg_t touch_pwr_ctrl; + volatile pmu_ble_bandgap_ctrl_reg_t ble_bandgap_ctrl; + + uint32_t reserved[141]; + + union { + struct { + uint32_t pmu_date: 31; + uint32_t clk_en : 1; + }; + uint32_t val; + } date; +} pmu_dev_t; + +extern pmu_dev_t PMU; + +#ifndef __cplusplus +_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/pmu_struct_mp.h b/components/soc/esp32h4/register/soc/pmu_struct_mp.h deleted file mode 100644 index 5411c6eff1..0000000000 --- a/components/soc/esp32h4/register/soc/pmu_struct_mp.h +++ /dev/null @@ -1,3001 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: configure_register */ -/** Type of hp_active_dig_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:18; - /** hp_active_vdd_flash_mode : R/W; bitpos: [21:18]; default: 0; - * need_des - */ - uint32_t hp_active_vdd_flash_mode:4; - /** hp_active_hp_mem_dslp : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t hp_active_hp_mem_dslp:1; - /** hp_active_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_mem_pd_en:4; - /** hp_active_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_wifi_pd_en:1; - /** hp_active_pd_hp_peri_pd_en : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_peri_pd_en:1; - /** hp_active_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_cpu_pd_en:1; - /** hp_active_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_aon_pd_en:1; - /** hp_active_pd_top_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_active_pd_top_pd_en:1; - }; - uint32_t val; -} pmu_hp_active_dig_power_reg_t; - -/** Type of hp_active_icg_hp_func register - * need_des - */ -typedef union { - struct { - /** hp_active_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_active_dig_icg_func_en:32; - }; - uint32_t val; -} pmu_hp_active_icg_hp_func_reg_t; - -/** Type of hp_active_icg_hp_apb register - * need_des - */ -typedef union { - struct { - /** hp_active_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_active_dig_icg_apb_en:32; - }; - uint32_t val; -} pmu_hp_active_icg_hp_apb_reg_t; - -/** Type of hp_active_icg_modem register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** hp_active_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_active_dig_icg_modem_code:2; - }; - uint32_t val; -} pmu_hp_active_icg_modem_reg_t; - -/** Type of hp_active_hp_sys_cntl register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:24; - /** hp_active_uart_wakeup_en : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t hp_active_uart_wakeup_en:1; - /** hp_active_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_active_lp_pad_hold_all:1; - /** hp_active_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_active_hp_pad_hold_all:1; - /** hp_active_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_dig_pad_slp_sel:1; - /** hp_active_dig_pause_wdt : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_dig_pause_wdt:1; - /** hp_active_dig_cpu_stall : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_dig_cpu_stall:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} pmu_hp_active_hp_sys_cntl_reg_t; - -/** Type of hp_active_hp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_active_i2c_iso_en : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_active_i2c_iso_en:1; - /** hp_active_i2c_retention : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_i2c_retention:1; - /** hp_active_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bb_i2c:1; - /** hp_active_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bbpll_i2c:1; - /** hp_active_xpd_bbpll : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bbpll:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_hp_active_hp_ck_power_reg_t; - -/** Type of hp_active_bias register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:9; - /** hp_active_dcdc_ccm_enb : R/W; bitpos: [9]; default: 1; - * need_des - */ - uint32_t hp_active_dcdc_ccm_enb:1; - /** hp_active_dcdc_clear_rdy : R/W; bitpos: [10]; default: 0; - * need_des - */ - uint32_t hp_active_dcdc_clear_rdy:1; - /** hp_active_dig_pmu_dpcur_bias : R/W; bitpos: [12:11]; default: 3; - * need_des - */ - uint32_t hp_active_dig_pmu_dpcur_bias:2; - /** hp_active_dig_pmu_dsfmos : R/W; bitpos: [16:13]; default: 6; - * need_des - */ - uint32_t hp_active_dig_pmu_dsfmos:4; - /** hp_active_dcm_vset : R/W; bitpos: [21:17]; default: 23; - * need_des - */ - uint32_t hp_active_dcm_vset:5; - /** hp_active_dcm_mode : R/W; bitpos: [23:22]; default: 0; - * need_des - */ - uint32_t hp_active_dcm_mode:2; - /** hp_active_xpd_trx : R/W; bitpos: [24]; default: 1; - * need_des - */ - uint32_t hp_active_xpd_trx:1; - /** hp_active_xpd_bias : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bias:1; - uint32_t reserved_26:3; - /** hp_active_discnnt_dig_rtc : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_discnnt_dig_rtc:1; - /** hp_active_pd_cur : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_active_pd_cur:1; - /** hp_active_bias_sleep : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_active_bias_sleep:1; - }; - uint32_t val; -} pmu_hp_active_bias_reg_t; - -/** Type of hp_active_backup register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** hp_sleep2active_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_modem_clk_code:2; - /** hp_modem2active_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_modem_clk_code:2; - uint32_t reserved_8:6; - /** hp_sleep2active_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_clk_sel:2; - /** hp_modem2active_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_clk_sel:2; - /** hp_sleep2active_backup_mode : R/W; bitpos: [22:18]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_mode:5; - /** hp_modem2active_backup_mode : R/W; bitpos: [27:23]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_mode:5; - uint32_t reserved_28:1; - /** hp_sleep2active_backup_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_en:1; - /** hp_modem2active_backup_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_en:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_hp_active_backup_reg_t; - -/** Type of hp_active_backup_clk register - * need_des - */ -typedef union { - struct { - /** hp_active_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t hp_active_backup_icg_func_en:32; - }; - uint32_t val; -} pmu_hp_active_backup_clk_reg_t; - -/** Type of hp_active_sysclk register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_active_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_active_dig_sys_clk_no_div:1; - /** hp_active_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_icg_sys_clock_en:1; - /** hp_active_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_sys_clk_slp_sel:1; - /** hp_active_icg_slp_sel : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_icg_slp_sel:1; - /** hp_active_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_active_dig_sys_clk_sel:2; - }; - uint32_t val; -} pmu_hp_active_sysclk_reg_t; - -/** Type of hp_active_hp_regulator0 register - * need_des - */ -typedef union { - struct { - /** hp_active_hp_power_det_bypass : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t hp_active_hp_power_det_bypass:1; - uint32_t reserved_1:3; - /** lp_dbias_vol : RO; bitpos: [8:4]; default: 24; - * need_des - */ - uint32_t lp_dbias_vol:5; - /** hp_dbias_vol : RO; bitpos: [13:9]; default: 24; - * need_des - */ - uint32_t hp_dbias_vol:5; - /** dig_regulator0_dbias_sel : R/W; bitpos: [14]; default: 1; - * need_des - */ - uint32_t dig_regulator0_dbias_sel:1; - /** dig_dbias_init : WT; bitpos: [15]; default: 0; - * need_des - */ - uint32_t dig_dbias_init:1; - /** hp_active_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_mem_xpd:1; - /** hp_active_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_logic_xpd:1; - /** hp_active_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; - * need_des - */ - uint32_t hp_active_hp_regulator_xpd:1; - /** hp_active_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 8; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_mem_dbias:4; - /** hp_active_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 8; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_logic_dbias:4; - /** hp_active_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 16; - * need_des - */ - uint32_t hp_active_hp_regulator_dbias:5; - }; - uint32_t val; -} pmu_hp_active_hp_regulator0_reg_t; - -/** Type of hp_active_hp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** hp_active_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 16; - * need_des - */ - uint32_t hp_active_hp_regulator_drv_b:24; - }; - uint32_t val; -} pmu_hp_active_hp_regulator1_reg_t; - -/** Type of hp_active_xtal register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** hp_active_xpd_xtalx2 : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t hp_active_xpd_xtalx2:1; - /** hp_active_xpd_xtal : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t hp_active_xpd_xtal:1; - }; - uint32_t val; -} pmu_hp_active_xtal_reg_t; - -/** Type of hp_sleep_dig_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:18; - /** hp_sleep_vdd_flash_mode : R/W; bitpos: [21:18]; default: 0; - * need_des - */ - uint32_t hp_sleep_vdd_flash_mode:4; - /** hp_sleep_hp_mem_dslp : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_mem_dslp:1; - /** hp_sleep_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_mem_pd_en:4; - /** hp_sleep_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_wifi_pd_en:1; - /** hp_sleep_pd_hp_peri_pd_en : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_peri_pd_en:1; - /** hp_sleep_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_cpu_pd_en:1; - /** hp_sleep_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_aon_pd_en:1; - /** hp_sleep_pd_top_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_top_pd_en:1; - }; - uint32_t val; -} pmu_hp_sleep_dig_power_reg_t; - -/** Type of hp_sleep_icg_hp_func register - * need_des - */ -typedef union { - struct { - /** hp_sleep_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_sleep_dig_icg_func_en:32; - }; - uint32_t val; -} pmu_hp_sleep_icg_hp_func_reg_t; - -/** Type of hp_sleep_icg_hp_apb register - * need_des - */ -typedef union { - struct { - /** hp_sleep_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_sleep_dig_icg_apb_en:32; - }; - uint32_t val; -} pmu_hp_sleep_icg_hp_apb_reg_t; - -/** Type of hp_sleep_icg_modem register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** hp_sleep_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_icg_modem_code:2; - }; - uint32_t val; -} pmu_hp_sleep_icg_modem_reg_t; - -/** Type of hp_sleep_hp_sys_cntl register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:24; - /** hp_sleep_uart_wakeup_en : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t hp_sleep_uart_wakeup_en:1; - /** hp_sleep_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_pad_hold_all:1; - /** hp_sleep_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_pad_hold_all:1; - /** hp_sleep_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_pad_slp_sel:1; - /** hp_sleep_dig_pause_wdt : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_pause_wdt:1; - /** hp_sleep_dig_cpu_stall : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_cpu_stall:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} pmu_hp_sleep_hp_sys_cntl_reg_t; - -/** Type of hp_sleep_hp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_sleep_i2c_iso_en : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_sleep_i2c_iso_en:1; - /** hp_sleep_i2c_retention : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_i2c_retention:1; - /** hp_sleep_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bb_i2c:1; - /** hp_sleep_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bbpll_i2c:1; - /** hp_sleep_xpd_bbpll : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bbpll:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_hp_sleep_hp_ck_power_reg_t; - -/** Type of hp_sleep_bias register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:9; - /** hp_sleep_dcdc_ccm_enb : R/W; bitpos: [9]; default: 1; - * need_des - */ - uint32_t hp_sleep_dcdc_ccm_enb:1; - /** hp_sleep_dcdc_clear_rdy : R/W; bitpos: [10]; default: 0; - * need_des - */ - uint32_t hp_sleep_dcdc_clear_rdy:1; - /** hp_sleep_dig_pmu_dpcur_bias : R/W; bitpos: [12:11]; default: 1; - * need_des - */ - uint32_t hp_sleep_dig_pmu_dpcur_bias:2; - /** hp_sleep_dig_pmu_dsfmos : R/W; bitpos: [16:13]; default: 4; - * need_des - */ - uint32_t hp_sleep_dig_pmu_dsfmos:4; - /** hp_sleep_dcm_vset : R/W; bitpos: [21:17]; default: 23; - * need_des - */ - uint32_t hp_sleep_dcm_vset:5; - /** hp_sleep_dcm_mode : R/W; bitpos: [23:22]; default: 0; - * need_des - */ - uint32_t hp_sleep_dcm_mode:2; - /** hp_sleep_xpd_trx : R/W; bitpos: [24]; default: 1; - * need_des - */ - uint32_t hp_sleep_xpd_trx:1; - /** hp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bias:1; - uint32_t reserved_26:3; - /** hp_sleep_discnnt_dig_rtc : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_discnnt_dig_rtc:1; - /** hp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_cur:1; - /** hp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_bias_sleep:1; - }; - uint32_t val; -} pmu_hp_sleep_bias_reg_t; - -/** Type of hp_sleep_backup register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:6; - /** hp_modem2sleep_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_modem_clk_code:2; - /** hp_active2sleep_backup_modem_clk_code : R/W; bitpos: [9:8]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_modem_clk_code:2; - uint32_t reserved_10:6; - /** hp_modem2sleep_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_clk_sel:2; - /** hp_active2sleep_backup_clk_sel : R/W; bitpos: [19:18]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_clk_sel:2; - /** hp_modem2sleep_backup_mode : R/W; bitpos: [24:20]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_mode:5; - /** hp_active2sleep_backup_mode : R/W; bitpos: [29:25]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_mode:5; - /** hp_modem2sleep_backup_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_en:1; - /** hp_active2sleep_backup_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_en:1; - }; - uint32_t val; -} pmu_hp_sleep_backup_reg_t; - -/** Type of hp_sleep_backup_clk register - * need_des - */ -typedef union { - struct { - /** hp_sleep_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t hp_sleep_backup_icg_func_en:32; - }; - uint32_t val; -} pmu_hp_sleep_backup_clk_reg_t; - -/** Type of hp_sleep_sysclk register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_sleep_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_sys_clk_no_div:1; - /** hp_sleep_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_icg_sys_clock_en:1; - /** hp_sleep_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_sys_clk_slp_sel:1; - /** hp_sleep_icg_slp_sel : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_icg_slp_sel:1; - /** hp_sleep_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_sys_clk_sel:2; - }; - uint32_t val; -} pmu_hp_sleep_sysclk_reg_t; - -/** Type of hp_sleep_hp_regulator0 register - * need_des - */ -typedef union { - struct { - /** hp_sleep_hp_power_det_bypass : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_power_det_bypass:1; - uint32_t reserved_1:15; - /** hp_sleep_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_mem_xpd:1; - /** hp_sleep_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_logic_xpd:1; - /** hp_sleep_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; - * need_des - */ - uint32_t hp_sleep_hp_regulator_xpd:1; - /** hp_sleep_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 8; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_mem_dbias:4; - /** hp_sleep_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 8; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_logic_dbias:4; - /** hp_sleep_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 16; - * need_des - */ - uint32_t hp_sleep_hp_regulator_dbias:5; - }; - uint32_t val; -} pmu_hp_sleep_hp_regulator0_reg_t; - -/** Type of hp_sleep_hp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** hp_sleep_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 16; - * need_des - */ - uint32_t hp_sleep_hp_regulator_drv_b:24; - }; - uint32_t val; -} pmu_hp_sleep_hp_regulator1_reg_t; - -/** Type of hp_sleep_xtal register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** hp_sleep_xpd_xtalx2 : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t hp_sleep_xpd_xtalx2:1; - /** hp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t hp_sleep_xpd_xtal:1; - }; - uint32_t val; -} pmu_hp_sleep_xtal_reg_t; - -/** Type of hp_sleep_lp_regulator0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** hp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; - * need_des - */ - uint32_t hp_sleep_lp_regulator_slp_xpd:1; - /** hp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; - * need_des - */ - uint32_t hp_sleep_lp_regulator_xpd:1; - /** hp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 8; - * need_des - */ - uint32_t hp_sleep_lp_regulator_slp_dbias:4; - /** hp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_regulator_dbias:5; - }; - uint32_t val; -} pmu_hp_sleep_lp_regulator0_reg_t; - -/** Type of hp_sleep_lp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** hp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_regulator_drv_b:4; - }; - uint32_t val; -} pmu_hp_sleep_lp_regulator1_reg_t; - -/** Type of hp_sleep_lp_dig_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** hp_sleep_vdd_io_mode : R/W; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t hp_sleep_vdd_io_mode:4; - /** hp_sleep_bod_source_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_bod_source_sel:1; - /** hp_sleep_vddbat_mode : R/W; bitpos: [29:28]; default: 0; - * need_des - */ - uint32_t hp_sleep_vddbat_mode:2; - /** hp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_mem_dslp:1; - /** hp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_lp_peri_pd_en:1; - }; - uint32_t val; -} pmu_hp_sleep_lp_dig_power_reg_t; - -/** Type of hp_sleep_lp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** hp_sleep_xpd_lppll : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_lppll:1; - /** hp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_xtal32k:1; - /** hp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_rc32k:1; - /** hp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t hp_sleep_xpd_fosc_clk:1; - /** hp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_osc_clk:1; - }; - uint32_t val; -} pmu_hp_sleep_lp_ck_power_reg_t; - -/** Type of lp_sleep_lp_regulator0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** lp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; - * need_des - */ - uint32_t lp_sleep_lp_regulator_slp_xpd:1; - /** lp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; - * need_des - */ - uint32_t lp_sleep_lp_regulator_xpd:1; - /** lp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 8; - * need_des - */ - uint32_t lp_sleep_lp_regulator_slp_dbias:4; - /** lp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t lp_sleep_lp_regulator_dbias:5; - }; - uint32_t val; -} pmu_lp_sleep_lp_regulator0_reg_t; - -/** Type of lp_sleep_lp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** lp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; - * need_des - */ - uint32_t lp_sleep_lp_regulator_drv_b:4; - }; - uint32_t val; -} pmu_lp_sleep_lp_regulator1_reg_t; - -/** Type of lp_sleep_xtal register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** lp_sleep_xpd_xtalx2 : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t lp_sleep_xpd_xtalx2:1; - /** lp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t lp_sleep_xpd_xtal:1; - }; - uint32_t val; -} pmu_lp_sleep_xtal_reg_t; - -/** Type of lp_sleep_lp_dig_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** lp_sleep_vdd_io_mode : R/W; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t lp_sleep_vdd_io_mode:4; - /** lp_sleep_bod_source_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_sleep_bod_source_sel:1; - /** lp_sleep_vddbat_mode : R/W; bitpos: [29:28]; default: 0; - * need_des - */ - uint32_t lp_sleep_vddbat_mode:2; - /** lp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_sleep_lp_mem_dslp:1; - /** lp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_sleep_pd_lp_peri_pd_en:1; - }; - uint32_t val; -} pmu_lp_sleep_lp_dig_power_reg_t; - -/** Type of lp_sleep_lp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** lp_sleep_xpd_lppll : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_lppll:1; - /** lp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_xtal32k:1; - /** lp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_rc32k:1; - /** lp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t lp_sleep_xpd_fosc_clk:1; - /** lp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_sleep_pd_osc_clk:1; - }; - uint32_t val; -} pmu_lp_sleep_lp_ck_power_reg_t; - -/** Type of lp_sleep_bias register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:9; - /** lp_sleep_dcdc_ccm_enb : R/W; bitpos: [9]; default: 1; - * need_des - */ - uint32_t lp_sleep_dcdc_ccm_enb:1; - /** lp_sleep_dcdc_clear_rdy : R/W; bitpos: [10]; default: 0; - * need_des - */ - uint32_t lp_sleep_dcdc_clear_rdy:1; - /** lp_sleep_dig_pmu_dpcur_bias : R/W; bitpos: [12:11]; default: 1; - * need_des - */ - uint32_t lp_sleep_dig_pmu_dpcur_bias:2; - /** lp_sleep_dig_pmu_dsfmos : R/W; bitpos: [16:13]; default: 4; - * need_des - */ - uint32_t lp_sleep_dig_pmu_dsfmos:4; - /** lp_sleep_dcm_vset : R/W; bitpos: [21:17]; default: 23; - * need_des - */ - uint32_t lp_sleep_dcm_vset:5; - /** lp_sleep_dcm_mode : R/W; bitpos: [23:22]; default: 0; - * need_des - */ - uint32_t lp_sleep_dcm_mode:2; - uint32_t reserved_24:1; - /** lp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_bias:1; - uint32_t reserved_26:3; - /** lp_sleep_discnnt_dig_rtc : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t lp_sleep_discnnt_dig_rtc:1; - /** lp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_sleep_pd_cur:1; - /** lp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_sleep_bias_sleep:1; - }; - uint32_t val; -} pmu_lp_sleep_bias_reg_t; - -/** Type of imm_hp_ck_power register - * need_des - */ -typedef union { - struct { - /** tie_low_global_bbpll_icg : WT; bitpos: [0]; default: 0; - * need_des - */ - uint32_t tie_low_global_bbpll_icg:1; - /** tie_low_global_xtal_icg : WT; bitpos: [1]; default: 0; - * need_des - */ - uint32_t tie_low_global_xtal_icg:1; - /** tie_low_i2c_retention : WT; bitpos: [2]; default: 0; - * need_des - */ - uint32_t tie_low_i2c_retention:1; - /** tie_low_xpd_bb_i2c : WT; bitpos: [3]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_bb_i2c:1; - /** tie_low_xpd_bbpll_i2c : WT; bitpos: [4]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_bbpll_i2c:1; - /** tie_low_xpd_bbpll : WT; bitpos: [5]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_bbpll:1; - /** tie_low_xpd_xtal : WT; bitpos: [6]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_xtal:1; - /** tie_low_global_xtalx2_icg : WT; bitpos: [7]; default: 0; - * need_des - */ - uint32_t tie_low_global_xtalx2_icg:1; - /** tie_low_xpd_xtalx2 : WT; bitpos: [8]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_xtalx2:1; - uint32_t reserved_9:14; - /** tie_high_xtalx2 : WT; bitpos: [23]; default: 0; - * need_des - */ - uint32_t tie_high_xtalx2:1; - /** tie_high_global_xtalx2_icg : WT; bitpos: [24]; default: 0; - * need_des - */ - uint32_t tie_high_global_xtalx2_icg:1; - /** tie_high_global_bbpll_icg : WT; bitpos: [25]; default: 0; - * need_des - */ - uint32_t tie_high_global_bbpll_icg:1; - /** tie_high_global_xtal_icg : WT; bitpos: [26]; default: 0; - * need_des - */ - uint32_t tie_high_global_xtal_icg:1; - /** tie_high_i2c_retention : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t tie_high_i2c_retention:1; - /** tie_high_xpd_bb_i2c : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_bb_i2c:1; - /** tie_high_xpd_bbpll_i2c : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_bbpll_i2c:1; - /** tie_high_xpd_bbpll : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_bbpll:1; - /** tie_high_xpd_xtal : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_xtal:1; - }; - uint32_t val; -} pmu_imm_hp_ck_power_reg_t; - -/** Type of imm_sleep_sysclk register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** update_dig_icg_switch : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t update_dig_icg_switch:1; - /** tie_low_icg_slp_sel : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t tie_low_icg_slp_sel:1; - /** tie_high_icg_slp_sel : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_icg_slp_sel:1; - /** update_dig_sys_clk_sel : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_sys_clk_sel:1; - }; - uint32_t val; -} pmu_imm_sleep_sysclk_reg_t; - -/** Type of imm_hp_func_icg register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** update_dig_icg_func_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_icg_func_en:1; - }; - uint32_t val; -} pmu_imm_hp_func_icg_reg_t; - -/** Type of imm_hp_apb_icg register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** update_dig_icg_apb_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_icg_apb_en:1; - }; - uint32_t val; -} pmu_imm_hp_apb_icg_reg_t; - -/** Type of imm_modem_icg register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** update_dig_icg_modem_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_icg_modem_en:1; - }; - uint32_t val; -} pmu_imm_modem_icg_reg_t; - -/** Type of imm_lp_icg register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** tie_low_lp_rootclk_sel : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_low_lp_rootclk_sel:1; - /** tie_high_lp_rootclk_sel : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_high_lp_rootclk_sel:1; - }; - uint32_t val; -} pmu_imm_lp_icg_reg_t; - -/** Type of imm_pad_hold_all register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** tie_high_dig_pad_slp_sel : WT; bitpos: [26]; default: 0; - * need_des - */ - uint32_t tie_high_dig_pad_slp_sel:1; - /** tie_low_dig_pad_slp_sel : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t tie_low_dig_pad_slp_sel:1; - /** tie_high_lp_pad_hold_all : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t tie_high_lp_pad_hold_all:1; - /** tie_low_lp_pad_hold_all : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t tie_low_lp_pad_hold_all:1; - /** tie_high_hp_pad_hold_all : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_hp_pad_hold_all:1; - /** tie_low_hp_pad_hold_all : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_low_hp_pad_hold_all:1; - }; - uint32_t val; -} pmu_imm_pad_hold_all_reg_t; - -/** Type of imm_i2c_iso register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** tie_high_i2c_iso_en : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_i2c_iso_en:1; - /** tie_low_i2c_iso_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_low_i2c_iso_en:1; - }; - uint32_t val; -} pmu_imm_i2c_iso_reg_t; - -/** Type of power_wait_timer0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** dg_hp_powerdown_timer : R/W; bitpos: [13:5]; default: 255; - * need_des - */ - uint32_t dg_hp_powerdown_timer:9; - /** dg_hp_powerup_timer : R/W; bitpos: [22:14]; default: 255; - * need_des - */ - uint32_t dg_hp_powerup_timer:9; - /** dg_hp_pd_wait_timer : R/W; bitpos: [31:23]; default: 255; - * need_des - */ - uint32_t dg_hp_pd_wait_timer:9; - }; - uint32_t val; -} pmu_power_wait_timer0_reg_t; - -/** Type of power_wait_timer1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:9; - /** dg_lp_powerdown_timer : R/W; bitpos: [15:9]; default: 63; - * need_des - */ - uint32_t dg_lp_powerdown_timer:7; - /** dg_lp_powerup_timer : R/W; bitpos: [22:16]; default: 63; - * need_des - */ - uint32_t dg_lp_powerup_timer:7; - /** dg_lp_pd_wait_timer : R/W; bitpos: [31:23]; default: 255; - * need_des - */ - uint32_t dg_lp_pd_wait_timer:9; - }; - uint32_t val; -} pmu_power_wait_timer1_reg_t; - -/** Type of power_wait_timer2 register - * need_des - */ -typedef union { - struct { - /** dg_lp_iso_wait_timer : R/W; bitpos: [7:0]; default: 255; - * need_des - */ - uint32_t dg_lp_iso_wait_timer:8; - /** dg_lp_rst_wait_timer : R/W; bitpos: [15:8]; default: 255; - * need_des - */ - uint32_t dg_lp_rst_wait_timer:8; - /** dg_hp_iso_wait_timer : R/W; bitpos: [23:16]; default: 255; - * need_des - */ - uint32_t dg_hp_iso_wait_timer:8; - /** dg_hp_rst_wait_timer : R/W; bitpos: [31:24]; default: 255; - * need_des - */ - uint32_t dg_hp_rst_wait_timer:8; - }; - uint32_t val; -} pmu_power_wait_timer2_reg_t; - -/** Type of power_pd_top_cntl register - * need_des - */ -typedef union { - struct { - /** force_top_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_top_reset:1; - /** force_top_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_top_iso:1; - /** force_top_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_top_pu:1; - /** force_top_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_top_no_reset:1; - /** force_top_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_top_no_iso:1; - /** force_top_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_top_pd:1; - /** pd_top_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_top_mask:5; - uint32_t reserved_11:16; - /** pd_top_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_top_pd_mask:5; - }; - uint32_t val; -} pmu_power_pd_top_cntl_reg_t; - -/** Type of power_pd_hpaon_cntl register - * need_des - */ -typedef union { - struct { - /** force_hp_aon_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_aon_reset:1; - /** force_hp_aon_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_aon_iso:1; - /** force_hp_aon_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_aon_pu:1; - /** force_hp_aon_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_aon_no_reset:1; - /** force_hp_aon_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_aon_no_iso:1; - /** force_hp_aon_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_aon_pd:1; - /** pd_hp_aon_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_hp_aon_mask:5; - uint32_t reserved_11:16; - /** pd_hp_aon_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_aon_pd_mask:5; - }; - uint32_t val; -} pmu_power_pd_hpaon_cntl_reg_t; - -/** Type of power_pd_hpcpu_cntl register - * need_des - */ -typedef union { - struct { - /** force_hp_cpu_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_cpu_reset:1; - /** force_hp_cpu_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_cpu_iso:1; - /** force_hp_cpu_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_cpu_pu:1; - /** force_hp_cpu_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_cpu_no_reset:1; - /** force_hp_cpu_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_cpu_no_iso:1; - /** force_hp_cpu_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_cpu_pd:1; - /** pd_hp_cpu_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_hp_cpu_mask:5; - uint32_t reserved_11:16; - /** pd_hp_cpu_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_cpu_pd_mask:5; - }; - uint32_t val; -} pmu_power_pd_hpcpu_cntl_reg_t; - -/** Type of power_pd_hpperi_reserve register - * need_des - */ -typedef union { - struct { - /** force_hp_peri_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_peri_reset:1; - /** force_hp_peri_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_peri_iso:1; - /** force_hp_peri_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_peri_pu:1; - /** force_hp_peri_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_peri_no_reset:1; - /** force_hp_peri_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_peri_no_iso:1; - /** force_hp_peri_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_peri_pd:1; - /** pd_hp_peri_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_hp_peri_mask:5; - uint32_t reserved_11:16; - /** pd_hp_peri_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_peri_pd_mask:5; - }; - uint32_t val; -} pmu_power_pd_hpperi_reserve_reg_t; - -/** Type of power_pd_hpwifi_cntl register - * need_des - */ -typedef union { - struct { - /** force_hp_wifi_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_wifi_reset:1; - /** force_hp_wifi_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_wifi_iso:1; - /** force_hp_wifi_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_wifi_pu:1; - /** force_hp_wifi_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_wifi_no_reset:1; - /** force_hp_wifi_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_wifi_no_iso:1; - /** force_hp_wifi_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_wifi_pd:1; - /** pd_hp_wifi_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_hp_wifi_mask:5; - uint32_t reserved_11:16; - /** pd_hp_wifi_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_wifi_pd_mask:5; - }; - uint32_t val; -} pmu_power_pd_hpwifi_cntl_reg_t; - -/** Type of power_pd_lpperi_cntl register - * need_des - */ -typedef union { - struct { - /** force_lp_peri_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_lp_peri_reset:1; - /** force_lp_peri_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_lp_peri_iso:1; - /** force_lp_peri_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_lp_peri_pu:1; - /** force_lp_peri_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_lp_peri_no_reset:1; - /** force_lp_peri_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_lp_peri_no_iso:1; - /** force_lp_peri_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_lp_peri_pd:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} pmu_power_pd_lpperi_cntl_reg_t; - -/** Type of power_pd_mem_cntl register - * need_des - */ -typedef union { - struct { - /** force_hp_mem_iso : R/W; bitpos: [3:0]; default: 0; - * need_des - */ - uint32_t force_hp_mem_iso:4; - /** force_hp_mem_pd : R/W; bitpos: [7:4]; default: 0; - * need_des - */ - uint32_t force_hp_mem_pd:4; - uint32_t reserved_8:16; - /** force_hp_mem_no_iso : R/W; bitpos: [27:24]; default: 15; - * need_des - */ - uint32_t force_hp_mem_no_iso:4; - /** force_hp_mem_pu : R/W; bitpos: [31:28]; default: 15; - * need_des - */ - uint32_t force_hp_mem_pu:4; - }; - uint32_t val; -} pmu_power_pd_mem_cntl_reg_t; - -/** Type of power_pd_mem_mask register - * need_des - */ -typedef union { - struct { - /** pd_hp_mem2_pd_mask : R/W; bitpos: [4:0]; default: 0; - * need_des - */ - uint32_t pd_hp_mem2_pd_mask:5; - /** pd_hp_mem1_pd_mask : R/W; bitpos: [9:5]; default: 0; - * need_des - */ - uint32_t pd_hp_mem1_pd_mask:5; - /** pd_hp_mem0_pd_mask : R/W; bitpos: [14:10]; default: 0; - * need_des - */ - uint32_t pd_hp_mem0_pd_mask:5; - uint32_t reserved_15:2; - /** pd_hp_mem2_mask : R/W; bitpos: [21:17]; default: 0; - * need_des - */ - uint32_t pd_hp_mem2_mask:5; - /** pd_hp_mem1_mask : R/W; bitpos: [26:22]; default: 0; - * need_des - */ - uint32_t pd_hp_mem1_mask:5; - /** pd_hp_mem0_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_mem0_mask:5; - }; - uint32_t val; -} pmu_power_pd_mem_mask_reg_t; - -/** Type of power_hp_pad register - * need_des - */ -typedef union { - struct { - /** force_hp_pad_no_iso_all : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_pad_no_iso_all:1; - /** force_hp_pad_iso_all : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_pad_iso_all:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} pmu_power_hp_pad_reg_t; - -/** Type of power_flash1p8_ldo register - * need_des - */ -typedef union { - struct { - /** flash1p8_ldo_rdy : RO; bitpos: [0]; default: 1; - * need_des - */ - uint32_t flash1p8_ldo_rdy:1; - /** flash1p8_sw_en_xpd : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t flash1p8_sw_en_xpd:1; - /** flash1p8_sw_en_thru : R/W; bitpos: [2]; default: 0; - * need_des - */ - uint32_t flash1p8_sw_en_thru:1; - /** flash1p8_sw_en_standby : R/W; bitpos: [3]; default: 0; - * need_des - */ - uint32_t flash1p8_sw_en_standby:1; - /** flash1p8_sw_en_power_adjust : R/W; bitpos: [4]; default: 0; - * need_des - */ - uint32_t flash1p8_sw_en_power_adjust:1; - /** flash1p8_sw_en_endet : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t flash1p8_sw_en_endet:1; - uint32_t reserved_6:16; - /** flash1p8_bypass_ldo_rdy : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t flash1p8_bypass_ldo_rdy:1; - /** flash1p8_xpd : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t flash1p8_xpd:1; - /** flash1p8_thru : R/W; bitpos: [24]; default: 1; - * need_des - */ - uint32_t flash1p8_thru:1; - /** flash1p8_standby : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t flash1p8_standby:1; - /** flash1p8_power_adjust : R/W; bitpos: [29:26]; default: 0; - * need_des - */ - uint32_t flash1p8_power_adjust:4; - uint32_t reserved_30:1; - /** flash1p8_endet : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t flash1p8_endet:1; - }; - uint32_t val; -} pmu_power_flash1p8_ldo_reg_t; - -/** Type of power_flash1p2_ldo register - * need_des - */ -typedef union { - struct { - /** flash1p2_ldo_rdy : RO; bitpos: [0]; default: 1; - * need_des - */ - uint32_t flash1p2_ldo_rdy:1; - /** flash1p2_sw_en_xpd : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t flash1p2_sw_en_xpd:1; - /** flash1p2_sw_en_thru : R/W; bitpos: [2]; default: 0; - * need_des - */ - uint32_t flash1p2_sw_en_thru:1; - /** flash1p2_sw_en_standby : R/W; bitpos: [3]; default: 0; - * need_des - */ - uint32_t flash1p2_sw_en_standby:1; - /** flash1p2_sw_en_power_adjust : R/W; bitpos: [4]; default: 0; - * need_des - */ - uint32_t flash1p2_sw_en_power_adjust:1; - /** flash1p2_sw_en_endet : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t flash1p2_sw_en_endet:1; - uint32_t reserved_6:16; - /** flash1p2_bypass_ldo_rdy : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t flash1p2_bypass_ldo_rdy:1; - /** flash1p2_xpd : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t flash1p2_xpd:1; - /** flash1p2_thru : R/W; bitpos: [24]; default: 1; - * need_des - */ - uint32_t flash1p2_thru:1; - /** flash1p2_standby : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t flash1p2_standby:1; - /** flash1p2_power_adjust : R/W; bitpos: [29:26]; default: 0; - * need_des - */ - uint32_t flash1p2_power_adjust:4; - uint32_t reserved_30:1; - /** flash1p2_endet : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t flash1p2_endet:1; - }; - uint32_t val; -} pmu_power_flash1p2_ldo_reg_t; - -/** Type of power_vdd_flash register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:22; - /** flash_ldo_sw_en_tiel : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t flash_ldo_sw_en_tiel:1; - /** flash_ldo_power_sel : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t flash_ldo_power_sel:1; - /** flash_ldo_sw_en_power_sel : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t flash_ldo_sw_en_power_sel:1; - /** flash_ldo_wait_target : R/W; bitpos: [28:25]; default: 15; - * need_des - */ - uint32_t flash_ldo_wait_target:4; - /** flash_ldo_tiel_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t flash_ldo_tiel_en:1; - /** flash_ldo_tiel : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t flash_ldo_tiel:1; - /** flash_ldo_sw_update : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t flash_ldo_sw_update:1; - }; - uint32_t val; -} pmu_power_vdd_flash_reg_t; - -/** Type of power_io_ldo register - * need_des - */ -typedef union { - struct { - /** io_ldo_rdy : RO; bitpos: [0]; default: 1; - * need_des - */ - uint32_t io_ldo_rdy:1; - /** io_sw_en_xpd : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t io_sw_en_xpd:1; - uint32_t reserved_2:1; - /** io_sw_en_thru : R/W; bitpos: [3]; default: 0; - * need_des - */ - uint32_t io_sw_en_thru:1; - /** io_sw_en_standby : R/W; bitpos: [4]; default: 0; - * need_des - */ - uint32_t io_sw_en_standby:1; - /** io_sw_en_power_adjust : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t io_sw_en_power_adjust:1; - /** io_sw_en_endet : R/W; bitpos: [6]; default: 0; - * need_des - */ - uint32_t io_sw_en_endet:1; - uint32_t reserved_7:15; - /** io_bypass_ldo_rdy : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t io_bypass_ldo_rdy:1; - /** io_xpd : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t io_xpd:1; - /** io_thru : R/W; bitpos: [24]; default: 1; - * need_des - */ - uint32_t io_thru:1; - /** io_standby : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t io_standby:1; - /** io_power_adjust : R/W; bitpos: [29:26]; default: 0; - * need_des - */ - uint32_t io_power_adjust:4; - uint32_t reserved_30:1; - /** io_endet : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t io_endet:1; - }; - uint32_t val; -} pmu_power_io_ldo_reg_t; - -/** Type of power_vdd_io register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** io_ldo_power_sel : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t io_ldo_power_sel:1; - /** io_ldo_sw_en_power_sel : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t io_ldo_sw_en_power_sel:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} pmu_power_vdd_io_reg_t; - -/** Type of power_ck_wait_cntl register - * need_des - */ -typedef union { - struct { - /** wait_xtl_stable : R/W; bitpos: [15:0]; default: 384; - * need_des - */ - uint32_t wait_xtl_stable:16; - /** wait_pll_stable : R/W; bitpos: [31:16]; default: 256; - * need_des - */ - uint32_t wait_pll_stable:16; - }; - uint32_t val; -} pmu_power_ck_wait_cntl_reg_t; - -/** Type of slp_wakeup_cntl0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** sleep_req : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t sleep_req:1; - }; - uint32_t val; -} pmu_slp_wakeup_cntl0_reg_t; - -/** Type of slp_wakeup_cntl1 register - * need_des - */ -typedef union { - struct { - /** sleep_reject_ena : R/W; bitpos: [30:0]; default: 0; - * need_des - */ - uint32_t sleep_reject_ena:31; - /** slp_reject_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t slp_reject_en:1; - }; - uint32_t val; -} pmu_slp_wakeup_cntl1_reg_t; - -/** Type of slp_wakeup_cntl2 register - * need_des - */ -typedef union { - struct { - /** wakeup_ena : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t wakeup_ena:32; - }; - uint32_t val; -} pmu_slp_wakeup_cntl2_reg_t; - -/** Type of slp_wakeup_cntl3 register - * need_des - */ -typedef union { - struct { - /** lp_min_slp_val : R/W; bitpos: [7:0]; default: 0; - * need_des - */ - uint32_t lp_min_slp_val:8; - /** hp_min_slp_val : R/W; bitpos: [15:8]; default: 0; - * need_des - */ - uint32_t hp_min_slp_val:8; - /** sleep_prt_sel : R/W; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t sleep_prt_sel:2; - uint32_t reserved_18:14; - }; - uint32_t val; -} pmu_slp_wakeup_cntl3_reg_t; - -/** Type of slp_wakeup_cntl4 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** slp_reject_cause_clr : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t slp_reject_cause_clr:1; - }; - uint32_t val; -} pmu_slp_wakeup_cntl4_reg_t; - -/** Type of slp_wakeup_cntl5 register - * need_des - */ -typedef union { - struct { - /** modem_wait_target : R/W; bitpos: [19:0]; default: 128; - * need_des - */ - uint32_t modem_wait_target:20; - uint32_t reserved_20:4; - /** lp_ana_wait_target : R/W; bitpos: [31:24]; default: 1; - * need_des - */ - uint32_t lp_ana_wait_target:8; - }; - uint32_t val; -} pmu_slp_wakeup_cntl5_reg_t; - -/** Type of slp_wakeup_cntl6 register - * need_des - */ -typedef union { - struct { - /** soc_wakeup_wait : R/W; bitpos: [19:0]; default: 128; - * need_des - */ - uint32_t soc_wakeup_wait:20; - uint32_t reserved_20:10; - /** soc_wakeup_wait_cfg : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t soc_wakeup_wait_cfg:2; - }; - uint32_t val; -} pmu_slp_wakeup_cntl6_reg_t; - -/** Type of slp_wakeup_cntl7 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:15; - /** ana_wait_clk_sel : R/W; bitpos: [15]; default: 0; - * need_des - */ - uint32_t ana_wait_clk_sel:1; - /** ana_wait_target : R/W; bitpos: [31:16]; default: 1; - * need_des - */ - uint32_t ana_wait_target:16; - }; - uint32_t val; -} pmu_slp_wakeup_cntl7_reg_t; - -/** Type of slp_wakeup_status0 register - * need_des - */ -typedef union { - struct { - /** wakeup_cause : RO; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t wakeup_cause:32; - }; - uint32_t val; -} pmu_slp_wakeup_status0_reg_t; - -/** Type of slp_wakeup_status1 register - * need_des - */ -typedef union { - struct { - /** reject_cause : RO; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t reject_cause:32; - }; - uint32_t val; -} pmu_slp_wakeup_status1_reg_t; - -/** Type of hp_ck_poweron register - * need_des - */ -typedef union { - struct { - /** i2c_por_wait_target : R/W; bitpos: [7:0]; default: 50; - * need_des - */ - uint32_t i2c_por_wait_target:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} pmu_hp_ck_poweron_reg_t; - -/** Type of hp_ck_cntl register - * need_des - */ -typedef union { - struct { - /** modify_icg_cntl_wait : R/W; bitpos: [7:0]; default: 10; - * need_des - */ - uint32_t modify_icg_cntl_wait:8; - /** switch_icg_cntl_wait : R/W; bitpos: [15:8]; default: 10; - * need_des - */ - uint32_t switch_icg_cntl_wait:8; - uint32_t reserved_16:16; - }; - uint32_t val; -} pmu_hp_ck_cntl_reg_t; - -/** Type of por_status register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** por_done : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t por_done:1; - }; - uint32_t val; -} pmu_por_status_reg_t; - -/** Type of rf_pwc register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** xpd_force_rftx : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t xpd_force_rftx:1; - /** xpd_perif_i2c : R/W; bitpos: [27]; default: 1; - * need_des - */ - uint32_t xpd_perif_i2c:1; - /** xpd_rftx_i2c : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t xpd_rftx_i2c:1; - /** xpd_rfrx_i2c : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t xpd_rfrx_i2c:1; - /** xpd_rfpll : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t xpd_rfpll:1; - /** xpd_force_rfpll : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t xpd_force_rfpll:1; - }; - uint32_t val; -} pmu_rf_pwc_reg_t; - -/** Type of vddbat_cfg register - * need_des - */ -typedef union { - struct { - /** vddbat_mode : RO; bitpos: [1:0]; default: 0; - * need_des - */ - uint32_t vddbat_mode:2; - uint32_t reserved_2:29; - /** vddbat_sw_update : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t vddbat_sw_update:1; - }; - uint32_t val; -} pmu_vddbat_cfg_reg_t; - -/** Type of backup_cfg register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** backup_sys_clk_no_div : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t backup_sys_clk_no_div:1; - }; - uint32_t val; -} pmu_backup_cfg_reg_t; - -/** Type of int_raw register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** lp_cpu_exc_int_raw : R/WTC/SS; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_raw:1; - /** sdio_idle_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_raw:1; - /** sw_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_raw:1; - /** soc_sleep_reject_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_raw:1; - /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_raw:1; - }; - uint32_t val; -} pmu_int_raw_reg_t; - -/** Type of hp_int_st register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** lp_cpu_exc_int_st : RO; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_st:1; - /** sdio_idle_int_st : RO; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_st:1; - /** sw_int_st : RO; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_st:1; - /** soc_sleep_reject_int_st : RO; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_st:1; - /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_st:1; - }; - uint32_t val; -} pmu_hp_int_st_reg_t; - -/** Type of hp_int_ena register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** lp_cpu_exc_int_ena : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_ena:1; - /** sdio_idle_int_ena : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_ena:1; - /** sw_int_ena : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_ena:1; - /** soc_sleep_reject_int_ena : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_ena:1; - /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_ena:1; - }; - uint32_t val; -} pmu_hp_int_ena_reg_t; - -/** Type of hp_int_clr register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** lp_cpu_exc_int_clr : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_clr:1; - /** sdio_idle_int_clr : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_clr:1; - /** sw_int_clr : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_clr:1; - /** soc_sleep_reject_int_clr : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_clr:1; - /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_clr:1; - }; - uint32_t val; -} pmu_hp_int_clr_reg_t; - -/** Type of lp_int_raw register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** lp_cpu_wakeup_int_raw : R/WTC/SS; bitpos: [20]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_raw:1; - /** modem_switch_active_end_int_raw : R/WTC/SS; bitpos: [21]; default: 0; - * need_des - */ - uint32_t modem_switch_active_end_int_raw:1; - /** sleep_switch_active_end_int_raw : R/WTC/SS; bitpos: [22]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_raw:1; - /** sleep_switch_modem_end_int_raw : R/WTC/SS; bitpos: [23]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_end_int_raw:1; - /** modem_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [24]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_end_int_raw:1; - /** active_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [25]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_raw:1; - /** modem_switch_active_start_int_raw : R/WTC/SS; bitpos: [26]; default: 0; - * need_des - */ - uint32_t modem_switch_active_start_int_raw:1; - /** sleep_switch_active_start_int_raw : R/WTC/SS; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_raw:1; - /** sleep_switch_modem_start_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_start_int_raw:1; - /** modem_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_start_int_raw:1; - /** active_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_raw:1; - /** hp_sw_trigger_int_raw : R/WTC/SS; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_raw:1; - }; - uint32_t val; -} pmu_lp_int_raw_reg_t; - -/** Type of lp_int_st register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** lp_cpu_wakeup_int_st : RO; bitpos: [20]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_st:1; - /** modem_switch_active_end_int_st : RO; bitpos: [21]; default: 0; - * need_des - */ - uint32_t modem_switch_active_end_int_st:1; - /** sleep_switch_active_end_int_st : RO; bitpos: [22]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_st:1; - /** sleep_switch_modem_end_int_st : RO; bitpos: [23]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_end_int_st:1; - /** modem_switch_sleep_end_int_st : RO; bitpos: [24]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_end_int_st:1; - /** active_switch_sleep_end_int_st : RO; bitpos: [25]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_st:1; - /** modem_switch_active_start_int_st : RO; bitpos: [26]; default: 0; - * need_des - */ - uint32_t modem_switch_active_start_int_st:1; - /** sleep_switch_active_start_int_st : RO; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_st:1; - /** sleep_switch_modem_start_int_st : RO; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_start_int_st:1; - /** modem_switch_sleep_start_int_st : RO; bitpos: [29]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_start_int_st:1; - /** active_switch_sleep_start_int_st : RO; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_st:1; - /** hp_sw_trigger_int_st : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_st:1; - }; - uint32_t val; -} pmu_lp_int_st_reg_t; - -/** Type of lp_int_ena register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** lp_cpu_wakeup_int_ena : R/W; bitpos: [20]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_ena:1; - /** modem_switch_active_end_int_ena : R/W; bitpos: [21]; default: 0; - * need_des - */ - uint32_t modem_switch_active_end_int_ena:1; - /** sleep_switch_active_end_int_ena : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_ena:1; - /** sleep_switch_modem_end_int_ena : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_end_int_ena:1; - /** modem_switch_sleep_end_int_ena : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_end_int_ena:1; - /** active_switch_sleep_end_int_ena : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_ena:1; - /** modem_switch_active_start_int_ena : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t modem_switch_active_start_int_ena:1; - /** sleep_switch_active_start_int_ena : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_ena:1; - /** sleep_switch_modem_start_int_ena : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_start_int_ena:1; - /** modem_switch_sleep_start_int_ena : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_start_int_ena:1; - /** active_switch_sleep_start_int_ena : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_ena:1; - /** hp_sw_trigger_int_ena : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_ena:1; - }; - uint32_t val; -} pmu_lp_int_ena_reg_t; - -/** Type of lp_int_clr register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** lp_cpu_wakeup_int_clr : WT; bitpos: [20]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_clr:1; - /** modem_switch_active_end_int_clr : WT; bitpos: [21]; default: 0; - * need_des - */ - uint32_t modem_switch_active_end_int_clr:1; - /** sleep_switch_active_end_int_clr : WT; bitpos: [22]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_clr:1; - /** sleep_switch_modem_end_int_clr : WT; bitpos: [23]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_end_int_clr:1; - /** modem_switch_sleep_end_int_clr : WT; bitpos: [24]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_end_int_clr:1; - /** active_switch_sleep_end_int_clr : WT; bitpos: [25]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_clr:1; - /** modem_switch_active_start_int_clr : WT; bitpos: [26]; default: 0; - * need_des - */ - uint32_t modem_switch_active_start_int_clr:1; - /** sleep_switch_active_start_int_clr : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_clr:1; - /** sleep_switch_modem_start_int_clr : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_start_int_clr:1; - /** modem_switch_sleep_start_int_clr : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_start_int_clr:1; - /** active_switch_sleep_start_int_clr : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_clr:1; - /** hp_sw_trigger_int_clr : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_clr:1; - }; - uint32_t val; -} pmu_lp_int_clr_reg_t; - -/** Type of lp_cpu_pwr0 register - * need_des - */ -typedef union { - struct { - /** lp_cpu_waiti_rdy : RO; bitpos: [0]; default: 0; - * need_des - */ - uint32_t lp_cpu_waiti_rdy:1; - /** lp_cpu_stall_rdy : RO; bitpos: [1]; default: 0; - * need_des - */ - uint32_t lp_cpu_stall_rdy:1; - uint32_t reserved_2:16; - /** lp_cpu_force_stall : R/W; bitpos: [18]; default: 0; - * need_des - */ - uint32_t lp_cpu_force_stall:1; - /** lp_cpu_slp_waiti_flag_en : R/W; bitpos: [19]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_waiti_flag_en:1; - /** lp_cpu_slp_stall_flag_en : R/W; bitpos: [20]; default: 1; - * need_des - */ - uint32_t lp_cpu_slp_stall_flag_en:1; - /** lp_cpu_slp_stall_wait : R/W; bitpos: [28:21]; default: 255; - * need_des - */ - uint32_t lp_cpu_slp_stall_wait:8; - /** lp_cpu_slp_stall_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_stall_en:1; - /** lp_cpu_slp_reset_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_reset_en:1; - /** lp_cpu_slp_bypass_intr_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_bypass_intr_en:1; - }; - uint32_t val; -} pmu_lp_cpu_pwr0_reg_t; - -/** Type of lp_cpu_pwr1 register - * need_des - */ -typedef union { - struct { - /** lp_cpu_wakeup_en : R/W; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_en:16; - uint32_t reserved_16:15; - /** lp_cpu_sleep_req : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_cpu_sleep_req:1; - }; - uint32_t val; -} pmu_lp_cpu_pwr1_reg_t; - -/** Type of hp_lp_cpu_comm register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** lp_trigger_hp : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_trigger_hp:1; - /** hp_trigger_lp : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_trigger_lp:1; - }; - uint32_t val; -} pmu_hp_lp_cpu_comm_reg_t; - -/** Type of hp_regulator_cfg register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** dig_regulator_en_cal : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t dig_regulator_en_cal:1; - }; - uint32_t val; -} pmu_hp_regulator_cfg_reg_t; - -/** Type of main_state register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:11; - /** main_last_st_state : RO; bitpos: [17:11]; default: 256; - * need_des - */ - uint32_t main_last_st_state:7; - /** main_tar_st_state : RO; bitpos: [24:18]; default: 4; - * need_des - */ - uint32_t main_tar_st_state:7; - /** main_cur_st_state : RO; bitpos: [31:25]; default: 1; - * need_des - */ - uint32_t main_cur_st_state:7; - }; - uint32_t val; -} pmu_main_state_reg_t; - -/** Type of pwr_state register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:13; - /** backup_st_state : RO; bitpos: [17:13]; default: 1; - * need_des - */ - uint32_t backup_st_state:5; - /** lp_pwr_st_state : RO; bitpos: [22:18]; default: 0; - * need_des - */ - uint32_t lp_pwr_st_state:5; - /** hp_pwr_st_state : RO; bitpos: [31:23]; default: 1; - * need_des - */ - uint32_t hp_pwr_st_state:9; - }; - uint32_t val; -} pmu_pwr_state_reg_t; - -/** Type of dcm_ctrl register - * need_des - */ -typedef union { - struct { - /** dsfmos_use_por : R/W; bitpos: [0]; default: 1; - * need_des - */ - uint32_t dsfmos_use_por:1; - uint32_t reserved_1:21; - /** dcdc_dcm_update : WT; bitpos: [22]; default: 0; - * need_des - */ - uint32_t dcdc_dcm_update:1; - /** dcdc_pcur_limit : R/W; bitpos: [25:23]; default: 1; - * need_des - */ - uint32_t dcdc_pcur_limit:3; - /** dcdc_bias_cal_done : RO; bitpos: [26]; default: 1; - * need_des - */ - uint32_t dcdc_bias_cal_done:1; - /** dcdc_ccm_sw_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t dcdc_ccm_sw_en:1; - /** dcdc_vcm_enb : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t dcdc_vcm_enb:1; - /** dcdc_ccm_rdy : RO; bitpos: [29]; default: 0; - * need_des - */ - uint32_t dcdc_ccm_rdy:1; - /** dcdc_vcm_rdy : RO; bitpos: [30]; default: 1; - * need_des - */ - uint32_t dcdc_vcm_rdy:1; - /** dcdc_rdy_clr : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t dcdc_rdy_clr:1; - }; - uint32_t val; -} pmu_dcm_ctrl_reg_t; - -/** Type of dcm_boost_ctrl register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:24; - /** dcdc_boost_ccm_ctrlen : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t dcdc_boost_ccm_ctrlen:1; - /** dcdc_boost_ccm_enb : R/W; bitpos: [25]; default: 1; - * need_des - */ - uint32_t dcdc_boost_ccm_enb:1; - /** dcdc_boost_en : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t dcdc_boost_en:1; - /** dcdc_boost_dreg : R/W; bitpos: [31:27]; default: 23; - * need_des - */ - uint32_t dcdc_boost_dreg:5; - }; - uint32_t val; -} pmu_dcm_boost_ctrl_reg_t; - -/** Type of touch_pwr_ctrl register - * need_des - */ -typedef union { - struct { - /** touch_sleep_cycles : R/W; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t touch_sleep_cycles:16; - uint32_t reserved_16:5; - /** touch_wait_cycles : R/W; bitpos: [29:21]; default: 0; - * need_des - */ - uint32_t touch_wait_cycles:9; - /** touch_sleep_timer_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t touch_sleep_timer_en:1; - /** touch_force_done : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t touch_force_done:1; - }; - uint32_t val; -} pmu_touch_pwr_ctrl_reg_t; - -/** Type of ble_bandgap_ctrl register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** ext_ocode : R/W; bitpos: [30:23]; default: 120; - * need_des - */ - uint32_t ext_ocode:8; - /** ext_force_ocode : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t ext_force_ocode:1; - }; - uint32_t val; -} pmu_ble_bandgap_ctrl_reg_t; - -/** Type of date register - * need_des - */ -typedef union { - struct { - /** pmu_date : R/W; bitpos: [30:0]; default: 38814336; - * need_des - */ - uint32_t pmu_date:31; - /** clk_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t clk_en:1; - }; - uint32_t val; -} pmu_date_reg_t; - - -/** Group: status_register */ -/** Type of clk_state0 register - * need_des - */ -typedef union { - struct { - /** stable_xpd_bbpll_state : RO; bitpos: [0]; default: 0; - * need_des - */ - uint32_t stable_xpd_bbpll_state:1; - /** stable_xpd_xtal_state : RO; bitpos: [1]; default: 0; - * need_des - */ - uint32_t stable_xpd_xtal_state:1; - uint32_t reserved_2:13; - /** sys_clk_slp_sel_state : RO; bitpos: [15]; default: 0; - * need_des - */ - uint32_t sys_clk_slp_sel_state:1; - /** sys_clk_sel_state : RO; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t sys_clk_sel_state:2; - /** sys_clk_no_div_state : RO; bitpos: [18]; default: 0; - * need_des - */ - uint32_t sys_clk_no_div_state:1; - /** icg_sys_clk_en_state : RO; bitpos: [19]; default: 1; - * need_des - */ - uint32_t icg_sys_clk_en_state:1; - /** icg_modem_switch_state : RO; bitpos: [20]; default: 0; - * need_des - */ - uint32_t icg_modem_switch_state:1; - /** icg_modem_code_state : RO; bitpos: [22:21]; default: 0; - * need_des - */ - uint32_t icg_modem_code_state:2; - /** icg_slp_sel_state : RO; bitpos: [23]; default: 0; - * need_des - */ - uint32_t icg_slp_sel_state:1; - /** icg_global_xtal_state : RO; bitpos: [24]; default: 0; - * need_des - */ - uint32_t icg_global_xtal_state:1; - /** icg_global_pll_state : RO; bitpos: [25]; default: 0; - * need_des - */ - uint32_t icg_global_pll_state:1; - /** ana_i2c_iso_en_state : RO; bitpos: [26]; default: 0; - * need_des - */ - uint32_t ana_i2c_iso_en_state:1; - /** ana_i2c_retention_state : RO; bitpos: [27]; default: 0; - * need_des - */ - uint32_t ana_i2c_retention_state:1; - /** ana_xpd_bb_i2c_state : RO; bitpos: [28]; default: 0; - * need_des - */ - uint32_t ana_xpd_bb_i2c_state:1; - /** ana_xpd_bbpll_i2c_state : RO; bitpos: [29]; default: 0; - * need_des - */ - uint32_t ana_xpd_bbpll_i2c_state:1; - /** ana_xpd_bbpll_state : RO; bitpos: [30]; default: 0; - * need_des - */ - uint32_t ana_xpd_bbpll_state:1; - /** ana_xpd_xtal_state : RO; bitpos: [31]; default: 1; - * need_des - */ - uint32_t ana_xpd_xtal_state:1; - }; - uint32_t val; -} pmu_clk_state0_reg_t; - -/** Type of clk_state1 register - * need_des - */ -typedef union { - struct { - /** icg_func_en_state : RO; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t icg_func_en_state:32; - }; - uint32_t val; -} pmu_clk_state1_reg_t; - -/** Type of clk_state2 register - * need_des - */ -typedef union { - struct { - /** icg_apb_en_state : RO; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t icg_apb_en_state:32; - }; - uint32_t val; -} pmu_clk_state2_reg_t; - - -typedef struct { - volatile pmu_hp_active_dig_power_reg_t hp_active_dig_power; - volatile pmu_hp_active_icg_hp_func_reg_t hp_active_icg_hp_func; - volatile pmu_hp_active_icg_hp_apb_reg_t hp_active_icg_hp_apb; - volatile pmu_hp_active_icg_modem_reg_t hp_active_icg_modem; - volatile pmu_hp_active_hp_sys_cntl_reg_t hp_active_hp_sys_cntl; - volatile pmu_hp_active_hp_ck_power_reg_t hp_active_hp_ck_power; - volatile pmu_hp_active_bias_reg_t hp_active_bias; - volatile pmu_hp_active_backup_reg_t hp_active_backup; - volatile pmu_hp_active_backup_clk_reg_t hp_active_backup_clk; - volatile pmu_hp_active_sysclk_reg_t hp_active_sysclk; - volatile pmu_hp_active_hp_regulator0_reg_t hp_active_hp_regulator0; - volatile pmu_hp_active_hp_regulator1_reg_t hp_active_hp_regulator1; - volatile pmu_hp_active_xtal_reg_t hp_active_xtal; - uint32_t reserved_034[13]; - volatile pmu_hp_sleep_dig_power_reg_t hp_sleep_dig_power; - volatile pmu_hp_sleep_icg_hp_func_reg_t hp_sleep_icg_hp_func; - volatile pmu_hp_sleep_icg_hp_apb_reg_t hp_sleep_icg_hp_apb; - volatile pmu_hp_sleep_icg_modem_reg_t hp_sleep_icg_modem; - volatile pmu_hp_sleep_hp_sys_cntl_reg_t hp_sleep_hp_sys_cntl; - volatile pmu_hp_sleep_hp_ck_power_reg_t hp_sleep_hp_ck_power; - volatile pmu_hp_sleep_bias_reg_t hp_sleep_bias; - volatile pmu_hp_sleep_backup_reg_t hp_sleep_backup; - volatile pmu_hp_sleep_backup_clk_reg_t hp_sleep_backup_clk; - volatile pmu_hp_sleep_sysclk_reg_t hp_sleep_sysclk; - volatile pmu_hp_sleep_hp_regulator0_reg_t hp_sleep_hp_regulator0; - volatile pmu_hp_sleep_hp_regulator1_reg_t hp_sleep_hp_regulator1; - volatile pmu_hp_sleep_xtal_reg_t hp_sleep_xtal; - volatile pmu_hp_sleep_lp_regulator0_reg_t hp_sleep_lp_regulator0; - volatile pmu_hp_sleep_lp_regulator1_reg_t hp_sleep_lp_regulator1; - uint32_t reserved_0a4; - volatile pmu_hp_sleep_lp_dig_power_reg_t hp_sleep_lp_dig_power; - volatile pmu_hp_sleep_lp_ck_power_reg_t hp_sleep_lp_ck_power; - uint32_t reserved_0b0; - volatile pmu_lp_sleep_lp_regulator0_reg_t lp_sleep_lp_regulator0; - volatile pmu_lp_sleep_lp_regulator1_reg_t lp_sleep_lp_regulator1; - volatile pmu_lp_sleep_xtal_reg_t lp_sleep_xtal; - volatile pmu_lp_sleep_lp_dig_power_reg_t lp_sleep_lp_dig_power; - volatile pmu_lp_sleep_lp_ck_power_reg_t lp_sleep_lp_ck_power; - volatile pmu_lp_sleep_bias_reg_t lp_sleep_bias; - volatile pmu_imm_hp_ck_power_reg_t imm_hp_ck_power; - volatile pmu_imm_sleep_sysclk_reg_t imm_sleep_sysclk; - volatile pmu_imm_hp_func_icg_reg_t imm_hp_func_icg; - volatile pmu_imm_hp_apb_icg_reg_t imm_hp_apb_icg; - volatile pmu_imm_modem_icg_reg_t imm_modem_icg; - volatile pmu_imm_lp_icg_reg_t imm_lp_icg; - volatile pmu_imm_pad_hold_all_reg_t imm_pad_hold_all; - volatile pmu_imm_i2c_iso_reg_t imm_i2c_iso; - volatile pmu_power_wait_timer0_reg_t power_wait_timer0; - volatile pmu_power_wait_timer1_reg_t power_wait_timer1; - volatile pmu_power_wait_timer2_reg_t power_wait_timer2; - volatile pmu_power_pd_top_cntl_reg_t power_pd_top_cntl; - volatile pmu_power_pd_hpaon_cntl_reg_t power_pd_hpaon_cntl; - volatile pmu_power_pd_hpcpu_cntl_reg_t power_pd_hpcpu_cntl; - volatile pmu_power_pd_hpperi_reserve_reg_t power_pd_hpperi_reserve; - volatile pmu_power_pd_hpwifi_cntl_reg_t power_pd_hpwifi_cntl; - volatile pmu_power_pd_lpperi_cntl_reg_t power_pd_lpperi_cntl; - volatile pmu_power_pd_mem_cntl_reg_t power_pd_mem_cntl; - volatile pmu_power_pd_mem_mask_reg_t power_pd_mem_mask; - volatile pmu_power_hp_pad_reg_t power_hp_pad; - volatile pmu_power_flash1p8_ldo_reg_t power_flash1p8_ldo; - volatile pmu_power_flash1p2_ldo_reg_t power_flash1p2_ldo; - volatile pmu_power_vdd_flash_reg_t power_vdd_flash; - volatile pmu_power_io_ldo_reg_t power_io_ldo; - volatile pmu_power_vdd_io_reg_t power_vdd_io; - volatile pmu_power_ck_wait_cntl_reg_t power_ck_wait_cntl; - volatile pmu_slp_wakeup_cntl0_reg_t slp_wakeup_cntl0; - volatile pmu_slp_wakeup_cntl1_reg_t slp_wakeup_cntl1; - volatile pmu_slp_wakeup_cntl2_reg_t slp_wakeup_cntl2; - volatile pmu_slp_wakeup_cntl3_reg_t slp_wakeup_cntl3; - volatile pmu_slp_wakeup_cntl4_reg_t slp_wakeup_cntl4; - volatile pmu_slp_wakeup_cntl5_reg_t slp_wakeup_cntl5; - volatile pmu_slp_wakeup_cntl6_reg_t slp_wakeup_cntl6; - volatile pmu_slp_wakeup_cntl7_reg_t slp_wakeup_cntl7; - volatile pmu_slp_wakeup_status0_reg_t slp_wakeup_status0; - volatile pmu_slp_wakeup_status1_reg_t slp_wakeup_status1; - volatile pmu_hp_ck_poweron_reg_t hp_ck_poweron; - volatile pmu_hp_ck_cntl_reg_t hp_ck_cntl; - volatile pmu_por_status_reg_t por_status; - volatile pmu_rf_pwc_reg_t rf_pwc; - volatile pmu_vddbat_cfg_reg_t vddbat_cfg; - volatile pmu_backup_cfg_reg_t backup_cfg; - volatile pmu_int_raw_reg_t int_raw; - volatile pmu_hp_int_st_reg_t hp_int_st; - volatile pmu_hp_int_ena_reg_t hp_int_ena; - volatile pmu_hp_int_clr_reg_t hp_int_clr; - volatile pmu_lp_int_raw_reg_t lp_int_raw; - volatile pmu_lp_int_st_reg_t lp_int_st; - volatile pmu_lp_int_ena_reg_t lp_int_ena; - volatile pmu_lp_int_clr_reg_t lp_int_clr; - volatile pmu_lp_cpu_pwr0_reg_t lp_cpu_pwr0; - volatile pmu_lp_cpu_pwr1_reg_t lp_cpu_pwr1; - volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_comm; - volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg; - volatile pmu_main_state_reg_t main_state; - volatile pmu_pwr_state_reg_t pwr_state; - volatile pmu_clk_state0_reg_t clk_state0; - volatile pmu_clk_state1_reg_t clk_state1; - volatile pmu_clk_state2_reg_t clk_state2; - volatile pmu_dcm_ctrl_reg_t dcm_ctrl; - volatile pmu_dcm_boost_ctrl_reg_t dcm_boost_ctrl; - volatile pmu_touch_pwr_ctrl_reg_t touch_pwr_ctrl; - volatile pmu_ble_bandgap_ctrl_reg_t ble_bandgap_ctrl; - uint32_t reserved_1c8[141]; - volatile pmu_date_reg_t date; -} pmu_dev_t; - - -#ifndef __cplusplus -_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif