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gdma: fix potential unaligned cache writeback issue

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This commit is contained in:
Armando
2023-02-22 19:20:15 +08:00
parent 1ecd1e3bf0
commit 663e881868
3 changed files with 4 additions and 6 deletions
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5
components/esp_hw_support/dma/gdma.c
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@@ -18,6 +18,7 @@
#include "esp_memory_utils.h" #include "esp_memory_utils.h"
#include "esp_private/periph_ctrl.h" #include "esp_private/periph_ctrl.h"
#include "gdma_priv.h" #include "gdma_priv.h"
#include "hal/cache_hal.h"
static const char *TAG = "gdma"; static const char *TAG = "gdma";
@@ -290,6 +291,7 @@ esp_err_t gdma_set_transfer_ability(gdma_channel_handle_t dma_chan, const gdma_t
ESP_GOTO_ON_FALSE((sram_alignment & (sram_alignment - 1)) == 0, ESP_ERR_INVALID_ARG, err, TAG, "invalid sram alignment: %zu", sram_alignment); ESP_GOTO_ON_FALSE((sram_alignment & (sram_alignment - 1)) == 0, ESP_ERR_INVALID_ARG, err, TAG, "invalid sram alignment: %zu", sram_alignment);
#if SOC_GDMA_SUPPORT_PSRAM #if SOC_GDMA_SUPPORT_PSRAM
uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_TYPE_DATA);
int block_size_index = 0; int block_size_index = 0;
switch (psram_alignment) { switch (psram_alignment) {
case 64: // 64 Bytes alignment case 64: // 64 Bytes alignment
@@ -303,12 +305,13 @@ esp_err_t gdma_set_transfer_ability(gdma_channel_handle_t dma_chan, const gdma_t
break; break;
case 0: // no alignment is requirement case 0: // no alignment is requirement
block_size_index = GDMA_LL_EXT_MEM_BK_SIZE_16B; block_size_index = GDMA_LL_EXT_MEM_BK_SIZE_16B;
psram_alignment = SOC_GDMA_PSRAM_MIN_ALIGN; // fall back to minimal alignment psram_alignment = data_cache_line_size; // fall back to use the same size of the psram data cache line size
break; break;
default: default:
ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "invalid psram alignment: %zu", psram_alignment); ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "invalid psram alignment: %zu", psram_alignment);
break; break;
} }
ESP_GOTO_ON_FALSE(((psram_alignment % data_cache_line_size) == 0), ESP_ERR_INVALID_ARG, err, TAG, "psram alignment (%d)B should be multiple of the data cache line size (%d)B", psram_alignment, data_cache_line_size);
#endif // #if SOC_GDMA_SUPPORT_PSRAM #endif // #if SOC_GDMA_SUPPORT_PSRAM
if (dma_chan->direction == GDMA_CHANNEL_DIRECTION_TX) { if (dma_chan->direction == GDMA_CHANNEL_DIRECTION_TX) {

4
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
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@@ -363,10 +363,6 @@ config SOC_GDMA_SUPPORT_PSRAM
bool bool
default y default y
config SOC_GDMA_PSRAM_MIN_ALIGN
int
default 16
config SOC_GPIO_PORT config SOC_GPIO_PORT
int int
default 1 default 1

1
components/soc/esp32s3/include/soc/soc_caps.h
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@@ -145,7 +145,6 @@
#define SOC_GDMA_GROUPS (1) // Number of GDMA groups #define SOC_GDMA_GROUPS (1) // Number of GDMA groups
#define SOC_GDMA_PAIRS_PER_GROUP (5) // Number of GDMA pairs in each group #define SOC_GDMA_PAIRS_PER_GROUP (5) // Number of GDMA pairs in each group
#define SOC_GDMA_SUPPORT_PSRAM (1) // GDMA can access external PSRAM #define SOC_GDMA_SUPPORT_PSRAM (1) // GDMA can access external PSRAM
#define SOC_GDMA_PSRAM_MIN_ALIGN (16) // Minimal alignment for PSRAM transaction
/*-------------------------- GPIO CAPS ---------------------------------------*/ /*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-S3 has 1 GPIO peripheral // ESP32-S3 has 1 GPIO peripheral