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esp32-h2 beta2: update to the latest regs

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This commit is contained in:
laokaiyao
2022-03-18 15:30:00 +08:00
committed by Kevin (Lao Kaiyao)
parent c1bcb8756b
commit 667c7f94e6
4 changed files with 102 additions and 86 deletions
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21
components/soc/esp32h2/include/rev2/soc/clkrst_reg.h
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@@ -1,8 +1,9 @@
/** /*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#pragma once #pragma once
#include <stdint.h> #include <stdint.h>
@@ -121,6 +122,13 @@ extern "C" {
#define SYSTEM_COEX_LPCLK_DIV_M (SYSTEM_COEX_LPCLK_DIV_V << SYSTEM_COEX_LPCLK_DIV_S) #define SYSTEM_COEX_LPCLK_DIV_M (SYSTEM_COEX_LPCLK_DIV_V << SYSTEM_COEX_LPCLK_DIV_S)
#define SYSTEM_COEX_LPCLK_DIV_V 0x000003FFU #define SYSTEM_COEX_LPCLK_DIV_V 0x000003FFU
#define SYSTEM_COEX_LPCLK_DIV_S 6 #define SYSTEM_COEX_LPCLK_DIV_S 6
/** SYSTEM_BT_DFM_CLK_INV_PHASE : R/W; bitpos: [17:16]; default: 0;
* Need add description
*/
#define SYSTEM_BT_DFM_CLK_INV_PHASE 0x00000003U
#define SYSTEM_BT_DFM_CLK_INV_PHASE_M (SYSTEM_BT_DFM_CLK_INV_PHASE_V << SYSTEM_BT_DFM_CLK_INV_PHASE_S)
#define SYSTEM_BT_DFM_CLK_INV_PHASE_V 0x00000003U
#define SYSTEM_BT_DFM_CLK_INV_PHASE_S 16
/** SYSTEM_CLK_OUT_EN_REG register /** SYSTEM_CLK_OUT_EN_REG register
* register description * register description
@@ -355,6 +363,13 @@ extern "C" {
#define SYSTEM_DATA_DUMP_CLK_EN_M (SYSTEM_DATA_DUMP_CLK_EN_V << SYSTEM_DATA_DUMP_CLK_EN_S) #define SYSTEM_DATA_DUMP_CLK_EN_M (SYSTEM_DATA_DUMP_CLK_EN_V << SYSTEM_DATA_DUMP_CLK_EN_S)
#define SYSTEM_DATA_DUMP_CLK_EN_V 0x00000001U #define SYSTEM_DATA_DUMP_CLK_EN_V 0x00000001U
#define SYSTEM_DATA_DUMP_CLK_EN_S 21 #define SYSTEM_DATA_DUMP_CLK_EN_S 21
/** SYSTEM_BT_DFM_CLK_EN : R/W; bitpos: [22]; default: 0;
* Need add description
*/
#define SYSTEM_BT_DFM_CLK_EN (BIT(22))
#define SYSTEM_BT_DFM_CLK_EN_M (SYSTEM_BT_DFM_CLK_EN_V << SYSTEM_BT_DFM_CLK_EN_S)
#define SYSTEM_BT_DFM_CLK_EN_V 0x00000001U
#define SYSTEM_BT_DFM_CLK_EN_S 22
/** SYSTEM_MODEM_RST_EN_REG register /** SYSTEM_MODEM_RST_EN_REG register
* register description * register description
@@ -1261,7 +1276,7 @@ extern "C" {
* register description * register description
*/ */
#define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0x38) #define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0x38)
/** SYSTEM_DATE : R/W; bitpos: [27:0]; default: 34640435; /** SYSTEM_DATE : R/W; bitpos: [27:0]; default: 34672962;
* Need add description * Need add description
*/ */
#define SYSTEM_DATE 0x0FFFFFFFU #define SYSTEM_DATE 0x0FFFFFFFU

53
components/soc/esp32h2/include/rev2/soc/ecc_mult_reg.h
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@@ -1,8 +1,9 @@
/** /*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#pragma once #pragma once
#include <stdint.h> #include <stdint.h>
@@ -12,11 +13,11 @@ extern "C" {
#endif #endif
/** ECC_MULT_INT_RAW_REG register /** ECC_MULT_INT_RAW_REG register
* Add later. * ECC interrupt raw register, valid in level.
*/ */
#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc) #define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; /** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* Add later. * The raw interrupt status bit for the ecc calculate done interrupt
*/ */
#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0)) #define ECC_MULT_CALC_DONE_INT_RAW (BIT(0))
#define ECC_MULT_CALC_DONE_INT_RAW_M (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S) #define ECC_MULT_CALC_DONE_INT_RAW_M (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
@@ -24,11 +25,11 @@ extern "C" {
#define ECC_MULT_CALC_DONE_INT_RAW_S 0 #define ECC_MULT_CALC_DONE_INT_RAW_S 0
/** ECC_MULT_INT_ST_REG register /** ECC_MULT_INT_ST_REG register
* Add later. * ECC interrupt status register.
*/ */
#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10) #define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0; /** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* Add later. * The masked interrupt status bit for the ecc calculate done interrupt
*/ */
#define ECC_MULT_CALC_DONE_INT_ST (BIT(0)) #define ECC_MULT_CALC_DONE_INT_ST (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ST_M (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S) #define ECC_MULT_CALC_DONE_INT_ST_M (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
@@ -36,11 +37,11 @@ extern "C" {
#define ECC_MULT_CALC_DONE_INT_ST_S 0 #define ECC_MULT_CALC_DONE_INT_ST_S 0
/** ECC_MULT_INT_ENA_REG register /** ECC_MULT_INT_ENA_REG register
* Add later. * ECC interrupt enable register.
*/ */
#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14) #define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; /** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* Add later. * The interrupt enable bit for the ecc calculate done interrupt
*/ */
#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0)) #define ECC_MULT_CALC_DONE_INT_ENA (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ENA_M (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S) #define ECC_MULT_CALC_DONE_INT_ENA_M (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
@@ -48,11 +49,11 @@ extern "C" {
#define ECC_MULT_CALC_DONE_INT_ENA_S 0 #define ECC_MULT_CALC_DONE_INT_ENA_S 0
/** ECC_MULT_INT_CLR_REG register /** ECC_MULT_INT_CLR_REG register
* Add later. * ECC interrupt clear register.
*/ */
#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18) #define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0; /** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Add later. * Set this bit to clear the ecc calculate done interrupt
*/ */
#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0)) #define ECC_MULT_CALC_DONE_INT_CLR (BIT(0))
#define ECC_MULT_CALC_DONE_INT_CLR_M (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S) #define ECC_MULT_CALC_DONE_INT_CLR_M (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
@@ -60,64 +61,64 @@ extern "C" {
#define ECC_MULT_CALC_DONE_INT_CLR_S 0 #define ECC_MULT_CALC_DONE_INT_CLR_S 0
/** ECC_MULT_CONF_REG register /** ECC_MULT_CONF_REG register
* Add later. * ECC configure register
*/ */
#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c) #define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0; /** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
* Add later. * Set this bit to start a ECC operation.
*/ */
#define ECC_MULT_START (BIT(0)) #define ECC_MULT_START (BIT(0))
#define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S) #define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S)
#define ECC_MULT_START_V 0x00000001U #define ECC_MULT_START_V 0x00000001U
#define ECC_MULT_START_S 0 #define ECC_MULT_START_S 0
/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0; /** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
* Add later. * Set this bit to reset ECC
*/ */
#define ECC_MULT_RESET (BIT(1)) #define ECC_MULT_RESET (BIT(1))
#define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S) #define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
#define ECC_MULT_RESET_V 0x00000001U #define ECC_MULT_RESET_V 0x00000001U
#define ECC_MULT_RESET_S 1 #define ECC_MULT_RESET_S 1
/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0; /** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0;
* Add later. * 0:192bit key length mode. 1:256bit key length mode
*/ */
#define ECC_MULT_KEY_LENGTH (BIT(2)) #define ECC_MULT_KEY_LENGTH (BIT(2))
#define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S) #define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
#define ECC_MULT_KEY_LENGTH_V 0x00000001U #define ECC_MULT_KEY_LENGTH_V 0x00000001U
#define ECC_MULT_KEY_LENGTH_S 2 #define ECC_MULT_KEY_LENGTH_S 2
/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [3]; default: 0; /** ECC_MULT_SECURITY_MODE : R/W; bitpos: [3]; default: 0;
* Add later. * Reserved
*/ */
#define ECC_MULT_SECURITY_MODE (BIT(3)) #define ECC_MULT_SECURITY_MODE (BIT(3))
#define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S) #define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
#define ECC_MULT_SECURITY_MODE_V 0x00000001U #define ECC_MULT_SECURITY_MODE_V 0x00000001U
#define ECC_MULT_SECURITY_MODE_S 3 #define ECC_MULT_SECURITY_MODE_S 3
/** ECC_MULT_CLK_EN : R/W; bitpos: [4]; default: 0; /** ECC_MULT_CLK_EN : R/W; bitpos: [4]; default: 0;
* Add later. * clk gate
*/ */
#define ECC_MULT_CLK_EN (BIT(4)) #define ECC_MULT_CLK_EN (BIT(4))
#define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S) #define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
#define ECC_MULT_CLK_EN_V 0x00000001U #define ECC_MULT_CLK_EN_V 0x00000001U
#define ECC_MULT_CLK_EN_S 4 #define ECC_MULT_CLK_EN_S 4
/** ECC_MULT_WORK_MODE : R/W; bitpos: [6:5]; default: 0; /** ECC_MULT_WORK_MODE : R/W; bitpos: [7:5]; default: 0;
* Add later. * ECC operation mode register.
*/ */
#define ECC_MULT_WORK_MODE 0x00000003U #define ECC_MULT_WORK_MODE 0x00000007U
#define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S) #define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
#define ECC_MULT_WORK_MODE_V 0x00000003U #define ECC_MULT_WORK_MODE_V 0x00000007U
#define ECC_MULT_WORK_MODE_S 5 #define ECC_MULT_WORK_MODE_S 5
/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [7]; default: 0; /** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [8]; default: 0;
* Add later. * ECC verification result register.
*/ */
#define ECC_MULT_VERIFICATION_RESULT (BIT(7)) #define ECC_MULT_VERIFICATION_RESULT (BIT(8))
#define ECC_MULT_VERIFICATION_RESULT_M (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S) #define ECC_MULT_VERIFICATION_RESULT_M (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
#define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U #define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U
#define ECC_MULT_VERIFICATION_RESULT_S 7 #define ECC_MULT_VERIFICATION_RESULT_S 8
/** ECC_MULT_DATE_REG register /** ECC_MULT_DATE_REG register
* Add later. * Version control register
*/ */
#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc) #define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 33628720; /** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 34636176;
* ECC mult version control register * ECC mult version control register
*/ */
#define ECC_MULT_DATE 0x0FFFFFFFU #define ECC_MULT_DATE 0x0FFFFFFFU

48
components/soc/esp32h2/include/rev2/soc/ecc_mult_struct.h
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@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -12,12 +12,12 @@ extern "C" {
/** Group: Interrupt registers */ /** Group: Interrupt registers */
/** Type of int_raw register /** Type of int_raw register
* Add later. * ECC interrupt raw register, valid in level.
*/ */
typedef union { typedef union {
struct { struct {
/** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* Add later. * The raw interrupt status bit for the ecc calculate done interrupt
*/ */
uint32_t calc_done_int_raw:1; uint32_t calc_done_int_raw:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
@@ -26,12 +26,12 @@ typedef union {
} ecc_mult_int_raw_reg_t; } ecc_mult_int_raw_reg_t;
/** Type of int_st register /** Type of int_st register
* Add later. * ECC interrupt status register.
*/ */
typedef union { typedef union {
struct { struct {
/** calc_done_int_st : RO; bitpos: [0]; default: 0; /** calc_done_int_st : RO; bitpos: [0]; default: 0;
* Add later. * The masked interrupt status bit for the ecc calculate done interrupt
*/ */
uint32_t calc_done_int_st:1; uint32_t calc_done_int_st:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
@@ -40,12 +40,12 @@ typedef union {
} ecc_mult_int_st_reg_t; } ecc_mult_int_st_reg_t;
/** Type of int_ena register /** Type of int_ena register
* Add later. * ECC interrupt enable register.
*/ */
typedef union { typedef union {
struct { struct {
/** calc_done_int_ena : R/W; bitpos: [0]; default: 0; /** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
* Add later. * The interrupt enable bit for the ecc calculate done interrupt
*/ */
uint32_t calc_done_int_ena:1; uint32_t calc_done_int_ena:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
@@ -54,12 +54,12 @@ typedef union {
} ecc_mult_int_ena_reg_t; } ecc_mult_int_ena_reg_t;
/** Type of int_clr register /** Type of int_clr register
* Add later. * ECC interrupt clear register.
*/ */
typedef union { typedef union {
struct { struct {
/** calc_done_int_clr : WT; bitpos: [0]; default: 0; /** calc_done_int_clr : WT; bitpos: [0]; default: 0;
* Add later. * Set this bit to clear the ecc calculate done interrupt
*/ */
uint32_t calc_done_int_clr:1; uint32_t calc_done_int_clr:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
@@ -68,41 +68,41 @@ typedef union {
} ecc_mult_int_clr_reg_t; } ecc_mult_int_clr_reg_t;
/** Group: RX Control and configuration registers */ /** Group: Configuration registers */
/** Type of conf register /** Type of conf register
* Add later. * ECC configure register
*/ */
typedef union { typedef union {
struct { struct {
/** start : R/W/SC; bitpos: [0]; default: 0; /** start : R/W/SC; bitpos: [0]; default: 0;
* Add later. * Set this bit to start a ECC operation.
*/ */
uint32_t start:1; uint32_t start:1;
/** reset : WT; bitpos: [1]; default: 0; /** reset : WT; bitpos: [1]; default: 0;
* Add later. * Set this bit to reset ECC
*/ */
uint32_t reset:1; uint32_t reset:1;
/** key_length : R/W; bitpos: [2]; default: 0; /** key_length : R/W; bitpos: [2]; default: 0;
* Add later. * 0:192bit key length mode. 1:256bit key length mode
*/ */
uint32_t key_length:1; uint32_t key_length:1;
/** security_mode : R/W; bitpos: [3]; default: 0; /** security_mode : R/W; bitpos: [3]; default: 0;
* Add later. * Reserved
*/ */
uint32_t security_mode:1; uint32_t security_mode:1;
/** clk_en : R/W; bitpos: [4]; default: 0; /** clk_en : R/W; bitpos: [4]; default: 0;
* Add later. * clk gate
*/ */
uint32_t clk_en:1; uint32_t clk_en:1;
/** work_mode : R/W; bitpos: [6:5]; default: 0; /** work_mode : R/W; bitpos: [7:5]; default: 0;
* Add later. * ECC operation mode register.
*/ */
uint32_t work_mode:2; uint32_t work_mode:3;
/** verification_result : RO/SS; bitpos: [7]; default: 0; /** verification_result : RO/SS; bitpos: [8]; default: 0;
* Add later. * ECC verification result register.
*/ */
uint32_t verification_result:1; uint32_t verification_result:1;
uint32_t reserved_8:24; uint32_t reserved_9:23;
}; };
uint32_t val; uint32_t val;
} ecc_mult_conf_reg_t; } ecc_mult_conf_reg_t;
@@ -110,11 +110,11 @@ typedef union {
/** Group: Version register */ /** Group: Version register */
/** Type of date register /** Type of date register
* Add later. * Version control register
*/ */
typedef union { typedef union {
struct { struct {
/** date : R/W; bitpos: [27:0]; default: 33628720; /** date : R/W; bitpos: [27:0]; default: 34636176;
* ECC mult version control register * ECC mult version control register
*/ */
uint32_t date:28; uint32_t date:28;

62
components/soc/esp32h2/include/rev2/soc/gpio_sd_reg.h
View File

@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -34,58 +34,58 @@ extern "C" {
* Duty Cycle Configure Register of SDM1 * Duty Cycle Configure Register of SDM1
*/ */
#define GPIO_SD_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x4) #define GPIO_SD_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x4)
/** GPIO_SD_SD0_IN : R/W; bitpos: [7:0]; default: 0; /** GPIO_SD_SD1_IN : R/W; bitpos: [7:0]; default: 0;
* This field is used to configure the duty cycle of sigma delta modulation output. * This field is used to configure the duty cycle of sigma delta modulation output.
*/ */
#define GPIO_SD_SD0_IN 0x000000FFU #define GPIO_SD_SD1_IN 0x000000FFU
#define GPIO_SD_SD0_IN_M (GPIO_SD_SD0_IN_V << GPIO_SD_SD0_IN_S) #define GPIO_SD_SD1_IN_M (GPIO_SD_SD1_IN_V << GPIO_SD_SD1_IN_S)
#define GPIO_SD_SD0_IN_V 0x000000FFU #define GPIO_SD_SD1_IN_V 0x000000FFU
#define GPIO_SD_SD0_IN_S 0 #define GPIO_SD_SD1_IN_S 0
/** GPIO_SD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; /** GPIO_SD_SD1_PRESCALE : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock. * This field is used to set a divider value to divide APB clock.
*/ */
#define GPIO_SD_SD0_PRESCALE 0x000000FFU #define GPIO_SD_SD1_PRESCALE 0x000000FFU
#define GPIO_SD_SD0_PRESCALE_M (GPIO_SD_SD0_PRESCALE_V << GPIO_SD_SD0_PRESCALE_S) #define GPIO_SD_SD1_PRESCALE_M (GPIO_SD_SD1_PRESCALE_V << GPIO_SD_SD1_PRESCALE_S)
#define GPIO_SD_SD0_PRESCALE_V 0x000000FFU #define GPIO_SD_SD1_PRESCALE_V 0x000000FFU
#define GPIO_SD_SD0_PRESCALE_S 8 #define GPIO_SD_SD1_PRESCALE_S 8
/** GPIO_SD_SIGMADELTA2_REG register /** GPIO_SD_SIGMADELTA2_REG register
* Duty Cycle Configure Register of SDM2 * Duty Cycle Configure Register of SDM2
*/ */
#define GPIO_SD_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x8) #define GPIO_SD_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x8)
/** GPIO_SD_SD0_IN : R/W; bitpos: [7:0]; default: 0; /** GPIO_SD_SD2_IN : R/W; bitpos: [7:0]; default: 0;
* This field is used to configure the duty cycle of sigma delta modulation output. * This field is used to configure the duty cycle of sigma delta modulation output.
*/ */
#define GPIO_SD_SD0_IN 0x000000FFU #define GPIO_SD_SD2_IN 0x000000FFU
#define GPIO_SD_SD0_IN_M (GPIO_SD_SD0_IN_V << GPIO_SD_SD0_IN_S) #define GPIO_SD_SD2_IN_M (GPIO_SD_SD2_IN_V << GPIO_SD_SD2_IN_S)
#define GPIO_SD_SD0_IN_V 0x000000FFU #define GPIO_SD_SD2_IN_V 0x000000FFU
#define GPIO_SD_SD0_IN_S 0 #define GPIO_SD_SD2_IN_S 0
/** GPIO_SD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; /** GPIO_SD_SD2_PRESCALE : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock. * This field is used to set a divider value to divide APB clock.
*/ */
#define GPIO_SD_SD0_PRESCALE 0x000000FFU #define GPIO_SD_SD2_PRESCALE 0x000000FFU
#define GPIO_SD_SD0_PRESCALE_M (GPIO_SD_SD0_PRESCALE_V << GPIO_SD_SD0_PRESCALE_S) #define GPIO_SD_SD2_PRESCALE_M (GPIO_SD_SD2_PRESCALE_V << GPIO_SD_SD2_PRESCALE_S)
#define GPIO_SD_SD0_PRESCALE_V 0x000000FFU #define GPIO_SD_SD2_PRESCALE_V 0x000000FFU
#define GPIO_SD_SD0_PRESCALE_S 8 #define GPIO_SD_SD2_PRESCALE_S 8
/** GPIO_SD_SIGMADELTA3_REG register /** GPIO_SD_SIGMADELTA3_REG register
* Duty Cycle Configure Register of SDM3 * Duty Cycle Configure Register of SDM3
*/ */
#define GPIO_SD_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0xc) #define GPIO_SD_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0xc)
/** GPIO_SD_SD0_IN : R/W; bitpos: [7:0]; default: 0; /** GPIO_SD_SD3_IN : R/W; bitpos: [7:0]; default: 0;
* This field is used to configure the duty cycle of sigma delta modulation output. * This field is used to configure the duty cycle of sigma delta modulation output.
*/ */
#define GPIO_SD_SD0_IN 0x000000FFU #define GPIO_SD_SD3_IN 0x000000FFU
#define GPIO_SD_SD0_IN_M (GPIO_SD_SD0_IN_V << GPIO_SD_SD0_IN_S) #define GPIO_SD_SD3_IN_M (GPIO_SD_SD3_IN_V << GPIO_SD_SD3_IN_S)
#define GPIO_SD_SD0_IN_V 0x000000FFU #define GPIO_SD_SD3_IN_V 0x000000FFU
#define GPIO_SD_SD0_IN_S 0 #define GPIO_SD_SD3_IN_S 0
/** GPIO_SD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; /** GPIO_SD_SD3_PRESCALE : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock. * This field is used to set a divider value to divide APB clock.
*/ */
#define GPIO_SD_SD0_PRESCALE 0x000000FFU #define GPIO_SD_SD3_PRESCALE 0x000000FFU
#define GPIO_SD_SD0_PRESCALE_M (GPIO_SD_SD0_PRESCALE_V << GPIO_SD_SD0_PRESCALE_S) #define GPIO_SD_SD3_PRESCALE_M (GPIO_SD_SD3_PRESCALE_V << GPIO_SD_SD3_PRESCALE_S)
#define GPIO_SD_SD0_PRESCALE_V 0x000000FFU #define GPIO_SD_SD3_PRESCALE_V 0x000000FFU
#define GPIO_SD_SD0_PRESCALE_S 8 #define GPIO_SD_SD3_PRESCALE_S 8
/** GPIO_SD_SIGMADELTA_CG_REG register /** GPIO_SD_SIGMADELTA_CG_REG register
* Clock Gating Configure Register * Clock Gating Configure Register