diff --git a/components/esp_mm/esp_cache_msync.c b/components/esp_mm/esp_cache_msync.c
index b76a9c80f3..68ecd2fb23 100644
--- a/components/esp_mm/esp_cache_msync.c
+++ b/components/esp_mm/esp_cache_msync.c
@@ -101,7 +101,10 @@ esp_err_t esp_cache_msync(void *addr, size_t size, int flags)
     uint32_t cache_level = 0;
     uint32_t cache_id = 0;
     valid = cache_hal_vaddr_to_cache_level_id(vaddr, size, &cache_level, &cache_id);
-    ESP_RETURN_ON_FALSE_ISR(valid, ESP_ERR_INVALID_ARG, TAG, "invalid addr or null pointer");
+    if (!valid) {
+        ESP_EARLY_LOGD(TAG, "vaddr is not in cacheable range, do nothing");
+        return ESP_ERR_NOT_SUPPORTED;
+    }
 
     cache_type_t cache_type = CACHE_TYPE_DATA;
     if (flags & ESP_CACHE_MSYNC_FLAG_TYPE_INST) {
diff --git a/components/esp_mm/include/esp_cache.h b/components/esp_mm/include/esp_cache.h
index cc30faf227..71080518af 100644
--- a/components/esp_mm/include/esp_cache.h
+++ b/components/esp_mm/include/esp_cache.h
@@ -76,6 +76,7 @@ extern "C" {
  *                  - Successful msync
  *                  - For C2M direction, if this chip doesn't support cache writeback, if the input addr is a cache supported one, this API will return ESP_OK
  *        - ESP_ERR_INVALID_ARG:   Invalid argument, not cache supported addr, see printed logs
+ *        - ESP_ERR_NOT_SUPPORTED: Vaddr is not in cacheable range, API will do nothing
  */
 esp_err_t esp_cache_msync(void *addr, size_t size, int flags);