diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c
index 6102340e95..0b2708d24e 100644
--- a/components/esp_system/port/cpu_start.c
+++ b/components/esp_system/port/cpu_start.c
@@ -94,6 +94,7 @@
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
 #include "hal/efuse_ll.h"
+#include "hal/cpu_utility_ll.h"
 #include "soc/periph_defs.h"
 #include "esp_cpu.h"
 #include "esp_private/esp_clk.h"
@@ -229,16 +230,8 @@ void IRAM_ATTR call_start_cpu1(void)
     esp_rom_output_set_as_console(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32
-    DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE);
-    DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
-#elif CONFIG_IDF_TARGET_ESP32P4
-    REG_SET_BIT(ASSIST_DEBUG_CORE_1_RCD_EN_REG, ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN);
-    REG_SET_BIT(ASSIST_DEBUG_CORE_1_RCD_EN_REG, ASSIST_DEBUG_CORE_1_RCD_RECORDEN);
-#elif CONFIG_IDF_TARGET_ESP32S3
-    REG_WRITE(ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_REG, 1);
-    REG_WRITE(ASSIST_DEBUG_CORE_1_RCD_RECORDING_REG, 1);
-#endif
+    cpu_utility_ll_enable_debug(1);
+    cpu_utility_ll_enable_record(1);
 
     s_cpu_up[1] = true;
     ESP_EARLY_LOGD(TAG, "App cpu up");
@@ -292,35 +285,7 @@ static void start_other_core(void)
     // enabled clock and taken APP CPU out of reset. In this case don't reset
     // APP CPU again, as that will clear the breakpoints which may have already
     // been set.
-#if CONFIG_IDF_TARGET_ESP32
-    if (!DPORT_GET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN)) {
-        DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
-        DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
-        DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
-        DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
-    }
-#elif CONFIG_IDF_TARGET_ESP32S3
-    if (!REG_GET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN)) {
-        REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
-        REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
-        REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING);
-        REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING);
-    }
-#elif CONFIG_IDF_TARGET_ESP32P4
-    if (!REG_GET_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN)) {
-        REG_SET_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN);
-    }
-    if (REG_GET_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL)) {
-        REG_CLR_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL);
-    }
-#elif CONFIG_IDF_TARGET_ESP32H4
-    if (!REG_GET_BIT(PCR_CORE1_CONF_REG, PCR_CORE1_CLK_EN)) {
-        REG_SET_BIT(PCR_CORE1_CONF_REG, PCR_CORE1_CLK_EN);
-    }
-    if (REG_GET_BIT(PCR_CORE1_CONF_REG, PCR_CORE1_RST_EN)) {
-        REG_CLR_BIT(PCR_CORE1_CONF_REG, PCR_CORE1_RST_EN);
-    }
-#endif
+    cpu_utility_ll_enable_clock_and_reset_app_cpu();
 
     ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
 
diff --git a/components/hal/esp32/include/hal/cpu_utility_ll.h b/components/hal/esp32/include/hal/cpu_utility_ll.h
index 91d762bc27..0a731fac77 100644
--- a/components/hal/esp32/include/hal/cpu_utility_ll.h
+++ b/components/hal/esp32/include/hal/cpu_utility_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,6 +8,7 @@
 #include "soc/soc.h"
 #include "soc/soc_caps.h"
 #include "soc/rtc_cntl_reg.h"
+#include "soc/dport_reg.h"
 #include "esp_attr.h"
 
 #ifdef __cplusplus
@@ -63,6 +64,37 @@ FORCE_INLINE_ATTR void cpu_utility_ll_unstall_cpu(uint32_t cpu_no)
     int rtc_cntl_c1 = (cpu_no == 0) ? RTC_CNTL_SW_STALL_PROCPU_C1_M : RTC_CNTL_SW_STALL_APPCPU_C1_M;
     CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, rtc_cntl_c1);
 }
+
+FORCE_INLINE_ATTR void cpu_utility_ll_enable_debug(uint32_t cpu_no)
+{
+    if (cpu_no == 0) {
+        DPORT_REG_SET_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_PDEBUG_ENABLE);
+    } else {
+        DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE);
+    }
+}
+
+FORCE_INLINE_ATTR void cpu_utility_ll_enable_record(uint32_t cpu_no)
+{
+    if (cpu_no == 0) {
+        DPORT_REG_SET_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_RECORD_ENABLE);
+        DPORT_REG_CLR_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_RECORD_ENABLE);
+    } else {
+        DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
+        DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
+    }
+}
+
+FORCE_INLINE_ATTR void cpu_utility_ll_enable_clock_and_reset_app_cpu(void)
+{
+    if (!DPORT_GET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN)) {
+        DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
+        DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
+        DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
+        DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
+    }
+}
+
 #endif // SOC_CPU_CORES_NUM > 1
 
 #ifdef __cplusplus
diff --git a/components/hal/esp32h4/include/cpu_utility_ll.h b/components/hal/esp32h4/include/cpu_utility_ll.h
new file mode 100644
index 0000000000..82e21bd846
--- /dev/null
+++ b/components/hal/esp32h4/include/cpu_utility_ll.h
@@ -0,0 +1,56 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+#include "soc/soc.h"
+#include "soc/lp_aon_reg.h"
+#include "soc/lp_aon_struct.h"
+#include "soc/pcr_reg.h"
+#include "esp_attr.h"
+
+//TODO: [ESP32H4] IDF-12484, need check
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+FORCE_INLINE_ATTR void cpu_utility_ll_reset_cpu(uint32_t cpu_no)
+{
+    if (cpu_no == 0) {
+        LP_AON.cpucore_cfg.aon_cpu_core0_sw_reset = 1;
+    } else {
+        LP_AON.cpucore_cfg.aon_cpu_core1_sw_reset = 1;
+    }
+}
+
+FORCE_INLINE_ATTR uint32_t cpu_utility_ll_wait_mode(void)
+{
+    return REG_GET_BIT(PCR_CPU_WAITI_CONF_REG, PCR_CPU0_WAIT_MODE_FORCE_ON);
+}
+
+FORCE_INLINE_ATTR void cpu_utility_ll_enable_debug(uint32_t cpu_no)
+{
+    // TODO
+}
+
+FORCE_INLINE_ATTR void cpu_utility_ll_enable_record(uint32_t cpu_no)
+{
+    // TODO
+}
+
+FORCE_INLINE_ATTR void cpu_utility_ll_enable_clock_and_reset_app_cpu(void)
+{
+    if (!REG_GET_BIT(PCR_CORE1_CONF_REG, PCR_CORE1_CLK_EN)) {
+        REG_SET_BIT(PCR_CORE1_CONF_REG, PCR_CORE1_CLK_EN);
+    }
+    if (REG_GET_BIT(PCR_CORE1_CONF_REG, PCR_CORE1_RST_EN)) {
+        REG_CLR_BIT(PCR_CORE1_CONF_REG, PCR_CORE1_RST_EN);
+    }
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32p4/include/hal/cpu_utility_ll.h b/components/hal/esp32p4/include/hal/cpu_utility_ll.h
index f9686b8cea..3c8b235d81 100644
--- a/components/hal/esp32p4/include/hal/cpu_utility_ll.h
+++ b/components/hal/esp32p4/include/hal/cpu_utility_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,6 +10,8 @@
 #include "soc/lp_clkrst_struct.h"
 #include "soc/pmu_struct.h"
 #include "soc/hp_system_reg.h"
+#include "soc/hp_sys_clkrst_reg.h"
+#include "soc/assist_debug_reg.h"
 #include "esp_attr.h"
 #include "hal/misc.h"
 
@@ -48,6 +50,35 @@ FORCE_INLINE_ATTR void cpu_utility_ll_unstall_cpu(uint32_t cpu_no)
         while(REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE1_CORESTALLED_ST));
     }
 }
+
+FORCE_INLINE_ATTR void cpu_utility_ll_enable_debug(uint32_t cpu_no)
+{
+    if (cpu_no == 0) {
+        REG_SET_BIT(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN);
+    } else {
+        REG_SET_BIT(ASSIST_DEBUG_CORE_1_RCD_EN_REG, ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN);
+    }
+}
+
+FORCE_INLINE_ATTR void cpu_utility_ll_enable_record(uint32_t cpu_no)
+{
+    if (cpu_no == 0) {
+        REG_SET_BIT(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
+    } else {
+        REG_SET_BIT(ASSIST_DEBUG_CORE_1_RCD_EN_REG, ASSIST_DEBUG_CORE_1_RCD_RECORDEN);
+    }
+}
+
+FORCE_INLINE_ATTR void cpu_utility_ll_enable_clock_and_reset_app_cpu(void)
+{
+    if (!REG_GET_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN)) {
+        REG_SET_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN);
+    }
+    if (REG_GET_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL)) {
+        REG_CLR_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL);
+    }
+}
+
 #endif // SOC_CPU_CORES_NUM > 1
 
 FORCE_INLINE_ATTR uint32_t cpu_utility_ll_wait_mode(void)
diff --git a/components/hal/esp32s3/include/hal/cpu_utility_ll.h b/components/hal/esp32s3/include/hal/cpu_utility_ll.h
index 91d762bc27..c0fd710e2a 100644
--- a/components/hal/esp32s3/include/hal/cpu_utility_ll.h
+++ b/components/hal/esp32s3/include/hal/cpu_utility_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,7 +7,9 @@
 #pragma once
 #include "soc/soc.h"
 #include "soc/soc_caps.h"
+#include "soc/system_reg.h"
 #include "soc/rtc_cntl_reg.h"
+#include "soc/assist_debug_reg.h"
 #include "esp_attr.h"
 
 #ifdef __cplusplus
@@ -63,6 +65,35 @@ FORCE_INLINE_ATTR void cpu_utility_ll_unstall_cpu(uint32_t cpu_no)
     int rtc_cntl_c1 = (cpu_no == 0) ? RTC_CNTL_SW_STALL_PROCPU_C1_M : RTC_CNTL_SW_STALL_APPCPU_C1_M;
     CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, rtc_cntl_c1);
 }
+
+FORCE_INLINE_ATTR void cpu_utility_ll_enable_debug(uint32_t cpu_no)
+{
+    if (cpu_no == 0) {
+        REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_REG, 1);
+    } else {
+        REG_WRITE(ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_REG, 1);
+    }
+}
+
+FORCE_INLINE_ATTR void cpu_utility_ll_enable_record(uint32_t cpu_no)
+{
+    if (cpu_no == 0) {
+        REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_RECORDING_REG, 1);
+    } else {
+        REG_WRITE(ASSIST_DEBUG_CORE_1_RCD_RECORDING_REG, 1);
+    }
+}
+
+FORCE_INLINE_ATTR void cpu_utility_ll_enable_clock_and_reset_app_cpu(void)
+{
+    if (!REG_GET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN)) {
+        REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
+        REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
+        REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING);
+        REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING);
+    }
+}
+
 #endif // SOC_CPU_CORES_NUM > 1
 
 #ifdef __cplusplus