diff --git a/.gitlab/ci/assign-test.yml b/.gitlab/ci/assign-test.yml index 19c28ce49c..9dd3bb58e6 100644 --- a/.gitlab/ci/assign-test.yml +++ b/.gitlab/ci/assign-test.yml @@ -10,6 +10,7 @@ assign_test: - build_ssc_esp32 - build_esp_idf_tests_cmake_esp32 - build_esp_idf_tests_cmake_esp32s2 + - build_esp_idf_tests_cmake_esp32s3 - build_esp_idf_tests_cmake_esp32c3 variables: SUBMODULES_TO_FETCH: "components/esptool_py/esptool" @@ -58,6 +59,7 @@ update_test_cases: needs: - build_esp_idf_tests_cmake_esp32 - build_esp_idf_tests_cmake_esp32s2 + - build_esp_idf_tests_cmake_esp32s3 - build_esp_idf_tests_cmake_esp32c3 artifacts: when: always diff --git a/.gitlab/ci/build.yml b/.gitlab/ci/build.yml index 756c38263a..06b2094acb 100644 --- a/.gitlab/ci/build.yml +++ b/.gitlab/ci/build.yml @@ -289,6 +289,13 @@ build_component_ut_esp32s2: variables: IDF_TARGET: esp32s2 +build_component_ut_esp32s3: + extends: + - .build_component_ut_template + - .rules:build:component_ut-esp32s3 + variables: + IDF_TARGET: esp32s3 + build_component_ut_esp32c3: extends: - .build_component_ut_template diff --git a/.gitlab/ci/target-test.yml b/.gitlab/ci/target-test.yml index 51f802479e..150f4a8df2 100644 --- a/.gitlab/ci/target-test.yml +++ b/.gitlab/ci/target-test.yml @@ -382,6 +382,11 @@ test_app_test_esp32_generic: - .component_ut_template - .rules:test:component_ut-esp32s2 +.component_ut_esp32s3_template: + extends: + - .component_ut_template + - .rules:test:component_ut-esp32s3 + .component_ut_esp32c3_template: extends: - .component_ut_template @@ -399,6 +404,12 @@ component_ut_test_esp32s2: - ESP32S2 - COMPONENT_UT_GENERIC +component_ut_test_esp32s3: + extends: .component_ut_esp32s3_template + tags: + - ESP32S3 + - COMPONENT_UT_GENERIC + component_ut_test_esp32c3: extends: .component_ut_esp32c3_template tags: @@ -421,6 +432,11 @@ component_ut_test_esp32c3: - .unit_test_template - .rules:test:unit_test-esp32s2 +.unit_test_esp32s3_template: + extends: + - .unit_test_template + - .rules:test:unit_test-esp32s3 + .unit_test_esp32c3_template: extends: - .unit_test_template @@ -674,6 +690,13 @@ UT_C3_FLASH_SUSPEND: - ESP32C3_IDF - UT_T1_Flash_Suspend +UT_S3: + extends: .unit_test_esp32s3_template + parallel: 20 + tags: + - ESP32S3_IDF + - UT_T1_1 + .integration_test_template: extends: - .target_test_job_template diff --git a/components/driver/test/test_dedicated_gpio.c b/components/driver/test/test_dedicated_gpio.c index 7ba69abe4d..206819d1d7 100644 --- a/components/driver/test/test_dedicated_gpio.c +++ b/components/driver/test/test_dedicated_gpio.c @@ -58,6 +58,8 @@ TEST_CASE("Dedicated GPIO bundle install/uninstall", "[dedic_gpio]") #define TEST_GPIO_GROUP_SIZE (4) +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) +// TODO ESP32-S3 IDF-3387 typedef struct { SemaphoreHandle_t sem; const int gpios[TEST_GPIO_GROUP_SIZE]; @@ -159,6 +161,8 @@ TEST_CASE("Dedicated GPIO run on multiple CPU core", "[dedic_gpio]") vSemaphoreDelete(sem); } +#endif //#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) + IRAM_ATTR static void test_dedic_gpio_isr_callback(void *args) { SemaphoreHandle_t sem = (SemaphoreHandle_t)args; diff --git a/components/driver/test/test_gdma.c b/components/driver/test/test_gdma.c index 05a142a5d4..86ef4683e9 100644 --- a/components/driver/test/test_gdma.c +++ b/components/driver/test/test_gdma.c @@ -26,6 +26,12 @@ TEST_CASE("GDMA channel allocation", "[gdma]") }; TEST_ASSERT_EQUAL(ESP_ERR_NOT_FOUND, gdma_new_channel(&channel_config, &tx_channels[0])); + // Free interrupts before installing RX interrupts to ensure enough free interrupts + for (int i = 0; i < SOC_GDMA_PAIRS_PER_GROUP; i++) { + TEST_ESP_OK(gdma_disconnect(tx_channels[i])); + TEST_ESP_OK(gdma_del_channel(tx_channels[i])); + } + // install RX channels for different peripherals channel_config.direction = GDMA_CHANNEL_DIRECTION_RX; for (int i = 0; i < SOC_GDMA_PAIRS_PER_GROUP; i++) { @@ -36,9 +42,7 @@ TEST_CASE("GDMA channel allocation", "[gdma]") TEST_ASSERT_EQUAL(ESP_ERR_NOT_FOUND, gdma_new_channel(&channel_config, &rx_channels[0])); for (int i = 0; i < SOC_GDMA_PAIRS_PER_GROUP; i++) { - TEST_ESP_OK(gdma_disconnect(tx_channels[i])); TEST_ESP_OK(gdma_disconnect(rx_channels[i])); - TEST_ESP_OK(gdma_del_channel(tx_channels[i])); TEST_ESP_OK(gdma_del_channel(rx_channels[i])); } diff --git a/components/driver/test/test_gpio.c b/components/driver/test/test_gpio.c index efbb620009..57da8b7614 100644 --- a/components/driver/test/test_gpio.c +++ b/components/driver/test/test_gpio.c @@ -5,7 +5,7 @@ */ /** * About test environment UT_T1_GPIO: - * Please connect GPIO18 and GPIO19 + * Please connect TEST_GPIO_EXT_OUT_IO and TEST_GPIO_EXT_IN_IO */ #include #include @@ -40,8 +40,9 @@ #define TEST_GPIO_INPUT_ONLY_PIN 46 #define TEST_GPIO_OUTPUT_MAX GPIO_NUM_46 #elif CONFIG_IDF_TARGET_ESP32S3 -#define TEST_GPIO_EXT_OUT_IO 19 // default output GPIO -#define TEST_GPIO_EXT_IN_IO 20 // default input GPIO +// IO19 and IO20 are connected as USB functions and should be avoided for testing +#define TEST_GPIO_EXT_OUT_IO 17 // default output GPIO +#define TEST_GPIO_EXT_IN_IO 21 // default input GPIO #define TEST_GPIO_OUTPUT_PIN 12 #define TEST_GPIO_INPUT_ONLY_PIN 46 #define TEST_GPIO_OUTPUT_MAX GPIO_NUM_MAX diff --git a/components/driver/test/test_spi_slave_hd.c b/components/driver/test/test_spi_slave_hd.c index 70539defb3..8951b4bea5 100644 --- a/components/driver/test/test_spi_slave_hd.c +++ b/components/driver/test/test_spi_slave_hd.c @@ -19,6 +19,8 @@ #if !DISABLED_FOR_TARGETS(ESP32C3) //There is only one GPSPI controller on ESP32C3, so single-board test is disabled. +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) +// TODO ESP32S3 IDF-3226 #if SOC_SPI_SUPPORT_SLAVE_HD_VER2 #include "driver/spi_slave_hd.h" @@ -595,7 +597,7 @@ TEST_CASE("test spi slave hd segment mode, master too long", "[spi][spi_slv_hd]" } #endif //SOC_SPI_SUPPORT_SLAVE_HD_VER2 - +#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) #endif //#if !DISABLED_FOR_TARGETS(ESP32C3) #if !DISABLED_FOR_TARGETS(ESP32, ESP32S2, ESP32S3) diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt index 60e0122101..e05a3d4e48 100644 --- a/components/esp_rom/CMakeLists.txt +++ b/components/esp_rom/CMakeLists.txt @@ -4,7 +4,8 @@ set(sources "patches/esp_rom_crc.c" "patches/esp_rom_sys.c" "patches/esp_rom_uart.c") -if(CONFIG_IDF_TARGET_ARCH_XTENSA) +if(CONFIG_IDF_TARGET_ARCH_XTENSA AND NOT (target STREQUAL "esp32s3")) + # Temporarily disabled on S3 due to it breaking longjmp TODO ESP32S3 IDF-3391 list(APPEND sources "patches/esp_rom_longjmp.S") endif() @@ -102,7 +103,8 @@ else() # Regular app build endif() endif() - if(CONFIG_IDF_TARGET_ARCH_XTENSA) + if(CONFIG_IDF_TARGET_ARCH_XTENSA AND NOT (target STREQUAL "esp32s3")) + # Temporarily disabled on S3 due to it breaking longjmp TODO ESP32S3 IDF-3391 target_link_libraries(${COMPONENT_LIB} INTERFACE "-Wl,--wrap=longjmp") endif() endif() diff --git a/components/esp_rom/include/esp32s3/rom/rtc.h b/components/esp_rom/include/esp32s3/rom/rtc.h index b8ff8519bf..b23b22d4b9 100644 --- a/components/esp_rom/include/esp32s3/rom/rtc.h +++ b/components/esp_rom/include/esp32s3/rom/rtc.h @@ -63,6 +63,7 @@ extern "C" { #define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG #define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG #define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG +#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG #define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG #define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code. diff --git a/components/esp_system/port/soc/esp32s3/reset_reason.c b/components/esp_system/port/soc/esp32s3/reset_reason.c index b53641ca7b..e14159e161 100644 --- a/components/esp_system/port/soc/esp32s3/reset_reason.c +++ b/components/esp_system/port/soc/esp32s3/reset_reason.c @@ -97,13 +97,23 @@ esp_reset_reason_t esp_reset_reason(void) /* in IRAM, can be called from panic handler */ void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint) { + assert((hint & (~RST_REASON_MASK)) == 0); + uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT; + REG_WRITE(RTC_RESET_CAUSE_REG, val); } /* in IRAM, can be called from panic handler */ esp_reset_reason_t IRAM_ATTR esp_reset_reason_get_hint(void) { - return ESP_RST_UNKNOWN; + uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG); + uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK; + uint32_t low = reset_reason_hint & RST_REASON_MASK; + if ((reset_reason_hint & RST_REASON_BIT) == 0 || high != low) { + return ESP_RST_UNKNOWN; + } + return (esp_reset_reason_t) low; } static void esp_reset_reason_clear_hint(void) { + REG_WRITE(RTC_RESET_CAUSE_REG, 0); } diff --git a/components/fatfs/test/test_fatfs_sdmmc.c b/components/fatfs/test/test_fatfs_sdmmc.c index 8f996a8ede..d4d0e8b77c 100644 --- a/components/fatfs/test/test_fatfs_sdmmc.c +++ b/components/fatfs/test/test_fatfs_sdmmc.c @@ -39,6 +39,8 @@ #if SOC_SDMMC_HOST_SUPPORTED +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) +// No runner #include "driver/sdmmc_host.h" @@ -305,9 +307,11 @@ TEST_CASE("(SD) opendir, readdir, rewinddir, seekdir work as expected using UTF- } #endif // CONFIG_FATFS_API_ENCODING_UTF_8 && CONFIG_FATFS_CODEPAGE == 936 +#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) #endif //SDMMC HOST SUPPORTED -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3) + +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3) //no runners static void sdspi_speed_test(void *buf, size_t buf_size, size_t file_size, bool write); diff --git a/components/mbedtls/test/test_esp_crt_bundle.c b/components/mbedtls/test/test_esp_crt_bundle.c index 82b57ee60d..7cf45e5417 100644 --- a/components/mbedtls/test/test_esp_crt_bundle.c +++ b/components/mbedtls/test/test_esp_crt_bundle.c @@ -82,6 +82,9 @@ typedef enum { int esp_crt_verify_callback(void *buf, mbedtls_x509_crt *crt, int data, uint32_t *flags); +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) +// TODO ESP32-S3 IDF-1878 + static const char *TAG = "cert_bundle_test"; static volatile bool exit_flag; @@ -341,6 +344,8 @@ TEST_CASE("custom certificate bundle", "[mbedtls]") vSemaphoreDelete(exit_sema); } +#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) + TEST_CASE("custom certificate bundle - weak hash", "[mbedtls]") { /* A weak signature hash on the trusted certificate should not stop diff --git a/components/newlib/test_apps/app_test.py b/components/newlib/test_apps/app_test.py index e9ed329db6..7ea8e5428d 100644 --- a/components/newlib/test_apps/app_test.py +++ b/components/newlib/test_apps/app_test.py @@ -7,7 +7,7 @@ except ImportError: pass -@ttfw_idf.idf_component_unit_test(env_tag='COMPONENT_UT_GENERIC', target=['esp32', 'esp32s2', 'esp32c3']) +@ttfw_idf.idf_component_unit_test(env_tag='COMPONENT_UT_GENERIC', target=['esp32', 'esp32s2', 'esp32s3', 'esp32c3']) def test_component_ut_newlib(env, _): # type: (tiny_test_fw.Env, typing.Any) -> None dut = env.get_dut('newlib', 'components/newlib/test_apps') dut.start_app() diff --git a/components/soc/esp32s3/include/soc/uart_reg.h b/components/soc/esp32s3/include/soc/uart_reg.h index 28b5dcaf6f..a7b1d0e61b 100644 --- a/components/soc/esp32s3/include/soc/uart_reg.h +++ b/components/soc/esp32s3/include/soc/uart_reg.h @@ -798,43 +798,43 @@ ware flow control..*/ #define UART_PARITY_S 0 #define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) -/* UART_RX_TOUT_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/* UART_RX_TOUT_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ /*description: This is the enble bit for uart receiver's timeout function..*/ -#define UART_RX_TOUT_EN (BIT(21)) -#define UART_RX_TOUT_EN_M (BIT(21)) +#define UART_RX_TOUT_EN (BIT(23)) +#define UART_RX_TOUT_EN_M (BIT(23)) #define UART_RX_TOUT_EN_V 0x1 -#define UART_RX_TOUT_EN_S 21 -/* UART_RX_FLOW_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +#define UART_RX_TOUT_EN_S 23 +/* UART_RX_FLOW_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ /*description: This is the flow enable bit for UART receiver..*/ -#define UART_RX_FLOW_EN (BIT(20)) -#define UART_RX_FLOW_EN_M (BIT(20)) +#define UART_RX_FLOW_EN (BIT(22)) +#define UART_RX_FLOW_EN_M (BIT(22)) #define UART_RX_FLOW_EN_V 0x1 -#define UART_RX_FLOW_EN_S 20 -/* UART_RX_TOUT_FLOW_DIS : R/W ;bitpos:[19] ;default: 1'b0 ; */ +#define UART_RX_FLOW_EN_S 22 +/* UART_RX_TOUT_FLOW_DIS : R/W ;bitpos:[21] ;default: 1'b0 ; */ /*description: Set this bit to stop accumulating idle_cnt when hardware flow control works..*/ -#define UART_RX_TOUT_FLOW_DIS (BIT(19)) -#define UART_RX_TOUT_FLOW_DIS_M (BIT(19)) +#define UART_RX_TOUT_FLOW_DIS (BIT(21)) +#define UART_RX_TOUT_FLOW_DIS_M (BIT(21)) #define UART_RX_TOUT_FLOW_DIS_V 0x1 -#define UART_RX_TOUT_FLOW_DIS_S 19 -/* UART_DIS_RX_DAT_OVF : R/W ;bitpos:[18] ;default: 1'h0 ; */ +#define UART_RX_TOUT_FLOW_DIS_S 21 +/* UART_DIS_RX_DAT_OVF : R/W ;bitpos:[20] ;default: 1'h0 ; */ /*description: Disable UART Rx data overflow detect. .*/ -#define UART_DIS_RX_DAT_OVF (BIT(18)) -#define UART_DIS_RX_DAT_OVF_M (BIT(18)) +#define UART_DIS_RX_DAT_OVF (BIT(20)) +#define UART_DIS_RX_DAT_OVF_M (BIT(20)) #define UART_DIS_RX_DAT_OVF_V 0x1 -#define UART_DIS_RX_DAT_OVF_S 18 -/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[17:9] ;default: 9'h60 ; */ +#define UART_DIS_RX_DAT_OVF_S 20 +/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[19:10] ;default: 10'h60 ; */ /*description: It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is le ss than this register value..*/ -#define UART_TXFIFO_EMPTY_THRHD 0x000001FF +#define UART_TXFIFO_EMPTY_THRHD 0x000003FF #define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S)) -#define UART_TXFIFO_EMPTY_THRHD_V 0x1FF -#define UART_TXFIFO_EMPTY_THRHD_S 9 -/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[8:0] ;default: 9'h60 ; */ +#define UART_TXFIFO_EMPTY_THRHD_V 0x3FF +#define UART_TXFIFO_EMPTY_THRHD_S 10 +/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[9:0] ;default: 10'h60 ; */ /*description: It will produce rxfifo_full_int interrupt when receiver receives more data than this register value..*/ -#define UART_RXFIFO_FULL_THRHD 0x000001FF +#define UART_RXFIFO_FULL_THRHD 0x000003FF #define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S)) -#define UART_RXFIFO_FULL_THRHD_V 0x1FF +#define UART_RXFIFO_FULL_THRHD_V 0x3FF #define UART_RXFIFO_FULL_THRHD_S 0 #define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28) @@ -913,33 +913,33 @@ ore times than this register value..*/ #define UART_ACTIVE_THRESHOLD_S 0 #define UART_SWFC_CONF0_REG(i) (REG_UART_BASE(i) + 0x3C) -/* UART_XOFF_CHAR : R/W ;bitpos:[16:9] ;default: 8'h13 ; */ +/* UART_XOFF_CHAR : R/W ;bitpos:[17:10] ;default: 8'h13 ; */ /*description: This register stores the Xoff flow control char..*/ #define UART_XOFF_CHAR 0x000000FF #define UART_XOFF_CHAR_M ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S)) #define UART_XOFF_CHAR_V 0xFF -#define UART_XOFF_CHAR_S 9 -/* UART_XOFF_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'he0 ; */ +#define UART_XOFF_CHAR_S 10 +/* UART_XOFF_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'he0 ; */ /*description: When the data amount in Rx-FIFO is more than this register value with uart_sw_fl ow_con_en set to 1, it will send a Xoff char..*/ -#define UART_XOFF_THRESHOLD 0x000001FF +#define UART_XOFF_THRESHOLD 0x000003FF #define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S)) -#define UART_XOFF_THRESHOLD_V 0x1FF +#define UART_XOFF_THRESHOLD_V 0x3FF #define UART_XOFF_THRESHOLD_S 0 #define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40) -/* UART_XON_CHAR : R/W ;bitpos:[16:9] ;default: 8'h11 ; */ +/* UART_XON_CHAR : R/W ;bitpos:[17:10] ;default: 8'h11 ; */ /*description: This register stores the Xon flow control char..*/ #define UART_XON_CHAR 0x000000FF #define UART_XON_CHAR_M ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S)) #define UART_XON_CHAR_V 0xFF -#define UART_XON_CHAR_S 9 -/* UART_XON_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +#define UART_XON_CHAR_S 10 +/* UART_XON_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ /*description: When the data amount in Rx-FIFO is less than this register value with uart_sw_fl ow_con_en set to 1, it will send a Xon char..*/ -#define UART_XON_THRESHOLD 0x000001FF +#define UART_XON_THRESHOLD 0x000003FF #define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S)) -#define UART_XON_THRESHOLD_V 0x1FF +#define UART_XON_THRESHOLD_V 0x3FF #define UART_XON_THRESHOLD_S 0 #define UART_TXBRK_CONF_REG(i) (REG_UART_BASE(i) + 0x44) @@ -1053,32 +1053,32 @@ y receiver..*/ #define UART_AT_CMD_CHAR_S 0 #define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60) -/* UART_MEM_FORCE_PU : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/* UART_MEM_FORCE_PU : R/W ;bitpos:[28] ;default: 1'b0 ; */ /*description: Set this bit to force power up UART memory..*/ -#define UART_MEM_FORCE_PU (BIT(27)) -#define UART_MEM_FORCE_PU_M (BIT(27)) +#define UART_MEM_FORCE_PU (BIT(28)) +#define UART_MEM_FORCE_PU_M (BIT(28)) #define UART_MEM_FORCE_PU_V 0x1 -#define UART_MEM_FORCE_PU_S 27 -/* UART_MEM_FORCE_PD : R/W ;bitpos:[26] ;default: 1'b0 ; */ +#define UART_MEM_FORCE_PU_S 28 +/* UART_MEM_FORCE_PD : R/W ;bitpos:[27] ;default: 1'b0 ; */ /*description: Set this bit to force power down UART memory..*/ -#define UART_MEM_FORCE_PD (BIT(26)) -#define UART_MEM_FORCE_PD_M (BIT(26)) +#define UART_MEM_FORCE_PD (BIT(27)) +#define UART_MEM_FORCE_PD_M (BIT(27)) #define UART_MEM_FORCE_PD_V 0x1 -#define UART_MEM_FORCE_PD_S 26 -/* UART_RX_TOUT_THRHD : R/W ;bitpos:[25:16] ;default: 10'ha ; */ +#define UART_MEM_FORCE_PD_S 27 +/* UART_RX_TOUT_THRHD : R/W ;bitpos:[26:17] ;default: 10'ha ; */ /*description: This register is used to configure the threshold time that receiver takes to rec eive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver t akes more time to receive one byte with rx_tout_en set to 1..*/ #define UART_RX_TOUT_THRHD 0x000003FF #define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S)) #define UART_RX_TOUT_THRHD_V 0x3FF -#define UART_RX_TOUT_THRHD_S 16 -/* UART_RX_FLOW_THRHD : R/W ;bitpos:[15:7] ;default: 9'h0 ; */ +#define UART_RX_TOUT_THRHD_S 17 +/* UART_RX_FLOW_THRHD : R/W ;bitpos:[16:7] ;default: 10'h0 ; */ /*description: This register is used to configure the maximum amount of data that can be receiv ed when hardware flow control works..*/ -#define UART_RX_FLOW_THRHD 0x000001FF +#define UART_RX_FLOW_THRHD 0x000003FF #define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S)) -#define UART_RX_FLOW_THRHD_V 0x1FF +#define UART_RX_FLOW_THRHD_V 0x3FF #define UART_RX_FLOW_THRHD_S 7 /* UART_TX_SIZE : R/W ;bitpos:[6:4] ;default: 3'h1 ; */ /*description: This register is used to configure the amount of mem allocated for transmit-FIFO @@ -1253,6 +1253,7 @@ e registers. .*/ #define UART_ID_V 0x3FFFFFFF #define UART_ID_S 0 + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s3/include/soc/uart_struct.h b/components/soc/esp32s3/include/soc/uart_struct.h index 187f58d256..c979c3c2c6 100644 --- a/components/soc/esp32s3/include/soc/uart_struct.h +++ b/components/soc/esp32s3/include/soc/uart_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -18,11 +18,12 @@ #ifdef __cplusplus extern "C" { #endif +#include "soc.h" typedef volatile struct { union { struct { - uint32_t rw_byte; /*UART $n accesses FIFO via this register.*/ + uint32_t rw_byte ; /*UART $n accesses FIFO via this register.*/ }; uint32_t val; } ahb_fifo; @@ -197,13 +198,13 @@ typedef volatile struct { } conf0; union { struct { - uint32_t rxfifo_full_thrhd : 9; /*It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.*/ - uint32_t txfifo_empty_thrhd : 9; /*It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.*/ + uint32_t rxfifo_full_thrhd : 10; /*It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.*/ + uint32_t txfifo_empty_thrhd : 10; /*It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.*/ uint32_t dis_rx_dat_ovf : 1; /*Disable UART Rx data overflow detect. */ uint32_t rx_tout_flow_dis : 1; /*Set this bit to stop accumulating idle_cnt when hardware flow control works.*/ uint32_t rx_flow_en : 1; /*This is the flow enable bit for UART receiver.*/ uint32_t rx_tout_en : 1; /*This is the enble bit for uart receiver's timeout function.*/ - uint32_t reserved22 : 10; + uint32_t reserved24 : 8; }; uint32_t val; } conf1; @@ -249,17 +250,17 @@ typedef volatile struct { } sleep_conf; union { struct { - uint32_t xoff_threshold : 9; /*When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.*/ + uint32_t xoff_threshold : 10; /*When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.*/ uint32_t xoff_char : 8; /*This register stores the Xoff flow control char.*/ - uint32_t reserved17 : 15; /*Reserved*/ + uint32_t reserved18 : 14; /*Reserved*/ }; uint32_t val; } swfc_conf0; union { struct { - uint32_t xon_threshold : 9; /*When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.*/ + uint32_t xon_threshold : 10; /*When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.*/ uint32_t xon_char : 8; /*This register stores the Xon flow control char.*/ - uint32_t reserved17 : 15; /*Reserved*/ + uint32_t reserved18 : 14; /*Reserved*/ }; uint32_t val; } swfc_conf1; @@ -325,11 +326,11 @@ typedef volatile struct { uint32_t reserved0 : 1; uint32_t rx_size : 3; /*This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.*/ uint32_t tx_size : 3; /*This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.*/ - uint32_t rx_flow_thrhd : 9; /*This register is used to configure the maximum amount of data that can be received when hardware flow control works.*/ + uint32_t rx_flow_thrhd : 10; /*This register is used to configure the maximum amount of data that can be received when hardware flow control works.*/ uint32_t rx_tout_thrhd : 10; /*This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.*/ uint32_t force_pd : 1; /*Set this bit to force power down UART memory.*/ uint32_t force_pu : 1; /*Set this bit to force power up UART memory.*/ - uint32_t reserved28 : 4; + uint32_t reserved29 : 3; }; uint32_t val; } mem_conf; diff --git a/components/spi_flash/test/test_esp_flash.c b/components/spi_flash/test/test_esp_flash.c index ce1151dd20..477904d924 100644 --- a/components/spi_flash/test/test_esp_flash.c +++ b/components/spi_flash/test/test_esp_flash.c @@ -137,8 +137,8 @@ typedef void (*flash_test_func_t)(const esp_partition_t *part); These tests run for all the flash chip configs shown in config_list, below (internal and external). */ -#if defined(CONFIG_SPIRAM) - +#if defined(CONFIG_SPIRAM) || TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) +// No S3 runner #define FLASH_TEST_CASE_3(STR, FUNCT_TO_RUN) #define FLASH_TEST_CASE_3_IGNORE(STR, FUNCT_TO_RUN) #else //CONFIG_SPIRAM @@ -900,12 +900,15 @@ TEST_CASE("SPI flash test reading with all speed/mode permutations", "[esp_flash } #ifndef CONFIG_SPIRAM +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) +// No S3 runner TEST_CASE("SPI flash test reading with all speed/mode permutations, 3 chips", "[esp_flash_3][test_env=UT_T1_ESP_FLASH]") { for (int i = 0; i < TEST_CONFIG_NUM; i++) { test_permutations_chip(&config_list[i]); } } +#endif// !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) #endif @@ -976,6 +979,9 @@ static void test_write_large_buffer(const esp_partition_t* part, const uint8_t * #if !CONFIG_SPIRAM +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) +// No S3 runner + typedef struct { uint32_t us_start; size_t len; @@ -1151,7 +1157,11 @@ static void test_flash_read_write_performance(const esp_partition_t *part) free(data_read); } + + TEST_CASE("Test esp_flash read/write performance", "[esp_flash][test_env=UT_T1_ESP_FLASH]") {flash_test_func(test_flash_read_write_performance, 1);} +#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) + #endif // !CONFIG_SPIRAM FLASH_TEST_CASE_3("Test esp_flash read/write performance"", 3 chips", test_flash_read_write_performance); diff --git a/components/spi_flash/test/test_mmap.c b/components/spi_flash/test/test_mmap.c index 28ae98c06b..489fc4e3c2 100644 --- a/components/spi_flash/test/test_mmap.c +++ b/components/spi_flash/test/test_mmap.c @@ -153,8 +153,8 @@ TEST_CASE("Can mmap into data address space", "[spi_flash][mmap]") TEST_ASSERT_EQUAL_PTR(NULL, spi_flash_phys2cache(start, SPI_FLASH_MMAP_DATA)); } -#if !DISABLED_FOR_TARGETS(ESP32C3) -/* On C3 the cache is programmatically split between Icache and dcache and with the default setup we dont leave a lot pages +#if !DISABLED_FOR_TARGETS(ESP32S3, ESP32C3) +/* On S3/C3 the cache is programmatically split between Icache and dcache and with the default setup we dont leave a lot pages available for additional mmaps into instruction space. Disabling this test for now since any hypothetical use case for this is no longer supported "out of the box" */ @@ -215,7 +215,7 @@ TEST_CASE("Can mmap into instruction address space", "[spi_flash][mmap]") } -#endif //!DISABLED_FOR_TARGETS(ESP32C3) +#endif //!DISABLED_FOR_TARGETS(ESP32S3, ESP32C3) TEST_CASE("Can mmap unordered pages into contiguous memory", "[spi_flash][mmap]") diff --git a/components/spi_flash/test/test_spi_flash.c b/components/spi_flash/test/test_spi_flash.c index 99cc7110a7..cc5e1d276a 100644 --- a/components/spi_flash/test/test_spi_flash.c +++ b/components/spi_flash/test/test_spi_flash.c @@ -32,8 +32,6 @@ struct flash_test_ctx { SemaphoreHandle_t done; }; -static const char TAG[] = "test_spi_flash"; - /* Base offset in flash for tests. */ static size_t start; @@ -204,6 +202,11 @@ TEST_CASE("spi flash functions can run along with IRAM interrupts", "[spi_flash] free(read_arg.buf); } +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) +// TODO ESP32-S3 IDF-2021 + +static const char TAG[] = "test_spi_flash"; + typedef struct { uint32_t us_start; size_t len; @@ -332,6 +335,7 @@ TEST_CASE("Test spi_flash read/write performance", "[spi_flash]") free(data_read); } +#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) #if portNUM_PROCESSORS > 1 diff --git a/tools/ci/mypy_ignore_list.txt b/tools/ci/mypy_ignore_list.txt index b4ae4b6bac..13927c8a20 100644 --- a/tools/ci/mypy_ignore_list.txt +++ b/tools/ci/mypy_ignore_list.txt @@ -195,6 +195,7 @@ tools/ci/python_packages/ttfw_idf/DebugUtils.py tools/ci/python_packages/ttfw_idf/IDFApp.py tools/ci/python_packages/ttfw_idf/IDFAssignTest.py tools/ci/python_packages/ttfw_idf/IDFDUT.py +tools/ci/python_packages/ttfw_idf/__init__.py tools/ci/python_packages/ttfw_idf/unity_test_parser.py tools/ci/python_packages/wifi_tools.py tools/ci/test_autocomplete.py diff --git a/tools/ci/python_packages/ttfw_idf/IDFAssignTest.py b/tools/ci/python_packages/ttfw_idf/IDFAssignTest.py index e963536a93..402d61ef0b 100644 --- a/tools/ci/python_packages/ttfw_idf/IDFAssignTest.py +++ b/tools/ci/python_packages/ttfw_idf/IDFAssignTest.py @@ -12,7 +12,7 @@ import yaml try: from yaml import CLoader as Loader except ImportError: - from yaml import Loader as Loader + from yaml import Loader as Loader # type: ignore import gitlab_api from tiny_test_fw.Utility import CIAssignTest @@ -79,30 +79,30 @@ class IDFAssignTest(CIAssignTest.AssignTest): class ExampleGroup(IDFCaseGroup): SORT_KEYS = CI_JOB_MATCH_KEYS = ['env_tag', 'target'] - LOCAL_BUILD_DIR = 'build_examples' + LOCAL_BUILD_DIR = 'build_examples' # type: ignore EXAMPLE_TARGETS = SUPPORTED_TARGETS + PREVIEW_TARGETS - BUILD_JOB_NAMES = ['build_examples_cmake_{}'.format(target) for target in EXAMPLE_TARGETS] + BUILD_JOB_NAMES = ['build_examples_cmake_{}'.format(target) for target in EXAMPLE_TARGETS] # type: ignore class TestAppsGroup(ExampleGroup): LOCAL_BUILD_DIR = 'build_test_apps' TEST_APP_TARGETS = SUPPORTED_TARGETS + PREVIEW_TARGETS - BUILD_JOB_NAMES = ['build_test_apps_{}'.format(target) for target in TEST_APP_TARGETS] + BUILD_JOB_NAMES = ['build_test_apps_{}'.format(target) for target in TEST_APP_TARGETS] # type: ignore class ComponentUTGroup(TestAppsGroup): LOCAL_BUILD_DIR = 'build_component_ut' UNIT_TEST_TARGETS = SUPPORTED_TARGETS + PREVIEW_TARGETS - BUILD_JOB_NAMES = ['build_component_ut_{}'.format(target) for target in UNIT_TEST_TARGETS] + BUILD_JOB_NAMES = ['build_component_ut_{}'.format(target) for target in UNIT_TEST_TARGETS] # type: ignore class UnitTestGroup(IDFCaseGroup): SORT_KEYS = ['test environment', 'tags', 'chip_target'] CI_JOB_MATCH_KEYS = ['test environment'] - LOCAL_BUILD_DIR = 'tools/unit-test-app/builds' + LOCAL_BUILD_DIR = 'tools/unit-test-app/builds' # type: ignore UNIT_TEST_TARGETS = SUPPORTED_TARGETS + PREVIEW_TARGETS - BUILD_JOB_NAMES = ['build_esp_idf_tests_cmake_{}'.format(target) for target in UNIT_TEST_TARGETS] + BUILD_JOB_NAMES = ['build_esp_idf_tests_cmake_{}'.format(target) for target in UNIT_TEST_TARGETS] # type: ignore MAX_CASE = 50 ATTR_CONVERT_TABLE = { @@ -111,6 +111,7 @@ class UnitTestGroup(IDFCaseGroup): DUT_CLS_NAME = { 'esp32': 'ESP32DUT', 'esp32s2': 'ESP32S2DUT', + 'esp32s3': 'ESP32S3DUT', 'esp32c3': 'ESP32C3DUT', 'esp8266': 'ESP8266DUT', } @@ -322,7 +323,7 @@ if __name__ == '__main__': SUPPORTED_TARGETS.extend(PREVIEW_TARGETS) - test_case_paths = [os.path.join(IDF_PATH_FROM_ENV, path) if not os.path.isabs(path) else path for path in args.test_case_paths] + test_case_paths = [os.path.join(IDF_PATH_FROM_ENV, path) if not os.path.isabs(path) else path for path in args.test_case_paths] # type: ignore args_list = [test_case_paths, args.config] if args.case_group == 'example_test': assigner = ExampleAssignTest(*args_list) diff --git a/tools/ci/python_packages/ttfw_idf/IDFDUT.py b/tools/ci/python_packages/ttfw_idf/IDFDUT.py index 8b9d657a9a..d067f5da75 100644 --- a/tools/ci/python_packages/ttfw_idf/IDFDUT.py +++ b/tools/ci/python_packages/ttfw_idf/IDFDUT.py @@ -29,7 +29,7 @@ import pexpect try: import Queue as _queue except ImportError: - import queue as _queue + import queue as _queue # type: ignore from serial.tools import list_ports from tiny_test_fw import DUT, Utility @@ -531,6 +531,18 @@ class ESP32S2DUT(IDFDUT): raise NotImplementedError() +class ESP32S3DUT(IDFDUT): + TARGET = 'esp32s3' + TOOLCHAIN_PREFIX = 'xtensa-esp32s3-elf-' + + @classmethod + def _get_rom(cls): + return esptool.ESP32S3ROM + + def erase_partition(self, esp, partition): + raise NotImplementedError() + + class ESP32C3DUT(IDFDUT): TARGET = 'esp32c3' TOOLCHAIN_PREFIX = 'riscv32-esp-elf-' @@ -556,7 +568,7 @@ class ESP8266DUT(IDFDUT): def get_target_by_rom_class(cls): - for c in [ESP32DUT, ESP32S2DUT, ESP32C3DUT, ESP8266DUT, IDFQEMUDUT]: + for c in [ESP32DUT, ESP32S2DUT, ESP32S3DUT, ESP32C3DUT, ESP8266DUT, IDFQEMUDUT]: if c._get_rom() == cls: return c.TARGET return None @@ -652,5 +664,5 @@ class IDFQEMUDUT(IDFDUT): class ESP32QEMUDUT(IDFQEMUDUT): - TARGET = 'esp32' - TOOLCHAIN_PREFIX = 'xtensa-esp32-elf-' + TARGET = 'esp32' # type: ignore + TOOLCHAIN_PREFIX = 'xtensa-esp32-elf-' # type: ignore diff --git a/tools/ci/python_packages/ttfw_idf/__init__.py b/tools/ci/python_packages/ttfw_idf/__init__.py index f6ffbb8a8b..d4e2768473 100644 --- a/tools/ci/python_packages/ttfw_idf/__init__.py +++ b/tools/ci/python_packages/ttfw_idf/__init__.py @@ -23,19 +23,21 @@ from tiny_test_fw import TinyFW, Utility from .DebugUtils import CustomProcess, GDBBackend, OCDBackend # noqa: export DebugUtils for users from .IDFApp import UT, ComponentUTApp, Example, IDFApp, LoadableElfTestApp, TestApp # noqa: export all Apps for users -from .IDFDUT import ESP32C3DUT, ESP32DUT, ESP32QEMUDUT, ESP32S2DUT, ESP8266DUT, IDFDUT # noqa: export DUTs for users +from .IDFDUT import (ESP32C3DUT, ESP32DUT, ESP32QEMUDUT, ESP32S2DUT, ESP32S3DUT, # noqa: export DUTs for users + ESP8266DUT, IDFDUT) from .unity_test_parser import TestFormat, TestResults # pass TARGET_DUT_CLS_DICT to Env.py to avoid circular dependency issue. TARGET_DUT_CLS_DICT = { 'ESP32': ESP32DUT, 'ESP32S2': ESP32S2DUT, + 'ESP32S3': ESP32S3DUT, 'ESP32C3': ESP32C3DUT, } try: - string_type = basestring + string_type = basestring # type: ignore except NameError: string_type = str diff --git a/tools/unit-test-app/tools/ConfigDependency.yml b/tools/unit-test-app/tools/ConfigDependency.yml index e5e5721cc3..5a29de2952 100644 --- a/tools/unit-test-app/tools/ConfigDependency.yml +++ b/tools/unit-test-app/tools/ConfigDependency.yml @@ -2,4 +2,5 @@ "8Mpsram": "CONFIG_SPIRAM_BANKSWITCH_ENABLE=y" "ESP32_IDF": "CONFIG_IDF_TARGET_ESP32=y" "ESP32S2_IDF": "CONFIG_IDF_TARGET_ESP32S2=y" +"ESP32S3_IDF": "CONFIG_IDF_TARGET_ESP32S3=y" "ESP32C3_IDF": "CONFIG_IDF_TARGET_ESP32C3=y" diff --git a/tools/unit-test-app/tools/UnitTestParser.py b/tools/unit-test-app/tools/UnitTestParser.py index 5b6e6c58c6..897984a906 100644 --- a/tools/unit-test-app/tools/UnitTestParser.py +++ b/tools/unit-test-app/tools/UnitTestParser.py @@ -53,6 +53,8 @@ class Parser(object): TOOLCHAIN_FOR_TARGET = { 'esp32': 'xtensa-esp32-elf-', 'esp32s2': 'xtensa-esp32s2-elf-', + 'esp32s3': 'xtensa-esp32s3-elf-', + 'esp32c3': 'riscv32-esp-elf-', } def __init__(self, binary_folder, node_index):