From 91da3bcdc1ec584b497dd3c6de319f2f914f58cf Mon Sep 17 00:00:00 2001 From: Armando Date: Tue, 5 Sep 2023 11:18:52 +0800 Subject: [PATCH 1/3] adc: fix adc continuous driver conv_frame_size not bigger than 4092 issue --- components/driver/adc.c | 14 +++--- components/hal/adc_hal.c | 62 +++++++++++++++++++------- components/hal/include/hal/adc_hal.h | 11 +++-- components/hal/include/hal/dma_types.h | 1 + 4 files changed, 64 insertions(+), 24 deletions(-) diff --git a/components/driver/adc.c b/components/driver/adc.c index 92ab6714ce..b533f3c22d 100644 --- a/components/driver/adc.c +++ b/components/driver/adc.c @@ -176,7 +176,9 @@ esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config) } //malloc dma descriptor - s_adc_digi_ctx->hal.rx_desc = heap_caps_calloc(1, (sizeof(dma_descriptor_t)) * INTERNAL_BUF_NUM, MALLOC_CAP_DMA); + uint32_t dma_desc_num_per_frame = (init_config->conv_num_each_intr + DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED - 1) / DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED; + uint32_t dma_desc_max_num = dma_desc_num_per_frame * INTERNAL_BUF_NUM; + s_adc_digi_ctx->hal.rx_desc = heap_caps_calloc(1, (sizeof(dma_descriptor_t)) * dma_desc_max_num, MALLOC_CAP_DMA); if (!s_adc_digi_ctx->hal.rx_desc) { ret = ESP_ERR_NO_MEM; goto cleanup; @@ -279,7 +281,8 @@ esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config) #elif CONFIG_IDF_TARGET_ESP32 .dev = (void *)I2S_LL_GET_HW(s_adc_digi_ctx->i2s_host), #endif - .desc_max_num = INTERNAL_BUF_NUM, + .eof_desc_num = INTERNAL_BUF_NUM, + .eof_step = dma_desc_num_per_frame, .dma_chan = dma_chan, .eof_num = init_config->conv_num_each_intr / SOC_ADC_DIGI_DATA_BYTES_PER_CONV }; @@ -336,15 +339,16 @@ static IRAM_ATTR bool s_adc_dma_intr(adc_digi_context_t *adc_digi_ctx) portBASE_TYPE taskAwoken = 0; BaseType_t ret; adc_hal_dma_desc_status_t status = false; - dma_descriptor_t *current_desc = NULL; + uint8_t *finished_buffer = NULL; + uint32_t finished_size = 0; while (1) { - status = adc_hal_get_reading_result(&adc_digi_ctx->hal, adc_digi_ctx->rx_eof_desc_addr, ¤t_desc); + status = adc_hal_get_reading_result(&adc_digi_ctx->hal, adc_digi_ctx->rx_eof_desc_addr, &finished_buffer, &finished_size); if (status != ADC_HAL_DMA_DESC_VALID) { break; } - ret = xRingbufferSendFromISR(adc_digi_ctx->ringbuf_hdl, current_desc->buffer, current_desc->dw0.length, &taskAwoken); + ret = xRingbufferSendFromISR(adc_digi_ctx->ringbuf_hdl, finished_buffer, finished_size, &taskAwoken); if (ret == pdFALSE) { //ringbuffer overflow adc_digi_ctx->ringbuf_overflow_flag = 1; diff --git a/components/hal/adc_hal.c b/components/hal/adc_hal.c index 3eeeae828b..b5d2fa8b57 100644 --- a/components/hal/adc_hal.c +++ b/components/hal/adc_hal.c @@ -303,7 +303,8 @@ void adc_hal_context_config(adc_hal_context_t *hal, const adc_hal_config_t *conf { hal->desc_dummy_head.next = hal->rx_desc; hal->dev = config->dev; - hal->desc_max_num = config->desc_max_num; + hal->eof_desc_num = config->eof_desc_num; + hal->eof_step = config->eof_step; hal->dma_chan = config->dma_chan; hal->eof_num = config->eof_num; } @@ -325,23 +326,33 @@ void adc_hal_digi_init(adc_hal_context_t *hal) #endif } -static void adc_hal_digi_dma_link_descriptors(dma_descriptor_t *desc, uint8_t *data_buf, uint32_t size, uint32_t num) +static void adc_hal_digi_dma_link_descriptors(dma_descriptor_t *desc, uint8_t *data_buf, uint32_t per_eof_size, uint32_t eof_step, uint32_t eof_num) { HAL_ASSERT(((uint32_t)data_buf % 4) == 0); - HAL_ASSERT((size % 4) == 0); + HAL_ASSERT((per_eof_size % 4) == 0); uint32_t n = 0; - while (num--) { - desc[n] = (dma_descriptor_t) { - .dw0.size = size, - .dw0.length = 0, - .dw0.suc_eof = 0, - .dw0.owner = 1, - .buffer = data_buf, - .next = &desc[n+1] - }; - data_buf += size; - n++; + while (eof_num--) { + uint32_t eof_size = per_eof_size; + + for (int i = 0; i < eof_step; i++) { + uint32_t this_len = eof_size; + if (this_len > DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED) { + this_len = DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED; + } + + desc[n] = (dma_descriptor_t) { + .dw0.size = this_len, + .dw0.length = 0, + .dw0.suc_eof = 0, + .dw0.owner = 1, + .buffer = data_buf, + .next = &desc[n+1] + }; + eof_size -= this_len; + data_buf += this_len; + n++; + } } desc[n-1].next = NULL; } @@ -380,12 +391,14 @@ bool adc_hal_check_event(adc_hal_context_t *hal, uint32_t mask) } #endif //#if !SOC_GDMA_SUPPORTED -adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_context_t *hal, const intptr_t eof_desc_addr, dma_descriptor_t **cur_desc) +adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_dma_ctx_t *hal, const intptr_t eof_desc_addr, uint8_t **buffer, uint32_t *len) { HAL_ASSERT(hal->cur_desc_ptr); + if (!hal->cur_desc_ptr->next) { return ADC_HAL_DMA_DESC_NULL; } + if ((intptr_t)hal->cur_desc_ptr == eof_desc_addr) { return ADC_HAL_DMA_DESC_WAITING; } @@ -393,6 +406,25 @@ adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_context_t *hal, con hal->cur_desc_ptr = hal->cur_desc_ptr->next; *cur_desc = hal->cur_desc_ptr; + uint8_t *buffer_start = NULL; + uint32_t eof_len = 0; + dma_descriptor_t *eof_desc = hal->cur_desc_ptr; + + //Find the eof list start + eof_desc = eof_desc->next; + buffer_start = eof_desc->buffer; + eof_len += eof_desc->dw0.length; + + //Find the eof list end + for (int i = 1; i < hal->eof_step; i++) { + eof_desc = eof_desc->next; + eof_len += eof_desc->dw0.length; + } + + hal->cur_desc_ptr = eof_desc; + *buffer = buffer_start; + *len = eof_len; + return ADC_HAL_DMA_DESC_VALID; } diff --git a/components/hal/include/hal/adc_hal.h b/components/hal/include/hal/adc_hal.h index 19b60d0dc5..3973c40489 100644 --- a/components/hal/include/hal/adc_hal.h +++ b/components/hal/include/hal/adc_hal.h @@ -57,7 +57,8 @@ typedef enum adc_hal_dma_desc_status_t { */ typedef struct adc_hal_config_t { void *dev; ///< DMA peripheral address - uint32_t desc_max_num; ///< Number of the descriptors linked once + uint32_t eof_desc_num; ///< Number of dma descriptors that is eof + uint32_t eof_step; ///< Number of linked descriptors that is one eof uint32_t dma_chan; ///< DMA channel to be used uint32_t eof_num; ///< Bytes between 2 in_suc_eof interrupts } adc_hal_config_t; @@ -75,7 +76,8 @@ typedef struct adc_hal_context_t { /**< these need to be configured by `adc_hal_config_t` via driver layer*/ void *dev; ///< DMA address - uint32_t desc_max_num; ///< Number of the descriptors linked once + uint32_t eof_desc_num; ///< Number of dma descriptors that is eof + uint32_t eof_step; ///< Number of linked descriptors that is one eof uint32_t dma_chan; ///< DMA channel to be used uint32_t eof_num; ///< Words between 2 in_suc_eof interrupts } adc_hal_context_t; @@ -217,11 +219,12 @@ bool adc_hal_check_event(adc_hal_context_t *hal, uint32_t mask); * * @param hal Context of the HAL * @param eof_desc_addr The last descriptor that is finished by HW. Should be got from DMA - * @param[out] cur_desc The descriptor with ADC reading result (from the 1st one to the last one (``eof_desc_addr``)) + * @param[out] buffer ADC reading result buffer + * @param[out] len ADC reading result len * * @return See ``adc_hal_dma_desc_status_t`` */ -adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_context_t *hal, const intptr_t eof_desc_addr, dma_descriptor_t **cur_desc); +adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_dma_ctx_t *hal, const intptr_t eof_desc_addr, uint8_t **buffer, uint32_t *len); /** * @brief Clear interrupt diff --git a/components/hal/include/hal/dma_types.h b/components/hal/include/hal/dma_types.h index 5a83295099..4cd87f1d43 100644 --- a/components/hal/include/hal/dma_types.h +++ b/components/hal/include/hal/dma_types.h @@ -44,6 +44,7 @@ ESP_STATIC_ASSERT(sizeof(dma_descriptor_t) == 12, "dma_descriptor_t should occup #define DMA_DESCRIPTOR_BUFFER_OWNER_CPU (0) /*!< DMA buffer is allowed to be accessed by CPU */ #define DMA_DESCRIPTOR_BUFFER_OWNER_DMA (1) /*!< DMA buffer is allowed to be accessed by DMA engine */ #define DMA_DESCRIPTOR_BUFFER_MAX_SIZE (4095) /*!< Maximum size of the buffer that can be attached to descriptor */ +#define DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED (4095-3) /*!< Maximum size of the buffer that can be attached to descriptor, and aligned to 4B */ #ifdef __cplusplus } From 85ce6abdec9da5136fbb0157364f1607450a3f84 Mon Sep 17 00:00:00 2001 From: Armando Date: Wed, 12 Jul 2023 16:58:46 +0800 Subject: [PATCH 2/3] Fix #10804 by running continuous ADC DMA in endless loop instead of restarting after each run (descriptor chain) to avoid losing samples. Use descriptor error callback for GDMA to check for DMA buffer overrun. --- components/driver/adc.c | 17 +++++++++++------ components/hal/adc_hal.c | 7 ++++++- components/hal/include/hal/adc_hal.h | 9 ++++++++- 3 files changed, 25 insertions(+), 8 deletions(-) diff --git a/components/driver/adc.c b/components/driver/adc.c index b533f3c22d..3311d1c799 100644 --- a/components/driver/adc.c +++ b/components/driver/adc.c @@ -114,6 +114,7 @@ static IRAM_ATTR bool s_adc_dma_intr(adc_digi_context_t *adc_digi_ctx); #if SOC_GDMA_SUPPORTED static IRAM_ATTR bool adc_dma_in_suc_eof_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data); +static bool adc_dma_descr_err_callback(gdma_channel_handle_t dma_chan, void *user_data); #else static IRAM_ATTR void adc_dma_intr_handler(void *arg); #endif @@ -230,7 +231,8 @@ esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config) gdma_apply_strategy(s_adc_digi_ctx->rx_dma_channel, &strategy_config); gdma_rx_event_callbacks_t cbs = { - .on_recv_eof = adc_dma_in_suc_eof_callback + .on_recv_eof = adc_dma_in_suc_eof_callback, + .on_descr_err = adc_dma_descr_err_callback }; gdma_register_rx_event_callbacks(s_adc_digi_ctx->rx_dma_channel, &cbs, s_adc_digi_ctx); @@ -312,6 +314,13 @@ static IRAM_ATTR bool adc_dma_in_suc_eof_callback(gdma_channel_handle_t dma_chan s_adc_digi_ctx->rx_eof_desc_addr = event_data->rx_eof_desc_addr; return s_adc_dma_intr(user_data); } + +static bool adc_dma_descr_err_callback(gdma_channel_handle_t dma_chan, void *user_data) +{ + ESP_EARLY_LOGE(ADC_TAG, "GDMA descriptor error occurred, probable ADC data loss, CPU load too high?"); + return false; +} + #else static IRAM_ATTR void adc_dma_intr_handler(void *arg) { @@ -349,17 +358,13 @@ static IRAM_ATTR bool s_adc_dma_intr(adc_digi_context_t *adc_digi_ctx) } ret = xRingbufferSendFromISR(adc_digi_ctx->ringbuf_hdl, finished_buffer, finished_size, &taskAwoken); + adc_hal_read_desc_finish (&adc_digi_ctx->hal); if (ret == pdFALSE) { //ringbuffer overflow adc_digi_ctx->ringbuf_overflow_flag = 1; } } - if (status == ADC_HAL_DMA_DESC_NULL) { - //start next turns of dma operation - adc_hal_digi_start(&adc_digi_ctx->hal, adc_digi_ctx->rx_dma_buf); - } - return (taskAwoken == pdTRUE); } diff --git a/components/hal/adc_hal.c b/components/hal/adc_hal.c index b5d2fa8b57..a9ea744f5d 100644 --- a/components/hal/adc_hal.c +++ b/components/hal/adc_hal.c @@ -354,7 +354,7 @@ static void adc_hal_digi_dma_link_descriptors(dma_descriptor_t *desc, uint8_t *d n++; } } - desc[n-1].next = NULL; + desc[n-1].next = desc; } void adc_hal_digi_start(adc_hal_context_t *hal, uint8_t *data_buf) @@ -428,6 +428,11 @@ adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_dma_ctx_t *hal, con return ADC_HAL_DMA_DESC_VALID; } +void adc_hal_read_desc_finish(adc_hal_dma_ctx_t *hal) { + // Allow DMA to re-use descriptor. + hal->cur_desc_ptr->dw0.owner = 1; +} + void adc_hal_digi_clr_intr(adc_hal_context_t *hal, uint32_t mask) { adc_dma_ll_rx_clear_intr(hal->dev, hal->dma_chan, mask); diff --git a/components/hal/include/hal/adc_hal.h b/components/hal/include/hal/adc_hal.h index 3973c40489..4708c52754 100644 --- a/components/hal/include/hal/adc_hal.h +++ b/components/hal/include/hal/adc_hal.h @@ -215,7 +215,7 @@ bool adc_hal_check_event(adc_hal_context_t *hal, uint32_t mask); #endif /** - * @brief Get the ADC reading result + * @brief Get the ADC reading result. Call adc_hal_read_desc_finish after using the descriptor. * * @param hal Context of the HAL * @param eof_desc_addr The last descriptor that is finished by HW. Should be got from DMA @@ -375,3 +375,10 @@ uint32_t adc_hal_self_calibration(adc_ll_num_t adc_n, adc_channel_t channel, adc * @prarm adc_n ADC unit. */ #define adc_hal_rtc_output_invert(adc_n, inv_en) adc_ll_rtc_output_invert(adc_n, inv_en) + +/** + * @brief Finishes reading the current descriptor and frees it for repeated usage by DMA. + * + * @param hal Context of the HAL + */ +void adc_hal_read_desc_finish(adc_hal_dma_ctx_t *hal); From b282c244cb7d7df9323cebc85e74e01d17da581b Mon Sep 17 00:00:00 2001 From: Armando Date: Wed, 12 Jul 2023 17:01:39 +0800 Subject: [PATCH 3/3] DMA EOF may happens per multiple dma descriptors, instead of only one. Closes https://github.com/espressif/esp-idf/pull/11500 --- components/driver/adc.c | 12 +----------- components/hal/adc_hal.c | 25 ++++++++++++++----------- components/hal/include/hal/adc_hal.h | 11 ++--------- 3 files changed, 17 insertions(+), 31 deletions(-) diff --git a/components/driver/adc.c b/components/driver/adc.c index 3311d1c799..440328694b 100644 --- a/components/driver/adc.c +++ b/components/driver/adc.c @@ -114,7 +114,6 @@ static IRAM_ATTR bool s_adc_dma_intr(adc_digi_context_t *adc_digi_ctx); #if SOC_GDMA_SUPPORTED static IRAM_ATTR bool adc_dma_in_suc_eof_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data); -static bool adc_dma_descr_err_callback(gdma_channel_handle_t dma_chan, void *user_data); #else static IRAM_ATTR void adc_dma_intr_handler(void *arg); #endif @@ -231,8 +230,7 @@ esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config) gdma_apply_strategy(s_adc_digi_ctx->rx_dma_channel, &strategy_config); gdma_rx_event_callbacks_t cbs = { - .on_recv_eof = adc_dma_in_suc_eof_callback, - .on_descr_err = adc_dma_descr_err_callback + .on_recv_eof = adc_dma_in_suc_eof_callback }; gdma_register_rx_event_callbacks(s_adc_digi_ctx->rx_dma_channel, &cbs, s_adc_digi_ctx); @@ -314,13 +312,6 @@ static IRAM_ATTR bool adc_dma_in_suc_eof_callback(gdma_channel_handle_t dma_chan s_adc_digi_ctx->rx_eof_desc_addr = event_data->rx_eof_desc_addr; return s_adc_dma_intr(user_data); } - -static bool adc_dma_descr_err_callback(gdma_channel_handle_t dma_chan, void *user_data) -{ - ESP_EARLY_LOGE(ADC_TAG, "GDMA descriptor error occurred, probable ADC data loss, CPU load too high?"); - return false; -} - #else static IRAM_ATTR void adc_dma_intr_handler(void *arg) { @@ -358,7 +349,6 @@ static IRAM_ATTR bool s_adc_dma_intr(adc_digi_context_t *adc_digi_ctx) } ret = xRingbufferSendFromISR(adc_digi_ctx->ringbuf_hdl, finished_buffer, finished_size, &taskAwoken); - adc_hal_read_desc_finish (&adc_digi_ctx->hal); if (ret == pdFALSE) { //ringbuffer overflow adc_digi_ctx->ringbuf_overflow_flag = 1; diff --git a/components/hal/adc_hal.c b/components/hal/adc_hal.c index a9ea744f5d..614a3117a7 100644 --- a/components/hal/adc_hal.c +++ b/components/hal/adc_hal.c @@ -331,6 +331,7 @@ static void adc_hal_digi_dma_link_descriptors(dma_descriptor_t *desc, uint8_t *d HAL_ASSERT(((uint32_t)data_buf % 4) == 0); HAL_ASSERT((per_eof_size % 4) == 0); uint32_t n = 0; + dma_descriptor_t *desc_head = desc; while (eof_num--) { uint32_t eof_size = per_eof_size; @@ -354,7 +355,7 @@ static void adc_hal_digi_dma_link_descriptors(dma_descriptor_t *desc, uint8_t *d n++; } } - desc[n-1].next = desc; + desc[n-1].next = desc_head; } void adc_hal_digi_start(adc_hal_context_t *hal, uint8_t *data_buf) @@ -369,7 +370,7 @@ void adc_hal_digi_start(adc_hal_context_t *hal, uint8_t *data_buf) //reset the current descriptor address hal->cur_desc_ptr = &hal->desc_dummy_head; - adc_hal_digi_dma_link_descriptors(hal->rx_desc, data_buf, hal->eof_num * SOC_ADC_DIGI_DATA_BYTES_PER_CONV, hal->desc_max_num); + adc_hal_digi_dma_link_descriptors(hal->rx_desc, data_buf, hal->eof_num * SOC_ADC_DIGI_DATA_BYTES_PER_CONV, hal->eof_step, hal->eof_desc_num); //start DMA adc_dma_ll_rx_start(hal->dev, hal->dma_chan, (lldesc_t *)hal->rx_desc); @@ -391,7 +392,7 @@ bool adc_hal_check_event(adc_hal_context_t *hal, uint32_t mask) } #endif //#if !SOC_GDMA_SUPPORTED -adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_dma_ctx_t *hal, const intptr_t eof_desc_addr, uint8_t **buffer, uint32_t *len) +adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_context_t *hal, const intptr_t eof_desc_addr, uint8_t **buffer, uint32_t *len) { HAL_ASSERT(hal->cur_desc_ptr); @@ -403,24 +404,31 @@ adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_dma_ctx_t *hal, con return ADC_HAL_DMA_DESC_WAITING; } - hal->cur_desc_ptr = hal->cur_desc_ptr->next; - *cur_desc = hal->cur_desc_ptr; - uint8_t *buffer_start = NULL; uint32_t eof_len = 0; dma_descriptor_t *eof_desc = hal->cur_desc_ptr; //Find the eof list start eof_desc = eof_desc->next; + eof_desc->dw0.owner = 1; buffer_start = eof_desc->buffer; eof_len += eof_desc->dw0.length; + if ((intptr_t)eof_desc == eof_desc_addr) { + goto valid; + } //Find the eof list end for (int i = 1; i < hal->eof_step; i++) { eof_desc = eof_desc->next; + eof_desc->dw0.owner = 1; eof_len += eof_desc->dw0.length; + if ((intptr_t)eof_desc == eof_desc_addr) { + goto valid; + } } + +valid: hal->cur_desc_ptr = eof_desc; *buffer = buffer_start; *len = eof_len; @@ -428,11 +436,6 @@ adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_dma_ctx_t *hal, con return ADC_HAL_DMA_DESC_VALID; } -void adc_hal_read_desc_finish(adc_hal_dma_ctx_t *hal) { - // Allow DMA to re-use descriptor. - hal->cur_desc_ptr->dw0.owner = 1; -} - void adc_hal_digi_clr_intr(adc_hal_context_t *hal, uint32_t mask) { adc_dma_ll_rx_clear_intr(hal->dev, hal->dma_chan, mask); diff --git a/components/hal/include/hal/adc_hal.h b/components/hal/include/hal/adc_hal.h index 4708c52754..ab08a5dd47 100644 --- a/components/hal/include/hal/adc_hal.h +++ b/components/hal/include/hal/adc_hal.h @@ -215,7 +215,7 @@ bool adc_hal_check_event(adc_hal_context_t *hal, uint32_t mask); #endif /** - * @brief Get the ADC reading result. Call adc_hal_read_desc_finish after using the descriptor. + * @brief Get the ADC reading result * * @param hal Context of the HAL * @param eof_desc_addr The last descriptor that is finished by HW. Should be got from DMA @@ -224,7 +224,7 @@ bool adc_hal_check_event(adc_hal_context_t *hal, uint32_t mask); * * @return See ``adc_hal_dma_desc_status_t`` */ -adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_dma_ctx_t *hal, const intptr_t eof_desc_addr, uint8_t **buffer, uint32_t *len); +adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_context_t *hal, const intptr_t eof_desc_addr, uint8_t **buffer, uint32_t *len); /** * @brief Clear interrupt @@ -375,10 +375,3 @@ uint32_t adc_hal_self_calibration(adc_ll_num_t adc_n, adc_channel_t channel, adc * @prarm adc_n ADC unit. */ #define adc_hal_rtc_output_invert(adc_n, inv_en) adc_ll_rtc_output_invert(adc_n, inv_en) - -/** - * @brief Finishes reading the current descriptor and frees it for repeated usage by DMA. - * - * @param hal Context of the HAL - */ -void adc_hal_read_desc_finish(adc_hal_dma_ctx_t *hal);