ci: partially enable ut tests for esp32c2

Disabled test cases are tracked in:

 IDF-4465, IDF-5045, IDF-5057, IDF-5058, IDF-5059, IDF-5060, IDF-5061, IDF-5131

- test_fatfs: IDF-5136

- test_pm: IDF-5053

- test_cache_mmu: IDF-5138

- test_partitions: IDF-5137

- test_vfs: IDF-5139

- test_freertos: IDF-5140

- test_wpa_supplicant: IDF-5046

- test_mbedtls: IDF-5141

- test_pthread: IDF-5142

- test_protocomm: IDF-5143

- test_lightsleep: IDF-5053

- test_taskwdt: IDF-5055

- test_tcp_transport: IDF-5144

- test_app_update: IDF-5145

- test_timer: IDF-5052

- test_spi: IDF-5146

- test_rtc_clk: IDF-5060

- test_heap: IDF-5167

ci: fixed issues for tests of libgcc, ets_timer, newlib

test_pm: support on C2

components/driver/test/test_spi_bus_lock.c

@@ -283,11 +283,12 @@ static void test_bus_lock(bool test_flash)
 
 #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3, ESP32S3, ESP32C2)
 //no runners
+//IDF-5049
 TEST_CASE("spi bus lock, with flash","[spi][test_env=UT_T1_ESP_FLASH]")
 {
     test_bus_lock(true);
 }
-#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
+#endif //!TEMPORARY_DISABLED_FOR_TARGETS(...)
 
 
 TEST_CASE("spi bus lock","[spi]")

components/driver/test/test_spi_master.c

@@ -30,6 +30,7 @@
 #include "soc/soc_memory_layout.h"
 #include "driver/spi_common_internal.h"
 #include "esp_private/esp_clk.h"
+#include "test_utils.h"
 
 
 const static char TAG[] = "test_spi";
@@ -604,6 +605,8 @@ TEST_CASE("SPI Master no response when switch from host1 (SPI2) to host2 (SPI3)"
     TEST_ESP_OK(spi_bus_free(host));
 }
 
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
+//IDF-5146
 DRAM_ATTR  static uint32_t data_dram[80] = {0};
 //force to place in code area.
 static const uint8_t data_drom[320 + 3] = {
@@ -717,6 +720,7 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]")
     free(data_iram);
 #endif
 }
+#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
 
 //this part tests 3 DMA issues in master mode, full-duplex in IDF2.1
 // 1. RX buffer not aligned (start and end)
@@ -1123,6 +1127,7 @@ TEST_CASE("SPI master hd dma TX without RX test", "[spi]")
 }
 #endif  //#if (TEST_SPI_PERIPH_NUM >= 2)
 
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
 #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32)    //TODO: IDF-3494
 #define FD_TEST_BUF_SIZE    32
 #define TEST_NUM            4
@@ -1298,6 +1303,7 @@ static void fd_slave(void)
 
 TEST_CASE_MULTIPLE_DEVICES("SPI Master: FD, DMA, Master Single Direction Test", "[spi_ms][test_env=Example_SPI_Multi_device]", fd_master, fd_slave);
 #endif  //#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32)    //TODO: IDF-3494
+#endif  //#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)    //TODO: IDF-3494
 
 //NOTE: Explained in IDF-1445 | MR !14996
 #if !(CONFIG_SPIRAM) || (CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL >= 16384)
@@ -1306,6 +1312,8 @@ TEST_CASE_MULTIPLE_DEVICES("SPI Master: FD, DMA, Master Single Direction Test",
  ********************************************************************************/
 //Disabled since the check in portENTER_CRITICAL in esp_intr_enable/disable increase the delay
 #ifndef CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
+//IDF-5146
 
 #define RECORD_TIME_PREPARE() uint32_t __t1, __t2
 #define RECORD_TIME_START()   do {__t1 = esp_cpu_get_ccount();}while(0)
@@ -1446,5 +1454,7 @@ TEST_CASE("spi_speed", "[spi]")
     spi_device_release_bus(spi);
     master_free_device_bus(spi);
 }
+#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
+
 #endif // CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE
 #endif // !(CONFIG_SPIRAM) || (CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL >= 16384)

components/driver/test/test_spi_param.c

@@ -622,7 +622,7 @@ TEST_CASE("Slave receive correct data", "[spi]")
     }
 }
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3)
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2)
 //These tests are ESP32 only due to lack of runners
 /********************************************************************************
  *      Test By Master & Slave (2 boards)
@@ -1175,6 +1175,6 @@ spitest_param_set_t mode_conf[] = {
 };
 TEST_SPI_MASTER_SLAVE(MODE, mode_conf, "")
 
-#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3)
+#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2)
 
 #endif // #if (TEST_SPI_PERIPH_NUM >= 2)

components/driver/test/test_spi_slave.c

@@ -261,6 +261,7 @@ TEST_CASE("test slave send unaligned","[spi]")
 
 #endif // #if (TEST_SPI_PERIPH_NUM >= 2)
 
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
 #if (TEST_SPI_PERIPH_NUM == 1)
 //These tests are for chips which only have 1 SPI controller
 /********************************************************************************
@@ -384,3 +385,4 @@ static void unaligned_test_slave(void)
 TEST_CASE_MULTIPLE_DEVICES("SPI_Slave_Unaligned_Test", "[spi_ms][test_env=Example_SPI_Multi_device][timeout=120]", unaligned_test_master, unaligned_test_slave);
 
 #endif  //#if (TEST_SPI_PERIPH_NUM == 1)
+#endif //!TEMPORARY_DISABLED_FOR_TARGETS(...)

components/driver/test/test_spi_slave_hd.c

@@ -601,6 +601,7 @@ TEST_CASE("test spi slave hd segment mode, master too long", "[spi][spi_slv_hd]"
 
 #if (TEST_SPI_PERIPH_NUM == 1)
 #if SOC_SPI_SUPPORT_SLAVE_HD_VER2
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
 //These tests are for chips which only have 1 SPI controller
 /********************************************************************************
  *      Test By Master & Slave (2 boards)
@@ -747,9 +748,7 @@ static void hd_slave(void)
     spi_slave_hd_deinit(TEST_SLAVE_HOST);
 }
 
-
 TEST_CASE_MULTIPLE_DEVICES("SPI Slave HD: segment mode, master sends too long", "[spi_ms][test_env=Example_SPI_Multi_device]", hd_master, hd_slave);
-
+#endif //!TEMPORARY_DISABLED_FOR_TARGETS(...)
 #endif  //#if SOC_SPI_SUPPORT_SLAVE_HD_VER2
-
 #endif  //#if (TEST_SPI_PERIPH_NUM == 1)