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fix(lp_io): w1ts/w1tc register access performance is improved

Browse Source 
by avoiding "read-modify-write" operation. The registers designed to be
write only.
This commit is contained in:
Song Ruo Jing
2025-07-22 12:17:31 +08:00
parent 63050580f5
commit 6b0eb7fcb3
8 changed files with 38 additions and 38 deletions
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10
components/hal/esp32/include/hal/rtc_io_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -73,7 +73,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
*/ */
static inline void rtcio_ll_output_enable(int rtcio_num) static inline void rtcio_ll_output_enable(int rtcio_num)
{ {
RTCIO.enable_w1ts.w1ts = (1U << rtcio_num); RTCIO.enable_w1ts.val = (1U << (rtcio_num + RTC_GPIO_ENABLE_W1TS_S));
} }
/** /**
@@ -83,7 +83,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num)
*/ */
static inline void rtcio_ll_output_disable(int rtcio_num) static inline void rtcio_ll_output_disable(int rtcio_num)
{ {
RTCIO.enable_w1tc.w1tc = (1U << rtcio_num); RTCIO.enable_w1tc.val = (1U << (rtcio_num + RTC_GPIO_ENABLE_W1TC_S));
} }
/** /**
@@ -95,9 +95,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num)
static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
{ {
if (level) { if (level) {
RTCIO.out_w1ts.w1ts = (1U << rtcio_num); RTCIO.out_w1ts.val = (1U << (rtcio_num + RTC_GPIO_OUT_DATA_W1TS_S));
} else { } else {
RTCIO.out_w1tc.w1tc = (1U << rtcio_num); RTCIO.out_w1tc.val = (1U << (rtcio_num + RTC_GPIO_OUT_DATA_W1TC_S));
} }
} }

10
components/hal/esp32c5/include/hal/rtc_io_ll.h
View File

@@ -105,7 +105,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
*/ */
static inline void rtcio_ll_output_enable(int rtcio_num) static inline void rtcio_ll_output_enable(int rtcio_num)
{ {
LP_GPIO.enable_w1ts.enable_w1ts = BIT(rtcio_num); LP_GPIO.enable_w1ts.val = BIT(rtcio_num);
} }
/** /**
@@ -115,7 +115,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num)
*/ */
static inline void rtcio_ll_output_disable(int rtcio_num) static inline void rtcio_ll_output_disable(int rtcio_num)
{ {
LP_GPIO.enable_w1tc.enable_w1tc = BIT(rtcio_num); LP_GPIO.enable_w1tc.val = BIT(rtcio_num);
} }
/** /**
@@ -127,9 +127,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num)
static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
{ {
if (level) { if (level) {
LP_GPIO.out_w1ts.out_w1ts = BIT(rtcio_num); LP_GPIO.out_w1ts.val = BIT(rtcio_num);
} else { } else {
LP_GPIO.out_w1tc.out_w1tc = BIT(rtcio_num); LP_GPIO.out_w1tc.val = BIT(rtcio_num);
} }
} }
@@ -440,7 +440,7 @@ static inline uint32_t rtcio_ll_get_interrupt_status(void)
*/ */
static inline void rtcio_ll_clear_interrupt_status(void) static inline void rtcio_ll_clear_interrupt_status(void)
{ {
LP_GPIO.status_w1tc.status_w1tc = 0x7F; LP_GPIO.status_w1tc.val = 0x7F;
} }
#ifdef __cplusplus #ifdef __cplusplus

10
components/hal/esp32c6/include/hal/rtc_io_ll.h
View File

@@ -103,7 +103,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
*/ */
static inline void rtcio_ll_output_enable(int rtcio_num) static inline void rtcio_ll_output_enable(int rtcio_num)
{ {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_enable_w1ts, enable_w1ts, BIT(rtcio_num)); LP_IO.out_enable_w1ts.val = BIT(rtcio_num);
} }
/** /**
@@ -113,7 +113,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num)
*/ */
static inline void rtcio_ll_output_disable(int rtcio_num) static inline void rtcio_ll_output_disable(int rtcio_num)
{ {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_enable_w1tc, enable_w1tc, BIT(rtcio_num)); LP_IO.out_enable_w1tc.val = BIT(rtcio_num);
} }
/** /**
@@ -125,9 +125,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num)
static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
{ {
if (level) { if (level) {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1ts, out_w1ts, BIT(rtcio_num)); LP_IO.out_data_w1ts.val = BIT(rtcio_num);
} else { } else {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1tc, out_w1tc, BIT(rtcio_num)); LP_IO.out_data_w1tc.val = BIT(rtcio_num);
} }
} }
@@ -446,7 +446,7 @@ static inline uint32_t rtcio_ll_get_interrupt_status(void)
*/ */
static inline void rtcio_ll_clear_interrupt_status(void) static inline void rtcio_ll_clear_interrupt_status(void)
{ {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.status_w1tc, status_intr_w1tc, 0xff); LP_IO.status_w1tc.val = 0xFF;
} }
#ifdef __cplusplus #ifdef __cplusplus

10
components/hal/esp32c61/include/hal/rtc_io_ll.h
View File

@@ -104,7 +104,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
*/ */
static inline void rtcio_ll_output_enable(int rtcio_num) static inline void rtcio_ll_output_enable(int rtcio_num)
{ {
LP_GPIO.enable_w1ts.enable_w1ts = BIT(rtcio_num); LP_GPIO.enable_w1ts.val = BIT(rtcio_num);
} }
/** /**
@@ -114,7 +114,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num)
*/ */
static inline void rtcio_ll_output_disable(int rtcio_num) static inline void rtcio_ll_output_disable(int rtcio_num)
{ {
LP_GPIO.enable_w1tc.enable_w1tc = BIT(rtcio_num); LP_GPIO.enable_w1tc.val = BIT(rtcio_num);
} }
/** /**
@@ -126,9 +126,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num)
static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
{ {
if (level) { if (level) {
LP_GPIO.out_w1ts.out_w1ts = BIT(rtcio_num); LP_GPIO.out_w1ts.val = BIT(rtcio_num);
} else { } else {
LP_GPIO.out_w1tc.out_w1tc = BIT(rtcio_num); LP_GPIO.out_w1tc.val = BIT(rtcio_num);
} }
} }
@@ -439,7 +439,7 @@ static inline uint32_t rtcio_ll_get_interrupt_status(void)
*/ */
static inline void rtcio_ll_clear_interrupt_status(void) static inline void rtcio_ll_clear_interrupt_status(void)
{ {
LP_GPIO.status_w1tc.status_w1tc = 0x7F; LP_GPIO.status_w1tc.val = 0x7F;
} }
#ifdef __cplusplus #ifdef __cplusplus

10
components/hal/esp32h4/include/hal/rtc_io_ll.h
View File

@@ -104,7 +104,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
*/ */
static inline void rtcio_ll_output_enable(int rtcio_num) static inline void rtcio_ll_output_enable(int rtcio_num)
{ {
LP_GPIO.enable_w1ts.enable_w1ts = BIT(rtcio_num); LP_GPIO.enable_w1ts.val = BIT(rtcio_num);
} }
/** /**
@@ -114,7 +114,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num)
*/ */
static inline void rtcio_ll_output_disable(int rtcio_num) static inline void rtcio_ll_output_disable(int rtcio_num)
{ {
LP_GPIO.enable_w1tc.enable_w1tc = BIT(rtcio_num); LP_GPIO.enable_w1tc.val = BIT(rtcio_num);
} }
/** /**
@@ -126,9 +126,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num)
static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
{ {
if (level) { if (level) {
LP_GPIO.out_w1ts.out_w1ts = BIT(rtcio_num); LP_GPIO.out_w1ts.val = BIT(rtcio_num);
} else { } else {
LP_GPIO.out_w1tc.out_w1tc = BIT(rtcio_num); LP_GPIO.out_w1tc.val = BIT(rtcio_num);
} }
} }
@@ -439,7 +439,7 @@ static inline uint32_t rtcio_ll_get_interrupt_status(void)
*/ */
static inline void rtcio_ll_clear_interrupt_status(void) static inline void rtcio_ll_clear_interrupt_status(void)
{ {
LP_GPIO.status_w1tc.status_w1tc = 0x3F; LP_GPIO.status_w1tc.val = 0x3F;
} }
#ifdef __cplusplus #ifdef __cplusplus

10
components/hal/esp32p4/include/hal/rtc_io_ll.h
View File

@@ -137,7 +137,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
*/ */
static inline void rtcio_ll_output_enable(int rtcio_num) static inline void rtcio_ll_output_enable(int rtcio_num)
{ {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1ts, reg_gpio_enable_data_w1ts, BIT(rtcio_num)); LP_GPIO.enable_w1ts.val = BIT(rtcio_num);
} }
/** /**
@@ -147,7 +147,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num)
*/ */
static inline void rtcio_ll_output_disable(int rtcio_num) static inline void rtcio_ll_output_disable(int rtcio_num)
{ {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1tc, reg_gpio_enable_data_w1tc, BIT(rtcio_num)); LP_GPIO.enable_w1tc.val = BIT(rtcio_num);
// Ensure no other output signal is routed via LP_GPIO matrix to this pin // Ensure no other output signal is routed via LP_GPIO matrix to this pin
LP_GPIO.func_out_sel_cfg[rtcio_num].func_out_sel = SIG_LP_GPIO_OUT_IDX; LP_GPIO.func_out_sel_cfg[rtcio_num].func_out_sel = SIG_LP_GPIO_OUT_IDX;
} }
@@ -161,9 +161,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num)
static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
{ {
if (level) { if (level) {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1ts, reg_gpio_out_data_w1ts, BIT(rtcio_num)); LP_GPIO.out_w1ts.val = BIT(rtcio_num);
} else { } else {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1tc, reg_gpio_out_data_w1tc, BIT(rtcio_num)); LP_GPIO.out_w1tc.val = BIT(rtcio_num);
} }
} }
@@ -474,7 +474,7 @@ static inline uint32_t rtcio_ll_get_interrupt_status(void)
*/ */
static inline void rtcio_ll_clear_interrupt_status(void) static inline void rtcio_ll_clear_interrupt_status(void)
{ {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.status_w1tc, reg_gpio_status_data_w1tc, 0xFFFF); LP_GPIO.status_w1tc.val = 0xFFFF;
} }
#ifdef __cplusplus #ifdef __cplusplus

8
components/hal/esp32s2/include/hal/rtc_io_ll.h
View File

@@ -84,7 +84,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
*/ */
static inline void rtcio_ll_output_enable(int rtcio_num) static inline void rtcio_ll_output_enable(int rtcio_num)
{ {
RTCIO.enable_w1ts.w1ts = (1U << rtcio_num); RTCIO.enable_w1ts.val = (1U << (rtcio_num + RTC_GPIO_ENABLE_W1TS_S));
} }
/** /**
@@ -94,7 +94,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num)
*/ */
static inline void rtcio_ll_output_disable(int rtcio_num) static inline void rtcio_ll_output_disable(int rtcio_num)
{ {
RTCIO.enable_w1tc.w1tc = (1U << rtcio_num); RTCIO.enable_w1tc.val = (1U << (rtcio_num + RTC_GPIO_ENABLE_W1TC_S));
} }
/** /**
@@ -106,9 +106,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num)
static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
{ {
if (level) { if (level) {
RTCIO.out_w1ts.w1ts = (1U << rtcio_num); RTCIO.out_w1ts.val = (1U << (rtcio_num + RTC_GPIO_OUT_DATA_W1TS_S));
} else { } else {
RTCIO.out_w1tc.w1tc = (1U << rtcio_num); RTCIO.out_w1tc.val = (1U << (rtcio_num + RTC_GPIO_OUT_DATA_W1TC_S));
} }
} }

8
components/hal/esp32s3/include/hal/rtc_io_ll.h
View File

@@ -93,7 +93,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
*/ */
static inline void rtcio_ll_output_enable(int rtcio_num) static inline void rtcio_ll_output_enable(int rtcio_num)
{ {
RTCIO.enable_w1ts.w1ts = (1U << rtcio_num); RTCIO.enable_w1ts.val = (1U << (rtcio_num + RTC_GPIO_ENABLE_W1TS_S));
} }
/** /**
@@ -103,7 +103,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num)
*/ */
static inline void rtcio_ll_output_disable(int rtcio_num) static inline void rtcio_ll_output_disable(int rtcio_num)
{ {
RTCIO.enable_w1tc.w1tc = (1U << rtcio_num); RTCIO.enable_w1tc.val = (1U << (rtcio_num + RTC_GPIO_ENABLE_W1TC_S));
} }
/** /**
@@ -115,9 +115,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num)
static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
{ {
if (level) { if (level) {
RTCIO.out_w1ts.w1ts = (1U << rtcio_num); RTCIO.out_w1ts.val = (1U << (rtcio_num + RTC_GPIO_OUT_DATA_W1TS_S));
} else { } else {
RTCIO.out_w1tc.w1tc = (1U << rtcio_num); RTCIO.out_w1tc.val = (1U << (rtcio_num + RTC_GPIO_OUT_DATA_W1TC_S));
} }
} }