diff --git a/components/hal/esp32s3/include/hal/adc_ll.h b/components/hal/esp32s3/include/hal/adc_ll.h index 276d587adf..188c44788e 100644 --- a/components/hal/esp32s3/include/hal/adc_ll.h +++ b/components/hal/esp32s3/include/hal/adc_ll.h @@ -13,17 +13,23 @@ // limitations under the License. #pragma once +#include +#include #include "soc/adc_periph.h" #include "hal/adc_types.h" #include "soc/apb_saradc_struct.h" #include "soc/apb_saradc_reg.h" #include "soc/rtc_cntl_struct.h" -#include +#include "soc/rtc_cntl_reg.h" #ifdef __cplusplus extern "C" { #endif +#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15 +#define ADC_LL_CLKM_DIV_B_DEFAULT 1 +#define ADC_LL_CLKM_DIV_A_DEFAULT 0 + typedef enum { ADC_NUM_1 = 0, /*!< SAR ADC 1 */ ADC_NUM_2 = 1, /*!< SAR ADC 2 */ @@ -44,6 +50,40 @@ typedef enum { ADC_RTC_DATA_FAIL = -1, } adc_ll_rtc_raw_data_t; +typedef enum { + ADC_LL_CTRL_RTC = 0, ///< For ADC1. Select RTC controller. + ADC_LL_CTRL_ULP = 1, ///< For ADC1 and ADC2. Select ULP controller. + ADC_LL_CTRL_DIG = 2, ///< For ADC1. Select DIG controller. + ADC_LL_CTRL_ARB = 4, ///< For ADC2. The controller is selected by the arbiter. +} adc_ll_controller_t; + +/** + * @brief ADC digital controller (DMA mode) work mode. + * + * @note The conversion mode affects the sampling frequency: + * SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once. + * SINGLE_UNIT_2: When the measurement is triggered, only ADC2 is sampled once. + * BOTH_UNIT : When the measurement is triggered, ADC1 and ADC2 are sampled at the same time. + * ALTER_UNIT : When the measurement is triggered, ADC1 or ADC2 samples alternately. + */ +typedef enum { + ADC_LL_DIGI_CONV_ONLY_ADC1 = 0, // Only use ADC1 for conversion + ADC_LL_DIGI_CONV_ONLY_ADC2 = 1, // Only use ADC2 for conversion + ADC_LL_DIGI_CONV_BOTH_UNIT = 2, // Use Both ADC1 and ADC2 for conversion simultaneously + ADC_LL_DIGI_CONV_ALTER_UNIT = 3 // Use both ADC1 and ADC2 for conversion by turn. e.g. ADC1 -> ADC2 -> ADC1 -> ADC2 ..... +} adc_ll_digi_convert_mode_t; + +typedef struct { + union { + struct { + uint8_t atten: 2; + uint8_t channel: 4; + uint8_t reserved: 2; + }; + uint8_t val; + }; +} __attribute__((packed)) adc_ll_digi_pattern_table_t; + #ifdef _MSC_VER #pragma pack(push, 1) #endif /* _MSC_VER */ @@ -70,23 +110,6 @@ typedef struct { #pragma pack(pop) #endif /* _MSC_VER */ -/** - * @brief ADC controller type selection. - * - * @note For ADC2, use the force option with care. The system power consumption detection will use ADC2. - * If it is forced to switch to another controller, it may cause the system to obtain incorrect values. - * @note Normally, there is no need to switch the controller manually. - */ -typedef enum { - ADC_CTRL_RTC = 0, /*!> offset)); //Clear old data + tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; //Fill in the new data + APB_SARADC.sar1_patt_tab[index].sar1_patt_tab = tab; //Write back + } else { + tab = APB_SARADC.sar2_patt_tab[index].sar2_patt_tab; //Read old register value + tab &= (~(0xFC0000 >> offset)); //clear old data + tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; //Fill in the new data + APB_SARADC.sar2_patt_tab[index].sar2_patt_tab = tab; //Write back + } } /** @@ -268,10 +300,11 @@ static inline void adc_ll_digi_output_invert(adc_ll_num_t adc_n, bool inv_en) } /** - * Sets the number of interval clock cycles for the digital controller to trigger the measurement. + * Set the interval clock cycle for the digital controller to trigger the measurement. + * Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. * - * @note The trigger interval should not be less than the sampling time of the SAR ADC. - * @param cycle The number of clock cycles for the trigger interval. The unit is the divided clock. Range: 40 ~ 4095. + * @note The trigger interval should not be smaller than the sampling time of the SAR ADC. + * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095. */ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle) { @@ -293,16 +326,15 @@ static inline void adc_ll_digi_trigger_enable(void) static inline void adc_ll_digi_trigger_disable(void) { APB_SARADC.ctrl2.timer_en = 0; - APB_SARADC.ctrl2.timer_sel = 0; } /** * Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock. - * Expression: controller_clk = APLL/APB * (div_num + div_b / div_a). + * Expression: controller_clk = (APLL or APB) / (div_num + div_a / div_b + 1). * - * @param div_num Division factor. Range: 1 ~ 255. + * @param div_num Division factor. Range: 0 ~ 255. * @param div_b Division factor. Range: 1 ~ 63. - * @param div_a Division factor. Range: 1 ~ 63. + * @param div_a Division factor. Range: 0 ~ 63. */ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a) { @@ -342,6 +374,7 @@ static inline void adc_ll_digi_controller_clk_disable(void) */ static inline void adc_ll_digi_filter_reset(adc_ll_num_t adc_n) { + abort(); } /** @@ -352,6 +385,7 @@ static inline void adc_ll_digi_filter_reset(adc_ll_num_t adc_n) */ static inline void adc_ll_digi_filter_set_factor(adc_ll_num_t adc_n, adc_digi_filter_mode_t factor) { + abort(); } /** @@ -362,6 +396,7 @@ static inline void adc_ll_digi_filter_set_factor(adc_ll_num_t adc_n, adc_digi_fi */ static inline void adc_ll_digi_filter_get_factor(adc_ll_num_t adc_n, adc_digi_filter_mode_t *factor) { + abort(); } /** @@ -373,6 +408,7 @@ static inline void adc_ll_digi_filter_get_factor(adc_ll_num_t adc_n, adc_digi_fi */ static inline void adc_ll_digi_filter_enable(adc_ll_num_t adc_n, bool enable) { + abort(); } /** @@ -385,7 +421,7 @@ static inline void adc_ll_digi_filter_enable(adc_ll_num_t adc_n, bool enable) */ static inline uint32_t adc_ll_digi_filter_read_data(adc_ll_num_t adc_n) { - return 0; + abort(); } /** @@ -398,6 +434,7 @@ static inline uint32_t adc_ll_digi_filter_read_data(adc_ll_num_t adc_n) */ static inline void adc_ll_digi_monitor_set_mode(adc_ll_num_t adc_n, bool is_larger) { + abort(); } /** @@ -409,6 +446,7 @@ static inline void adc_ll_digi_monitor_set_mode(adc_ll_num_t adc_n, bool is_larg */ static inline void adc_ll_digi_monitor_set_thres(adc_ll_num_t adc_n, uint32_t threshold) { + abort(); } /** @@ -419,88 +457,7 @@ static inline void adc_ll_digi_monitor_set_thres(adc_ll_num_t adc_n, uint32_t th */ static inline void adc_ll_digi_monitor_enable(adc_ll_num_t adc_n, bool enable) { -} - -/** - * Enable interrupt of adc digital controller by bitmask. - * - * @param adc_n ADC unit. - * @param intr Interrupt bitmask. - */ -static inline void adc_ll_digi_intr_enable(adc_ll_num_t adc_n, adc_digi_intr_t intr) -{ - if (adc_n == ADC_NUM_1) { - if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) { - APB_SARADC.int_ena.adc1_done = 1; - } - } else { // adc_n == ADC_NUM_2 - if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) { - APB_SARADC.int_ena.adc2_done = 1; - } - } -} - -/** - * Disable interrupt of adc digital controller by bitmask. - * - * @param adc_n ADC unit. - * @param intr Interrupt bitmask. - */ -static inline void adc_ll_digi_intr_disable(adc_ll_num_t adc_n, adc_digi_intr_t intr) -{ - if (adc_n == ADC_NUM_1) { - if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) { - APB_SARADC.int_ena.adc1_done = 0; - } - } else { // adc_n == ADC_NUM_2 - if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) { - APB_SARADC.int_ena.adc2_done = 0; - } - } -} - -/** - * Clear interrupt of adc digital controller by bitmask. - * - * @param adc_n ADC unit. - * @param intr Interrupt bitmask. - */ -static inline void adc_ll_digi_intr_clear(adc_ll_num_t adc_n, adc_digi_intr_t intr) -{ - if (adc_n == ADC_NUM_1) { - if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) { - APB_SARADC.int_clr.adc1_done = 1; - } - } else { // adc_n == ADC_NUM_2 - if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) { - APB_SARADC.int_clr.adc2_done = 1; - } - } -} - -/** - * Get interrupt status mask of adc digital controller. - * - * @param adc_n ADC unit. - * @return - * - intr Interrupt bitmask. - */ -static inline uint32_t adc_ll_digi_get_intr_status(adc_ll_num_t adc_n) -{ - uint32_t int_st = APB_SARADC.int_st.val; - uint32_t ret_msk = 0; - - if (adc_n == ADC_NUM_1) { - if (int_st & APB_SARADC_ADC1_DONE_INT_ST_M) { - ret_msk |= ADC_DIGI_INTR_MASK_MEAS_DONE; - } - } else { // adc_n == ADC_NUM_2 - if (int_st & APB_SARADC_ADC2_DONE_INT_ST_M) { - ret_msk |= ADC_DIGI_INTR_MASK_MEAS_DONE; - } - } - - return ret_msk; + abort(); } /** @@ -566,207 +523,6 @@ static inline uint32_t adc_ll_pwdet_get_cct(void) return SENS.sar_meas2_mux.sar2_pwdet_cct; } -/*--------------------------------------------------------------- - RTC controller setting ----------------------------------------------------------------*/ -/** - * Set adc output data format for RTC controller. - * - * @note ESP32S2 RTC controller only support 13bit. - * @prarm adc_n ADC unit. - * @prarm bits Output data bits width option. - */ -static inline void adc_ll_rtc_set_output_format(adc_ll_num_t adc_n, adc_bits_width_t bits) -{ - return; -} - -/** - * Enable adc channel to start convert. - * - * @note Only one channel can be selected for once measurement. - * - * @param adc_n ADC unit. - * @param channel ADC channel number for each ADCn. - */ -static inline void adc_ll_rtc_enable_channel(adc_ll_num_t adc_n, int channel) -{ - if (adc_n == ADC_NUM_1) { - SENS.sar_meas1_ctrl2.sar1_en_pad = (1 << channel); //only one channel is selected. - } else { // adc_n == ADC_NUM_2 - SENS.sar_meas2_ctrl2.sar2_en_pad = (1 << channel); //only one channel is selected. - } -} - -/** - * Disable adc channel to start convert. - * - * @note Only one channel can be selected in once measurement. - * - * @param adc_n ADC unit. - * @param channel ADC channel number for each ADCn. - */ -static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n) -{ - if (adc_n == ADC_NUM_1) { - SENS.sar_meas1_ctrl2.sar1_en_pad = 0; //only one channel is selected. - } else { // adc_n == ADC_NUM_2 - SENS.sar_meas2_ctrl2.sar2_en_pad = 0; //only one channel is selected. - } -} - -/** - * Start conversion once by software for RTC controller. - * - * @note It may be block to wait conversion idle for ADC1. - * - * @param adc_n ADC unit. - * @param channel ADC channel number for each ADCn. - */ -static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel) -{ - if (adc_n == ADC_NUM_1) { - while (SENS.sar_slave_addr1.meas_status != 0); - SENS.sar_meas1_ctrl2.meas1_start_sar = 0; - SENS.sar_meas1_ctrl2.meas1_start_sar = 1; - } else { // adc_n == ADC_NUM_2 - SENS.sar_meas2_ctrl2.meas2_start_sar = 0; //start force 0 - SENS.sar_meas2_ctrl2.meas2_start_sar = 1; //start force 1 - } -} - -/** - * Check the conversion done flag for each ADCn for RTC controller. - * - * @param adc_n ADC unit. - * @return - * -true : The conversion process is finish. - * -false : The conversion process is not finish. - */ -static inline bool adc_ll_rtc_convert_is_done(adc_ll_num_t adc_n) -{ - bool ret = true; - if (adc_n == ADC_NUM_1) { - ret = (bool)SENS.sar_meas1_ctrl2.meas1_done_sar; - } else { // adc_n == ADC_NUM_2 - ret = (bool)SENS.sar_meas2_ctrl2.meas2_done_sar; - } - return ret; -} - -/** - * Get the converted value for each ADCn for RTC controller. - * - * @param adc_n ADC unit. - * @return - * - Converted value. - */ -static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n) -{ - int ret_val = 0; - if (adc_n == ADC_NUM_1) { - ret_val = SENS.sar_meas1_ctrl2.meas1_data_sar; - } else { // adc_n == ADC_NUM_2 - ret_val = SENS.sar_meas2_ctrl2.meas2_data_sar; - } - return ret_val; -} - -/** - * ADC module RTC output data invert or not. - * - * @param adc_n ADC unit. - * @param inv_en data invert or not. - */ -static inline void adc_ll_rtc_output_invert(adc_ll_num_t adc_n, bool inv_en) -{ - if (adc_n == ADC_NUM_1) { - SENS.sar_reader1_ctrl.sar1_data_inv = inv_en; // Enable / Disable ADC data invert - } else { // adc_n == ADC_NUM_2 - SENS.sar_reader2_ctrl.sar2_data_inv = inv_en; // Enable / Disable ADC data invert - } -} - -/** - * Enable ADCn conversion complete interrupt for RTC controller. - * - * @param adc_n ADC unit. - */ -static inline void adc_ll_rtc_intr_enable(adc_ll_num_t adc_n) -{ - if (adc_n == ADC_NUM_1) { - SENS.sar_reader1_ctrl.sar1_int_en = 1; - RTCCNTL.int_ena.rtc_saradc1 = 1; - } else { // adc_n == ADC_NUM_2 - SENS.sar_reader2_ctrl.sar2_int_en = 1; - RTCCNTL.int_ena.rtc_saradc2 = 1; - } -} - -/** - * Disable ADCn conversion complete interrupt for RTC controller. - * - * @param adc_n ADC unit. - */ -static inline void adc_ll_rtc_intr_disable(adc_ll_num_t adc_n) -{ - if (adc_n == ADC_NUM_1) { - SENS.sar_reader1_ctrl.sar1_int_en = 0; - RTCCNTL.int_ena.rtc_saradc1 = 0; - } else { // adc_n == ADC_NUM_2 - SENS.sar_reader2_ctrl.sar2_int_en = 0; - RTCCNTL.int_ena.rtc_saradc2 = 0; - } -} - -/** - * Reset RTC controller FSM. - */ -static inline void adc_ll_rtc_reset(void) -{ -} - -/** - * Sets the number of cycles required for the conversion to complete and wait for the arbiter to stabilize. - * - * @note Only ADC2 have arbiter function. - * @param cycle range: [0,4]. - */ -static inline void adc_ll_rtc_set_arbiter_stable_cycle(uint32_t cycle) -{ - SENS.sar_reader2_ctrl.sar2_wait_arb_cycle = cycle; -} - -/** - * Analyze whether the obtained raw data is correct. - * ADC2 can use arbiter. The arbitration result can be judged by the flag bit in the original data. - * - * @param adc_n ADC unit. - * @param raw_data ADC raw data input (convert value). - * @return - * - 0: The data is correct to use. - * - 1: The data is invalid. The current controller is not enabled by the arbiter. - * - 2: The data is invalid. The current controller process was interrupted by a higher priority controller. - * - -1: The data is error. - */ -static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_ll_num_t adc_n, uint16_t raw_data) -{ - /* ADC1 don't need check data */ - if (adc_n == ADC_NUM_1) { - return ADC_RTC_DATA_OK; - } - adc_ll_rtc_output_data_t *temp = (adc_ll_rtc_output_data_t *)&raw_data; - if (temp->flag == 0) { - return ADC_RTC_DATA_OK; - } else if (temp->flag == 1) { - return ADC_RTC_CTRL_UNSELECTED; - } else if (temp->flag == 2) { - return ADC_RTC_CTRL_BREAK; - } else { - return ADC_RTC_DATA_FAIL; - } -} - /*--------------------------------------------------------------- Common setting ---------------------------------------------------------------*/ @@ -777,88 +533,15 @@ static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_ll_num_t ad */ static inline void adc_ll_set_power_manage(adc_ll_power_t manage) { -} - -/** - * Get ADC module power management. - * - * @return - * - ADC power status. - */ -static inline adc_ll_power_t adc_ll_get_power_manage(void) -{ - return ADC_POWER_SW_OFF; -} - -/** - * ADC SAR clock division factor setting. ADC SAR clock devided from `RTC_FAST_CLK`. - * - * @param div Division factor. - */ -static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div) -{ - if (adc_n == ADC_NUM_1) { - SENS.sar_reader1_ctrl.sar1_clk_div = div; - } else { // adc_n == ADC_NUM_2 - SENS.sar_reader2_ctrl.sar2_clk_div = div; - } -} - -/** - * Set the attenuation of a particular channel on ADCn. - * - * @note For any given channel, this function must be called before the first time conversion. - * - * The default ADC full-scale voltage is 1.1V. To read higher voltages (up to the pin maximum voltage, - * usually 3.3V) requires setting >0dB signal attenuation for that ADC channel. - * - * When VDD_A is 3.3V: - * - * - 0dB attenuaton (ADC_ATTEN_DB_0) gives full-scale voltage 1.1V - * - 2.5dB attenuation (ADC_ATTEN_DB_2_5) gives full-scale voltage 1.5V - * - 6dB attenuation (ADC_ATTEN_DB_6) gives full-scale voltage 2.2V - * - 11dB attenuation (ADC_ATTEN_DB_11) gives full-scale voltage 3.9V (see note below) - * - * @note The full-scale voltage is the voltage corresponding to a maximum reading (depending on ADC1 configured - * bit width, this value is: 4095 for 12-bits, 2047 for 11-bits, 1023 for 10-bits, 511 for 9 bits.) - * - * @note At 11dB attenuation the maximum voltage is limited by VDD_A, not the full scale voltage. - * - * Due to ADC characteristics, most accurate results are obtained within the following approximate voltage ranges: - * - * - 0dB attenuaton (ADC_ATTEN_DB_0) between 100 and 950mV - * - 2.5dB attenuation (ADC_ATTEN_DB_2_5) between 100 and 1250mV - * - 6dB attenuation (ADC_ATTEN_DB_6) between 150 to 1750mV - * - 11dB attenuation (ADC_ATTEN_DB_11) between 150 to 2450mV - * - * For maximum accuracy, use the ADC calibration APIs and measure voltages within these recommended ranges. - * - * @param adc_n ADC unit. - * @param channel ADCn channel number. - * @param atten The attenuation option. - */ -static inline void adc_ll_set_atten(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten) -{ - if (adc_n == ADC_NUM_1) { - SENS.sar_atten1 = ( SENS.sar_atten1 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2)); - } else { // adc_n == ADC_NUM_2 - SENS.sar_atten2 = ( SENS.sar_atten2 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2)); - } -} - -/** - * Get the attenuation of a particular channel on ADCn. - * - * @param adc_n ADC unit. - * @param channel ADCn channel number. - * @return atten The attenuation option. - */ -static inline adc_atten_t adc_ll_get_atten(adc_ll_num_t adc_n, adc_channel_t channel) -{ - if (adc_n == ADC_NUM_1) { - return (adc_atten_t)((SENS.sar_atten1 >> (channel * 2)) & 0x3); - } else { - return (adc_atten_t)((SENS.sar_atten2 >> (channel * 2)) & 0x3); + if (manage == ADC_POWER_SW_ON) { + APB_SARADC.ctrl.sar_clk_gated = 1; + APB_SARADC.ctrl.xpd_sar_force = 3; + } else if (manage == ADC_POWER_BY_FSM) { + APB_SARADC.ctrl.sar_clk_gated = 1; + APB_SARADC.ctrl.xpd_sar_force = 0; + } else if (manage == ADC_POWER_SW_OFF) { + APB_SARADC.ctrl.sar_clk_gated = 0; + APB_SARADC.ctrl.xpd_sar_force = 2; } } @@ -875,45 +558,38 @@ static inline adc_atten_t adc_ll_get_atten(adc_ll_num_t adc_n, adc_channel_t cha static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t ctrl) { if (adc_n == ADC_NUM_1) { - switch ( ctrl ) { - case ADC_CTRL_RTC: - SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control. - SENS.sar_meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start. - SENS.sar_meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map; - break; - case ADC_CTRL_ULP: - SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control. - SENS.sar_meas1_ctrl2.meas1_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start. - SENS.sar_meas1_ctrl2.sar1_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map; - break; - case ADC_CTRL_DIG: - SENS.sar_meas1_mux.sar1_dig_force = 1; // 1: Select digital control; 0: Select RTC control. - SENS.sar_meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start. - SENS.sar_meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map; - break; - default: - break; + switch (ctrl) { + case ADC_LL_CTRL_RTC: + SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control. + SENS.sar_meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start. + SENS.sar_meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map; + break; + case ADC_LL_CTRL_ULP: + SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control. + SENS.sar_meas1_ctrl2.meas1_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start. + SENS.sar_meas1_ctrl2.sar1_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map; + break; + case ADC_LL_CTRL_DIG: + SENS.sar_meas1_mux.sar1_dig_force = 1; // 1: Select digital control; 0: Select RTC control. + SENS.sar_meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start. + SENS.sar_meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map; + break; + default: + break; } } else { // adc_n == ADC_NUM_2 - switch ( ctrl ) { - case ADC_CTRL_RTC: - SENS.sar_meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start. - SENS.sar_meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map; - break; - case ADC_CTRL_ULP: - SENS.sar_meas2_ctrl2.meas2_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start. - SENS.sar_meas2_ctrl2.sar2_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map; - break; - case ADC_CTRL_DIG: - SENS.sar_meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start. - SENS.sar_meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map; - break; - case ADC2_CTRL_PWDET: // currently only used by Wi-Fi - SENS.sar_meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start. - SENS.sar_meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map; - break; - default: - break; + //If ADC2 is not controlled by ULP, the arbiter will decide which controller to use ADC2. + switch (ctrl) { + case ADC_LL_CTRL_ARB: + SENS.sar_meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start. + SENS.sar_meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map; + break; + case ADC_LL_CTRL_ULP: + SENS.sar_meas2_ctrl2.meas2_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start. + SENS.sar_meas2_ctrl2.sar2_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map; + break; + default: + break; } } } @@ -930,15 +606,14 @@ static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t */ static inline void adc_ll_set_arbiter_work_mode(adc_arbiter_mode_t mode) { - SENS.sar_meas2_mux.sar2_rtc_force = 0; // Enable arbiter in wakeup mode if (mode == ADC_ARB_MODE_FIX) { APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 0; APB_SARADC.apb_adc_arb_ctrl.adc_arb_fix_priority = 1; } else if (mode == ADC_ARB_MODE_LOOP) { APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 0; APB_SARADC.apb_adc_arb_ctrl.adc_arb_fix_priority = 0; - } else { - APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 1; // Shield arbiter. + } else { // Shield arbiter. + APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 1; } } @@ -1014,46 +689,6 @@ static inline void adc_ll_disable_sleep_controller(void) SENS.sar_meas2_mux.sar2_rtc_force = 0; } -/* ADC calibration code. */ -#include "soc/rtc_cntl_reg.h" -#include "regi2c_ctrl.h" - -#define I2C_ADC 0X69 -#define I2C_ADC_HOSTID 0 - -#define SAR1_ENCAL_GND_ADDR 0x7 -#define SAR1_ENCAL_GND_ADDR_MSB 5 -#define SAR1_ENCAL_GND_ADDR_LSB 5 - -#define SAR2_ENCAL_GND_ADDR 0x7 -#define SAR2_ENCAL_GND_ADDR_MSB 7 -#define SAR2_ENCAL_GND_ADDR_LSB 7 - -#define SAR1_INITIAL_CODE_HIGH_ADDR 0x1 -#define SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3 -#define SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0 - -#define SAR1_INITIAL_CODE_LOW_ADDR 0x0 -#define SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7 -#define SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0 - -#define SAR2_INITIAL_CODE_HIGH_ADDR 0x4 -#define SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3 -#define SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0 - -#define SAR2_INITIAL_CODE_LOW_ADDR 0x3 -#define SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7 -#define SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0 - -#define SAR1_DREF_ADDR 0x2 -#define SAR1_DREF_ADDR_MSB 0x6 -#define SAR1_DREF_ADDR_LSB 0x4 - -#define SAR2_DREF_ADDR 0x5 -#define SAR2_DREF_ADDR_MSB 0x6 -#define SAR2_DREF_ADDR_LSB 0x4 - - /** * Configure the registers for ADC calibration. You need to call the ``adc_ll_calibration_finish`` interface to resume after calibration. * @@ -1066,30 +701,7 @@ static inline void adc_ll_disable_sleep_controller(void) */ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t channel, bool internal_gnd) { - /* Enable i2s_write_reg function. */ - void phy_get_romfunc_addr(void); - phy_get_romfunc_addr(); - // CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M);//TODO: finish it in MR-10423. - // SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);//TODO: finish it in MR-10423. - CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M); - SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M); - - /* Enable/disable internal connect GND (for calibration). */ - if (adc_n == ADC_NUM_1) { - REGI2C_WRITE_MASK(I2C_ADC, SAR1_DREF_ADDR, 4); - if (internal_gnd) { - REGI2C_WRITE_MASK(I2C_ADC, SAR1_ENCAL_GND_ADDR, 1); - } else { - REGI2C_WRITE_MASK(I2C_ADC, SAR1_ENCAL_GND_ADDR, 0); - } - } else { - REGI2C_WRITE_MASK(I2C_ADC, SAR2_DREF_ADDR, 4); - if (internal_gnd) { - REGI2C_WRITE_MASK(I2C_ADC, SAR2_ENCAL_GND_ADDR, 1); - } else { - REGI2C_WRITE_MASK(I2C_ADC, SAR2_ENCAL_GND_ADDR, 0); - } - } + abort(); } /** @@ -1099,11 +711,7 @@ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t */ static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n) { - if (adc_n == ADC_NUM_1) { - REGI2C_WRITE_MASK(I2C_ADC, SAR1_ENCAL_GND_ADDR, 0); - } else { - REGI2C_WRITE_MASK(I2C_ADC, SAR2_ENCAL_GND_ADDR, 0); - } + abort(); } /** @@ -1115,24 +723,8 @@ static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n) */ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t param) { - uint8_t msb = param >> 8; - uint8_t lsb = param & 0xFF; - /* Enable i2s_write_reg function. */ - void phy_get_romfunc_addr(void); - phy_get_romfunc_addr(); - // SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M); //TODO: finish it in MR-10423. - CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M); - SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M); - - if (adc_n == ADC_NUM_1) { - REGI2C_WRITE_MASK(I2C_ADC, SAR1_INITIAL_CODE_HIGH_ADDR, msb); - REGI2C_WRITE_MASK(I2C_ADC, SAR1_INITIAL_CODE_LOW_ADDR, lsb); - } else { - REGI2C_WRITE_MASK(I2C_ADC, SAR2_INITIAL_CODE_HIGH_ADDR, msb); - REGI2C_WRITE_MASK(I2C_ADC, SAR2_INITIAL_CODE_LOW_ADDR, lsb); - } + abort(); } -/* Temp code end. */ /** * Output ADC internal reference voltage to channels, only available for ADC2 on ESP32. @@ -1147,32 +739,204 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par */ static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en) { - // if (adc != ADC_NUM_2) return; - - // if (en) { - // RTCCNTL.bias_conf.dbg_atten_monitor = 0; //Check DBG effect outside sleep mode - // //set dtest (MUX_SEL : 0 -> RTC; 1-> vdd_sar2) - // RTCCNTL.test_mux.dtest_rtc = 1; //Config test mux to route v_ref to ADC2 Channels - // //set ent - // RTCCNTL.test_mux.ent_rtc = 1; - // //set sar2_en_test - // SENS.sar_start_force.sar2_en_test = 1; - // //set sar2 en force - // SENS.sar_meas_start2.sar2_en_pad_force = 1; //Pad bitmap controlled by SW - // //set en_pad for channels 7,8,9 (bits 0x380) - // SENS.sar_meas_start2.sar2_en_pad = 1 << channel; - // } else { - // RTCCNTL.test_mux.dtest_rtc = 0; //Config test mux to route v_ref to ADC2 Channels - // //set ent - // RTCCNTL.test_mux.ent_rtc = 0; - // //set sar2_en_test - // SENS.sar_start_force.sar2_en_test = 0; - // //set sar2 en force - // SENS.sar_meas_start2.sar2_en_pad_force = 0; //Pad bitmap controlled by SW - // //set en_pad for channels 7,8,9 (bits 0x380) - // SENS.sar_meas_start2.sar2_en_pad = 0; - // } + abort(); } + +/*--------------------------------------------------------------- + RTC controller setting +---------------------------------------------------------------*/ +/** + * ADC SAR clock division factor setting. ADC SAR clock devided from `RTC_FAST_CLK`. + * + * @param div Division factor. + */ +static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div) +{ + abort(); +} + +/** + * Set adc output data format for RTC controller. + * + * @note ESP32S2 RTC controller only support 13bit. + * @prarm adc_n ADC unit. + * @prarm bits Output data bits width option. + */ +static inline void adc_ll_rtc_set_output_format(adc_ll_num_t adc_n, adc_bits_width_t bits) +{ + abort(); +} + +/** + * Enable adc channel to start convert. + * + * @note Only one channel can be selected for once measurement. + * + * @param adc_n ADC unit. + * @param channel ADC channel number for each ADCn. + */ +static inline void adc_ll_rtc_enable_channel(adc_ll_num_t adc_n, int channel) +{ + abort(); +} + +/** + * Disable adc channel to start convert. + * + * @note Only one channel can be selected in once measurement. + * + * @param adc_n ADC unit. + * @param channel ADC channel number for each ADCn. + */ +static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n) +{ + abort(); +} + +/** + * Start conversion once by software for RTC controller. + * + * @note It may be block to wait conversion idle for ADC1. + * + * @param adc_n ADC unit. + * @param channel ADC channel number for each ADCn. + */ +static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel) +{ + abort(); +} + +/** + * Check the conversion done flag for each ADCn for RTC controller. + * + * @param adc_n ADC unit. + * @return + * -true : The conversion process is finish. + * -false : The conversion process is not finish. + */ +static inline bool adc_ll_rtc_convert_is_done(adc_ll_num_t adc_n) +{ + abort(); +} + +/** + * Get the converted value for each ADCn for RTC controller. + * + * @param adc_n ADC unit. + * @return + * - Converted value. + */ +static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n) +{ + abort(); +} + +/** + * ADC module RTC output data invert or not. + * + * @param adc_n ADC unit. + * @param inv_en data invert or not. + */ +static inline void adc_ll_rtc_output_invert(adc_ll_num_t adc_n, bool inv_en) +{ + abort(); +} + +/** + * Enable ADCn conversion complete interrupt for RTC controller. + * + * @param adc_n ADC unit. + */ +static inline void adc_ll_rtc_intr_enable(adc_ll_num_t adc_n) +{ + abort(); +} + +/** + * Disable ADCn conversion complete interrupt for RTC controller. + * + * @param adc_n ADC unit. + */ +static inline void adc_ll_rtc_intr_disable(adc_ll_num_t adc_n) +{ + abort(); +} + +/** + * Reset RTC controller FSM. + */ +static inline void adc_ll_rtc_reset(void) +{ + abort(); +} + +/** + * Sets the number of cycles required for the conversion to complete and wait for the arbiter to stabilize. + * + * @note Only ADC2 have arbiter function. + * @param cycle range: [0,4]. + */ +static inline void adc_ll_rtc_set_arbiter_stable_cycle(uint32_t cycle) +{ + abort(); +} + +/** + * Analyze whether the obtained raw data is correct. + * ADC2 can use arbiter. The arbitration result can be judged by the flag bit in the original data. + * + * @param adc_n ADC unit. + * @param raw_data ADC raw data input (convert value). + * @return + * - 0: The data is correct to use. + * - 1: The data is invalid. The current controller is not enabled by the arbiter. + * - 2: The data is invalid. The current controller process was interrupted by a higher priority controller. + * - -1: The data is error. + */ +static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_ll_num_t adc_n, uint16_t raw_data) +{ + abort(); +} + +/** + * Set the attenuation of a particular channel on ADCn. + * + * @note For any given channel, this function must be called before the first time conversion. + * + * The default ADC full-scale voltage is 1.1V. To read higher voltages (up to the pin maximum voltage, + * usually 3.3V) requires setting >0dB signal attenuation for that ADC channel. + * + * When VDD_A is 3.3V: + * + * - 0dB attenuaton (ADC_ATTEN_DB_0) gives full-scale voltage 1.1V + * - 2.5dB attenuation (ADC_ATTEN_DB_2_5) gives full-scale voltage 1.5V + * - 6dB attenuation (ADC_ATTEN_DB_6) gives full-scale voltage 2.2V + * - 11dB attenuation (ADC_ATTEN_DB_11) gives full-scale voltage 3.9V (see note below) + * + * @note The full-scale voltage is the voltage corresponding to a maximum reading (depending on ADC1 configured + * bit width, this value is: 4095 for 12-bits, 2047 for 11-bits, 1023 for 10-bits, 511 for 9 bits.) + * + * @note At 11dB attenuation the maximum voltage is limited by VDD_A, not the full scale voltage. + * + * Due to ADC characteristics, most accurate results are obtained within the following approximate voltage ranges: + * + * - 0dB attenuaton (ADC_ATTEN_DB_0) between 100 and 950mV + * - 2.5dB attenuation (ADC_ATTEN_DB_2_5) between 100 and 1250mV + * - 6dB attenuation (ADC_ATTEN_DB_6) between 150 to 1750mV + * - 11dB attenuation (ADC_ATTEN_DB_11) between 150 to 2450mV + * + * For maximum accuracy, use the ADC calibration APIs and measure voltages within these recommended ranges. + * + * @param adc_n ADC unit. + * @param channel ADCn channel number. + * @param atten The attenuation option. + */ +static inline void adc_ll_set_atten(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten) +{ + abort(); +} + + #ifdef __cplusplus } #endif