From 6bfdc0ce632b96f33922e7c76f6370c25b6b8993 Mon Sep 17 00:00:00 2001 From: wanckl Date: Fri, 11 Apr 2025 20:07:24 +0800 Subject: [PATCH] feat(driver_twai): c5 eco2 support clock source pll80m to output 8m twai --- .../test_apps/twaifd_test/main/test_twaifd.c | 14 +- .../hal/esp32c5/include/hal/twaifd_ll.h | 2 +- .../soc/esp32c5/include/soc/clk_tree_defs.h | 8 +- components/soc/esp32c5/register/soc/pcr_reg.h | 461 +++++++++--------- .../soc/esp32c5/register/soc/pcr_struct.h | 418 ++++++++-------- 5 files changed, 427 insertions(+), 476 deletions(-) diff --git a/components/esp_driver_twai/test_apps/twaifd_test/main/test_twaifd.c b/components/esp_driver_twai/test_apps/twaifd_test/main/test_twaifd.c index 282c798adb..e488c1d2b2 100644 --- a/components/esp_driver_twai/test_apps/twaifd_test/main/test_twaifd.c +++ b/components/esp_driver_twai/test_apps/twaifd_test/main/test_twaifd.c @@ -121,7 +121,7 @@ TEST_CASE("twai transmit stop resume (loopback)", "[TWAI]") twai_onchip_node_config_t node_config = { .io_cfg.tx = TEST_TX_GPIO, .io_cfg.rx = TEST_TX_GPIO, // Using same pin for test without transceiver - .bit_timing.bitrate = 1000000, + .bit_timing.bitrate = 20000, .data_timing.bitrate = 4000000, .data_timing.ssp_permill = 700, // ssp 70.0% .tx_queue_depth = TEST_TWAI_QUEUE_DEPTH, @@ -130,14 +130,14 @@ TEST_CASE("twai transmit stop resume (loopback)", "[TWAI]") }; TEST_ESP_OK(twai_new_node_onchip(&node_config, &node_hdl)); - // reconfig fd timing to 48M/(12+5+6+1)=2MHz, ssp=20/(12+5+6+1)=83% + // reconfig fd timing to 80M/(4+3+2+1)=8MHz, ssp=8/(4+3+2+1)=80% twai_timing_advanced_config_t timing_fd = { .brp = 1, - .prop_seg = 12, - .tseg_1 = 5, - .tseg_2 = 6, - .sjw = 3, - .ssp_offset = 20, + .prop_seg = 4, + .tseg_1 = 3, + .tseg_2 = 2, + .sjw = 2, + .ssp_offset = 8, }; TEST_ESP_OK(twai_node_reconfig_timing(node_hdl, NULL, &timing_fd)); diff --git a/components/hal/esp32c5/include/hal/twaifd_ll.h b/components/hal/esp32c5/include/hal/twaifd_ll.h index e742e9634b..6fbd9bc0fc 100644 --- a/components/hal/esp32c5/include/hal/twaifd_ll.h +++ b/components/hal/esp32c5/include/hal/twaifd_ll.h @@ -92,7 +92,7 @@ static inline void twaifd_ll_reset_register(uint8_t twai_id) */ static inline void twaifd_ll_set_clock_source(uint8_t twai_id, twai_clock_source_t clk_src) { - PCR.twai[twai_id].twai_func_clk_conf.twai_func_clk_sel = (clk_src == TWAI_CLK_SRC_RC_FAST) ? 1 : 0; + PCR.twai[twai_id].twai_func_clk_conf.twai_func_clk_sel = (clk_src == TWAI_CLK_SRC_XTAL) ? 0 : 1; } /** diff --git a/components/soc/esp32c5/include/soc/clk_tree_defs.h b/components/soc/esp32c5/include/soc/clk_tree_defs.h index 902fae9407..04341d8d63 100644 --- a/components/soc/esp32c5/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c5/include/soc/clk_tree_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -422,15 +422,15 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of TWAI */ -#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} +#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M} /** * @brief TWAI clock source */ typedef enum { TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - TWAI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ - TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */ + TWAI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as the source clock */ + TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as the default clock choice */ } soc_periph_twai_clk_src_t; //////////////////////////////////////////////////ADC/////////////////////////////////////////////////////////////////// diff --git a/components/soc/esp32c5/register/soc/pcr_reg.h b/components/soc/esp32c5/register/soc/pcr_reg.h index e9e7316b2a..e535f0e79c 100644 --- a/components/soc/esp32c5/register/soc/pcr_reg.h +++ b/components/soc/esp32c5/register/soc/pcr_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,7 +23,7 @@ extern "C" { #define PCR_UART0_CLK_EN_V 0x00000001U #define PCR_UART0_CLK_EN_S 0 /** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart0 module + * Set 1 to reset uart0 module */ #define PCR_UART0_RST_EN (BIT(1)) #define PCR_UART0_RST_EN_M (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S) @@ -63,10 +63,10 @@ extern "C" { #define PCR_UART0_SCLK_DIV_NUM_V 0x000000FFU #define PCR_UART0_SCLK_DIV_NUM_S 12 /** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of UART0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of UART0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_UART0_SCLK_SEL 0x00000003U #define PCR_UART0_SCLK_SEL_M (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S) @@ -111,7 +111,7 @@ extern "C" { #define PCR_UART1_CLK_EN_V 0x00000001U #define PCR_UART1_CLK_EN_S 0 /** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart1 module + * Set 1 to reset uart1 module */ #define PCR_UART1_RST_EN (BIT(1)) #define PCR_UART1_RST_EN_M (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S) @@ -151,10 +151,10 @@ extern "C" { #define PCR_UART1_SCLK_DIV_NUM_V 0x000000FFU #define PCR_UART1_SCLK_DIV_NUM_S 12 /** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of UART1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of UART1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_UART1_SCLK_SEL 0x00000003U #define PCR_UART1_SCLK_SEL_M (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S) @@ -199,7 +199,7 @@ extern "C" { #define PCR_MSPI_CLK_EN_V 0x00000001U #define PCR_MSPI_CLK_EN_S 0 /** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset mspi module + * Set 1 to reset mspi module */ #define PCR_MSPI_RST_EN (BIT(1)) #define PCR_MSPI_RST_EN_M (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S) @@ -226,7 +226,7 @@ extern "C" { #define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c) /** PCR_MSPI_FAST_DIV_NUM : R/W; bitpos: [7:0]; default: 0; * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed - * clock-source to drive clk_mspi_fast. Only available when the clock-source is a + * clock-source to drive clk_mspi_fast. Only available when the clck-source is a * low-speed clock-source such as XTAL/FOSC. */ #define PCR_MSPI_FAST_DIV_NUM 0x000000FFU @@ -234,10 +234,10 @@ extern "C" { #define PCR_MSPI_FAST_DIV_NUM_V 0x000000FFU #define PCR_MSPI_FAST_DIV_NUM_S 0 /** PCR_MSPI_FUNC_CLK_SEL : R/W; bitpos: [9:8]; default: 0; - * Configures the clock source for MSPI.\\ - * 0(default): XTAL_CLK\\ - * 1 RC_FAST_CLK\\ - * 2: PLL_F480M_CLK\\ + * Configures the clock source for MSPI. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK */ #define PCR_MSPI_FUNC_CLK_SEL 0x00000003U #define PCR_MSPI_FUNC_CLK_SEL_M (PCR_MSPI_FUNC_CLK_SEL_V << PCR_MSPI_FUNC_CLK_SEL_S) @@ -251,7 +251,7 @@ extern "C" { #define PCR_MSPI_FUNC_CLK_EN_V 0x00000001U #define PCR_MSPI_FUNC_CLK_EN_S 10 /** PCR_MSPI_AXI_RST_EN : R/W; bitpos: [11]; default: 0; - * Set 0 to reset axi_clock domain of mspi module + * Set 1 to reset axi_clock domain of mspi module */ #define PCR_MSPI_AXI_RST_EN (BIT(11)) #define PCR_MSPI_AXI_RST_EN_M (PCR_MSPI_AXI_RST_EN_V << PCR_MSPI_AXI_RST_EN_S) @@ -270,7 +270,7 @@ extern "C" { #define PCR_I2C_CLK_EN_V 0x00000001U #define PCR_I2C_CLK_EN_S 0 /** PCR_I2C_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset i2c module + * Set 1 to reset i2c module */ #define PCR_I2C_RST_EN (BIT(1)) #define PCR_I2C_RST_EN_M (PCR_I2C_RST_EN_V << PCR_I2C_RST_EN_S) @@ -303,9 +303,9 @@ extern "C" { #define PCR_I2C_SCLK_DIV_NUM_V 0x000000FFU #define PCR_I2C_SCLK_DIV_NUM_S 12 /** PCR_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of I2C.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of I2C. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ #define PCR_I2C_SCLK_SEL (BIT(20)) #define PCR_I2C_SCLK_SEL_M (PCR_I2C_SCLK_SEL_V << PCR_I2C_SCLK_SEL_S) @@ -331,7 +331,7 @@ extern "C" { #define PCR_TWAI0_CLK_EN_V 0x00000001U #define PCR_TWAI0_CLK_EN_S 0 /** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset twai0 module + * Set 1 to reset twai0 module */ #define PCR_TWAI0_RST_EN (BIT(1)) #define PCR_TWAI0_RST_EN_M (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S) @@ -350,9 +350,9 @@ extern "C" { */ #define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x2c) /** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of TWAI0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of TWAI0. + * 0 (default): XTAL_CLK + * 1: PLL_F80M_CLK */ #define PCR_TWAI0_FUNC_CLK_SEL (BIT(20)) #define PCR_TWAI0_FUNC_CLK_SEL_M (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S) @@ -378,7 +378,7 @@ extern "C" { #define PCR_TWAI1_CLK_EN_V 0x00000001U #define PCR_TWAI1_CLK_EN_S 0 /** PCR_TWAI1_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset twai1 module + * Set 1 to reset twai1 module */ #define PCR_TWAI1_RST_EN (BIT(1)) #define PCR_TWAI1_RST_EN_M (PCR_TWAI1_RST_EN_V << PCR_TWAI1_RST_EN_S) @@ -397,9 +397,9 @@ extern "C" { */ #define PCR_TWAI1_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x34) /** PCR_TWAI1_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of TWAI1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of TWAI1. + * 0 (default): XTAL_CLK + * 1: PLL_F80M_CLK */ #define PCR_TWAI1_FUNC_CLK_SEL (BIT(20)) #define PCR_TWAI1_FUNC_CLK_SEL_M (PCR_TWAI1_FUNC_CLK_SEL_V << PCR_TWAI1_FUNC_CLK_SEL_S) @@ -425,7 +425,7 @@ extern "C" { #define PCR_UHCI_CLK_EN_V 0x00000001U #define PCR_UHCI_CLK_EN_S 0 /** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uhci module + * Set 1 to reset uhci module */ #define PCR_UHCI_RST_EN (BIT(1)) #define PCR_UHCI_RST_EN_M (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S) @@ -451,7 +451,7 @@ extern "C" { #define PCR_RMT_CLK_EN_V 0x00000001U #define PCR_RMT_CLK_EN_S 0 /** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset rmt module + * Set 1 to reset rmt module */ #define PCR_RMT_RST_EN (BIT(1)) #define PCR_RMT_RST_EN_M (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S) @@ -484,10 +484,10 @@ extern "C" { #define PCR_RMT_SCLK_DIV_NUM_V 0x000000FFU #define PCR_RMT_SCLK_DIV_NUM_S 12 /** PCR_RMT_SCLK_SEL : R/W; bitpos: [21:20]; default: 1; - * Configures the clock source of RMT.\\ - * 0: XTAL_CLK\\ - * 1 (default): RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of RMT. + * 0: XTAL_CLK + * 1 (default): RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_RMT_SCLK_SEL 0x00000003U #define PCR_RMT_SCLK_SEL_M (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S) @@ -532,7 +532,7 @@ extern "C" { #define PCR_LEDC_CLK_EN_V 0x00000001U #define PCR_LEDC_CLK_EN_S 0 /** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ledc module + * Set 1 to reset ledc module */ #define PCR_LEDC_RST_EN (BIT(1)) #define PCR_LEDC_RST_EN_M (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S) @@ -551,10 +551,10 @@ extern "C" { */ #define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4c) /** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of LEDC.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of LEDC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_LEDC_SCLK_SEL 0x00000003U #define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S) @@ -599,7 +599,7 @@ extern "C" { #define PCR_TG0_CLK_EN_V 0x00000001U #define PCR_TG0_CLK_EN_S 0 /** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group0 module + * Set 1 to reset timer_group0 module */ #define PCR_TG0_RST_EN (BIT(1)) #define PCR_TG0_RST_EN_M (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S) @@ -632,10 +632,10 @@ extern "C" { */ #define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x58) /** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of general-purpose timers in Timer Group 0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of general-purpose timers in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_TG0_TIMER_CLK_SEL 0x00000003U #define PCR_TG0_TIMER_CLK_SEL_M (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S) @@ -654,10 +654,10 @@ extern "C" { */ #define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x5c) /** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of WDT in Timer Group 0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of WDT in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_TG0_WDT_CLK_SEL 0x00000003U #define PCR_TG0_WDT_CLK_SEL_M (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S) @@ -683,7 +683,7 @@ extern "C" { #define PCR_TG1_CLK_EN_V 0x00000001U #define PCR_TG1_CLK_EN_S 0 /** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 module + * Set 1 to reset timer_group1 module */ #define PCR_TG1_RST_EN (BIT(1)) #define PCR_TG1_RST_EN_M (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S) @@ -716,10 +716,10 @@ extern "C" { */ #define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x64) /** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of general-purpose timers in Timer Group 1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of general-purpose timers in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_TG1_TIMER_CLK_SEL 0x00000003U #define PCR_TG1_TIMER_CLK_SEL_M (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S) @@ -738,10 +738,10 @@ extern "C" { */ #define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68) /** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of WDT in Timer Group 1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of WDT in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_TG1_WDT_CLK_SEL 0x00000003U #define PCR_TG1_WDT_CLK_SEL_M (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S) @@ -767,7 +767,7 @@ extern "C" { #define PCR_SYSTIMER_CLK_EN_V 0x00000001U #define PCR_SYSTIMER_CLK_EN_S 0 /** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset systimer module + * Set 1 to reset systimer module */ #define PCR_SYSTIMER_RST_EN (BIT(1)) #define PCR_SYSTIMER_RST_EN_M (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S) @@ -786,9 +786,9 @@ extern "C" { */ #define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x70) /** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of System Timer.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of System Timer. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ #define PCR_SYSTIMER_FUNC_CLK_SEL (BIT(20)) #define PCR_SYSTIMER_FUNC_CLK_SEL_M (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S) @@ -814,7 +814,7 @@ extern "C" { #define PCR_I2S_CLK_EN_V 0x00000001U #define PCR_I2S_CLK_EN_S 0 /** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset i2s module + * Set 1 to reset i2s module */ #define PCR_I2S_RST_EN (BIT(1)) #define PCR_I2S_RST_EN_M (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S) @@ -850,11 +850,11 @@ extern "C" { #define PCR_I2S_TX_CLKM_DIV_NUM_V 0x000000FFU #define PCR_I2S_TX_CLKM_DIV_NUM_S 12 /** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of I2S TX.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F240M_CLK\\ - * 2: PLL_F160M_CLK\\ - * 3: I2S_MCLK_in\\ + * Configures the clock source of I2S TX. + * 0 (default): XTAL_CLK + * 1: PLL_F240M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in */ #define PCR_I2S_TX_CLKM_SEL 0x00000003U #define PCR_I2S_TX_CLKM_SEL_M (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S) @@ -917,11 +917,11 @@ extern "C" { #define PCR_I2S_RX_CLKM_DIV_NUM_V 0x000000FFU #define PCR_I2S_RX_CLKM_DIV_NUM_S 12 /** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of I2S RX.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F240M_CLK\\ - * 2: PLL_F160M_CLK\\ - * 3: I2S_MCLK_in\\ + * Configures the clock source of I2S RX. + * 0 (default): XTAL_CLK + * 1: PLL_F240M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in */ #define PCR_I2S_RX_CLKM_SEL 0x00000003U #define PCR_I2S_RX_CLKM_SEL_M (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S) @@ -935,9 +935,9 @@ extern "C" { #define PCR_I2S_RX_CLKM_EN_V 0x00000001U #define PCR_I2S_RX_CLKM_EN_S 22 /** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0; - * Configures to select master clock.\\ - * 0 (default): I2S_TX_CLK\\ - * 1: I2S_RX_CLK\\ + * Configures to select master clock. + * 0 (default): I2S_TX_CLK + * 1: I2S_RX_CLK */ #define PCR_I2S_MCLK_SEL (BIT(23)) #define PCR_I2S_MCLK_SEL_M (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S) @@ -993,7 +993,7 @@ extern "C" { #define PCR_SARADC_CLK_EN_V 0x00000001U #define PCR_SARADC_CLK_EN_S 0 /** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset function_register of saradc module + * Set 1 to reset function_register of saradc module */ #define PCR_SARADC_RST_EN (BIT(1)) #define PCR_SARADC_RST_EN_M (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S) @@ -1007,7 +1007,7 @@ extern "C" { #define PCR_SARADC_REG_CLK_EN_V 0x00000001U #define PCR_SARADC_REG_CLK_EN_S 2 /** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0; - * Set 0 to reset apb_register of saradc module + * Set 1 to reset apb_register of saradc module */ #define PCR_SARADC_REG_RST_EN (BIT(3)) #define PCR_SARADC_REG_RST_EN_M (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S) @@ -1040,10 +1040,10 @@ extern "C" { #define PCR_SARADC_CLKM_DIV_NUM_V 0x000000FFU #define PCR_SARADC_CLKM_DIV_NUM_S 12 /** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of SAR ADC.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of SAR ADC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_SARADC_CLKM_SEL 0x00000003U #define PCR_SARADC_CLKM_SEL_M (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S) @@ -1062,9 +1062,9 @@ extern "C" { */ #define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x90) /** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of the temperature sensor.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of the temperature sensor. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ #define PCR_TSENS_CLK_SEL (BIT(20)) #define PCR_TSENS_CLK_SEL_M (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S) @@ -1078,7 +1078,7 @@ extern "C" { #define PCR_TSENS_CLK_EN_V 0x00000001U #define PCR_TSENS_CLK_EN_S 22 /** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0; - * Set 0 to reset tsens module + * Set 1 to reset tsens module */ #define PCR_TSENS_RST_EN (BIT(23)) #define PCR_TSENS_RST_EN_M (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S) @@ -1097,7 +1097,7 @@ extern "C" { #define PCR_USB_DEVICE_CLK_EN_V 0x00000001U #define PCR_USB_DEVICE_CLK_EN_S 0 /** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset usb_device module + * Set 1 to reset usb_device module */ #define PCR_USB_DEVICE_RST_EN (BIT(1)) #define PCR_USB_DEVICE_RST_EN_M (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S) @@ -1123,7 +1123,7 @@ extern "C" { #define PCR_INTMTX_CLK_EN_V 0x00000001U #define PCR_INTMTX_CLK_EN_S 0 /** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset intmtx module + * Set 1 to reset intmtx module */ #define PCR_INTMTX_RST_EN (BIT(1)) #define PCR_INTMTX_RST_EN_M (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S) @@ -1149,7 +1149,7 @@ extern "C" { #define PCR_PCNT_CLK_EN_V 0x00000001U #define PCR_PCNT_CLK_EN_S 0 /** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset pcnt module + * Set 1 to reset pcnt module */ #define PCR_PCNT_RST_EN (BIT(1)) #define PCR_PCNT_RST_EN_M (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S) @@ -1175,7 +1175,7 @@ extern "C" { #define PCR_ETM_CLK_EN_V 0x00000001U #define PCR_ETM_CLK_EN_S 0 /** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset etm module + * Set 1 to reset etm module */ #define PCR_ETM_RST_EN (BIT(1)) #define PCR_ETM_RST_EN_M (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S) @@ -1201,7 +1201,7 @@ extern "C" { #define PCR_PWM_CLK_EN_V 0x00000001U #define PCR_PWM_CLK_EN_S 0 /** PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset pwm module + * Set 1 to reset pwm module */ #define PCR_PWM_RST_EN (BIT(1)) #define PCR_PWM_RST_EN_M (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S) @@ -1227,10 +1227,10 @@ extern "C" { #define PCR_PWM_DIV_NUM_V 0x000000FFU #define PCR_PWM_DIV_NUM_S 12 /** PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of MCPWM.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F160M_CLK\\ + * Configures the clock source of MCPWM. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F160M_CLK */ #define PCR_PWM_CLKM_SEL 0x00000003U #define PCR_PWM_CLKM_SEL_M (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S) @@ -1256,7 +1256,7 @@ extern "C" { #define PCR_PARL_CLK_EN_V 0x00000001U #define PCR_PARL_CLK_EN_S 0 /** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset parl apb reg + * Set 1 to reset parl apb reg */ #define PCR_PARL_RST_EN (BIT(1)) #define PCR_PARL_RST_EN_M (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S) @@ -1282,11 +1282,11 @@ extern "C" { #define PCR_PARL_CLK_RX_DIV_NUM_V 0x0000FFFFU #define PCR_PARL_CLK_RX_DIV_NUM_S 0 /** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0; - * Configures the clock source of Paraller IO RX\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F240M_CLK\\ - * 3: Use the clock from chip pin\\ + * Configures the clock source of Paraller IO RX + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F240M_CLK + * 3: Use the clock from chip pin */ #define PCR_PARL_CLK_RX_SEL 0x00000003U #define PCR_PARL_CLK_RX_SEL_M (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S) @@ -1300,7 +1300,7 @@ extern "C" { #define PCR_PARL_CLK_RX_EN_V 0x00000001U #define PCR_PARL_CLK_RX_EN_S 18 /** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0; - * Set 0 to reset parl rx module + * Set 1 to reset parl rx module */ #define PCR_PARL_RX_RST_EN (BIT(19)) #define PCR_PARL_RX_RST_EN_M (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S) @@ -1319,11 +1319,11 @@ extern "C" { #define PCR_PARL_CLK_TX_DIV_NUM_V 0x0000FFFFU #define PCR_PARL_CLK_TX_DIV_NUM_S 0 /** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0; - * Configures the clock source of Paraller IO RX\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F240M_CLK\\ - * 3: Use the clock from chip pin\\ + * Configures the clock source of Paraller IO RX + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F240M_CLK + * 3: Use the clock from chip pin */ #define PCR_PARL_CLK_TX_SEL 0x00000003U #define PCR_PARL_CLK_TX_SEL_M (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S) @@ -1337,7 +1337,7 @@ extern "C" { #define PCR_PARL_CLK_TX_EN_V 0x00000001U #define PCR_PARL_CLK_TX_EN_S 18 /** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0; - * Set 0 to reset parl tx module + * Set 1 to reset parl tx module */ #define PCR_PARL_TX_RST_EN (BIT(19)) #define PCR_PARL_TX_RST_EN_M (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S) @@ -1356,7 +1356,7 @@ extern "C" { #define PCR_PVT_MONITOR_CLK_EN_V 0x00000001U #define PCR_PVT_MONITOR_CLK_EN_S 0 /** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset all pvt monitor module + * Set 1 to reset all pvt monitor module */ #define PCR_PVT_MONITOR_RST_EN (BIT(1)) #define PCR_PVT_MONITOR_RST_EN_M (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S) @@ -1396,9 +1396,9 @@ extern "C" { #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 /** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of PVT MONITOR.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F160M_CLK\\ + * Configures the clock source of PVT MONITOR. + * 0 (default): XTAL_CLK + * 1: PLL_F160M_CLK */ #define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20)) #define PCR_PVT_MONITOR_FUNC_CLK_SEL_M (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S) @@ -1424,7 +1424,7 @@ extern "C" { #define PCR_GDMA_CLK_EN_V 0x00000001U #define PCR_GDMA_CLK_EN_S 0 /** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset gdma module + * Set 1 to reset gdma module */ #define PCR_GDMA_RST_EN (BIT(1)) #define PCR_GDMA_RST_EN_M (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S) @@ -1443,7 +1443,7 @@ extern "C" { #define PCR_SPI2_CLK_EN_V 0x00000001U #define PCR_SPI2_CLK_EN_S 0 /** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset spi2 module + * Set 1 to reset spi2 module */ #define PCR_SPI2_RST_EN (BIT(1)) #define PCR_SPI2_RST_EN_M (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S) @@ -1469,11 +1469,11 @@ extern "C" { #define PCR_SPI2_CLKM_DIV_NUM_V 0x000000FFU #define PCR_SPI2_CLKM_DIV_NUM_S 12 /** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of SPI2.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F160M_CLK\\ - * 2: RC_FAST_CLK\\ - * 3: PLL_F120M_CLK\\ + * Configures the clock source of SPI2. + * 0 (default): XTAL_CLK + * 1: PLL_F160M_CLK + * 2: RC_FAST_CLK + * 3: PLL_F120M_CLK */ #define PCR_SPI2_CLKM_SEL 0x00000003U #define PCR_SPI2_CLKM_SEL_M (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S) @@ -1499,7 +1499,7 @@ extern "C" { #define PCR_AES_CLK_EN_V 0x00000001U #define PCR_AES_CLK_EN_S 0 /** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset aes module + * Set 1 to reset aes module */ #define PCR_AES_RST_EN (BIT(1)) #define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S) @@ -1525,7 +1525,7 @@ extern "C" { #define PCR_SHA_CLK_EN_V 0x00000001U #define PCR_SHA_CLK_EN_S 0 /** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset sha module + * Set 1 to reset sha module */ #define PCR_SHA_RST_EN (BIT(1)) #define PCR_SHA_RST_EN_M (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S) @@ -1551,7 +1551,7 @@ extern "C" { #define PCR_RSA_CLK_EN_V 0x00000001U #define PCR_RSA_CLK_EN_S 0 /** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset rsa module + * Set 1 to reset rsa module */ #define PCR_RSA_RST_EN (BIT(1)) #define PCR_RSA_RST_EN_M (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S) @@ -1603,7 +1603,7 @@ extern "C" { #define PCR_ECC_CLK_EN_V 0x00000001U #define PCR_ECC_CLK_EN_S 0 /** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ecc module + * Set 1 to reset ecc module */ #define PCR_ECC_RST_EN (BIT(1)) #define PCR_ECC_RST_EN_M (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S) @@ -1655,7 +1655,7 @@ extern "C" { #define PCR_DS_CLK_EN_V 0x00000001U #define PCR_DS_CLK_EN_S 0 /** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ds module + * Set 1 to reset ds module */ #define PCR_DS_RST_EN (BIT(1)) #define PCR_DS_RST_EN_M (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S) @@ -1681,7 +1681,7 @@ extern "C" { #define PCR_HMAC_CLK_EN_V 0x00000001U #define PCR_HMAC_CLK_EN_S 0 /** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset hmac module + * Set 1 to reset hmac module */ #define PCR_HMAC_RST_EN (BIT(1)) #define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S) @@ -1707,7 +1707,7 @@ extern "C" { #define PCR_ECDSA_CLK_EN_V 0x00000001U #define PCR_ECDSA_CLK_EN_S 0 /** PCR_ECDSA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ecdsa module + * Set 1 to reset ecdsa module */ #define PCR_ECDSA_RST_EN (BIT(1)) #define PCR_ECDSA_RST_EN_M (PCR_ECDSA_RST_EN_V << PCR_ECDSA_RST_EN_S) @@ -1733,7 +1733,7 @@ extern "C" { #define PCR_IOMUX_CLK_EN_V 0x00000001U #define PCR_IOMUX_CLK_EN_S 0 /** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset iomux module + * Set 1 to reset iomux module */ #define PCR_IOMUX_RST_EN (BIT(1)) #define PCR_IOMUX_RST_EN_M (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S) @@ -1745,10 +1745,10 @@ extern "C" { */ #define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xf4) /** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of IO MUX.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of IO MUX. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_IOMUX_FUNC_CLK_SEL 0x00000003U #define PCR_IOMUX_FUNC_CLK_SEL_M (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S) @@ -1774,7 +1774,7 @@ extern "C" { #define PCR_REGDMA_CLK_EN_V 0x00000001U #define PCR_REGDMA_CLK_EN_S 0 /** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset regdma module + * Set 1 to reset regdma module */ #define PCR_REGDMA_RST_EN (BIT(1)) #define PCR_REGDMA_RST_EN_M (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S) @@ -1793,7 +1793,7 @@ extern "C" { #define PCR_TRACE_CLK_EN_V 0x00000001U #define PCR_TRACE_CLK_EN_S 0 /** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset trace module + * Set 1 to reset trace module */ #define PCR_TRACE_RST_EN (BIT(1)) #define PCR_TRACE_RST_EN_M (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S) @@ -1812,7 +1812,7 @@ extern "C" { #define PCR_ASSIST_CLK_EN_V 0x00000001U #define PCR_ASSIST_CLK_EN_S 0 /** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset assist module + * Set 1 to reset assist module */ #define PCR_ASSIST_RST_EN (BIT(1)) #define PCR_ASSIST_RST_EN_M (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S) @@ -1831,7 +1831,7 @@ extern "C" { #define PCR_CACHE_CLK_EN_V 0x00000001U #define PCR_CACHE_CLK_EN_S 0 /** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset cache module + * Set 1 to reset cache module */ #define PCR_CACHE_RST_EN (BIT(1)) #define PCR_CACHE_RST_EN_M (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S) @@ -1884,14 +1884,14 @@ extern "C" { */ #define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x10c) /** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset cpu_peri timeout module + * Set 1 to reset cpu_peri timeout module */ #define PCR_CPU_TIMEOUT_RST_EN (BIT(1)) #define PCR_CPU_TIMEOUT_RST_EN_M (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S) #define PCR_CPU_TIMEOUT_RST_EN_V 0x00000001U #define PCR_CPU_TIMEOUT_RST_EN_S 1 /** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0; - * Set 0 to reset hp_peri timeout module and hp_modem timeout module + * Set 1 to reset hp_peri timeout module and hp_modem timeout module */ #define PCR_HP_TIMEOUT_RST_EN (BIT(2)) #define PCR_HP_TIMEOUT_RST_EN_M (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S) @@ -1902,12 +1902,27 @@ extern "C" { * SYSCLK configuration register */ #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x110) +/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ +#define PCR_LS_DIV_NUM 0x000000FFU +#define PCR_LS_DIV_NUM_M (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S) +#define PCR_LS_DIV_NUM_V 0x000000FFU +#define PCR_LS_DIV_NUM_S 0 +/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ +#define PCR_HS_DIV_NUM 0x000000FFU +#define PCR_HS_DIV_NUM_M (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S) +#define PCR_HS_DIV_NUM_V 0x000000FFU +#define PCR_HS_DIV_NUM_S 8 /** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0; - * Configures to select the clock source of HP_ROOT_CLK.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F160M_CLK\\ - * 2: PLL_F240M_CLK\\ + * Configures to select the clock source of HP_ROOT_CLK. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F160M_CLK + * 2: PLL_F240M_CLK */ #define PCR_SOC_CLK_SEL 0x00000003U #define PCR_SOC_CLK_SEL_M (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S) @@ -1933,20 +1948,6 @@ extern "C" { * CPU_WAITI configuration register */ #define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x114) -/** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1; - * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM - */ -#define PCR_CPUPERIOD_SEL 0x00000003U -#define PCR_CPUPERIOD_SEL_M (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S) -#define PCR_CPUPERIOD_SEL_V 0x00000003U -#define PCR_CPUPERIOD_SEL_S 0 -/** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1; - * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM - */ -#define PCR_PLL_FREQ_SEL (BIT(2)) -#define PCR_PLL_FREQ_SEL_M (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S) -#define PCR_PLL_FREQ_SEL_V 0x00000001U -#define PCR_PLL_FREQ_SEL_S 2 /** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; * Set 1 to force cpu_waiti_clk enable. */ @@ -1968,7 +1969,7 @@ extern "C" { */ #define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118) /** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Set this field to generate clk_cpu driven by clk_hproot. The clk_cpu is + * Set this field to generate clk_cpu derived by clk_hproot. The clk_cpu is * div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. */ @@ -1982,7 +1983,7 @@ extern "C" { */ #define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c) /** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Set this field to generate clk_ahb driven by clk_hproot. The clk_ahb is + * Set this field to generate clk_ahb derived by clk_hproot. The clk_ahb is * div1(default)/div2/div4/div8 of clk_hproot. This field is only available for * low-speed clock-source such as XTAL/FOSC, and should be used together with * PCR_CPU_DIV_NUM. @@ -2010,7 +2011,7 @@ extern "C" { #define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU #define PCR_APB_DECREASE_DIV_NUM_S 0 /** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; - * Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is + * Set as one within (0,1,3) to generate clk_apb derived by clk_ahb. The clk_apb is * div1(default)/div2/div4 of clk_ahb. */ #define PCR_APB_DIV_NUM 0x000000FFU @@ -2042,7 +2043,7 @@ extern "C" { */ #define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x128) /** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1; - * This field is used to open 240 MHz clock (div2 of SPLL) driven from SPLL. 0: close, + * This field is used to open 240 MHz clock (div2 of SPLL) derived from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_240M_CLK_EN (BIT(0)) @@ -2050,7 +2051,7 @@ extern "C" { #define PCR_PLL_240M_CLK_EN_V 0x00000001U #define PCR_PLL_240M_CLK_EN_S 0 /** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1; - * This field is used to open 160 MHz clock (div3 of SPLL) driven from SPLL. 0: close, + * This field is used to open 160 MHz clock (div3 of SPLL) derived from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_160M_CLK_EN (BIT(1)) @@ -2058,7 +2059,7 @@ extern "C" { #define PCR_PLL_160M_CLK_EN_V 0x00000001U #define PCR_PLL_160M_CLK_EN_S 1 /** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1; - * This field is used to open 120 MHz clock (div4 of SPLL) driven from SPLL. 0: close, + * This field is used to open 120 MHz clock (div4 of SPLL) derived from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_120M_CLK_EN (BIT(2)) @@ -2066,7 +2067,7 @@ extern "C" { #define PCR_PLL_120M_CLK_EN_V 0x00000001U #define PCR_PLL_120M_CLK_EN_S 2 /** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1; - * This field is used to open 80 MHz clock (div6 of SPLL) driven from SPLL. 0: close, + * This field is used to open 80 MHz clock (div6 of SPLL) derived from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_80M_CLK_EN (BIT(3)) @@ -2074,7 +2075,7 @@ extern "C" { #define PCR_PLL_80M_CLK_EN_V 0x00000001U #define PCR_PLL_80M_CLK_EN_S 3 /** PCR_PLL_60M_CLK_EN : R/W; bitpos: [4]; default: 1; - * This field is used to open 60 MHz clock (div8 of SPLL) driven from SPLL. 0: close, + * This field is used to open 60 MHz clock (div8 of SPLL) derived from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_60M_CLK_EN (BIT(4)) @@ -2082,7 +2083,7 @@ extern "C" { #define PCR_PLL_60M_CLK_EN_V 0x00000001U #define PCR_PLL_60M_CLK_EN_S 4 /** PCR_PLL_48M_CLK_EN : R/W; bitpos: [5]; default: 1; - * This field is used to open 48 MHz clock (div10 of SPLL) driven from SPLL. 0: close, + * This field is used to open 48 MHz clock (div10 of SPLL) derived from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_48M_CLK_EN (BIT(5)) @@ -2090,7 +2091,7 @@ extern "C" { #define PCR_PLL_48M_CLK_EN_V 0x00000001U #define PCR_PLL_48M_CLK_EN_S 5 /** PCR_PLL_40M_CLK_EN : R/W; bitpos: [6]; default: 1; - * This field is used to open 40 MHz clock (div12 of SPLL) driven from SPLL. 0: close, + * This field is used to open 40 MHz clock (div12 of SPLL) derived from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_40M_CLK_EN (BIT(6)) @@ -2098,7 +2099,7 @@ extern "C" { #define PCR_PLL_40M_CLK_EN_V 0x00000001U #define PCR_PLL_40M_CLK_EN_S 6 /** PCR_PLL_20M_CLK_EN : R/W; bitpos: [7]; default: 1; - * This field is used to open 20 MHz clock (div24 of SPLL) driven from SPLL. 0: close, + * This field is used to open 20 MHz clock (div24 of SPLL) derived from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_20M_CLK_EN (BIT(7)) @@ -2106,7 +2107,7 @@ extern "C" { #define PCR_PLL_20M_CLK_EN_V 0x00000001U #define PCR_PLL_20M_CLK_EN_S 7 /** PCR_PLL_12M_CLK_EN : R/W; bitpos: [8]; default: 1; - * This field is used to open 12 MHz clock (div40 of SPLL) driven from SPLL. 0: close, + * This field is used to open 12 MHz clock (div40 of SPLL) derived from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_12M_CLK_EN (BIT(8)) @@ -2201,12 +2202,12 @@ extern "C" { */ #define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x130) /** PCR_32K_SEL : R/W; bitpos: [2:0]; default: 0; - * Configures the 32KHz clock for TIMER_GROUP.\\ - * 0 (default): RC32K_CLK\\ - * 1: XTAL32K_CLK\\ - * 2: OSC_SLOW_CLK\\ - * 3: RC_SLOW_CLK\\ - * 4: RC_FAST_CLK\\ + * Configures the 32KHz clock for TIMER_GROUP. + * 0 (default): RC32K_CLK + * 1: XTAL32K_CLK + * 2: OSC_SLOW_CLK + * 3: RC_SLOW_CLK + * 4: RC_FAST_CLK */ #define PCR_32K_SEL 0x00000007U #define PCR_32K_SEL_M (PCR_32K_SEL_V << PCR_32K_SEL_S) @@ -2281,59 +2282,33 @@ extern "C" { #define PCR_SEC_CONF_REG (DR_REG_PCR_BASE + 0x13c) /** PCR_SEC_CLK_SEL : R/W; bitpos: [1:0]; default: 0; * Configures the clock source for the External Memory Encryption and Decryption - * module.\\ - * 0(default): XTAL_CLK\\ - * 1 RC_FAST_CLK\\ - * 2: PLL_F480M_CLK\\ + * module. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK */ #define PCR_SEC_CLK_SEL 0x00000003U #define PCR_SEC_CLK_SEL_M (PCR_SEC_CLK_SEL_V << PCR_SEC_CLK_SEL_S) #define PCR_SEC_CLK_SEL_V 0x00000003U #define PCR_SEC_CLK_SEL_S 0 /** PCR_SEC_RST_EN : R/W; bitpos: [2]; default: 0; - * Set 0 to reset sec module + * Set 1 to reset sec module */ #define PCR_SEC_RST_EN (BIT(2)) #define PCR_SEC_RST_EN_M (PCR_SEC_RST_EN_V << PCR_SEC_RST_EN_S) #define PCR_SEC_RST_EN_V 0x00000001U #define PCR_SEC_RST_EN_S 2 -/** PCR_ADC_DAC_INV_PHASE_CONF_REG register - * xxxx - */ -#define PCR_ADC_DAC_INV_PHASE_CONF_REG (DR_REG_PCR_BASE + 0x140) -/** PCR_CLK_RX_ADC_INV_PHASE_ENA : R/W; bitpos: [0]; default: 0; - * xxxx - */ -#define PCR_CLK_RX_ADC_INV_PHASE_ENA (BIT(0)) -#define PCR_CLK_RX_ADC_INV_PHASE_ENA_M (PCR_CLK_RX_ADC_INV_PHASE_ENA_V << PCR_CLK_RX_ADC_INV_PHASE_ENA_S) -#define PCR_CLK_RX_ADC_INV_PHASE_ENA_V 0x00000001U -#define PCR_CLK_RX_ADC_INV_PHASE_ENA_S 0 -/** PCR_CLK_TX_DAC_INV_PHASE_ENA : R/W; bitpos: [1]; default: 0; - * xxxx - */ -#define PCR_CLK_TX_DAC_INV_PHASE_ENA (BIT(1)) -#define PCR_CLK_TX_DAC_INV_PHASE_ENA_M (PCR_CLK_TX_DAC_INV_PHASE_ENA_V << PCR_CLK_TX_DAC_INV_PHASE_ENA_S) -#define PCR_CLK_TX_DAC_INV_PHASE_ENA_V 0x00000001U -#define PCR_CLK_TX_DAC_INV_PHASE_ENA_S 1 -/** PCR_CLK_PWDET_ADC_INV_PHASE_ENA : R/W; bitpos: [2]; default: 0; - * xxxx - */ -#define PCR_CLK_PWDET_ADC_INV_PHASE_ENA (BIT(2)) -#define PCR_CLK_PWDET_ADC_INV_PHASE_ENA_M (PCR_CLK_PWDET_ADC_INV_PHASE_ENA_V << PCR_CLK_PWDET_ADC_INV_PHASE_ENA_S) -#define PCR_CLK_PWDET_ADC_INV_PHASE_ENA_V 0x00000001U -#define PCR_CLK_PWDET_ADC_INV_PHASE_ENA_S 2 - /** PCR_BUS_CLK_UPDATE_REG register * Configuration register for applying updated high-performance system clock sources */ #define PCR_BUS_CLK_UPDATE_REG (DR_REG_PCR_BASE + 0x144) /** PCR_BUS_CLOCK_UPDATE : R/W/WTC; bitpos: [0]; default: 0; * Configures whether or not to update configurations for CPU_CLK division, AHB_CLK - * division and HP_ROOT_CLK clock source selection.\\ - * 0: Not update configurations\\ - * 1: Update configurations\\ - * This bit is automatically cleared when configurations have been updated.\\ + * division and HP_ROOT_CLK clock source selection. + * 0: Not update configurations + * 1: Update configurations + * This bit is automatically cleared when configurations have been updated. */ #define PCR_BUS_CLOCK_UPDATE (BIT(0)) #define PCR_BUS_CLOCK_UPDATE_M (PCR_BUS_CLOCK_UPDATE_V << PCR_BUS_CLOCK_UPDATE_S) @@ -2345,41 +2320,20 @@ extern "C" { */ #define PCR_SAR_CLK_DIV_REG (DR_REG_PCR_BASE + 0x148) /** PCR_SAR2_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 4; - * Configures the divisor for SAR ADC 2 clock to generate ADC analog control - * signals.\\ + * Configures the divisor for SAR ADC 2 clock to generate ADC analog control signals. */ #define PCR_SAR2_CLK_DIV_NUM 0x000000FFU #define PCR_SAR2_CLK_DIV_NUM_M (PCR_SAR2_CLK_DIV_NUM_V << PCR_SAR2_CLK_DIV_NUM_S) #define PCR_SAR2_CLK_DIV_NUM_V 0x000000FFU #define PCR_SAR2_CLK_DIV_NUM_S 0 /** PCR_SAR1_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 4; - * Configures the divisor for SAR ADC 1 clock to generate ADC analog control - * signals.\\ + * Configures the divisor for SAR ADC 1 clock to generate ADC analog control signals. */ #define PCR_SAR1_CLK_DIV_NUM 0x000000FFU #define PCR_SAR1_CLK_DIV_NUM_M (PCR_SAR1_CLK_DIV_NUM_V << PCR_SAR1_CLK_DIV_NUM_S) #define PCR_SAR1_CLK_DIV_NUM_V 0x000000FFU #define PCR_SAR1_CLK_DIV_NUM_S 8 -/** PCR_PWDET_SAR_CLK_CONF_REG register - * xxxx - */ -#define PCR_PWDET_SAR_CLK_CONF_REG (DR_REG_PCR_BASE + 0x14c) -/** PCR_PWDET_SAR_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 7; - * xxxx - */ -#define PCR_PWDET_SAR_CLK_DIV_NUM 0x000000FFU -#define PCR_PWDET_SAR_CLK_DIV_NUM_M (PCR_PWDET_SAR_CLK_DIV_NUM_V << PCR_PWDET_SAR_CLK_DIV_NUM_S) -#define PCR_PWDET_SAR_CLK_DIV_NUM_V 0x000000FFU -#define PCR_PWDET_SAR_CLK_DIV_NUM_S 0 -/** PCR_PWDET_SAR_CLK_EN : R/W; bitpos: [8]; default: 1; - * xxxx - */ -#define PCR_PWDET_SAR_CLK_EN (BIT(8)) -#define PCR_PWDET_SAR_CLK_EN_M (PCR_PWDET_SAR_CLK_EN_V << PCR_PWDET_SAR_CLK_EN_S) -#define PCR_PWDET_SAR_CLK_EN_V 0x00000001U -#define PCR_PWDET_SAR_CLK_EN_S 8 - /** PCR_BS_CONF_REG register * BS configuration register */ @@ -2392,7 +2346,7 @@ extern "C" { #define PCR_BS_CLK_EN_V 0x00000001U #define PCR_BS_CLK_EN_S 0 /** PCR_BS_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset bs module + * Set 1 to reset bs module */ #define PCR_BS_RST_EN (BIT(1)) #define PCR_BS_RST_EN_M (PCR_BS_RST_EN_V << PCR_BS_RST_EN_S) @@ -2404,14 +2358,14 @@ extern "C" { */ #define PCR_BS_FUNC_CONF_REG (DR_REG_PCR_BASE + 0x154) /** PCR_BS_TX_RST_EN : R/W; bitpos: [23]; default: 0; - * Set 0 to reset bs tx module + * Set 1 to reset bs tx module */ #define PCR_BS_TX_RST_EN (BIT(23)) #define PCR_BS_TX_RST_EN_M (PCR_BS_TX_RST_EN_V << PCR_BS_TX_RST_EN_S) #define PCR_BS_TX_RST_EN_V 0x00000001U #define PCR_BS_TX_RST_EN_S 23 /** PCR_BS_RX_RST_EN : R/W; bitpos: [24]; default: 0; - * Set 0 to reset bs rx module + * Set 1 to reset bs rx module */ #define PCR_BS_RX_RST_EN (BIT(24)) #define PCR_BS_RX_RST_EN_M (PCR_BS_RX_RST_EN_V << PCR_BS_RX_RST_EN_S) @@ -2442,14 +2396,14 @@ extern "C" { */ #define PCR_TIMERGROUP_WDT_CONF_REG (DR_REG_PCR_BASE + 0x15c) /** PCR_TG0_WDT_RST_EN : R/W; bitpos: [0]; default: 0; - * Set 0 to reset timer_group0 wdt module + * Set 1 to reset timer_group0 wdt module */ #define PCR_TG0_WDT_RST_EN (BIT(0)) #define PCR_TG0_WDT_RST_EN_M (PCR_TG0_WDT_RST_EN_V << PCR_TG0_WDT_RST_EN_S) #define PCR_TG0_WDT_RST_EN_V 0x00000001U #define PCR_TG0_WDT_RST_EN_S 0 /** PCR_TG1_WDT_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 wdt module + * Set 1 to reset timer_group1 wdt module */ #define PCR_TG1_WDT_RST_EN (BIT(1)) #define PCR_TG1_WDT_RST_EN_M (PCR_TG1_WDT_RST_EN_V << PCR_TG1_WDT_RST_EN_S) @@ -2461,14 +2415,14 @@ extern "C" { */ #define PCR_TIMERGROUP_XTAL_CONF_REG (DR_REG_PCR_BASE + 0x160) /** PCR_TG0_XTAL_RST_EN : R/W; bitpos: [0]; default: 0; - * Set 0 to reset timer_group0 xtal clock domain + * Set 1 to reset timer_group0 xtal clock domain */ #define PCR_TG0_XTAL_RST_EN (BIT(0)) #define PCR_TG0_XTAL_RST_EN_M (PCR_TG0_XTAL_RST_EN_V << PCR_TG0_XTAL_RST_EN_S) #define PCR_TG0_XTAL_RST_EN_V 0x00000001U #define PCR_TG0_XTAL_RST_EN_S 0 /** PCR_TG1_XTAL_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 xtal clock domain + * Set 1 to reset timer_group1 xtal clock domain */ #define PCR_TG1_XTAL_RST_EN (BIT(1)) #define PCR_TG1_XTAL_RST_EN_M (PCR_TG1_XTAL_RST_EN_V << PCR_TG1_XTAL_RST_EN_S) @@ -2494,7 +2448,7 @@ extern "C" { #define PCR_KM_CLK_EN_V 0x00000001U #define PCR_KM_CLK_EN_S 0 /** PCR_KM_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset km module + * Set 1 to reset km module */ #define PCR_KM_RST_EN (BIT(1)) #define PCR_KM_RST_EN_M (PCR_KM_RST_EN_V << PCR_KM_RST_EN_S) @@ -2539,7 +2493,7 @@ extern "C" { #define PCR_TCM_MEM_MONITOR_CLK_EN_V 0x00000001U #define PCR_TCM_MEM_MONITOR_CLK_EN_S 0 /** PCR_TCM_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset tcm_mem_monitor module + * Set 1 to reset tcm_mem_monitor module */ #define PCR_TCM_MEM_MONITOR_RST_EN (BIT(1)) #define PCR_TCM_MEM_MONITOR_RST_EN_M (PCR_TCM_MEM_MONITOR_RST_EN_V << PCR_TCM_MEM_MONITOR_RST_EN_S) @@ -2565,7 +2519,7 @@ extern "C" { #define PCR_PSRAM_MEM_MONITOR_CLK_EN_V 0x00000001U #define PCR_PSRAM_MEM_MONITOR_CLK_EN_S 0 /** PCR_PSRAM_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset psram_mem_monitor module + * Set 1 to reset psram_mem_monitor module */ #define PCR_PSRAM_MEM_MONITOR_RST_EN (BIT(1)) #define PCR_PSRAM_MEM_MONITOR_RST_EN_M (PCR_PSRAM_MEM_MONITOR_RST_EN_V << PCR_PSRAM_MEM_MONITOR_RST_EN_S) @@ -2623,6 +2577,25 @@ extern "C" { #define PCR_HPCORE_0_MEM_FORCE_PD_V 0x00000001U #define PCR_HPCORE_0_MEM_FORCE_PD_S 2 +/** PCR_SDIO_SLAVE_CONF_REG register + * SDIO_SLAVE configuration register + */ +#define PCR_SDIO_SLAVE_CONF_REG (DR_REG_PCR_BASE + 0x17c) +/** PCR_SDIO_SLAVE_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable sdio_slave clock + */ +#define PCR_SDIO_SLAVE_CLK_EN (BIT(0)) +#define PCR_SDIO_SLAVE_CLK_EN_M (PCR_SDIO_SLAVE_CLK_EN_V << PCR_SDIO_SLAVE_CLK_EN_S) +#define PCR_SDIO_SLAVE_CLK_EN_V 0x00000001U +#define PCR_SDIO_SLAVE_CLK_EN_S 0 +/** PCR_SDIO_SLAVE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset sdio_slave module + */ +#define PCR_SDIO_SLAVE_RST_EN (BIT(1)) +#define PCR_SDIO_SLAVE_RST_EN_M (PCR_SDIO_SLAVE_RST_EN_V << PCR_SDIO_SLAVE_RST_EN_S) +#define PCR_SDIO_SLAVE_RST_EN_V 0x00000001U +#define PCR_SDIO_SLAVE_RST_EN_S 1 + /** PCR_FPGA_DEBUG_REG register * fpga debug register */ @@ -2651,7 +2624,7 @@ extern "C" { * Date register. */ #define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc) -/** PCR_DATE : R/W; bitpos: [27:0]; default: 36774528; +/** PCR_DATE : R/W; bitpos: [27:0]; default: 2363425; * PCR version information. */ #define PCR_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c5/register/soc/pcr_struct.h b/components/soc/esp32c5/register/soc/pcr_struct.h index 299a2da15b..fddb127f87 100644 --- a/components/soc/esp32c5/register/soc/pcr_struct.h +++ b/components/soc/esp32c5/register/soc/pcr_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -21,7 +21,7 @@ typedef union { */ uint32_t uart0_clk_en:1; /** uart0_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart0 module + * Set 1 to reset uart0 module */ uint32_t uart0_rst_en:1; /** uart0_ready : RO; bitpos: [2]; default: 1; @@ -51,10 +51,10 @@ typedef union { */ uint32_t uart0_sclk_div_num:8; /** uart0_sclk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of UART0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of UART0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t uart0_sclk_sel:2; /** uart0_sclk_en : R/W; bitpos: [22]; default: 1; @@ -95,7 +95,7 @@ typedef union { */ uint32_t uart1_clk_en:1; /** uart1_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart1 module + * Set 1 to reset uart1 module */ uint32_t uart1_rst_en:1; /** uart1_ready : RO; bitpos: [2]; default: 1; @@ -125,10 +125,10 @@ typedef union { */ uint32_t uart1_sclk_div_num:8; /** uart1_sclk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of UART1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of UART1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t uart1_sclk_sel:2; /** uart1_sclk_en : R/W; bitpos: [22]; default: 1; @@ -169,7 +169,7 @@ typedef union { */ uint32_t mspi_clk_en:1; /** mspi_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset mspi module + * Set 1 to reset mspi module */ uint32_t mspi_rst_en:1; /** mspi_pll_clk_en : R/W; bitpos: [2]; default: 1; @@ -197,10 +197,10 @@ typedef union { */ uint32_t mspi_fast_div_num:8; /** mspi_func_clk_sel : R/W; bitpos: [9:8]; default: 0; - * Configures the clock source for MSPI.\\ - * 0(default): XTAL_CLK\\ - * 1 RC_FAST_CLK\\ - * 2: PLL_F480M_CLK\\ + * Configures the clock source for MSPI. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK */ uint32_t mspi_func_clk_sel:2; /** mspi_func_clk_en : R/W; bitpos: [10]; default: 1; @@ -208,7 +208,7 @@ typedef union { */ uint32_t mspi_func_clk_en:1; /** mspi_axi_rst_en : R/W; bitpos: [11]; default: 0; - * Set 0 to reset axi_clock domain of mspi module + * Set 1 to reset axi_clock domain of mspi module */ uint32_t mspi_axi_rst_en:1; uint32_t reserved_12:20; @@ -226,7 +226,7 @@ typedef union { */ uint32_t i2c_clk_en:1; /** i2c_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset i2c module + * Set 1 to reset i2c module */ uint32_t i2c_rst_en:1; uint32_t reserved_2:30; @@ -252,9 +252,9 @@ typedef union { */ uint32_t i2c_sclk_div_num:8; /** i2c_sclk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of I2C.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of I2C. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ uint32_t i2c_sclk_sel:1; uint32_t reserved_21:1; @@ -277,7 +277,7 @@ typedef union { */ uint32_t twai_clk_en:1; /** twai_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset twai module + * Set 1 to reset twai module */ uint32_t twai_rst_en:1; /** twai_ready : RO; bitpos: [2]; default: 1; @@ -296,9 +296,9 @@ typedef union { struct { uint32_t reserved_0:20; /** twai_func_clk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of TWAI.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of TWAI. + * 0 (default): XTAL_CLK + * 1: PLL_F80M_CLK */ uint32_t twai_func_clk_sel:1; uint32_t reserved_21:1; @@ -321,7 +321,7 @@ typedef union { */ uint32_t uhci_clk_en:1; /** uhci_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uhci module + * Set 1 to reset uhci module */ uint32_t uhci_rst_en:1; /** uhci_ready : RO; bitpos: [2]; default: 1; @@ -343,7 +343,7 @@ typedef union { */ uint32_t rmt_clk_en:1; /** rmt_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset rmt module + * Set 1 to reset rmt module */ uint32_t rmt_rst_en:1; uint32_t reserved_2:30; @@ -369,10 +369,10 @@ typedef union { */ uint32_t rmt_sclk_div_num:8; /** rmt_sclk_sel : R/W; bitpos: [21:20]; default: 1; - * Configures the clock source of RMT.\\ - * 0: XTAL_CLK\\ - * 1 (default): RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of RMT. + * 0: XTAL_CLK + * 1 (default): RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t rmt_sclk_sel:2; /** rmt_sclk_en : R/W; bitpos: [22]; default: 0; @@ -413,7 +413,7 @@ typedef union { */ uint32_t ledc_clk_en:1; /** ledc_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ledc module + * Set 1 to reset ledc module */ uint32_t ledc_rst_en:1; /** ledc_ready : RO; bitpos: [2]; default: 1; @@ -432,10 +432,10 @@ typedef union { struct { uint32_t reserved_0:20; /** ledc_sclk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of LEDC.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of LEDC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t ledc_sclk_sel:2; /** ledc_sclk_en : R/W; bitpos: [22]; default: 0; @@ -476,7 +476,7 @@ typedef union { */ uint32_t tg0_clk_en:1; /** tg0_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group0 module + * Set 1 to reset timer_group0 module */ uint32_t tg0_rst_en:1; /** tg0_wdt_ready : RO; bitpos: [2]; default: 1; @@ -503,10 +503,10 @@ typedef union { struct { uint32_t reserved_0:20; /** tg0_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of general-purpose timers in Timer Group 0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of general-purpose timers in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t tg0_timer_clk_sel:2; /** tg0_timer_clk_en : R/W; bitpos: [22]; default: 1; @@ -525,10 +525,10 @@ typedef union { struct { uint32_t reserved_0:20; /** tg0_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of WDT in Timer Group 0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of WDT in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t tg0_wdt_clk_sel:2; /** tg0_wdt_clk_en : R/W; bitpos: [22]; default: 1; @@ -550,7 +550,7 @@ typedef union { */ uint32_t tg1_clk_en:1; /** tg1_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 module + * Set 1 to reset timer_group1 module */ uint32_t tg1_rst_en:1; /** tg1_wdt_ready : RO; bitpos: [2]; default: 1; @@ -577,10 +577,10 @@ typedef union { struct { uint32_t reserved_0:20; /** tg1_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of general-purpose timers in Timer Group 1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of general-purpose timers in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t tg1_timer_clk_sel:2; /** tg1_timer_clk_en : R/W; bitpos: [22]; default: 1; @@ -599,10 +599,10 @@ typedef union { struct { uint32_t reserved_0:20; /** tg1_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of WDT in Timer Group 1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of WDT in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t tg1_wdt_clk_sel:2; /** tg1_wdt_clk_en : R/W; bitpos: [22]; default: 1; @@ -624,7 +624,7 @@ typedef union { */ uint32_t systimer_clk_en:1; /** systimer_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset systimer module + * Set 1 to reset systimer module */ uint32_t systimer_rst_en:1; /** systimer_ready : RO; bitpos: [2]; default: 1; @@ -643,9 +643,9 @@ typedef union { struct { uint32_t reserved_0:20; /** systimer_func_clk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of System Timer.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of System Timer. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ uint32_t systimer_func_clk_sel:1; uint32_t reserved_21:1; @@ -668,7 +668,7 @@ typedef union { */ uint32_t i2s_clk_en:1; /** i2s_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset i2s module + * Set 1 to reset i2s module */ uint32_t i2s_rst_en:1; /** i2s_rx_ready : RO; bitpos: [2]; default: 1; @@ -698,11 +698,11 @@ typedef union { */ uint32_t i2s_tx_clkm_div_num:8; /** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of I2S TX.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F240M_CLK\\ - * 2: PLL_F160M_CLK\\ - * 3: I2S_MCLK_in\\ + * Configures the clock source of I2S TX. + * 0 (default): XTAL_CLK + * 1: PLL_F240M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in */ uint32_t i2s_tx_clkm_sel:2; /** i2s_tx_clkm_en : R/W; bitpos: [22]; default: 0; @@ -755,11 +755,11 @@ typedef union { */ uint32_t i2s_rx_clkm_div_num:8; /** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of I2S RX.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F240M_CLK\\ - * 2: PLL_F160M_CLK\\ - * 3: I2S_MCLK_in\\ + * Configures the clock source of I2S RX. + * 0 (default): XTAL_CLK + * 1: PLL_F240M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in */ uint32_t i2s_rx_clkm_sel:2; /** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 0; @@ -767,9 +767,9 @@ typedef union { */ uint32_t i2s_rx_clkm_en:1; /** i2s_mclk_sel : R/W; bitpos: [23]; default: 0; - * Configures to select master clock.\\ - * 0 (default): I2S_TX_CLK\\ - * 1: I2S_RX_CLK\\ + * Configures to select master clock. + * 0 (default): I2S_TX_CLK + * 1: I2S_RX_CLK */ uint32_t i2s_mclk_sel:1; uint32_t reserved_24:8; @@ -817,7 +817,7 @@ typedef union { */ uint32_t saradc_clk_en:1; /** saradc_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset function_register of saradc module + * Set 1 to reset function_register of saradc module */ uint32_t saradc_rst_en:1; /** saradc_reg_clk_en : R/W; bitpos: [2]; default: 0; @@ -825,7 +825,7 @@ typedef union { */ uint32_t saradc_reg_clk_en:1; /** saradc_reg_rst_en : R/W; bitpos: [3]; default: 0; - * Set 0 to reset apb_register of saradc module + * Set 1 to reset apb_register of saradc module */ uint32_t saradc_reg_rst_en:1; uint32_t reserved_4:28; @@ -851,10 +851,10 @@ typedef union { */ uint32_t saradc_clkm_div_num:8; /** saradc_clkm_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of SAR ADC.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of SAR ADC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t saradc_clkm_sel:2; /** saradc_clkm_en : R/W; bitpos: [22]; default: 0; @@ -873,9 +873,9 @@ typedef union { struct { uint32_t reserved_0:20; /** tsens_clk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of the temperature sensor.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of the temperature sensor. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ uint32_t tsens_clk_sel:1; uint32_t reserved_21:1; @@ -884,7 +884,7 @@ typedef union { */ uint32_t tsens_clk_en:1; /** tsens_rst_en : R/W; bitpos: [23]; default: 0; - * Set 0 to reset tsens module + * Set 1 to reset tsens module */ uint32_t tsens_rst_en:1; uint32_t reserved_24:8; @@ -902,7 +902,7 @@ typedef union { */ uint32_t usb_device_clk_en:1; /** usb_device_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset usb_device module + * Set 1 to reset usb_device module */ uint32_t usb_device_rst_en:1; /** usb_device_ready : RO; bitpos: [2]; default: 1; @@ -924,7 +924,7 @@ typedef union { */ uint32_t intmtx_clk_en:1; /** intmtx_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset intmtx module + * Set 1 to reset intmtx module */ uint32_t intmtx_rst_en:1; /** intmtx_ready : RO; bitpos: [2]; default: 1; @@ -946,7 +946,7 @@ typedef union { */ uint32_t pcnt_clk_en:1; /** pcnt_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset pcnt module + * Set 1 to reset pcnt module */ uint32_t pcnt_rst_en:1; /** pcnt_ready : RO; bitpos: [2]; default: 1; @@ -968,7 +968,7 @@ typedef union { */ uint32_t etm_clk_en:1; /** etm_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset etm module + * Set 1 to reset etm module */ uint32_t etm_rst_en:1; /** etm_ready : RO; bitpos: [2]; default: 1; @@ -990,7 +990,7 @@ typedef union { */ uint32_t pwm_clk_en:1; /** pwm_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset pwm module + * Set 1 to reset pwm module */ uint32_t pwm_rst_en:1; /** pwm_ready : RO; bitpos: [2]; default: 1; @@ -1013,10 +1013,10 @@ typedef union { */ uint32_t pwm_div_num:8; /** pwm_clkm_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of MCPWM.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F160M_CLK\\ + * Configures the clock source of MCPWM. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F160M_CLK */ uint32_t pwm_clkm_sel:2; /** pwm_clkm_en : R/W; bitpos: [22]; default: 0; @@ -1038,7 +1038,7 @@ typedef union { */ uint32_t parl_clk_en:1; /** parl_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset parl apb reg + * Set 1 to reset parl apb reg */ uint32_t parl_rst_en:1; /** parl_ready : RO; bitpos: [2]; default: 1; @@ -1060,11 +1060,11 @@ typedef union { */ uint32_t parl_clk_rx_div_num:16; /** parl_clk_rx_sel : R/W; bitpos: [17:16]; default: 0; - * Configures the clock source of Paraller IO RX\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F240M_CLK\\ - * 3: Use the clock from chip pin\\ + * Configures the clock source of Paraller IO RX + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F240M_CLK + * 3: Use the clock from chip pin */ uint32_t parl_clk_rx_sel:2; /** parl_clk_rx_en : R/W; bitpos: [18]; default: 0; @@ -1072,7 +1072,7 @@ typedef union { */ uint32_t parl_clk_rx_en:1; /** parl_rx_rst_en : R/W; bitpos: [19]; default: 0; - * Set 0 to reset parl rx module + * Set 1 to reset parl rx module */ uint32_t parl_rx_rst_en:1; uint32_t reserved_20:12; @@ -1090,11 +1090,11 @@ typedef union { */ uint32_t parl_clk_tx_div_num:16; /** parl_clk_tx_sel : R/W; bitpos: [17:16]; default: 0; - * Configures the clock source of Paraller IO RX\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F240M_CLK\\ - * 3: Use the clock from chip pin\\ + * Configures the clock source of Paraller IO RX + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F240M_CLK + * 3: Use the clock from chip pin */ uint32_t parl_clk_tx_sel:2; /** parl_clk_tx_en : R/W; bitpos: [18]; default: 0; @@ -1102,7 +1102,7 @@ typedef union { */ uint32_t parl_clk_tx_en:1; /** parl_tx_rst_en : R/W; bitpos: [19]; default: 0; - * Set 0 to reset parl tx module + * Set 1 to reset parl tx module */ uint32_t parl_tx_rst_en:1; uint32_t reserved_20:12; @@ -1120,7 +1120,7 @@ typedef union { */ uint32_t pvt_monitor_clk_en:1; /** pvt_monitor_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset all pvt monitor module + * Set 1 to reset all pvt monitor module */ uint32_t pvt_monitor_rst_en:1; /** pvt_monitor_site1_clk_en : R/W; bitpos: [2]; default: 1; @@ -1151,9 +1151,9 @@ typedef union { uint32_t pvt_monitor_func_clk_div_num:4; uint32_t reserved_4:16; /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of PVT MONITOR.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F160M_CLK\\ + * Configures the clock source of PVT MONITOR. + * 0 (default): XTAL_CLK + * 1: PLL_F160M_CLK */ uint32_t pvt_monitor_func_clk_sel:1; uint32_t reserved_21:1; @@ -1176,7 +1176,7 @@ typedef union { */ uint32_t gdma_clk_en:1; /** gdma_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset gdma module + * Set 1 to reset gdma module */ uint32_t gdma_rst_en:1; uint32_t reserved_2:30; @@ -1194,7 +1194,7 @@ typedef union { */ uint32_t spi2_clk_en:1; /** spi2_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset spi2 module + * Set 1 to reset spi2 module */ uint32_t spi2_rst_en:1; /** spi2_ready : RO; bitpos: [2]; default: 1; @@ -1217,11 +1217,11 @@ typedef union { */ uint32_t spi2_clkm_div_num:8; /** spi2_clkm_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of SPI2.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F160M_CLK\\ - * 2: RC_FAST_CLK\\ - * 3: PLL_F120M_CLK\\ + * Configures the clock source of SPI2. + * 0 (default): XTAL_CLK + * 1: PLL_F160M_CLK + * 2: RC_FAST_CLK + * 3: PLL_F120M_CLK */ uint32_t spi2_clkm_sel:2; /** spi2_clkm_en : R/W; bitpos: [22]; default: 1; @@ -1243,7 +1243,7 @@ typedef union { */ uint32_t aes_clk_en:1; /** aes_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset aes module + * Set 1 to reset aes module */ uint32_t aes_rst_en:1; /** aes_ready : RO; bitpos: [2]; default: 1; @@ -1265,7 +1265,7 @@ typedef union { */ uint32_t sha_clk_en:1; /** sha_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset sha module + * Set 1 to reset sha module */ uint32_t sha_rst_en:1; /** sha_ready : RO; bitpos: [2]; default: 1; @@ -1287,7 +1287,7 @@ typedef union { */ uint32_t rsa_clk_en:1; /** rsa_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset rsa module + * Set 1 to reset rsa module */ uint32_t rsa_rst_en:1; /** rsa_ready : RO; bitpos: [2]; default: 1; @@ -1331,7 +1331,7 @@ typedef union { */ uint32_t ecc_clk_en:1; /** ecc_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ecc module + * Set 1 to reset ecc module */ uint32_t ecc_rst_en:1; /** ecc_ready : RO; bitpos: [2]; default: 1; @@ -1375,7 +1375,7 @@ typedef union { */ uint32_t ds_clk_en:1; /** ds_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ds module + * Set 1 to reset ds module */ uint32_t ds_rst_en:1; /** ds_ready : RO; bitpos: [2]; default: 1; @@ -1397,7 +1397,7 @@ typedef union { */ uint32_t hmac_clk_en:1; /** hmac_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset hmac module + * Set 1 to reset hmac module */ uint32_t hmac_rst_en:1; /** hmac_ready : RO; bitpos: [2]; default: 1; @@ -1419,7 +1419,7 @@ typedef union { */ uint32_t ecdsa_clk_en:1; /** ecdsa_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ecdsa module + * Set 1 to reset ecdsa module */ uint32_t ecdsa_rst_en:1; /** ecdsa_ready : RO; bitpos: [2]; default: 1; @@ -1441,7 +1441,7 @@ typedef union { */ uint32_t iomux_clk_en:1; /** iomux_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset iomux module + * Set 1 to reset iomux module */ uint32_t iomux_rst_en:1; uint32_t reserved_2:30; @@ -1456,10 +1456,10 @@ typedef union { struct { uint32_t reserved_0:20; /** iomux_func_clk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of IO MUX.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of IO MUX. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t iomux_func_clk_sel:2; /** iomux_func_clk_en : R/W; bitpos: [22]; default: 1; @@ -1481,7 +1481,7 @@ typedef union { */ uint32_t regdma_clk_en:1; /** regdma_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset regdma module + * Set 1 to reset regdma module */ uint32_t regdma_rst_en:1; uint32_t reserved_2:30; @@ -1499,7 +1499,7 @@ typedef union { */ uint32_t trace_clk_en:1; /** trace_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset trace module + * Set 1 to reset trace module */ uint32_t trace_rst_en:1; uint32_t reserved_2:30; @@ -1517,7 +1517,7 @@ typedef union { */ uint32_t assist_clk_en:1; /** assist_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset assist module + * Set 1 to reset assist module */ uint32_t assist_rst_en:1; uint32_t reserved_2:30; @@ -1535,7 +1535,7 @@ typedef union { */ uint32_t cache_clk_en:1; /** cache_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset cache module + * Set 1 to reset cache module */ uint32_t cache_rst_en:1; /** cache_pu_en : R/W; bitpos: [2]; default: 1; @@ -1581,11 +1581,11 @@ typedef union { struct { uint32_t reserved_0:1; /** cpu_timeout_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset cpu_peri timeout module + * Set 1 to reset cpu_peri timeout module */ uint32_t cpu_timeout_rst_en:1; /** hp_timeout_rst_en : R/W; bitpos: [2]; default: 0; - * Set 0 to reset hp_peri timeout module and hp_modem timeout module + * Set 1 to reset hp_peri timeout module and hp_modem timeout module */ uint32_t hp_timeout_rst_en:1; uint32_t reserved_3:29; @@ -1598,13 +1598,21 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:16; + /** ls_div_num : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ + uint32_t ls_div_num:8; + /** hs_div_num : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ + uint32_t hs_div_num:8; /** soc_clk_sel : R/W; bitpos: [17:16]; default: 0; - * Configures to select the clock source of HP_ROOT_CLK.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F160M_CLK\\ - * 2: PLL_F240M_CLK\\ + * Configures to select the clock source of HP_ROOT_CLK. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F160M_CLK + * 2: PLL_F240M_CLK */ uint32_t soc_clk_sel:2; uint32_t reserved_18:6; @@ -1626,14 +1634,7 @@ typedef union { */ typedef union { struct { - /** cpuperiod_sel : HRO; bitpos: [1:0]; default: 1; - * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM - */ - uint32_t cpuperiod_sel:2; - /** pll_freq_sel : HRO; bitpos: [2]; default: 1; - * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM - */ - uint32_t pll_freq_sel:1; + uint32_t reserved_0:3; /** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1; * Set 1 to force cpu_waiti_clk enable. */ @@ -1821,12 +1822,12 @@ typedef union { typedef union { struct { /** 32k_sel : R/W; bitpos: [2:0]; default: 0; - * Configures the 32KHz clock for TIMER_GROUP.\\ - * 0 (default): RC32K_CLK\\ - * 1: XTAL32K_CLK\\ - * 2: OSC_SLOW_CLK\\ - * 3: RC_SLOW_CLK\\ - * 4: RC_FAST_CLK\\ + * Configures the 32KHz clock for TIMER_GROUP. + * 0 (default): RC32K_CLK + * 1: XTAL32K_CLK + * 2: OSC_SLOW_CLK + * 3: RC_SLOW_CLK + * 4: RC_FAST_CLK */ uint32_t clk_32k_sel:3; uint32_t reserved_3:5; @@ -1895,14 +1896,14 @@ typedef union { struct { /** sec_clk_sel : R/W; bitpos: [1:0]; default: 0; * Configures the clock source for the External Memory Encryption and Decryption - * module.\\ - * 0(default): XTAL_CLK\\ - * 1 RC_FAST_CLK\\ - * 2: PLL_F480M_CLK\\ + * module. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK */ uint32_t sec_clk_sel:2; /** sec_rst_en : R/W; bitpos: [2]; default: 0; - * Set 0 to reset sec module + * Set 1 to reset sec module */ uint32_t sec_rst_en:1; uint32_t reserved_3:29; @@ -1910,28 +1911,6 @@ typedef union { uint32_t val; } pcr_sec_conf_reg_t; -/** Type of adc_dac_inv_phase_conf register - * xxxx - */ -typedef union { - struct { - /** clk_rx_adc_inv_phase_ena : R/W; bitpos: [0]; default: 0; - * xxxx - */ - uint32_t clk_rx_adc_inv_phase_ena:1; - /** clk_tx_dac_inv_phase_ena : R/W; bitpos: [1]; default: 0; - * xxxx - */ - uint32_t clk_tx_dac_inv_phase_ena:1; - /** clk_pwdet_adc_inv_phase_ena : R/W; bitpos: [2]; default: 0; - * xxxx - */ - uint32_t clk_pwdet_adc_inv_phase_ena:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} pcr_adc_dac_inv_phase_conf_reg_t; - /** Type of bus_clk_update register * Configuration register for applying updated high-performance system clock sources */ @@ -1939,10 +1918,10 @@ typedef union { struct { /** bus_clock_update : R/W/WTC; bitpos: [0]; default: 0; * Configures whether or not to update configurations for CPU_CLK division, AHB_CLK - * division and HP_ROOT_CLK clock source selection.\\ - * 0: Not update configurations\\ - * 1: Update configurations\\ - * This bit is automatically cleared when configurations have been updated.\\ + * division and HP_ROOT_CLK clock source selection. + * 0: Not update configurations + * 1: Update configurations + * This bit is automatically cleared when configurations have been updated. */ uint32_t bus_clock_update:1; uint32_t reserved_1:31; @@ -1956,13 +1935,11 @@ typedef union { typedef union { struct { /** sar2_clk_div_num : R/W; bitpos: [7:0]; default: 4; - * Configures the divisor for SAR ADC 2 clock to generate ADC analog control - * signals.\\ + * Configures the divisor for SAR ADC 2 clock to generate ADC analog control signals. */ uint32_t sar2_clk_div_num:8; /** sar1_clk_div_num : R/W; bitpos: [15:8]; default: 4; - * Configures the divisor for SAR ADC 1 clock to generate ADC analog control - * signals.\\ + * Configures the divisor for SAR ADC 1 clock to generate ADC analog control signals. */ uint32_t sar1_clk_div_num:8; uint32_t reserved_16:16; @@ -1970,24 +1947,6 @@ typedef union { uint32_t val; } pcr_sar_clk_div_reg_t; -/** Type of pwdet_sar_clk_conf register - * xxxx - */ -typedef union { - struct { - /** pwdet_sar_clk_div_num : R/W; bitpos: [7:0]; default: 7; - * xxxx - */ - uint32_t pwdet_sar_clk_div_num:8; - /** pwdet_sar_clk_en : R/W; bitpos: [8]; default: 1; - * xxxx - */ - uint32_t pwdet_sar_clk_en:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} pcr_pwdet_sar_clk_conf_reg_t; - /** Type of bs_conf register * BS configuration register */ @@ -1998,7 +1957,7 @@ typedef union { */ uint32_t bs_clk_en:1; /** bs_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset bs module + * Set 1 to reset bs module */ uint32_t bs_rst_en:1; uint32_t reserved_2:30; @@ -2013,11 +1972,11 @@ typedef union { struct { uint32_t reserved_0:23; /** bs_tx_rst_en : R/W; bitpos: [23]; default: 0; - * Set 0 to reset bs tx module + * Set 1 to reset bs tx module */ uint32_t bs_tx_rst_en:1; /** bs_rx_rst_en : R/W; bitpos: [24]; default: 0; - * Set 0 to reset bs rx module + * Set 1 to reset bs rx module */ uint32_t bs_rx_rst_en:1; uint32_t reserved_25:7; @@ -2050,11 +2009,11 @@ typedef union { typedef union { struct { /** tg0_wdt_rst_en : R/W; bitpos: [0]; default: 0; - * Set 0 to reset timer_group0 wdt module + * Set 1 to reset timer_group0 wdt module */ uint32_t tg0_wdt_rst_en:1; /** tg1_wdt_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 wdt module + * Set 1 to reset timer_group1 wdt module */ uint32_t tg1_wdt_rst_en:1; uint32_t reserved_2:30; @@ -2068,11 +2027,11 @@ typedef union { typedef union { struct { /** tg0_xtal_rst_en : R/W; bitpos: [0]; default: 0; - * Set 0 to reset timer_group0 xtal clock domain + * Set 1 to reset timer_group0 xtal clock domain */ uint32_t tg0_xtal_rst_en:1; /** tg1_xtal_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 xtal clock domain + * Set 1 to reset timer_group1 xtal clock domain */ uint32_t tg1_xtal_rst_en:1; /** tg0_xtal_clk_en : R/W; bitpos: [2]; default: 1; @@ -2094,7 +2053,7 @@ typedef union { */ uint32_t km_clk_en:1; /** km_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset km module + * Set 1 to reset km module */ uint32_t km_rst_en:1; /** km_ready : RO; bitpos: [2]; default: 1; @@ -2135,7 +2094,7 @@ typedef union { */ uint32_t tcm_mem_monitor_clk_en:1; /** tcm_mem_monitor_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset tcm_mem_monitor module + * Set 1 to reset tcm_mem_monitor module */ uint32_t tcm_mem_monitor_rst_en:1; /** tcm_mem_monitor_ready : RO; bitpos: [2]; default: 1; @@ -2157,7 +2116,7 @@ typedef union { */ uint32_t psram_mem_monitor_clk_en:1; /** psram_mem_monitor_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset psram_mem_monitor module + * Set 1 to reset psram_mem_monitor module */ uint32_t psram_mem_monitor_rst_en:1; /** psram_mem_monitor_ready : RO; bitpos: [2]; default: 1; @@ -2212,6 +2171,24 @@ typedef union { uint32_t val; } pcr_hpcore_0_pd_ctrl_reg_t; +/** Type of sdio_slave_conf register + * SDIO_SLAVE configuration register + */ +typedef union { + struct { + /** sdio_slave_clk_en : R/W; bitpos: [0]; default: 0; + * Set 1 to enable sdio_slave clock + */ + uint32_t sdio_slave_clk_en:1; + /** sdio_slave_rst_en : R/W; bitpos: [1]; default: 0; + * Set 1 to reset sdio_slave module + */ + uint32_t sdio_slave_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_sdio_slave_conf_reg_t; + /** Type of clock_gate register * PCR clock gating configure register */ @@ -2268,7 +2245,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36774528; + /** date : R/W; bitpos: [27:0]; default: 2363425; * PCR version information. */ uint32_t date:28; @@ -2370,10 +2347,10 @@ typedef struct { volatile pcr_sram_power_conf_0_reg_t sram_power_conf_0; volatile pcr_sram_power_conf_1_reg_t sram_power_conf_1; volatile pcr_sec_conf_reg_t sec_conf; - volatile pcr_adc_dac_inv_phase_conf_reg_t adc_dac_inv_phase_conf; + uint32_t reserved_140; volatile pcr_bus_clk_update_reg_t bus_clk_update; volatile pcr_sar_clk_div_reg_t sar_clk_div; - volatile pcr_pwdet_sar_clk_conf_reg_t pwdet_sar_clk_conf; + uint32_t reserved_14c; volatile pcr_bs_conf_reg_t bs_conf; volatile pcr_bs_func_conf_reg_t bs_func_conf; volatile pcr_bs_pd_ctrl_reg_t bs_pd_ctrl; @@ -2385,7 +2362,8 @@ typedef struct { volatile pcr_psram_mem_monitor_conf_reg_t psram_mem_monitor_conf; volatile pcr_reset_event_bypass_reg_t reset_event_bypass; volatile pcr_hpcore_0_pd_ctrl_reg_t hpcore_0_pd_ctrl; - uint32_t reserved_17c[926]; + volatile pcr_sdio_slave_conf_reg_t sdio_slave_conf; + uint32_t reserved_180[925]; volatile pcr_fpga_debug_reg_t fpga_debug; volatile pcr_clock_gate_reg_t clock_gate; volatile pcr_date_reg_t date;