Merge branch 'feature/p4_eco5_real_chip' into 'master'

p4: p4 eco5 real chip

Closes IDF-13574 and IDF-13410

See merge request espressif/esp-idf!41396

Kconfig

@@ -123,8 +123,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
         bool
         default "y" if IDF_TARGET="esp32p4"
         select IDF_TARGET_ARCH_RISCV
-        select IDF_ENV_FPGA if ESP32P4_REV_MIN_200
-        select IDF_ENV_BRINGUP if ESP32P4_REV_MIN_200
 
     config IDF_TARGET_ESP32H2
         bool

components/bootloader/Kconfig.projbuild

@@ -43,7 +43,8 @@ menu "Bootloader config"
         int
         default 64 if IDF_TARGET_ESP32H2
         default 48 if IDF_TARGET_ESP32H21 || IDF_TARGET_ESP32H4
-        default 90 if IDF_TARGET_ESP32P4
+        default 90 if IDF_TARGET_ESP32P4 && ESP32P4_SELECTS_REV_LESS_V3
+        default 100 if IDF_TARGET_ESP32P4 && !ESP32P4_SELECTS_REV_LESS_V3
         default 80
         help
             The CPU clock frequency to be at least raised to in 2nd bootloader. Invisible for users.

components/bootloader/subproject/CMakeLists.txt

@@ -69,8 +69,8 @@ idf_build_set_property(__OUTPUT_SDKCONFIG 0)
 set(LD_DEFAULT_PATH "${CMAKE_CURRENT_SOURCE_DIR}/main/ld/${IDF_TARGET}")
 idf_build_set_property(BOOTLOADER_LINKER_SCRIPT "${LD_DEFAULT_PATH}/bootloader.rom.ld" APPEND)
 project(bootloader)
-if(CONFIG_ESP32P4_REV_MIN_200)
-    target_linker_script("__idf_main" INTERFACE "${LD_DEFAULT_PATH}/bootloader.rev2.ld")
+if(CONFIG_ESP32P4_REV_MIN_300)
+    target_linker_script("__idf_main" INTERFACE "${LD_DEFAULT_PATH}/bootloader.rev3.ld")
 else()
     target_linker_script("__idf_main" INTERFACE "${LD_DEFAULT_PATH}/bootloader.ld")
 endif()

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c

@@ -224,6 +224,7 @@ static void bootloader_spi_flash_resume(void)
 
 esp_err_t bootloader_init_spi_flash(void)
 {
+    bootloader_init_mspi_clock();
     bootloader_init_flash_configure();
 
 #if CONFIG_BOOTLOADER_FLASH_DC_AWARE

components/bootloader_support/src/esp_image_format.c

@@ -386,7 +386,7 @@ err:
 }
 
 #ifdef BOOTLOADER_BUILD
-#if CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V2
+#if CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 #define ROM_STACK_START         (SOC_ROM_STACK_START_REV2)
 #else
 #define ROM_STACK_START         (SOC_ROM_STACK_START)

components/esp_hw_support/Kconfig

@@ -255,7 +255,6 @@ menu "Hardware Settings"
     config ESP_BRINGUP_BYPASS_CPU_CLK_SETTING
         bool
         default y if !SOC_CLK_TREE_SUPPORTED
-        default y if ESP32P4_REV_MIN_200 # TODO: IDF-13574
         default n
         help
             This option is only used for new chip bringup, when
@@ -265,7 +264,6 @@ menu "Hardware Settings"
     config ESP_BRINGUP_BYPASS_RANDOM_SETTING
         bool
         default y if !SOC_RNG_SUPPORTED
-        default y if ESP32P4_REV_MIN_200 # TODO: IDF-13574
         default n
         help
             This option is only used for new chip bringup, when

components/esp_hw_support/port/esp32p4/Kconfig.hw_support

@@ -1,13 +1,14 @@
-comment "NOTE! Support of ESP32-P4 rev. <2.0 and >=2.0 is mutually exclusive"
+comment "NOTE! Support of ESP32-P4 rev. <3.0 and >=3.0 is mutually exclusive"
 comment "Read the help text of the option below for explanation"
 
-config ESP32P4_SELECTS_REV_LESS_V2
-    bool "Select ESP32-P4 revisions <2.0 (No >=2.x Support)"
+config ESP32P4_SELECTS_REV_LESS_V3
+    bool "Select ESP32-P4 revisions <3.0 (No >=3.x Support)"
     default y
     help
         Select this option to support ESP32-P4 revisions 0.x and 1.x.
-        Revision 2.0 and revisions less than 2.0 have huge hardware difference.
-        Revisions higher than 2.0 (included) is not compatible with 0.x and 1.x.
+        Revisions higher than 3.0 (included) and revisions less than 3.0
+        have huge hardware difference.
+        Revisions higher than 3.0 (included) is not compatible with 0.x and 1.x.
 
 choice ESP32P4_REV_MIN
     prompt "Minimum Supported ESP32-P4 Revision"
@@ -21,18 +22,18 @@ choice ESP32P4_REV_MIN
         this will also help to reduce binary size.
 
     config ESP32P4_REV_MIN_0
-        depends on ESP32P4_SELECTS_REV_LESS_V2
+        depends on ESP32P4_SELECTS_REV_LESS_V3
         bool "Rev v0.0"
     config ESP32P4_REV_MIN_1
-        depends on ESP32P4_SELECTS_REV_LESS_V2
+        depends on ESP32P4_SELECTS_REV_LESS_V3
         bool "Rev v0.1"
     config ESP32P4_REV_MIN_100
-        depends on ESP32P4_SELECTS_REV_LESS_V2
+        depends on ESP32P4_SELECTS_REV_LESS_V3
         bool "Rev v1.0"
-    config ESP32P4_REV_MIN_200
-        bool "Rev v2.0"
-        depends on !ESP32P4_SELECTS_REV_LESS_V2
-        select ESPTOOLPY_NO_STUB if (IDF_ENV_FPGA || IDF_ENV_BRINGUP)
+    config ESP32P4_REV_MIN_300
+        bool "Rev v3.0"
+        depends on !ESP32P4_SELECTS_REV_LESS_V3
+        select ESPTOOLPY_NO_STUB # TODO: IDF-13911
 endchoice
 
 config ESP32P4_REV_MIN_FULL
@@ -40,7 +41,7 @@ config ESP32P4_REV_MIN_FULL
     default 0 if ESP32P4_REV_MIN_0
     default 1 if ESP32P4_REV_MIN_1
     default 100 if ESP32P4_REV_MIN_100
-    default 0 if ESP32P4_REV_MIN_200  # TODO: IDF-13410. To be updated to 200 when chip efuse is burnt
+    default 300 if ESP32P4_REV_MIN_300
 
 config ESP_REV_MIN_FULL
     int
@@ -50,7 +51,10 @@ config ESP_REV_MIN_FULL
     # MAX Revision
     #
 
-    comment "Maximum Supported ESP32-P4 Revision (Rev v2.99)"
+    comment "Maximum Supported ESP32-P4 Revision (Rev v1.99)"
+    depends on ESP32P4_SELECTS_REV_LESS_V3
+    comment "Maximum Supported ESP32-P4 Revision (Rev v3.99)"
+    depends on !ESP32P4_SELECTS_REV_LESS_V3
     # Maximum revision that IDF supports.
     # It can not be changed by user.
     # Only Espressif can change it when a new version will be supported in IDF.
@@ -58,7 +62,8 @@ config ESP_REV_MIN_FULL
 
 config ESP32P4_REV_MAX_FULL
     int
-    default 199 #TODO: IDF-13574
+    default 399 if !ESP32P4_SELECTS_REV_LESS_V3
+    default 199 if ESP32P4_SELECTS_REV_LESS_V3
     # keep in sync the "Maximum Supported Revision" description with this value
 
 config ESP_REV_MAX_FULL
@@ -78,6 +83,6 @@ config ESP_EFUSE_BLOCK_REV_MIN_FULL
 
 config ESP_EFUSE_BLOCK_REV_MAX_FULL
     int
-    default 99
+    default 199
     comment "Maximum Supported ESP32-P4 eFuse Block Revision (eFuse Block Rev v0.99)"
     # The revision in the comment must correspond to the default value of ESP_EFUSE_BLOCK_REV_MAX_FULL

components/esp_hw_support/port/esp32p4/pmu_param.c

@@ -336,7 +336,7 @@ uint32_t get_act_hp_dbias(void)
     uint32_t hp_cali_dbias = HP_CALI_ACTIVE_DBIAS_DEFAULT;
     uint32_t blk_version = efuse_hal_blk_version();
     uint32_t hp_cali_dbias_efuse = 0;
-    if (blk_version >= 2) {
+    if (blk_version >= 2 && blk_version < 100) {
         hp_cali_dbias_efuse = efuse_ll_get_active_hp_dbias();
     }
     if (hp_cali_dbias_efuse > 0) {
@@ -357,7 +357,7 @@ uint32_t get_act_lp_dbias(void)
     uint32_t lp_cali_dbias = LP_CALI_ACTIVE_DBIAS_DEFAULT;
     uint32_t blk_version = efuse_hal_blk_version();
     uint32_t lp_cali_dbias_efuse = 0;
-    if (blk_version >= 2) {
+    if (blk_version >= 2 && blk_version < 100) {
         lp_cali_dbias_efuse = efuse_ll_get_active_lp_dbias();
     }
     if (lp_cali_dbias_efuse > 0) {

components/esp_hw_support/port/esp32p4/pmu_pvt.c

@@ -33,7 +33,7 @@ static uint8_t get_lp_hp_gap(void)
     int8_t lp_hp_gap = 0;
     uint32_t blk_version = efuse_hal_blk_version();
     uint8_t lp_hp_gap_efuse = 0;
-    if (blk_version >= 2) {
+    if (blk_version >= 2 && blk_version < 100) {
         lp_hp_gap_efuse = efuse_ll_get_dbias_vol_gap();
         bool gap_flag = lp_hp_gap_efuse >> 4;
         uint8_t gap_abs_value = lp_hp_gap_efuse & 0xf;
@@ -77,7 +77,7 @@ static uint32_t pvt_get_lp_dbias(void)
 void pvt_auto_dbias_init(void)
 {
     uint32_t blk_version = efuse_hal_blk_version();
-    if (blk_version >= 2) {
+    if (blk_version >= 2 && blk_version < 100) {
         SET_PERI_REG_MASK(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_160M_CLK_EN);
         SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN);
         /*config for dbias func*/
@@ -120,7 +120,7 @@ void pvt_auto_dbias_init(void)
 void pvt_func_enable(bool enable)
 {
     uint32_t blk_version = efuse_hal_blk_version();
-    if (blk_version >= 2){
+    if (blk_version >= 2 && blk_version < 100){
 
         if (enable) {
             SET_PERI_REG_MASK(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_160M_CLK_EN);

components/esp_hw_support/port/esp32p4/rtc_clk.c

@@ -224,6 +224,7 @@ static void rtc_clk_cpu_freq_to_cpll_mhz(int cpu_freq_mhz, hal_utils_clk_div_t *
     uint32_t mem_divider = 1;
     uint32_t sys_divider = 1; // We are not going to change this
     uint32_t apb_divider = 1;
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
     switch (cpu_freq_mhz) {
     case 360:
         mem_divider = 2;
@@ -244,6 +245,28 @@ static void rtc_clk_cpu_freq_to_cpll_mhz(int cpu_freq_mhz, hal_utils_clk_div_t *
         // To avoid such case, we will strictly do abort here.
         abort();
     }
+#else
+    switch (cpu_freq_mhz) {
+    case 400:
+        mem_divider = 2;
+        apb_divider = 2;
+        break;
+    case 200:
+        mem_divider = 1;
+        apb_divider = 2;
+        break;
+    case 100:
+        mem_divider = 1;
+        apb_divider = 1;
+        break;
+    default:
+        // Unsupported configuration
+        // This is dangerous to modify dividers. Hardware could automatically correct the divider, and it won't be
+        // reflected to the registers. Therefore, you won't even be able to calculate out the real mem_clk, apb_clk freq.
+        // To avoid such case, we will strictly do abort here.
+        abort();
+    }
+#endif
 
     // If it's upscaling, the divider of MEM/SYS/APB needs to be increased, to avoid illegal intermediate states,
     // the clock divider should be updated in the order from the APB_CLK to CPU_CLK.
@@ -289,6 +312,7 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
 
     // Keep default CPLL at 360MHz
     uint32_t xtal_freq = (uint32_t)rtc_clk_xtal_freq_get();
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
     if (freq_mhz <= xtal_freq && freq_mhz != 0) {
         divider.integer = xtal_freq / freq_mhz;
         real_freq_mhz = (xtal_freq + divider.integer / 2) / divider.integer; /* round */
@@ -296,7 +320,6 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
             // no suitable divider
             return false;
         }
-
         source_freq_mhz = xtal_freq;
         source = SOC_CPU_CLK_SRC_XTAL;
     } else if (freq_mhz == 90) {
@@ -314,6 +337,30 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
         source = SOC_CPU_CLK_SRC_CPLL;
         source_freq_mhz = CLK_LL_PLL_360M_FREQ_MHZ;
         divider.integer = 1;
+    } else {
+        // unsupported frequency
+        return false;
+    }
+#else
+    if (freq_mhz <= xtal_freq && freq_mhz != 0) {
+        divider.integer = xtal_freq / freq_mhz;
+        real_freq_mhz = (xtal_freq + divider.integer / 2) / divider.integer; /* round */
+        if (real_freq_mhz != freq_mhz) {
+            // no suitable divider
+            return false;
+        }
+        source_freq_mhz = xtal_freq;
+        source = SOC_CPU_CLK_SRC_XTAL;
+    } else if (freq_mhz == 100) {
+        real_freq_mhz = freq_mhz;
+        source = SOC_CPU_CLK_SRC_CPLL;
+        source_freq_mhz = CLK_LL_PLL_400M_FREQ_MHZ;
+        divider.integer = 4;
+    } else if (freq_mhz == 200) {
+        real_freq_mhz = freq_mhz;
+        source = SOC_CPU_CLK_SRC_CPLL;
+        source_freq_mhz = CLK_LL_PLL_400M_FREQ_MHZ;
+        divider.integer = 2;
     } else if (freq_mhz == 400) {
         // If CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ selects 400MHz, then at app startup stage will need a CPLL calibration to raise its freq from 360MHz to 400MHz
         real_freq_mhz = freq_mhz;
@@ -324,6 +371,7 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
         // unsupported frequency
         return false;
     }
+#endif
     *out_config = (rtc_cpu_freq_config_t) {
         .source = source,
         .div = divider,

components/esp_rom/CMakeLists.txt

@@ -102,7 +102,7 @@ if(target STREQUAL "linux")
     endif()
 else()
     # TODO: IDF-13410. Update to (CONFIG_ESP32P4_REV_MIN_FULL GREATER_EQUAL 200) when chip efuse is correct.
-    if(CONFIG_ESP32P4_REV_MIN_200)
+    if(CONFIG_ESP32P4_REV_MIN_300)
         target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.eco5.ld")
     elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
         target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.beta5.ld")
@@ -117,7 +117,7 @@ else()
     endif()
 
     if(CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB)
-        if(CONFIG_ESP32P4_REV_MIN_200) # TODO: IDF-13410
+        if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410
             rom_linker_script("eco5.libgcc")
         elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
             rom_linker_script("beta5.libgcc")
@@ -125,7 +125,7 @@ else()
             rom_linker_script("libgcc")
         endif()
     else()
-        if(CONFIG_ESP32P4_REV_MIN_200) # TODO: IDF-13410.
+        if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410.
             rom_linker_script("eco5.rvfp")
         else()
             rom_linker_script("rvfp")
@@ -192,7 +192,7 @@ if(BOOTLOADER_BUILD)
         if(target STREQUAL "esp32" OR target STREQUAL "esp32s2")
             rom_linker_script("libc-funcs")
         else()
-            if(CONFIG_ESP32P4_REV_MIN_200) # TODO: IDF-13410
+            if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410
                 rom_linker_script("eco5.libc")
             elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
                 rom_linker_script("beta5.libc")
@@ -204,7 +204,7 @@ if(BOOTLOADER_BUILD)
                 rom_linker_script("libc-suboptimal_for_misaligned_mem")
             endif()
             if(CONFIG_LIBC_NEWLIB)
-                if(CONFIG_ESP32P4_REV_MIN_200) # TODO: IDF-13410
+                if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410
                     rom_linker_script("eco5.newlib")
                 elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
                     rom_linker_script("beta5.newlib")
@@ -363,7 +363,7 @@ else() # Regular app build
 
     if(CONFIG_ESP_ROM_HAS_NEWLIB AND NOT target STREQUAL "esp32" AND NOT target STREQUAL "esp32s2")
         # ESP32 and S2 are a bit different, keep them as special cases in the target specific include section
-        if(CONFIG_ESP32P4_REV_MIN_200) # TODO: IDF-13410
+        if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410
             rom_linker_script("eco5.libc")
         elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
             rom_linker_script("beta5.libc")
@@ -374,7 +374,7 @@ else() # Regular app build
             rom_linker_script("libc-suboptimal_for_misaligned_mem")
         endif()
         if(CONFIG_LIBC_NEWLIB)
-            if(CONFIG_ESP32P4_REV_MIN_200) # TODO: IDF-13410
+            if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410
                 rom_linker_script("eco5.newlib")
             elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
                 rom_linker_script("beta5.newlib")

components/esp_system/CMakeLists.txt

@@ -152,7 +152,7 @@ if(NOT BOOTLOADER_BUILD)
 endif()
 
 # For P4, since P4 REV2, the SRAM is contiguous
-if(CONFIG_ESP32P4_SELECTS_REV_LESS_V2)
+if(CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
     target_link_options(${COMPONENT_LIB} INTERFACE "-Wl,--enable-non-contiguous-regions")
 endif()
 

components/esp_system/fpga_overrides_clk.c

@@ -55,7 +55,7 @@ void bootloader_clock_configure(void)
 void esp_rtc_init(void)
 {
 #if SOC_PMU_SUPPORTED
-#if CONFIG_ESP32P4_REV_MIN_200
+#if CONFIG_ESP32P4_REV_MIN_300
     //TODO: IDF-13453
     ESP_EARLY_LOGW(TAG, "pmu_init not supported\n");
 #else

components/esp_system/ld/esp32p4/memory.ld.in

@@ -15,7 +15,7 @@
 #include "sdkconfig.h"
 #include "ld.common"
 
-#if CONFIG_ESP32P4_REV_MIN_200
+#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 #define SRAM_START       0x4FF00000 + CONFIG_CACHE_L2_CACHE_SIZE
 #define SRAM_END         0x4FFAEFC0  /* 2nd stage bootloader iram_loader_seg start address */
 #define SRAM_SIZE        SRAM_END - SRAM_START
@@ -71,7 +71,7 @@ MEMORY
    * Shared data RAM, excluding memory reserved for ROM bss/data/stack.
    * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
    */
-#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
   sram_low (RWX) :                 org = SRAM_LOW_START, len = SRAM_LOW_SIZE
   sram_high (RW) :                org = SRAM_HIGH_START, len = SRAM_HIGH_SIZE
 #else

components/esp_system/ld/ld.cmake

@@ -48,8 +48,8 @@ preprocess_linker_file("memory.ld.in" "memory.ld" ld_out_path)
 target_linker_script(${COMPONENT_LIB} INTERFACE "${ld_out_path}")
 
 # Generate sections.ld.in and pass it through linker script generator
-if(CONFIG_ESP32P4_REV_MIN_200) # TODO: IDF-13410
-    preprocess_linker_file("sections.rev2.ld.in" "sections.ld.in" ld_out_path)
+if(CONFIG_ESP32P4_REV_MIN_300)
+    preprocess_linker_file("sections.rev3.ld.in" "sections.ld.in" ld_out_path)
 else()
     preprocess_linker_file("sections.ld.in" "sections.ld.in" ld_out_path)
 endif()

components/esp_system/port/cpu_start.c

@@ -124,13 +124,13 @@
 #include "esp_private/startup_internal.h"
 #include "esp_private/system_internal.h"
 
-#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 extern int _bss_start_low, _bss_start_high;
 extern int _bss_end_low, _bss_end_high;
 #else
 extern int _bss_start;
 extern int _bss_end;
-#endif // CONFIG_ESP32P4_SELECTS_REV_LESS_V2
+#endif // CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 extern int _rtc_bss_start;
 extern int _rtc_bss_end;
 #if CONFIG_BT_LE_RELEASE_IRAM_SUPPORTED
@@ -426,12 +426,12 @@ FORCE_INLINE_ATTR IRAM_ATTR void get_reset_reason(soc_reset_reason_t *rst_reas)
 
 FORCE_INLINE_ATTR IRAM_ATTR void init_bss(const soc_reset_reason_t *rst_reas)
 {
-#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
     memset(&_bss_start_low, 0, (uintptr_t)&_bss_end_low - (uintptr_t)&_bss_start_low);
     memset(&_bss_start_high, 0, (uintptr_t)&_bss_end_high - (uintptr_t)&_bss_start_high);
 #else
     memset(&_bss_start, 0, (uintptr_t)&_bss_end - (uintptr_t)&_bss_start);
-#endif // CONFIG_ESP32P4_SELECTS_REV_LESS_V2
+#endif // CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 
 #if CONFIG_BT_LE_RELEASE_IRAM_SUPPORTED
     // Clear Bluetooth bss

components/esp_system/port/soc/esp32p4/Kconfig.cpu

@@ -1,7 +1,8 @@
 choice ESP_DEFAULT_CPU_FREQ_MHZ
     prompt "CPU frequency"
     default ESP_DEFAULT_CPU_FREQ_MHZ_40 if IDF_ENV_FPGA || ESP_BRINGUP_BYPASS_CPU_CLK_SETTING
-    default ESP_DEFAULT_CPU_FREQ_MHZ_360
+    default ESP_DEFAULT_CPU_FREQ_MHZ_360 if ESP32P4_SELECTS_REV_LESS_V3
+    default ESP_DEFAULT_CPU_FREQ_MHZ_400
     help
         CPU frequency to be set on application startup.
 
@@ -10,9 +11,13 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ
         depends on IDF_ENV_FPGA || ESP_BRINGUP_BYPASS_CPU_CLK_SETTING
     config ESP_DEFAULT_CPU_FREQ_MHZ_360
         bool "360 MHz"
+        depends on ESP32P4_SELECTS_REV_LESS_V3
+    config ESP_DEFAULT_CPU_FREQ_MHZ_400
+        bool "400 MHz"
 endchoice
 
 config ESP_DEFAULT_CPU_FREQ_MHZ
     int
     default 40 if ESP_DEFAULT_CPU_FREQ_MHZ_40
     default 360 if ESP_DEFAULT_CPU_FREQ_MHZ_360
+    default 400 if ESP_DEFAULT_CPU_FREQ_MHZ_400

components/hal/esp32p4/include/hal/clk_tree_ll.h

@@ -771,6 +771,9 @@ static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_tar
     case CLK_CAL_LP_PLL:
         timg_cali_clk_sel = 11;
         break;
+    case CLK_CAL_DSI_DPHY:
+        timg_cali_clk_sel = 12;
+        break;
     default:
         // Unsupported CLK_CAL mux input
         abort();

components/heap/port/esp32p4/memory_layout.c

@@ -74,7 +74,7 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
 /**
  * Register the shared buffer area of the last memory block into the heap during heap initialization
  */
-#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 #define ROM_STACK_START         (SOC_ROM_STACK_START)
 #define APP_USABLE_DIRAM_END    (ROM_STACK_START - SOC_ROM_STACK_SIZE) // 0x4ff3cfc0 - 0x2000 = 0x4ff3afc0
 #define STARTUP_DATA_SIZE       (SOC_DRAM_HIGH - CONFIG_CACHE_L2_CACHE_SIZE - APP_USABLE_DIRAM_END) // 0x4ffc0000 - 0x20000/0x40000/0x80000 - 0x4ff3afc0 = 0x65040 / 0x45040 / 0x5040
@@ -108,7 +108,7 @@ const soc_memory_region_t soc_memory_regions[] = {
 
 const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
 
-#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 extern int _data_start_low, _data_start_high, _heap_start_low, _heap_start_high, _iram_start, _iram_end, _rtc_force_slow_end;
 #else
 extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end;
@@ -124,7 +124,7 @@ extern int _rtc_ulp_memory_start;
  */
 
 // Static data region. DRAM used by data+bss and possibly rodata
-#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start_low, (intptr_t)&_heap_start_low, dram_data_low);
 SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start_high, (intptr_t)&_heap_start_high, dram_data_high);
 #else

components/heap/port/memory_layout_utils.c

@@ -60,7 +60,7 @@ static void s_prepare_reserved_regions(soc_reserved_region_t *reserved, size_t c
     /* Get the ROM layout to find which part of DRAM is reserved */
     const ets_rom_layout_t *layout = ets_rom_layout_p;
     reserved[0].start = (intptr_t)layout->dram0_rtos_reserved_start;
-#if SOC_DIRAM_ROM_RESERVE_HIGH && CONFIG_ESP32P4_SELECTS_REV_LESS_V2
+#if SOC_DIRAM_ROM_RESERVE_HIGH && CONFIG_ESP32P4_SELECTS_REV_LESS_V3
     reserved[0].end = SOC_DIRAM_ROM_RESERVE_HIGH;
 #else
     reserved[0].end = SOC_DIRAM_DRAM_HIGH;

components/riscv/include/esp_private/interrupt_clic.h

@@ -47,7 +47,7 @@ extern "C" {
 #define UTVT_CSR    0x007
 
 
-#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V2
+#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 
 /**
  * The ESP32-P4 and the beta version of the ESP32-C5 implement a non-standard version of the CLIC:
@@ -57,7 +57,7 @@ extern "C" {
 #define INTTHRESH_STANDARD  0
 #define MINTSTATUS_CSR      0x346
 
-#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H4 || !CONFIG_ESP32P4_SELECTS_REV_LESS_V2
+#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H4 || !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 
 /* The ESP32-C5 (MP), C61, H4 and P4 (since REV2) use the standard CLIC specification, for example, it defines the mintthresh CSR */
 #define INTTHRESH_STANDARD  1

components/soc/CMakeLists.txt

@@ -35,10 +35,10 @@ endif()
 
 # register headers that generated by script from CSV
 if(CONFIG_IDF_TARGET_ESP32P4)
-    if(CONFIG_ESP32P4_SELECTS_REV_LESS_V2)
+    if(CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
         list(APPEND includes "${target_folder}/register/hw_ver1")
     else()
-        list(APPEND includes "${target_folder}/register/hw_ver2")
+        list(APPEND includes "${target_folder}/register/hw_ver3")
     endif()
 elseif(CONFIG_IDF_TARGET_ESP32H21) # TODO: ESP32H21 IDF-13923
     list(APPEND includes "${target_folder}/register")

components/soc/esp32p4/include/soc/clk_tree_defs.h

@@ -801,6 +801,7 @@ typedef enum {
     CLK_CAL_RC32K,                                   /*!< Select to calculate frequency of RC32K_CLK */
     CLK_CAL_32K_XTAL,                                /*!< Select to calculate frequency of XTAL32K_CLK */
     CLK_CAL_LP_PLL,                                  /*!< Select to calculate frequency of LP_PLL_CLK */
+    CLK_CAL_DSI_DPHY,                                /*!< Select to calculate frequency of DSI_DPHY_lanebyteclk */
 } soc_clk_freq_calculation_src_t;
 
 #ifdef __cplusplus