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mcpwm: fix wrong meta information

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This commit is contained in:
morris
2021-01-07 17:31:18 +08:00
parent b92c290e56
commit 6dc7f95342
13 changed files with 326 additions and 376 deletions
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components/soc/esp32s3/include/soc/mcpwm_reg.h
+2
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@@ -19,6 +19,8 @@ extern "C" {
#include "soc.h"
#define REG_MCPWM_BASE(i) (DR_REG_PWM0_BASE + i * (0xE000))
#define MCPWM_CLK_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0000)
/* MCPWM_CLK_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
components/soc/esp32s3/include/soc/mcpwm_struct.h
+5 -4
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@@ -13,13 +13,13 @@
// limitations under the License.
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
typedef volatile struct {
typedef volatile struct mcpwm_dev_s {
union {
struct {
uint32_t prescale: 8;
@@ -50,7 +50,8 @@ typedef volatile struct {
uint32_t in_en: 1;
uint32_t sync_sw: 1; /*write the negate value will trigger a sw sync*/
uint32_t out_sel: 2;
uint32_t timer_phase: 17;
uint32_t timer_phase: 16;
uint32_t phase_direct : 1;
uint32_t reserved21: 11;
};
uint32_t val;
components/soc/esp32s3/include/soc/periph_defs.h
+2 -7
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@@ -32,8 +32,6 @@ typedef enum {
PERIPH_TIMG1_MODULE,
PERIPH_PWM0_MODULE,
PERIPH_PWM1_MODULE,
PERIPH_PWM2_MODULE,
PERIPH_PWM3_MODULE,
PERIPH_UHCI0_MODULE,
PERIPH_UHCI1_MODULE,
PERIPH_RMT_MODULE,
@@ -93,11 +91,8 @@ typedef enum {
ETS_UART2_INTR_SOURCE, /**< interrupt of UART2, level*/
ETS_SDIO_HOST_INTR_SOURCE, /**< interrupt of SD/SDIO/MMC HOST, level*/
ETS_PWM0_INTR_SOURCE, /**< interrupt of PWM0, level, Reserved*/
ETS_PWM1_INTR_SOURCE = 32, /**< interrupt of PWM1, level, Reserved*/
ETS_PWM2_INTR_SOURCE, /**< interrupt of PWM2, level*/
ETS_PWM3_INTR_SOURCE, /**< interruot of PWM3, level*/
ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/
ETS_PWM1_INTR_SOURCE, /**< interrupt of PWM1, level, Reserved*/
ETS_LEDC_INTR_SOURCE = 35, /**< interrupt of LED PWM, level*/
ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/
ETS_TWAI_INTR_SOURCE, /**< interrupt of can, level*/
ETS_USB_INTR_SOURCE, /**< interrupt of USB, level*/
components/soc/esp32s3/include/soc/soc.h
+1 -3
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@@ -74,7 +74,7 @@
#define DR_REG_EFUSE_BASE 0x6001A000
#define DR_REG_NRX_BASE 0x6001CC00
#define DR_REG_BB_BASE 0x6001D000
#define DR_REG_PWM_BASE 0x6001E000
#define DR_REG_PWM0_BASE 0x6001E000
#define DR_REG_TIMERGROUP0_BASE 0x6001F000
#define DR_REG_TIMERGROUP1_BASE 0x60020000
#define DR_REG_RTC_SLOWMEM_BASE 0x60021000
@@ -89,8 +89,6 @@
#define DR_REG_PWM1_BASE 0x6002C000
#define DR_REG_I2S1_BASE 0x6002D000
#define DR_REG_UART2_BASE 0x6002E000
#define DR_REG_PWM2_BASE 0x6002F000
#define DR_REG_PWM3_BASE 0x60030000
#define DR_REG_SPI4_BASE 0x60037000
#define DR_REG_USB_WRAP_BASE 0x60039000
#define DR_REG_APB_SARADC_BASE 0x60040000