mirror of
https://github.com/espressif/esp-idf.git
synced 2026-05-05 12:25:03 +02:00
Merge branch 'feature/logging' into 'master'
Add logging library Logging library, intended to be used across other components. Uses design similar to Android NDK logging APIs and allows for both compile time and run time filters, similar to logcat. Also includes cleanup of cpu_startup.c — i was changing some logging output in this file so decided to re-format it and reduce code duplication. Ref TW6703 See merge request !68
This commit is contained in:
Ivan Grokhotkov
+96
-158
@@ -20,8 +20,10 @@
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#include "rom/ets_sys.h"
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#include "rom/uart.h"
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#include "soc/cpu.h"
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#include "soc/dport_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/rtc_cntl_reg.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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@@ -39,194 +41,130 @@
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#include "esp_event.h"
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#include "esp_spi_flash.h"
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#include "esp_ipc.h"
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#include "esp_log.h"
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static void IRAM_ATTR user_start_cpu0(void);
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static void IRAM_ATTR call_user_start_cpu1();
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static void IRAM_ATTR user_start_cpu1(void);
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void Cache_Read_Enable();
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extern void ets_setup_syscalls(void);
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extern esp_err_t app_main(void *ctx);
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extern int __cpu1_entry_point;
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extern int _bss_start;
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extern int _bss_end;
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extern int _init_start;
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extern int _init_end;
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extern int _iram_romjumptable_start;
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extern int _iram_romjumptable_end;
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extern int _iram_text_start;
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extern int _iram_text_end;
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/*
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We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
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flash cache is down and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
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*/
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static bool app_cpu_started = false;
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void IRAM_ATTR call_user_start_cpu0() {
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//Kill wdt
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REG_CLR_BIT(0x3ff4808c, BIT(10)); //RTCCNTL+8C RTC_WDTCONFIG0 RTC_
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REG_CLR_BIT(0x6001f048, BIT(14)); //DR_REG_BB_BASE+48
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//Move exception vectors to IRAM
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asm volatile (\
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"wsr %0, vecbase\n" \
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::"r"(&_init_start));
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uartAttach();
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ets_install_uart_printf();
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//Make page 0 access raise an exception
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//Also some other unused pages so we can catch weirdness
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//ToDo: this but nicer.
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asm volatile (\
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"movi a4,0x00000000\n" \
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"movi a5,0xf\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0x80000000\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0xa0000000\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0xc0000000\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0xe0000000\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0x20000000\n" \
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"movi a5,0x0\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0x40000000\n" \
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"movi a5,0x2\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"isync\n" \
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:::"a4","a5");
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memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
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//Initialize heap allocator
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heap_alloc_caps_init();
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ets_printf("Pro cpu up.\n");
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#ifndef CONFIG_FREERTOS_UNICORE
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ets_printf("Starting app cpu, entry point is %p\n", call_user_start_cpu1);
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SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
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CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
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SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
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CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
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ets_set_appcpu_boot_addr((uint32_t)call_user_start_cpu1);
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while (!app_cpu_started) {
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ets_delay_us(100);
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}
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#else
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CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
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#endif
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ets_printf("Pro cpu start user code\n");
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user_start_cpu0();
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}
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extern int _init_start;
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void IRAM_ATTR call_user_start_cpu1() {
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asm volatile (\
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"wsr %0, vecbase\n" \
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::"r"(&_init_start));
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//Make page 0 access raise an exception
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//Also some other unused pages so we can catch weirdness
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//ToDo: this but nicer.
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asm volatile (\
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"movi a4,0x00000000\n" \
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"movi a5,0xf\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0x80000000\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0xa0000000\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0xc0000000\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0xe0000000\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0x20000000\n" \
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"movi a5,0x0\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0x40000000\n" \
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"movi a5,0x2\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"isync\n" \
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:::"a4","a5");
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ets_printf("App cpu up.\n");
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app_cpu_started = 1;
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user_start_cpu1();
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}
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extern volatile int port_xSchedulerRunning[2];
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void IRAM_ATTR user_start_cpu1(void) {
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// Wait for FreeRTOS initialization to finish on PRO CPU
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while (port_xSchedulerRunning[0] == 0) {
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;
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}
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ets_printf("Starting scheduler on APP CPU.\n");
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xPortStartScheduler();
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}
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extern void (*__init_array_start)(void);
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extern void (*__init_array_end)(void);
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extern volatile int port_xSchedulerRunning[2];
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static void do_global_ctors(void) {
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void (**p)(void);
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for(p = &__init_array_start; p != &__init_array_end; ++p)
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(*p)();
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static const char* TAG = "cpu_start";
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static bool app_cpu_started = false;
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/*
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* We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
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* and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
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*/
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void IRAM_ATTR call_user_start_cpu0()
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{
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//Kill wdt
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REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN);
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REG_CLR_BIT(0x6001f048, BIT(14)); //DR_REG_BB_BASE+48
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cpu_configure_region_protection();
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//Move exception vectors to IRAM
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asm volatile (\
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"wsr %0, vecbase\n" \
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::"r"(&_init_start));
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uartAttach();
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ets_install_uart_printf();
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memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
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// Initialize heap allocator
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heap_alloc_caps_init();
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ESP_EARLY_LOGI(TAG, "Pro cpu up.");
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#ifndef CONFIG_FREERTOS_UNICORE
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ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_user_start_cpu1);
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SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
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CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
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SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
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CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
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ets_set_appcpu_boot_addr((uint32_t)call_user_start_cpu1);
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while (!app_cpu_started) {
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ets_delay_us(100);
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}
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#else
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ESP_EARLY_LOGI(TAG, "Single core mode");
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CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
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#endif
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ESP_EARLY_LOGI(TAG, "Pro cpu start user code");
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user_start_cpu0();
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}
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extern esp_err_t app_main(void *ctx);
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void user_start_cpu0(void) {
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ets_setup_syscalls();
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do_global_ctors();
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esp_ipc_init();
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spi_flash_init();
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void IRAM_ATTR call_user_start_cpu1()
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{
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asm volatile (\
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"wsr %0, vecbase\n" \
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::"r"(&_init_start));
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cpu_configure_region_protection();
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ESP_EARLY_LOGI(TAG, "App cpu up.");
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app_cpu_started = 1;
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user_start_cpu1();
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}
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void IRAM_ATTR user_start_cpu1(void)
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{
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// Wait for FreeRTOS initialization to finish on PRO CPU
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while (port_xSchedulerRunning[0] == 0) {
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;
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}
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ESP_LOGI(TAG, "Starting scheduler on APP CPU.");
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xPortStartScheduler();
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}
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static void do_global_ctors(void)
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{
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void (**p)(void);
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for (p = &__init_array_start; p != &__init_array_end; ++p) {
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(*p)();
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}
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}
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void user_start_cpu0(void)
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{
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ets_setup_syscalls();
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do_global_ctors();
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esp_ipc_init();
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spi_flash_init();
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#if CONFIG_WIFI_ENABLED
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esp_err_t ret = nvs_flash_init(5, 3);
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if (ret != ESP_OK) {
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printf("nvs_flash_init failed, ret=%d\n", ret);
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ESP_LOGE(TAG, "nvs_flash_init failed, ret=%d", ret);
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}
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system_init();
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esp_event_init(NULL, NULL);
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tcpip_adapter_init();
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#endif
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#if CONFIG_WIFI_ENABLED && CONFIG_WIFI_AUTO_STARTUP
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#include "esp_wifi.h"
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esp_wifi_startup(app_main, NULL);
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esp_wifi_startup(app_main, NULL);
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#else
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app_main(NULL);
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app_main(NULL);
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#endif
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ets_printf("Starting scheduler on PRO CPU.\n");
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vTaskStartScheduler();
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ESP_LOGI(TAG, "Starting scheduler on PRO CPU.");
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vTaskStartScheduler();
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}
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@@ -17,6 +17,9 @@
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#include "heap_alloc_caps.h"
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#include "spiram.h"
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#include "esp_log.h"
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static const char* TAG = "heap_alloc_caps";
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/*
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This file, combined with a region allocator that supports tags, solves the problem that the ESP32 has RAM that's
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@@ -147,7 +150,7 @@ static void disable_mem_region(void *from, void *to) {
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regions[i].xSizeInBytes-=(uint8_t *)regEnd-(uint8_t *)from;
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} else if (regStart<from && regEnd>to) {
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//Range punches a hole in the region! We do not support this.
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ets_printf("%s: region %d: hole punching is not supported!\n", i);
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ESP_EARLY_LOGE(TAG, "region %d: hole punching is not supported!", i);
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regions[i].xTag=-1; //Just disable memory region. That'll teach them!
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}
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}
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@@ -204,12 +207,13 @@ void heap_alloc_caps_init() {
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}
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}
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#if 1 //Change to 1 to show the regions the heap allocator is initialized with.
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ets_printf("Initializing heap allocator:\n");
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ESP_EARLY_LOGI(TAG, "Initializing heap allocator:");
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for (i=0; regions[i].xSizeInBytes!=0; i++) {
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if ( regions[i].xTag != -1 ) ets_printf("Region %02d: %08X len %08X tag %d\n", i, (int)regions[i].pucStartAddress, regions[i].xSizeInBytes, regions[i].xTag);
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if (regions[i].xTag != -1) {
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ESP_EARLY_LOGI(TAG, "Region %02d: %08X len %08X tag %d", i,
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(int)regions[i].pucStartAddress, regions[i].xSizeInBytes, regions[i].xTag);
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}
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}
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#endif
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//Initialize the malloc implementation.
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vPortDefineHeapRegionsTagged( regions );
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}
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@@ -33,4 +33,39 @@ static inline bool cpu_in_interrupt_context(void)
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return (ps & PS_UM) == 0;
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}
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/* Functions to set page attributes for Region Protection option in the CPU.
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* See Xtensa ISA Reference manual for explanation of arguments (section 4.6.3.2).
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*/
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static inline void cpu_write_dtlb(uint32_t vpn, unsigned attr)
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{
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asm volatile ("wdtlb %1, %0; dsync\n" :: "r" (vpn), "r" (attr));
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}
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static inline void cpu_write_itlb(unsigned vpn, unsigned attr)
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{
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asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr));
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}
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/* Make page 0 access raise an exception.
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* Also protect some other unused pages so we can catch weirdness.
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* Useful attribute values:
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* 0 — cached, RW
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* 2 — bypass cache, RWX (default value after CPU reset)
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* 15 — no access, raise exception
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*/
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static inline void cpu_configure_region_protection()
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{
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const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000};
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for (int i = 0; i < sizeof(pages_to_protect)/sizeof(pages_to_protect[0]); ++i) {
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cpu_write_dtlb(pages_to_protect[i], 0xf);
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cpu_write_itlb(pages_to_protect[i], 0xf);
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}
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cpu_write_dtlb(0x20000000, 0);
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cpu_write_itlb(0x20000000, 0);
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}
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#endif
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