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Merge branch 'fix/fix_submode_assert_in_slowck_changed_ota' into 'master'

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fix(esp_hw_support): fix assert when changing 8MD256 RTC slow clock source during OTA

Closes PM-478

See merge request espressif/esp-idf!40292
This commit is contained in:
Wu Zheng Hui
2025-07-22 11:33:32 +08:00
parent b1d190826c d7e1a747a6
commit 6f8dbe8a89
3 changed files with 25 additions and 16 deletions
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33
components/esp_hw_support/sleep_modes.c
View File

@@ -2463,6 +2463,20 @@ esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain, esp_sleep_pd_option_
return ESP_OK; return ESP_OK;
} }
static const char* s_submode2str[] = {
[ESP_SLEEP_RTC_USE_RC_FAST_MODE] = "ESP_SLEEP_RTC_USE_RC_FAST_MODE",
[ESP_SLEEP_DIG_USE_RC_FAST_MODE] = "ESP_SLEEP_DIG_USE_RC_FAST_MODE",
[ESP_SLEEP_USE_ADC_TSEN_MONITOR_MODE] = "ESP_SLEEP_USE_ADC_TSEN_MONITOR_MODE",
[ESP_SLEEP_ULTRA_LOW_MODE] = "ESP_SLEEP_ULTRA_LOW_MODE",
[ESP_SLEEP_RTC_FAST_USE_XTAL_MODE] = "ESP_SLEEP_RTC_FAST_USE_XTAL_MODE",
[ESP_SLEEP_DIG_USE_XTAL_MODE] = "ESP_SLEEP_DIG_USE_XTAL_MODE",
[ESP_SLEEP_LP_USE_XTAL_MODE] = "ESP_SLEEP_LP_USE_XTAL_MODE",
[ESP_SLEEP_VBAT_POWER_DEEPSLEEP_MODE] = "ESP_SLEEP_VBAT_POWER_DEEPSLEEP_MODE",
#if CONFIG_IDF_TARGET_ESP32
[ESP_SLEEP_ANALOG_LOW_POWER_MODE] = "ESP_SLEEP_ANALOG_LOW_POWER_MODE",
#endif
};
esp_err_t esp_sleep_sub_mode_config(esp_sleep_sub_mode_t mode, bool activate) esp_err_t esp_sleep_sub_mode_config(esp_sleep_sub_mode_t mode, bool activate)
{ {
if (mode >= ESP_SLEEP_MODE_MAX) { if (mode >= ESP_SLEEP_MODE_MAX) {
@@ -2475,7 +2489,10 @@ esp_err_t esp_sleep_sub_mode_config(esp_sleep_sub_mode_t mode, bool activate)
} else { } else {
s_sleep_sub_mode_ref_cnt[mode]--; s_sleep_sub_mode_ref_cnt[mode]--;
} }
assert(s_sleep_sub_mode_ref_cnt[mode] >= 0); if (s_sleep_sub_mode_ref_cnt[mode] < 0) {
ESP_EARLY_LOGW(TAG, "%s disabled multiple times!! (If this log appears only once after OTA upgrade, it can be ignored.)", s_submode2str[mode]);
s_sleep_sub_mode_ref_cnt[mode] = 0;
}
esp_os_exit_critical_safe(&s_config.lock); esp_os_exit_critical_safe(&s_config.lock);
return ESP_OK; return ESP_OK;
} }
@@ -2496,19 +2513,7 @@ int32_t* esp_sleep_sub_mode_dump_config(FILE *stream) {
if (stream) { if (stream) {
for (uint32_t mode = 0; mode < ESP_SLEEP_MODE_MAX; mode++) { for (uint32_t mode = 0; mode < ESP_SLEEP_MODE_MAX; mode++) {
fprintf(stream, LOG_COLOR_I "%s : %s (cnt = %" PRId32 ")\n" LOG_RESET_COLOR, fprintf(stream, LOG_COLOR_I "%s : %s (cnt = %" PRId32 ")\n" LOG_RESET_COLOR,
(const char*[]){ s_submode2str[mode],
[ESP_SLEEP_RTC_USE_RC_FAST_MODE] = "ESP_SLEEP_RTC_USE_RC_FAST_MODE",
[ESP_SLEEP_DIG_USE_RC_FAST_MODE] = "ESP_SLEEP_DIG_USE_RC_FAST_MODE",
[ESP_SLEEP_USE_ADC_TSEN_MONITOR_MODE] = "ESP_SLEEP_USE_ADC_TSEN_MONITOR_MODE",
[ESP_SLEEP_ULTRA_LOW_MODE] = "ESP_SLEEP_ULTRA_LOW_MODE",
[ESP_SLEEP_RTC_FAST_USE_XTAL_MODE] = "ESP_SLEEP_RTC_FAST_USE_XTAL_MODE",
[ESP_SLEEP_DIG_USE_XTAL_MODE] = "ESP_SLEEP_DIG_USE_XTAL_MODE",
[ESP_SLEEP_LP_USE_XTAL_MODE] = "ESP_SLEEP_LP_USE_XTAL_MODE",
[ESP_SLEEP_VBAT_POWER_DEEPSLEEP_MODE] = "ESP_SLEEP_VBAT_POWER_DEEPSLEEP_MODE",
#if CONFIG_IDF_TARGET_ESP32
[ESP_SLEEP_ANALOG_LOW_POWER_MODE] = "ESP_SLEEP_ANALOG_LOW_POWER_MODE",
#endif
}[mode],
s_sleep_sub_mode_ref_cnt[mode] ? "ENABLED" : "DISABLED", s_sleep_sub_mode_ref_cnt[mode] ? "ENABLED" : "DISABLED",
s_sleep_sub_mode_ref_cnt[mode]); s_sleep_sub_mode_ref_cnt[mode]);
} }

4
components/esp_system/port/soc/esp32c5/clk.c
View File

@@ -96,7 +96,9 @@ __attribute__((weak)) void esp_clk_init(void)
rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST); rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
#elif CONFIG_RTC_FAST_CLK_SRC_XTAL #elif CONFIG_RTC_FAST_CLK_SRC_XTAL
rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_XTAL); rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_XTAL);
esp_sleep_sub_mode_config(ESP_SLEEP_RTC_FAST_USE_XTAL_MODE, true); if (esp_sleep_sub_mode_dump_config(NULL)[ESP_SLEEP_RTC_FAST_USE_XTAL_MODE] == 0) {
esp_sleep_sub_mode_config(ESP_SLEEP_RTC_FAST_USE_XTAL_MODE, true);
}
#else #else
#error "No RTC fast clock source configured" #error "No RTC fast clock source configured"
#endif #endif

4
components/esp_system/port/soc/esp32p4/clk.c
View File

@@ -95,7 +95,9 @@ __attribute__((weak)) void esp_clk_init(void)
rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST); rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
#elif CONFIG_RTC_FAST_CLK_SRC_XTAL #elif CONFIG_RTC_FAST_CLK_SRC_XTAL
rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_XTAL); rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_XTAL);
esp_sleep_sub_mode_config(ESP_SLEEP_RTC_FAST_USE_XTAL_MODE, true); if (esp_sleep_sub_mode_dump_config(NULL)[ESP_SLEEP_RTC_FAST_USE_XTAL_MODE] == 0) {
esp_sleep_sub_mode_config(ESP_SLEEP_RTC_FAST_USE_XTAL_MODE, true);
}
#else #else
#error "No RTC fast clock source configured" #error "No RTC fast clock source configured"
#endif #endif