diff --git a/components/hal/esp32c2/include/hal/uart_ll.h b/components/hal/esp32c2/include/hal/uart_ll.h index eb6752f2d1..5500ddd10b 100644 --- a/components/hal/esp32c2/include/hal/uart_ll.h +++ b/components/hal/esp32c2/include/hal/uart_ll.h @@ -11,6 +11,8 @@ #pragma once #include "hal/uart_types.h" #include "soc/uart_periph.h" +#include "hal/clk_tree_ll.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { @@ -59,7 +61,7 @@ typedef enum { * * @return None. */ -static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) +FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) { hw->clk_conf.rst_core = core_rst_en; } @@ -71,7 +73,7 @@ static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) * * @return None. */ -static inline void uart_ll_sclk_enable(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw) { hw->clk_conf.sclk_en = 1; hw->clk_conf.rx_sclk_en = 1; @@ -85,7 +87,7 @@ static inline void uart_ll_sclk_enable(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_sclk_disable(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw) { hw->clk_conf.sclk_en = 0; hw->clk_conf.rx_sclk_en = 0; @@ -101,7 +103,7 @@ static inline void uart_ll_sclk_disable(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk) +FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk) { switch (source_clk) { default: @@ -125,7 +127,7 @@ static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk) * * @return None. */ -static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk) +FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk) { switch (hw->clk_conf.sclk_sel) { default: @@ -150,7 +152,7 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk) * * @return None */ -static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { #define DIV_UP(a, b) (((a) + (b) - 1) / (b)) const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits @@ -173,7 +175,7 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t * * @return The current baudrate */ -static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) +FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) { typeof(hw->clk_div) div_reg = hw->clk_div; return ((sclk_freq << 4)) / (((div_reg.div_int << 4) | div_reg.div_frag) * (hw->clk_conf.sclk_div_num + 1)); @@ -187,7 +189,7 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) * * @return None */ -static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask) +FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask) { hw->int_ena.val |= mask; } @@ -200,7 +202,7 @@ static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask) * * @return None */ -static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask) +FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask) { hw->int_ena.val &= (~mask); } @@ -212,7 +214,7 @@ static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask) * * @return The UART interrupt status. */ -static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) { return hw->int_st.val; } @@ -225,7 +227,7 @@ static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) * * @return None */ -static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask) +FORCE_INLINE_ATTR void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask) { hw->int_clr.val = mask; } @@ -237,7 +239,7 @@ static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask) * * @return interrupt enable value */ -static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) { return hw->int_ena.val; } @@ -251,7 +253,7 @@ static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) +FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) { for (int i = 0; i < (int)rd_len; i++) { buf[i] = hw->ahb_fifo.rw_byte; @@ -267,7 +269,7 @@ static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd * * @return None */ -static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len) +FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len) { for (int i = 0; i < (int)wr_len; i++) { hw->ahb_fifo.rw_byte = buf[i]; @@ -281,7 +283,7 @@ static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint * * @return None */ -static inline void uart_ll_rxfifo_rst(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw) { hw->conf0.rxfifo_rst = 1; hw->conf0.rxfifo_rst = 0; @@ -294,7 +296,7 @@ static inline void uart_ll_rxfifo_rst(uart_dev_t *hw) * * @return None */ -static inline void uart_ll_txfifo_rst(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw) { hw->conf0.txfifo_rst = 1; hw->conf0.txfifo_rst = 0; @@ -307,7 +309,7 @@ static inline void uart_ll_txfifo_rst(uart_dev_t *hw) * * @return The readable data length in rxfifo. */ -static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) { return hw->status.rxfifo_cnt; } @@ -319,7 +321,7 @@ static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) * * @return The data length of txfifo can be written. */ -static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) { return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt; } @@ -332,7 +334,7 @@ static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit) +FORCE_INLINE_ATTR void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit) { hw->conf0.stop_bit_num = stop_bit; } @@ -345,7 +347,7 @@ static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_b * * @return None. */ -static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit) +FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit) { *stop_bit = hw->conf0.stop_bit_num; } @@ -358,7 +360,7 @@ static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_ * * @return None. */ -static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode) +FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode) { if (parity_mode != UART_PARITY_DISABLE) { hw->conf0.parity = parity_mode & 0x1; @@ -374,7 +376,7 @@ static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode) * * @return None. */ -static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode) +FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode) { if (hw->conf0.parity_en) { *parity_mode = 0X2 | hw->conf0.parity; @@ -392,7 +394,7 @@ static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode * * @return None. */ -static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd) +FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd) { hw->conf1.rxfifo_full_thrhd = full_thrhd; } @@ -406,7 +408,7 @@ static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thr * * @return None. */ -static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd) +FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd) { hw->conf1.txfifo_empty_thrhd = empty_thrhd; } @@ -420,7 +422,7 @@ static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_t * * @return None. */ -static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr) +FORCE_INLINE_ATTR void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr) { hw->idle_conf.rx_idle_thrhd = rx_idle_thr; } @@ -433,7 +435,7 @@ static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr) * * @return None. */ -static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num) +FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num) { hw->idle_conf.tx_idle_num = idle_num; } @@ -446,7 +448,7 @@ static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num) * * @return None. */ -static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) +FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) { if (break_num > 0) { hw->txbrk_conf.tx_brk_num = break_num; @@ -465,7 +467,7 @@ static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) * * @return None. */ -static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs) +FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs) { //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set. if (flow_ctrl & UART_HW_FLOWCTRL_RTS) { @@ -489,7 +491,7 @@ static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_ * * @return None. */ -static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl) +FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl) { *flow_ctrl = UART_HW_FLOWCTRL_DISABLE; if (hw->conf1.rx_flow_en) { @@ -509,7 +511,7 @@ static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_ * * @return None. */ -static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en) +FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en) { if (sw_flow_ctrl_en) { hw->flow_conf.xonoff_del = 1; @@ -537,7 +539,7 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t * * * @return None. */ -static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char) +FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char) { hw->at_cmd_char.data = cmd_char->cmd_char; hw->at_cmd_char.char_num = cmd_char->char_num; @@ -554,7 +556,7 @@ static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_ch * * @return None. */ -static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit) +FORCE_INLINE_ATTR void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit) { hw->conf0.bit_num = data_bit; } @@ -567,7 +569,7 @@ static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t d * * @return None. */ -static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level) +FORCE_INLINE_ATTR void uart_ll_set_rts_active_level(uart_dev_t *hw, int level) { hw->conf0.sw_rts = level & 0x1; } @@ -580,7 +582,7 @@ static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level) * * @return None. */ -static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level) +FORCE_INLINE_ATTR void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level) { hw->conf0.sw_dtr = level & 0x1; } @@ -594,7 +596,7 @@ static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level) * * @return None. */ -static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd) +FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd) { hw->sleep_conf.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH; } @@ -606,7 +608,7 @@ static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd) * * @return None. */ -static inline void uart_ll_set_mode_normal(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw) { hw->rs485_conf.en = 0; hw->rs485_conf.tx_rx_en = 0; @@ -621,7 +623,7 @@ static inline void uart_ll_set_mode_normal(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw) { // Application software control, remove echo hw->rs485_conf.rx_busy_tx_en = 1; @@ -640,7 +642,7 @@ static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw) { // Enable receiver, sw_rts = 1 generates low level on RTS pin hw->conf0.sw_rts = 1; @@ -662,7 +664,7 @@ static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw) { hw->conf0.irda_en = 0; // Enable full-duplex mode @@ -682,7 +684,7 @@ static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_mode_irda(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw) { hw->rs485_conf.en = 0; hw->rs485_conf.tx_rx_en = 0; @@ -699,7 +701,7 @@ static inline void uart_ll_set_mode_irda(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) +FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) { switch (mode) { default: @@ -730,7 +732,7 @@ static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) * * @return None. */ -static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num) +FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num) { *cmd_char = hw->at_cmd_char.data; *char_num = hw->at_cmd_char.char_num; @@ -743,7 +745,7 @@ static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, ui * * @return The UART wakeup threshold value. */ -static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw) { return hw->sleep_conf.active_threshold + UART_LL_MIN_WAKEUP_THRESH; } @@ -756,7 +758,7 @@ static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw) * * @return The bit mode. */ -static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit) +FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit) { *data_bit = hw->conf0.bit_num; } @@ -768,7 +770,7 @@ static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t * * * @return True if the state machine is in the IDLE state, otherwise false is returned. */ -static inline bool uart_ll_is_tx_idle(uart_dev_t *hw) +FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw) { return ((hw->status.txfifo_cnt == 0) && (hw->fsm_status.st_utx_out == 0)); } @@ -780,7 +782,7 @@ static inline bool uart_ll_is_tx_idle(uart_dev_t *hw) * * @return True if hw rts flow control is enabled, otherwise false is returned. */ -static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw) +FORCE_INLINE_ATTR bool uart_ll_is_hw_rts_en(uart_dev_t *hw) { return hw->conf1.rx_flow_en; } @@ -792,7 +794,7 @@ static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw) * * @return True if hw cts flow control is enabled, otherwise false is returned. */ -static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw) +FORCE_INLINE_ATTR bool uart_ll_is_hw_cts_en(uart_dev_t *hw) { return hw->conf0.tx_flow_en; } @@ -805,12 +807,12 @@ static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw) * * @return None */ -static inline void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en) +FORCE_INLINE_ATTR void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en) { hw->conf0.loopback = loop_back_en; } -static inline void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on) +FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on) { hw->flow_conf.force_xon = 1; if(!always_on) { @@ -827,7 +829,7 @@ static inline void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on) * * @return None. */ -static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask) +FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask) { typeof(hw->conf0) conf0_reg = hw->conf0; conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0; @@ -849,7 +851,7 @@ static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask) * * @return None. */ -static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd) +FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd) { uint16_t tout_val = tout_thrd; if(tout_thrd > 0) { @@ -867,7 +869,7 @@ static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd) * * @return tout_thr The timeout threshold value. If timeout feature is disabled returns 0. */ -static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw) +FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw) { uint16_t tout_thrd = 0; if(hw->conf1.rx_tout_en > 0) { @@ -883,7 +885,7 @@ static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw) * * @return maximum timeout threshold. */ -static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) +FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) { return UART_RX_TOUT_THRHD_V; } @@ -895,7 +897,7 @@ static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_force_xoff(uart_port_t uart_num) +FORCE_INLINE_ATTR void uart_ll_force_xoff(uart_port_t uart_num) { REG_CLR_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XON); REG_SET_BIT(UART_FLOW_CONF_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XOFF); @@ -909,7 +911,7 @@ static inline void uart_ll_force_xoff(uart_port_t uart_num) * * @return None. */ -static inline void uart_ll_force_xon(uart_port_t uart_num) +FORCE_INLINE_ATTR void uart_ll_force_xon(uart_port_t uart_num) { REG_CLR_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XOFF); REG_SET_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XON); @@ -924,7 +926,7 @@ static inline void uart_ll_force_xon(uart_port_t uart_num) * * @return UART module FSM status. */ -static inline uint32_t uart_ll_get_fsm_status(uart_port_t uart_num) +FORCE_INLINE_ATTR uint32_t uart_ll_get_fsm_status(uart_port_t uart_num) { return REG_GET_FIELD(UART_FSM_STATUS_REG(uart_num), UART_ST_UTX_OUT); } diff --git a/components/hal/esp32c3/include/hal/uart_ll.h b/components/hal/esp32c3/include/hal/uart_ll.h index 067c79ce37..252ec7dc48 100644 --- a/components/hal/esp32c3/include/hal/uart_ll.h +++ b/components/hal/esp32c3/include/hal/uart_ll.h @@ -14,6 +14,7 @@ #include "hal/uart_types.h" #include "soc/uart_periph.h" #include "soc/uart_struct.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { @@ -62,7 +63,7 @@ typedef enum { * * @return None. */ -static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) +FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) { hw->clk_conf.rst_core = core_rst_en; } @@ -74,7 +75,7 @@ static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) * * @return None. */ -static inline void uart_ll_sclk_enable(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw) { hw->clk_conf.sclk_en = 1; hw->clk_conf.rx_sclk_en = 1; @@ -88,7 +89,7 @@ static inline void uart_ll_sclk_enable(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_sclk_disable(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw) { hw->clk_conf.sclk_en = 0; hw->clk_conf.rx_sclk_en = 0; @@ -104,7 +105,7 @@ static inline void uart_ll_sclk_disable(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk) +FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk) { switch (source_clk) { default: @@ -128,7 +129,7 @@ static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk) * * @return None. */ -static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk) +FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk) { switch (hw->clk_conf.sclk_sel) { default: @@ -153,7 +154,7 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk) * * @return None */ -static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { #define DIV_UP(a, b) (((a) + (b) - 1) / (b)) const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits @@ -190,7 +191,7 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) * * @return None */ -static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask) +FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask) { hw->int_ena.val |= mask; } @@ -203,7 +204,7 @@ static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask) * * @return None */ -static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask) +FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask) { hw->int_ena.val &= (~mask); } @@ -215,7 +216,7 @@ static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask) * * @return The UART interrupt status. */ -static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) { return hw->int_st.val; } @@ -228,7 +229,7 @@ static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) * * @return None */ -static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask) +FORCE_INLINE_ATTR void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask) { hw->int_clr.val = mask; } @@ -240,7 +241,7 @@ static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask) * * @return interrupt enable value */ -static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) { return hw->int_ena.val; } @@ -254,7 +255,7 @@ static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) +FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) { for (int i = 0; i < (int)rd_len; i++) { buf[i] = hw->ahb_fifo.rw_byte; @@ -270,7 +271,7 @@ static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd * * @return None */ -static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len) +FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len) { for (int i = 0; i < (int)wr_len; i++) { hw->ahb_fifo.rw_byte = buf[i]; @@ -284,7 +285,7 @@ static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint * * @return None */ -static inline void uart_ll_rxfifo_rst(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw) { hw->conf0.rxfifo_rst = 1; hw->conf0.rxfifo_rst = 0; @@ -297,7 +298,7 @@ static inline void uart_ll_rxfifo_rst(uart_dev_t *hw) * * @return None */ -static inline void uart_ll_txfifo_rst(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw) { hw->conf0.txfifo_rst = 1; hw->conf0.txfifo_rst = 0; @@ -310,7 +311,7 @@ static inline void uart_ll_txfifo_rst(uart_dev_t *hw) * * @return The readable data length in rxfifo. */ -static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) { return hw->status.rxfifo_cnt; } @@ -322,7 +323,7 @@ static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) * * @return The data length of txfifo can be written. */ -static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) { return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt; } @@ -335,7 +336,7 @@ static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit) +FORCE_INLINE_ATTR void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit) { hw->conf0.stop_bit_num = stop_bit; } @@ -348,7 +349,7 @@ static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_b * * @return None. */ -static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit) +FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit) { *stop_bit = hw->conf0.stop_bit_num; } @@ -361,7 +362,7 @@ static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_ * * @return None. */ -static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode) +FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode) { if (parity_mode != UART_PARITY_DISABLE) { hw->conf0.parity = parity_mode & 0x1; @@ -377,7 +378,7 @@ static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode) * * @return None. */ -static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode) +FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode) { if (hw->conf0.parity_en) { *parity_mode = 0X2 | hw->conf0.parity; @@ -395,7 +396,7 @@ static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode * * @return None. */ -static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd) +FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd) { hw->conf1.rxfifo_full_thrhd = full_thrhd; } @@ -409,7 +410,7 @@ static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thr * * @return None. */ -static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd) +FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd) { hw->conf1.txfifo_empty_thrhd = empty_thrhd; } @@ -423,7 +424,7 @@ static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_t * * @return None. */ -static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr) +FORCE_INLINE_ATTR void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr) { hw->idle_conf.rx_idle_thrhd = rx_idle_thr; } @@ -436,7 +437,7 @@ static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr) * * @return None. */ -static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num) +FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num) { hw->idle_conf.tx_idle_num = idle_num; } @@ -449,7 +450,7 @@ static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num) * * @return None. */ -static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) +FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) { if (break_num > 0) { HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf, tx_brk_num, break_num); @@ -468,7 +469,7 @@ static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) * * @return None. */ -static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs) +FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs) { //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set. if (flow_ctrl & UART_HW_FLOWCTRL_RTS) { @@ -492,7 +493,7 @@ static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_ * * @return None. */ -static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl) +FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl) { *flow_ctrl = UART_HW_FLOWCTRL_DISABLE; if (hw->conf1.rx_flow_en) { @@ -512,7 +513,7 @@ static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_ * * @return None. */ -static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en) +FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en) { if (sw_flow_ctrl_en) { hw->flow_conf.xonoff_del = 1; @@ -540,7 +541,7 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t * * * @return None. */ -static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char) +FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char) { HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char); HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num); @@ -557,7 +558,7 @@ static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_ch * * @return None. */ -static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit) +FORCE_INLINE_ATTR void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit) { hw->conf0.bit_num = data_bit; } @@ -570,7 +571,7 @@ static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t d * * @return None. */ -static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level) +FORCE_INLINE_ATTR void uart_ll_set_rts_active_level(uart_dev_t *hw, int level) { hw->conf0.sw_rts = level & 0x1; } @@ -583,7 +584,7 @@ static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level) * * @return None. */ -static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level) +FORCE_INLINE_ATTR void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level) { hw->conf0.sw_dtr = level & 0x1; } @@ -597,7 +598,7 @@ static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level) * * @return None. */ -static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd) +FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd) { hw->sleep_conf.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH; } @@ -609,7 +610,7 @@ static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd) * * @return None. */ -static inline void uart_ll_set_mode_normal(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw) { hw->rs485_conf.en = 0; hw->rs485_conf.tx_rx_en = 0; @@ -624,7 +625,7 @@ static inline void uart_ll_set_mode_normal(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw) { // Application software control, remove echo hw->rs485_conf.rx_busy_tx_en = 1; @@ -643,7 +644,7 @@ static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw) { // Enable receiver, sw_rts = 1 generates low level on RTS pin hw->conf0.sw_rts = 1; @@ -665,7 +666,7 @@ static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw) { hw->conf0.irda_en = 0; // Enable full-duplex mode @@ -685,7 +686,7 @@ static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_mode_irda(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw) { hw->rs485_conf.en = 0; hw->rs485_conf.tx_rx_en = 0; @@ -702,7 +703,7 @@ static inline void uart_ll_set_mode_irda(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) +FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) { switch (mode) { default: @@ -733,7 +734,7 @@ static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) * * @return None. */ -static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num) +FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num) { *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, data); *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, char_num); @@ -746,7 +747,7 @@ static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, ui * * @return The UART wakeup threshold value. */ -static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw) { return hw->sleep_conf.active_threshold + UART_LL_MIN_WAKEUP_THRESH; } @@ -759,7 +760,7 @@ static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw) * * @return The bit mode. */ -static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit) +FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit) { *data_bit = hw->conf0.bit_num; } @@ -771,7 +772,7 @@ static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t * * * @return True if the state machine is in the IDLE state, otherwise false is returned. */ -static inline bool uart_ll_is_tx_idle(uart_dev_t *hw) +FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw) { return ((hw->status.txfifo_cnt == 0) && (hw->fsm_status.st_utx_out == 0)); } @@ -783,7 +784,7 @@ static inline bool uart_ll_is_tx_idle(uart_dev_t *hw) * * @return True if hw rts flow control is enabled, otherwise false is returned. */ -static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw) +FORCE_INLINE_ATTR bool uart_ll_is_hw_rts_en(uart_dev_t *hw) { return hw->conf1.rx_flow_en; } @@ -795,7 +796,7 @@ static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw) * * @return True if hw cts flow control is enabled, otherwise false is returned. */ -static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw) +FORCE_INLINE_ATTR bool uart_ll_is_hw_cts_en(uart_dev_t *hw) { return hw->conf0.tx_flow_en; } @@ -808,12 +809,12 @@ static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw) * * @return None */ -static inline void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en) +FORCE_INLINE_ATTR void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en) { hw->conf0.loopback = loop_back_en; } -static inline void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on) +FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on) { hw->flow_conf.force_xon = 1; if(!always_on) { @@ -830,7 +831,7 @@ static inline void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on) * * @return None. */ -static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask) +FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask) { typeof(hw->conf0) conf0_reg = hw->conf0; conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0; @@ -852,7 +853,7 @@ static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask) * * @return None. */ -static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd) +FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd) { uint16_t tout_val = tout_thrd; if(tout_thrd > 0) { @@ -870,7 +871,7 @@ static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd) * * @return tout_thr The timeout threshold value. If timeout feature is disabled returns 0. */ -static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw) +FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw) { uint16_t tout_thrd = 0; if(hw->conf1.rx_tout_en > 0) { @@ -886,7 +887,7 @@ static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw) * * @return maximum timeout threshold. */ -static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) +FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) { return UART_RX_TOUT_THRHD_V; } @@ -897,7 +898,7 @@ static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) * @param hw Beginning address of the peripheral registers. * @param enable Boolean marking whether the auto baudrate should be enabled or not. */ -static inline void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable) +FORCE_INLINE_ATTR void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable) { hw->conf0.autobaud_en = enable ? 1 : 0; } @@ -907,7 +908,7 @@ static inline void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable) * * @param hw Beginning address of the peripheral registers. */ -static inline uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw) { return hw->rxd_cnt.edge_cnt; } @@ -917,7 +918,7 @@ static inline uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw) * * @param hw Beginning address of the peripheral registers. */ -static inline uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw) { return hw->pospulse.min_cnt; } @@ -927,7 +928,7 @@ static inline uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw) * * @param hw Beginning address of the peripheral registers. */ -static inline uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw) { return hw->negpulse.min_cnt; } @@ -937,7 +938,7 @@ static inline uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw) * * @param hw Beginning address of the peripheral registers. */ -static inline uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw) { return hw->highpulse.min_cnt; } @@ -947,7 +948,7 @@ static inline uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw) * * @param hw Beginning address of the peripheral registers. */ -static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw) { return hw->lowpulse.min_cnt; } @@ -959,7 +960,7 @@ static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_force_xoff(uart_port_t uart_num) +FORCE_INLINE_ATTR void uart_ll_force_xoff(uart_port_t uart_num) { REG_CLR_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XON); REG_SET_BIT(UART_FLOW_CONF_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XOFF); @@ -973,7 +974,7 @@ static inline void uart_ll_force_xoff(uart_port_t uart_num) * * @return None. */ -static inline void uart_ll_force_xon(uart_port_t uart_num) +FORCE_INLINE_ATTR void uart_ll_force_xon(uart_port_t uart_num) { REG_CLR_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XOFF); REG_SET_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XON); @@ -988,7 +989,7 @@ static inline void uart_ll_force_xon(uart_port_t uart_num) * * @return UART module FSM status. */ -static inline uint32_t uart_ll_get_fsm_status(uart_port_t uart_num) +FORCE_INLINE_ATTR uint32_t uart_ll_get_fsm_status(uart_port_t uart_num) { return REG_GET_FIELD(UART_FSM_STATUS_REG(uart_num), UART_ST_UTX_OUT); } diff --git a/components/hal/esp32h4/include/hal/uart_ll.h b/components/hal/esp32h4/include/hal/uart_ll.h index d0eeca30a6..c3701805be 100644 --- a/components/hal/esp32h4/include/hal/uart_ll.h +++ b/components/hal/esp32h4/include/hal/uart_ll.h @@ -14,6 +14,7 @@ #include "hal/uart_types.h" #include "soc/uart_periph.h" #include "soc/uart_struct.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { @@ -62,7 +63,7 @@ typedef enum { * * @return None. */ -static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) +FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) { hw->clk_conf.rst_core = core_rst_en; } @@ -74,7 +75,7 @@ static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) * * @return None. */ -static inline void uart_ll_sclk_enable(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw) { hw->clk_conf.sclk_en = 1; hw->clk_conf.rx_sclk_en = 1; @@ -88,7 +89,7 @@ static inline void uart_ll_sclk_enable(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_sclk_disable(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw) { hw->clk_conf.sclk_en = 0; hw->clk_conf.rx_sclk_en = 0; @@ -104,7 +105,7 @@ static inline void uart_ll_sclk_disable(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk) +FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk) { switch (source_clk) { default: @@ -128,7 +129,7 @@ static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk) * * @return None. */ -static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk) +FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk) { switch (hw->clk_conf.sclk_sel) { default: @@ -153,7 +154,7 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk) * * @return None */ -static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { #define DIV_UP(a, b) (((a) + (b) - 1) / (b)) const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits @@ -176,7 +177,7 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t * * @return The current baudrate */ -static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) +FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) { typeof(hw->clk_div) div_reg = hw->clk_div; return ((sclk_freq << 4)) / (((div_reg.div_int << 4) | div_reg.div_frag) * (HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1)); @@ -190,7 +191,7 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) * * @return None */ -static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask) +FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask) { hw->int_ena.val |= mask; } @@ -203,7 +204,7 @@ static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask) * * @return None */ -static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask) +FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask) { hw->int_ena.val &= (~mask); } @@ -215,7 +216,7 @@ static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask) * * @return The UART interrupt status. */ -static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) { return hw->int_st.val; } @@ -228,7 +229,7 @@ static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) * * @return None */ -static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask) +FORCE_INLINE_ATTR void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask) { hw->int_clr.val = mask; } @@ -240,7 +241,7 @@ static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask) * * @return interrupt enable value */ -static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) { return hw->int_ena.val; } @@ -254,7 +255,7 @@ static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) +FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) { for (int i = 0; i < (int)rd_len; i++) { buf[i] = hw->ahb_fifo.rw_byte; @@ -270,7 +271,7 @@ static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd * * @return None */ -static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len) +FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len) { for (int i = 0; i < (int)wr_len; i++) { hw->ahb_fifo.rw_byte = buf[i]; @@ -284,7 +285,7 @@ static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint * * @return None */ -static inline void uart_ll_rxfifo_rst(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw) { hw->conf0.rxfifo_rst = 1; hw->conf0.rxfifo_rst = 0; @@ -297,7 +298,7 @@ static inline void uart_ll_rxfifo_rst(uart_dev_t *hw) * * @return None */ -static inline void uart_ll_txfifo_rst(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw) { hw->conf0.txfifo_rst = 1; hw->conf0.txfifo_rst = 0; @@ -310,7 +311,7 @@ static inline void uart_ll_txfifo_rst(uart_dev_t *hw) * * @return The readable data length in rxfifo. */ -static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) { return hw->status.rxfifo_cnt; } @@ -322,7 +323,7 @@ static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) * * @return The data length of txfifo can be written. */ -static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) { return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt; } @@ -335,7 +336,7 @@ static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit) +FORCE_INLINE_ATTR void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit) { hw->conf0.stop_bit_num = stop_bit; } @@ -348,7 +349,7 @@ static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_b * * @return None. */ -static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit) +FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit) { *stop_bit = hw->conf0.stop_bit_num; } @@ -361,7 +362,7 @@ static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_ * * @return None. */ -static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode) +FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode) { if (parity_mode != UART_PARITY_DISABLE) { hw->conf0.parity = parity_mode & 0x1; @@ -377,7 +378,7 @@ static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode) * * @return None. */ -static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode) +FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode) { if (hw->conf0.parity_en) { *parity_mode = 0X2 | hw->conf0.parity; @@ -395,7 +396,7 @@ static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode * * @return None. */ -static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd) +FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd) { hw->conf1.rxfifo_full_thrhd = full_thrhd; } @@ -409,7 +410,7 @@ static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thr * * @return None. */ -static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd) +FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd) { hw->conf1.txfifo_empty_thrhd = empty_thrhd; } @@ -423,7 +424,7 @@ static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_t * * @return None. */ -static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr) +FORCE_INLINE_ATTR void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr) { hw->idle_conf.rx_idle_thrhd = rx_idle_thr; } @@ -436,7 +437,7 @@ static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr) * * @return None. */ -static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num) +FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num) { hw->idle_conf.tx_idle_num = idle_num; } @@ -449,7 +450,7 @@ static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num) * * @return None. */ -static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) +FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) { if (break_num > 0) { HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf, tx_brk_num, break_num); @@ -468,7 +469,7 @@ static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) * * @return None. */ -static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs) +FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs) { //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set. if (flow_ctrl & UART_HW_FLOWCTRL_RTS) { @@ -492,7 +493,7 @@ static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_ * * @return None. */ -static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl) +FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl) { *flow_ctrl = UART_HW_FLOWCTRL_DISABLE; if (hw->conf1.rx_flow_en) { @@ -512,7 +513,7 @@ static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_ * * @return None. */ -static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en) +FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en) { if (sw_flow_ctrl_en) { hw->flow_conf.xonoff_del = 1; @@ -540,7 +541,7 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t * * * @return None. */ -static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char) +FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char) { HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char); HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num); @@ -557,7 +558,7 @@ static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_ch * * @return None. */ -static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit) +FORCE_INLINE_ATTR void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit) { hw->conf0.bit_num = data_bit; } @@ -570,7 +571,7 @@ static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t d * * @return None. */ -static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level) +FORCE_INLINE_ATTR void uart_ll_set_rts_active_level(uart_dev_t *hw, int level) { hw->conf0.sw_rts = level & 0x1; } @@ -583,7 +584,7 @@ static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level) * * @return None. */ -static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level) +FORCE_INLINE_ATTR void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level) { hw->conf0.sw_dtr = level & 0x1; } @@ -597,7 +598,7 @@ static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level) * * @return None. */ -static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd) +FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd) { hw->sleep_conf.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH; } @@ -609,7 +610,7 @@ static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd) * * @return None. */ -static inline void uart_ll_set_mode_normal(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw) { hw->rs485_conf.en = 0; hw->rs485_conf.tx_rx_en = 0; @@ -624,7 +625,7 @@ static inline void uart_ll_set_mode_normal(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw) { // Application software control, remove echo hw->rs485_conf.rx_busy_tx_en = 1; @@ -643,7 +644,7 @@ static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw) { // Enable receiver, sw_rts = 1 generates low level on RTS pin hw->conf0.sw_rts = 1; @@ -665,7 +666,7 @@ static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw) { hw->conf0.irda_en = 0; // Enable full-duplex mode @@ -685,7 +686,7 @@ static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_mode_irda(uart_dev_t *hw) +FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw) { hw->rs485_conf.en = 0; hw->rs485_conf.tx_rx_en = 0; @@ -702,7 +703,7 @@ static inline void uart_ll_set_mode_irda(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) +FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) { switch (mode) { default: @@ -733,7 +734,7 @@ static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) * * @return None. */ -static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num) +FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num) { *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, data); *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, char_num); @@ -746,7 +747,7 @@ static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, ui * * @return The UART wakeup threshold value. */ -static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw) { return hw->sleep_conf.active_threshold + UART_LL_MIN_WAKEUP_THRESH; } @@ -759,7 +760,7 @@ static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw) * * @return The bit mode. */ -static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit) +FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit) { *data_bit = hw->conf0.bit_num; } @@ -771,7 +772,7 @@ static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t * * * @return True if the state machine is in the IDLE state, otherwise false is returned. */ -static inline bool uart_ll_is_tx_idle(uart_dev_t *hw) +FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw) { return ((hw->status.txfifo_cnt == 0) && (hw->fsm_status.st_utx_out == 0)); } @@ -783,7 +784,7 @@ static inline bool uart_ll_is_tx_idle(uart_dev_t *hw) * * @return True if hw rts flow control is enabled, otherwise false is returned. */ -static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw) +FORCE_INLINE_ATTR bool uart_ll_is_hw_rts_en(uart_dev_t *hw) { return hw->conf1.rx_flow_en; } @@ -795,7 +796,7 @@ static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw) * * @return True if hw cts flow control is enabled, otherwise false is returned. */ -static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw) +FORCE_INLINE_ATTR bool uart_ll_is_hw_cts_en(uart_dev_t *hw) { return hw->conf0.tx_flow_en; } @@ -808,12 +809,12 @@ static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw) * * @return None */ -static inline void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en) +FORCE_INLINE_ATTR void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en) { hw->conf0.loopback = loop_back_en; } -static inline void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on) +FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on) { hw->flow_conf.force_xon = 1; if(!always_on) { @@ -830,7 +831,7 @@ static inline void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on) * * @return None. */ -static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask) +FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask) { typeof(hw->conf0) conf0_reg = hw->conf0; conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0; @@ -852,7 +853,7 @@ static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask) * * @return None. */ -static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd) +FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd) { uint16_t tout_val = tout_thrd; if(tout_thrd > 0) { @@ -870,7 +871,7 @@ static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd) * * @return tout_thr The timeout threshold value. If timeout feature is disabled returns 0. */ -static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw) +FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw) { uint16_t tout_thrd = 0; if(hw->conf1.rx_tout_en > 0) { @@ -886,7 +887,7 @@ static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw) * * @return maximum timeout threshold. */ -static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) +FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) { return UART_RX_TOUT_THRHD_V; } @@ -897,7 +898,7 @@ static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) * @param hw Beginning address of the peripheral registers. * @param enable Boolean marking whether the auto baudrate should be enabled or not. */ -static inline void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable) +FORCE_INLINE_ATTR void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable) { hw->conf0.autobaud_en = enable ? 1 : 0; } @@ -907,7 +908,7 @@ static inline void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable) * * @param hw Beginning address of the peripheral registers. */ -static inline uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw) { return hw->rxd_cnt.edge_cnt; } @@ -917,7 +918,7 @@ static inline uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw) * * @param hw Beginning address of the peripheral registers. */ -static inline uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw) { return hw->pospulse.min_cnt; } @@ -927,7 +928,7 @@ static inline uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw) * * @param hw Beginning address of the peripheral registers. */ -static inline uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw) { return hw->negpulse.min_cnt; } @@ -937,7 +938,7 @@ static inline uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw) * * @param hw Beginning address of the peripheral registers. */ -static inline uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw) { return hw->highpulse.min_cnt; } @@ -947,7 +948,7 @@ static inline uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw) * * @param hw Beginning address of the peripheral registers. */ -static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw) { return hw->lowpulse.min_cnt; } @@ -959,7 +960,7 @@ static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw) * * @return None. */ -static inline void uart_ll_force_xoff(uart_port_t uart_num) +FORCE_INLINE_ATTR void uart_ll_force_xoff(uart_port_t uart_num) { REG_CLR_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XON); REG_SET_BIT(UART_FLOW_CONF_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XOFF); @@ -973,7 +974,7 @@ static inline void uart_ll_force_xoff(uart_port_t uart_num) * * @return None. */ -static inline void uart_ll_force_xon(uart_port_t uart_num) +FORCE_INLINE_ATTR void uart_ll_force_xon(uart_port_t uart_num) { REG_CLR_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XOFF); REG_SET_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XON); @@ -988,7 +989,7 @@ static inline void uart_ll_force_xon(uart_port_t uart_num) * * @return UART module FSM status. */ -static inline uint32_t uart_ll_get_fsm_status(uart_port_t uart_num) +FORCE_INLINE_ATTR uint32_t uart_ll_get_fsm_status(uart_port_t uart_num) { return REG_GET_FIELD(UART_FSM_STATUS_REG(uart_num), UART_ST_UTX_OUT); }