Merge branch 'fix/fix_cam_iram_safe_compile_error_v5.4' into 'release/v5.4'

cam: fix cam iram safe compile error (v5.4)

See merge request espressif/esp-idf!37606
This commit is contained in:
morris
2025-03-31 16:42:44 +08:00
16 changed files with 47 additions and 33 deletions

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@ -2,8 +2,8 @@ menu "ESP-Driver:Camera Controller Configurations"
depends on SOC_MIPI_CSI_SUPPORTED || SOC_LCDCAM_CAM_SUPPORTED depends on SOC_MIPI_CSI_SUPPORTED || SOC_LCDCAM_CAM_SUPPORTED
config CAM_CTLR_MIPI_CSI_ISR_IRAM_SAFE config CAM_CTLR_MIPI_CSI_ISR_CACHE_SAFE
bool "CSI ISR IRAM-Safe" bool "CSI ISR Cache-Safe"
depends on SOC_MIPI_CSI_SUPPORTED depends on SOC_MIPI_CSI_SUPPORTED
default n default n
select DW_GDMA_ISR_IRAM_SAFE select DW_GDMA_ISR_IRAM_SAFE
@ -11,22 +11,22 @@ menu "ESP-Driver:Camera Controller Configurations"
select DW_GDMA_SETTER_FUNC_IN_IRAM select DW_GDMA_SETTER_FUNC_IN_IRAM
select DW_GDMA_GETTER_FUNC_IN_IRAM select DW_GDMA_GETTER_FUNC_IN_IRAM
help help
Ensure the CSI driver ISR is IRAM-Safe. When enabled, the ISR handler Ensure the CSI driver ISR is Cache-Safe. When enabled, the ISR handler
will be available when the cache is disabled. will be available when the cache is disabled.
config CAM_CTLR_ISP_DVP_ISR_IRAM_SAFE # IDF-10093 config CAM_CTLR_ISP_DVP_ISR_CACHE_SAFE # IDF-10093
bool "ISP_DVP ISR IRAM-Safe" bool "ISP_DVP ISR Cache-Safe"
default n default n
select DW_GDMA_ISR_IRAM_SAFE select DW_GDMA_ISR_IRAM_SAFE
select DW_GDMA_CTRL_FUNC_IN_IRAM select DW_GDMA_CTRL_FUNC_IN_IRAM
select DW_GDMA_SETTER_FUNC_IN_IRAM select DW_GDMA_SETTER_FUNC_IN_IRAM
select DW_GDMA_GETTER_FUNC_IN_IRAM select DW_GDMA_GETTER_FUNC_IN_IRAM
help help
Ensure the ISP_DVP driver ISR is IRAM-Safe. When enabled, the ISR handler Ensure the ISP_DVP driver ISR is Cache-Safe. When enabled, the ISR handler
will be available when the cache is disabled. will be available when the cache is disabled.
config CAM_CTLR_DVP_CAM_ISR_IRAM_SAFE config CAM_CTLR_DVP_CAM_ISR_CACHE_SAFE
bool "DVP ISR IRAM-Safe" bool "DVP ISR Cache-Safe"
depends on SOC_LCDCAM_CAM_SUPPORTED depends on SOC_LCDCAM_CAM_SUPPORTED
default n default n
select DW_GDMA_ISR_IRAM_SAFE select DW_GDMA_ISR_IRAM_SAFE
@ -34,7 +34,7 @@ menu "ESP-Driver:Camera Controller Configurations"
select DW_GDMA_SETTER_FUNC_IN_IRAM select DW_GDMA_SETTER_FUNC_IN_IRAM
select DW_GDMA_GETTER_FUNC_IN_IRAM select DW_GDMA_GETTER_FUNC_IN_IRAM
help help
Ensure the DVP driver ISR is IRAM-Safe. When enabled, the ISR handler Ensure the DVP driver ISR is Cache-Safe. When enabled, the ISR handler
will be available when the cache is disabled. will be available when the cache is disabled.
endmenu # ESP Camera Controller Configurations endmenu # ESP Camera Controller Configurations

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@ -12,6 +12,7 @@
#include "esp_heap_caps.h" #include "esp_heap_caps.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "freertos/idf_additions.h" #include "freertos/idf_additions.h"
#include "esp_memory_utils.h"
#include "esp_clk_tree.h" #include "esp_clk_tree.h"
#include "esp_cam_ctlr.h" #include "esp_cam_ctlr.h"
#include "esp_cam_ctlr_csi.h" #include "esp_cam_ctlr_csi.h"
@ -25,7 +26,7 @@
#include "esp_private/esp_clk_tree_common.h" #include "esp_private/esp_clk_tree_common.h"
#include "esp_cache.h" #include "esp_cache.h"
#if CONFIG_CAM_CTLR_MIPI_CSI_ISR_IRAM_SAFE #if CONFIG_CAM_CTLR_MIPI_CSI_ISR_CACHE_SAFE
#define CSI_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT) #define CSI_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
#else #else
#define CSI_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT #define CSI_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
@ -375,7 +376,7 @@ esp_err_t s_register_event_callbacks(esp_cam_ctlr_handle_t handle, const esp_cam
csi_controller_t *ctlr = __containerof(handle, csi_controller_t, base); csi_controller_t *ctlr = __containerof(handle, csi_controller_t, base);
ESP_RETURN_ON_FALSE(ctlr->csi_fsm == CSI_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "driver starts already, not allow cbs register"); ESP_RETURN_ON_FALSE(ctlr->csi_fsm == CSI_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "driver starts already, not allow cbs register");
#if CONFIG_CAM_CTLR_MIPI_CSI_ISR_IRAM_SAFE #if CONFIG_CAM_CTLR_MIPI_CSI_ISR_CACHE_SAFE
if (cbs->on_get_new_trans) { if (cbs->on_get_new_trans) {
ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_get_new_trans), ESP_ERR_INVALID_ARG, TAG, "on_get_new_trans callback not in IRAM"); ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_get_new_trans), ESP_ERR_INVALID_ARG, TAG, "on_get_new_trans callback not in IRAM");
} }

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@ -5,6 +5,7 @@
*/ */
#include <sys/param.h> #include <sys/param.h>
#include "esp_memory_utils.h"
#include "hal/gpio_ll.h" #include "hal/gpio_ll.h"
#include "hal/cam_ll.h" #include "hal/cam_ll.h"
#include "hal/color_hal.h" #include "hal/color_hal.h"
@ -24,7 +25,7 @@
#include "esp_private/esp_clk_tree_common.h" #include "esp_private/esp_clk_tree_common.h"
#include "../../dvp_share_ctrl.h" #include "../../dvp_share_ctrl.h"
#ifdef CONFIG_CAM_CTLR_DVP_CAM_ISR_IRAM_SAFE #ifdef CONFIG_CAM_CTLR_DVP_CAM_ISR_CACHE_SAFE
#define CAM_DVP_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT) #define CAM_DVP_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
#else #else
#define CAM_DVP_MEM_ALLOC_CAPS (MALLOC_CAP_DEFAULT) #define CAM_DVP_MEM_ALLOC_CAPS (MALLOC_CAP_DEFAULT)
@ -575,7 +576,7 @@ static esp_err_t esp_cam_ctlr_dvp_cam_register_event_callbacks(esp_cam_ctlr_hand
ESP_RETURN_ON_FALSE(cbs->on_trans_finished, ESP_ERR_INVALID_ARG, TAG, "invalid argument: on_trans_finished is null"); ESP_RETURN_ON_FALSE(cbs->on_trans_finished, ESP_ERR_INVALID_ARG, TAG, "invalid argument: on_trans_finished is null");
ESP_RETURN_ON_FALSE(cbs->on_get_new_trans || !ctlr->bk_buffer_dis, ESP_ERR_INVALID_ARG, TAG, "invalid argument: on_get_new_trans is null"); ESP_RETURN_ON_FALSE(cbs->on_get_new_trans || !ctlr->bk_buffer_dis, ESP_ERR_INVALID_ARG, TAG, "invalid argument: on_get_new_trans is null");
#if CONFIG_CAM_CTLR_DVP_CAM_ISR_IRAM_SAFE #if CONFIG_CAM_CTLR_DVP_CAM_ISR_CACHE_SAFE
if (cbs->on_get_new_trans) { if (cbs->on_get_new_trans) {
ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_get_new_trans), ESP_ERR_INVALID_ARG, TAG, "on_get_new_trans callback not in IRAM"); ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_get_new_trans), ESP_ERR_INVALID_ARG, TAG, "on_get_new_trans callback not in IRAM");
} }

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@ -11,6 +11,7 @@
#include "esp_heap_caps.h" #include "esp_heap_caps.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "freertos/idf_additions.h" #include "freertos/idf_additions.h"
#include "esp_memory_utils.h"
#include "driver/isp_types.h" #include "driver/isp_types.h"
#include "driver/gpio.h" #include "driver/gpio.h"
#include "hal/isp_hal.h" #include "hal/isp_hal.h"
@ -30,7 +31,7 @@
#include "esp_cam_ctlr_isp_dvp.h" #include "esp_cam_ctlr_isp_dvp.h"
#include "../../dvp_share_ctrl.h" #include "../../dvp_share_ctrl.h"
#if CONFIG_CAM_CTLR_ISP_DVP_ISR_IRAM_SAFE #if CONFIG_CAM_CTLR_ISP_DVP_ISR_CACHE_SAFE
#define ISP_DVP_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT) #define ISP_DVP_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
#else #else
#define ISP_DVP_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT #define ISP_DVP_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
@ -261,7 +262,7 @@ static esp_err_t s_isp_dvp_register_event_callbacks(esp_cam_ctlr_handle_t handle
isp_dvp_controller_t *dvp_ctlr = __containerof(handle, isp_dvp_controller_t, base); isp_dvp_controller_t *dvp_ctlr = __containerof(handle, isp_dvp_controller_t, base);
ESP_RETURN_ON_FALSE(dvp_ctlr->fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller isn't in init state"); ESP_RETURN_ON_FALSE(dvp_ctlr->fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller isn't in init state");
#if CONFIG_CAM_CTLR_MIPI_CSI_ISR_IRAM_SAFE #if CONFIG_CAM_CTLR_ISP_DVP_ISR_CACHE_SAFE
if (cbs->on_get_new_trans) { if (cbs->on_get_new_trans) {
ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_get_new_trans), ESP_ERR_INVALID_ARG, TAG, "on_get_new_trans callback not in IRAM"); ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_get_new_trans), ESP_ERR_INVALID_ARG, TAG, "on_get_new_trans callback not in IRAM");
} }

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@ -0,0 +1,6 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_CAM_CTLR_MIPI_CSI_ISR_IRAM_SAFE CONFIG_CAM_CTLR_MIPI_CSI_ISR_CACHE_SAFE
CONFIG_CAM_CTLR_ISP_DVP_ISR_IRAM_SAFE CONFIG_CAM_CTLR_ISP_DVP_ISR_CACHE_SAFE
CONFIG_CAM_CTLR_DVP_CAM_ISR_IRAM_SAFE CONFIG_CAM_CTLR_DVP_CAM_ISR_CACHE_SAFE

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@ -0,0 +1 @@
CONFIG_CAM_CTLR_MIPI_CSI_ISR_CACHE_SAFE=y

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@ -1,7 +1,2 @@
CONFIG_FREERTOS_HZ=1000 CONFIG_FREERTOS_HZ=1000
CONFIG_ESP_TASK_WDT_EN=n CONFIG_ESP_TASK_WDT_EN=n
CONFIG_SPIRAM=y
CONFIG_IDF_EXPERIMENTAL_FEATURES=y
CONFIG_SPIRAM_SPEED_200M=y
CONFIG_ESP_TASK_WDT_EN=n

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@ -0,0 +1,5 @@
CONFIG_IDF_TARGET="esp32p4"
CONFIG_SPIRAM=y
CONFIG_IDF_EXPERIMENTAL_FEATURES=y
CONFIG_SPIRAM_SPEED_200M=y

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@ -0,0 +1 @@
CONFIG_CAM_CTLR_MIPI_CSI_ISR_CACHE_SAFE=y

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@ -1,6 +1,5 @@
# This file was generated using idf.py save-defconfig. It can be edited manually. # This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) 5.4.0 Project Minimal Configuration # Espressif IoT Development Framework (ESP-IDF) 5.4.0 Project Minimal Configuration
# #
CONFIG_SPIRAM=y
CONFIG_ESP_TASK_WDT_EN=n CONFIG_ESP_TASK_WDT_EN=n
CONFIG_FREERTOS_HZ=1000 CONFIG_FREERTOS_HZ=1000

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@ -1,3 +1,5 @@
CONFIG_IDF_TARGET="esp32p4" CONFIG_IDF_TARGET="esp32p4"
CONFIG_SPIRAM=y
CONFIG_SPIRAM_SPEED_200M=y CONFIG_SPIRAM_SPEED_200M=y
CONFIG_IDF_EXPERIMENTAL_FEATURES=y CONFIG_IDF_EXPERIMENTAL_FEATURES=y

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@ -0,0 +1 @@
CONFIG_CAM_CTLR_MIPI_CSI_ISR_CACHE_SAFE=y

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@ -1,6 +1,2 @@
CONFIG_FREERTOS_HZ=1000 CONFIG_FREERTOS_HZ=1000
CONFIG_ESP_TASK_WDT_EN=n CONFIG_ESP_TASK_WDT_EN=n
CONFIG_SPIRAM=y
CONFIG_IDF_EXPERIMENTAL_FEATURES=y
CONFIG_SPIRAM_SPEED_200M=y

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@ -0,0 +1,5 @@
CONFIG_IDF_TARGET="esp32p4"
CONFIG_SPIRAM=y
CONFIG_IDF_EXPERIMENTAL_FEATURES=y
CONFIG_SPIRAM_SPEED_200M=y

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@ -184,8 +184,8 @@ The following Kconfig options affect the behavior of the interrupt handler when
.. list:: .. list::
:SOC_MIPI_CSI_SUPPORTED: - :ref:`CONFIG_CAM_CTLR_MIPI_CSI_ISR_IRAM_SAFE`, see :ref:`cam-thread-safety` for more details. :SOC_MIPI_CSI_SUPPORTED: - :ref:`CONFIG_CAM_CTLR_MIPI_CSI_ISR_CACHE_SAFE`, see :ref:`cam-thread-safety` for more details.
:SOC_ISP_DVP_SUPPORTED: - :ref:`CONFIG_CAM_CTLR_ISP_DVP_ISR_IRAM_SAFE`, see :ref:`cam-thread-safety` for more details. :SOC_ISP_DVP_SUPPORTED: - :ref:`CONFIG_CAM_CTLR_ISP_DVP_ISR_CACHE_SAFE`, see :ref:`cam-thread-safety` for more details.
.. _cam-iram-safe: .. _cam-iram-safe:
@ -198,8 +198,8 @@ There are Kconfig options
.. list:: .. list::
:SOC_MIPI_CSI_SUPPORTED: - :ref:`CONFIG_CAM_CTLR_MIPI_CSI_ISR_IRAM_SAFE` :SOC_MIPI_CSI_SUPPORTED: - :ref:`CONFIG_CAM_CTLR_MIPI_CSI_ISR_CACHE_SAFE`
:SOC_ISP_DVP_SUPPORTED: - :ref:`CONFIG_CAM_CTLR_ISP_DVP_ISR_IRAM_SAFE` :SOC_ISP_DVP_SUPPORTED: - :ref:`CONFIG_CAM_CTLR_ISP_DVP_ISR_CACHE_SAFE`
that that

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@ -184,8 +184,8 @@ Kconfig 选项
.. list:: .. list::
:SOC_MIPI_CSI_SUPPORTED: - :ref:`CONFIG_CAM_CTLR_MIPI_CSI_ISR_IRAM_SAFE`,详情请参阅 :ref:`cam-thread-safety`。 :SOC_MIPI_CSI_SUPPORTED: - :ref:`CONFIG_CAM_CTLR_MIPI_CSI_ISR_CACHE_SAFE`,详情请参阅 :ref:`cam-thread-safety`。
:SOC_ISP_DVP_SUPPORTED: - :ref:`CONFIG_CAM_CTLR_ISP_DVP_ISR_IRAM_SAFE`,详情请参阅 :ref:`cam-thread-safety`。 :SOC_ISP_DVP_SUPPORTED: - :ref:`CONFIG_CAM_CTLR_ISP_DVP_ISR_CACHE_SAFE`,详情请参阅 :ref:`cam-thread-safety`。
.. _cam-iram-safe: .. _cam-iram-safe:
@ -198,8 +198,8 @@ IRAM 安全
.. list:: .. list::
:SOC_MIPI_CSI_SUPPORTED: - :ref:`CONFIG_CAM_CTLR_MIPI_CSI_ISR_IRAM_SAFE` :SOC_MIPI_CSI_SUPPORTED: - :ref:`CONFIG_CAM_CTLR_MIPI_CSI_ISR_CACHE_SAFE`
:SOC_ISP_DVP_SUPPORTED: - :ref:`CONFIG_CAM_CTLR_ISP_DVP_ISR_IRAM_SAFE` :SOC_ISP_DVP_SUPPORTED: - :ref:`CONFIG_CAM_CTLR_ISP_DVP_ISR_CACHE_SAFE`
这些选项支持 这些选项支持