From 7931c033ed961cf5ed0ba26345cd9c24fa3dd2a3 Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Sun, 27 Mar 2022 03:02:22 +0800 Subject: [PATCH 1/2] pm: fixed RTC8M domain power issues introduced in e44ead535640525969c7e85892f38ca349d5ddf4 1. The int8M power domain config by default is PD. While LEDC is using RTC8M as clock source, this power domain will be kept on. But when 8MD256 is used as RTC clock source, the power domain should also be kept on. On ESP32, there was protection for it, but broken by commit e44ead535640525969c7e85892f38ca349d5ddf4. Currently the power domain will be forced on when LEDC is using RTC8M as clock source && !int8m_pd_en (user enable ESP_PDP_DOMAIN_RTC8M in lightsleep). Otherwise the power domain will be powered off, regardless of RTC clock source. In other words, int8M domain will be forced off (even when 8MD256 used as RTC clock source) if LEDC not using RTC8M as clock source, user doesn't enable ESP_PDP_DOMAIN_RTC8M, or in deep sleep. On later chips, there's no such protection, so 8MD256 could't be used as RTC clock source in sleep modes. This commit adds protection of 8MD256 clock to other chips. Fixes the incorrect protection logic overriding on ESP32. Now the power domain will be determiend by the logic below (order by priority): 1. When RTC clock source uses 8MD256, power up 2. When LEDC uses RTC8M clock source, power up 3. In deepsleep, power down 4. Otherwise determined by user config of ESP_PDP_DOMAIN_RTC8M, power down by default. (This is preferred to have highest priority, but it's kept as is because of current code structure.) 2. Before, after the macro `RTC_SLEEP_CONFIG_DEFAULT` decides dbias, the protection above may force the int8m PU. This may cause the inconsistent of dbias and the int8m PU status. This commit lifts the logic of pd int8m/xtal fpu logic to upper layer (sleep_modes.c). Related: https://github.com/espressif/esp-idf/issues/8007, https://github.com/espressif/esp-idf/pull/8089 temp --- components/esp_hw_support/port/esp32/rtc_clk.c | 5 +++++ .../esp_hw_support/port/esp32/rtc_sleep.c | 9 +-------- .../esp_hw_support/port/esp32c3/rtc_clk.c | 5 +++++ .../esp_hw_support/port/esp32c3/rtc_sleep.c | 4 +--- .../esp_hw_support/port/esp32s2/rtc_clk.c | 5 +++++ .../esp_hw_support/port/esp32s2/rtc_sleep.c | 4 +--- .../esp_hw_support/port/esp32s3/rtc_clk.c | 5 +++++ components/esp_system/sleep_modes.c | 17 ++++++++++++++++- components/soc/esp32/include/soc/rtc.h | 7 ++++++- components/soc/esp32/include/soc/soc_caps.h | 1 + components/soc/esp32c3/include/soc/rtc.h | 9 +++++++-- components/soc/esp32c3/include/soc/soc_caps.h | 2 ++ components/soc/esp32s2/include/soc/rtc.h | 9 +++++++-- components/soc/esp32s2/include/soc/soc_caps.h | 1 + components/soc/esp32s3/include/soc/rtc.h | 5 +++++ 15 files changed, 68 insertions(+), 20 deletions(-) diff --git a/components/esp_hw_support/port/esp32/rtc_clk.c b/components/esp_hw_support/port/esp32/rtc_clk.c index dc20cd378c..a9c246ba84 100644 --- a/components/esp_hw_support/port/esp32/rtc_clk.c +++ b/components/esp_hw_support/port/esp32/rtc_clk.c @@ -786,6 +786,11 @@ void rtc_dig_clk8m_disable(void) esp_rom_delay_us(DELAY_RTC_CLK_SWITCH); } +bool rtc_dig_8m_enabled(void) +{ + return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); +} + /* Name used in libphy.a:phy_chip_v7.o * TODO: update the library to use rtc_clk_xtal_freq_get */ diff --git a/components/esp_hw_support/port/esp32/rtc_sleep.c b/components/esp_hw_support/port/esp32/rtc_sleep.c index 56d338bb7e..b0ee8cedc3 100644 --- a/components/esp_hw_support/port/esp32/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32/rtc_sleep.c @@ -188,14 +188,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu); - if (REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL) == RTC_SLOW_FREQ_8MD256) { - REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); - } else { - REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); - } - //Keep the RTC8M_CLK on in light_sleep mode if the ledc low-speed channel is clocked by RTC8M_CLK. - if (!cfg.int_8m_pd_en && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) { - REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD); + if (!cfg.int_8m_pd_en) { REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); } else { REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); diff --git a/components/esp_hw_support/port/esp32c3/rtc_clk.c b/components/esp_hw_support/port/esp32c3/rtc_clk.c index b34f9c642a..fa931f5e1d 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c3/rtc_clk.c @@ -516,6 +516,11 @@ void rtc_dig_clk8m_disable(void) esp_rom_delay_us(DELAY_RTC_CLK_SWITCH); } +bool rtc_dig_8m_enabled(void) +{ + return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); +} + static bool rtc_clk_set_bbpll_always_on(void) { /* We just keep the rtc bbpll clock on just under the case that diff --git a/components/esp_hw_support/port/esp32c3/rtc_sleep.c b/components/esp_hw_support/port/esp32c3/rtc_sleep.c index cbaa4b689e..f1150910a1 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32c3/rtc_sleep.c @@ -121,9 +121,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) cfg.int_8m_pd_en ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP); } - //Keep the RTC8M_CLK on in light_sleep mode if the ledc low-speed channel is clocked by RTC8M_CLK. - if (!cfg.int_8m_pd_en && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) { - CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD); + if (!cfg.int_8m_pd_en) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING); } else { diff --git a/components/esp_hw_support/port/esp32s2/rtc_clk.c b/components/esp_hw_support/port/esp32s2/rtc_clk.c index 159f815298..e0e0146a59 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_clk.c +++ b/components/esp_hw_support/port/esp32s2/rtc_clk.c @@ -527,6 +527,11 @@ void rtc_dig_clk8m_disable(void) esp_rom_delay_us(DELAY_RTC_CLK_SWITCH); } +bool rtc_dig_8m_enabled(void) +{ + return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); +} + /* Name used in libphy.a:phy_chip_v7.o * TODO: update the library to use rtc_clk_xtal_freq_get */ diff --git a/components/esp_hw_support/port/esp32s2/rtc_sleep.c b/components/esp_hw_support/port/esp32s2/rtc_sleep.c index 9c7ded3249..2f7959d6d9 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32s2/rtc_sleep.c @@ -119,9 +119,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) cfg.int_8m_pd_en ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP); } - //Keep the RTC8M_CLK on in light_sleep mode if the ledc low-speed channel is clocked by RTC8M_CLK. - if (!cfg.int_8m_pd_en && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) { - REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD); + if (!cfg.int_8m_pd_en) { REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); } else { REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); diff --git a/components/esp_hw_support/port/esp32s3/rtc_clk.c b/components/esp_hw_support/port/esp32s3/rtc_clk.c index 56b13a6e15..4645393b91 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_clk.c +++ b/components/esp_hw_support/port/esp32s3/rtc_clk.c @@ -544,6 +544,11 @@ void rtc_dig_clk8m_disable(void) esp_rom_delay_us(DELAY_RTC_CLK_SWITCH); } +bool rtc_dig_8m_enabled(void) +{ + return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); +} + /* Name used in libphy.a:phy_chip_v7.o * TODO: update the library to use rtc_clk_xtal_freq_get */ diff --git a/components/esp_system/sleep_modes.c b/components/esp_system/sleep_modes.c index f1e59e9e6b..5e935bf314 100644 --- a/components/esp_system/sleep_modes.c +++ b/components/esp_system/sleep_modes.c @@ -504,6 +504,20 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags) suspend_uarts(); } +#if SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256 + //Keep the RTC8M_CLK on if RTC clock is 8MD256. + bool rtc_using_8md256 = (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_8MD256); +#else + bool rtc_using_8md256 = false; +#endif + //Keep the RTC8M_CLK on if the ledc low-speed channel is clocked by RTC8M_CLK in lightsleep mode + bool dig_8m_enabled = !deep_sleep && rtc_dig_8m_enabled(); + + //Override user-configured power modes. + if (rtc_using_8md256 || dig_8m_enabled) { + pd_flags &= ~RTC_SLEEP_PD_INT_8M; + } + // Save current frequency and switch to XTAL rtc_cpu_freq_config_t cpu_freq_config; rtc_clk_cpu_freq_get_config(&cpu_freq_config); @@ -562,6 +576,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags) } } #endif + uint32_t reject_triggers = 0; if ((pd_flags & RTC_SLEEP_PD_DIG) == 0 && (s_config.wakeup_triggers & RTC_GPIO_TRIG_EN)) { /* Light sleep, enable sleep reject for faster return from this function, @@ -666,7 +681,7 @@ void IRAM_ATTR esp_deep_sleep_start(void) // Correct the sleep time s_config.sleep_time_adjustment = DEEP_SLEEP_TIME_OVERHEAD_US; - uint32_t force_pd_flags = RTC_SLEEP_PD_DIG | RTC_SLEEP_PD_VDDSDIO; + uint32_t force_pd_flags = RTC_SLEEP_PD_DIG | RTC_SLEEP_PD_VDDSDIO | RTC_SLEEP_PD_INT_8M | RTC_SLEEP_PD_XTAL; #if SOC_PM_SUPPORT_WIFI_PD force_pd_flags |= RTC_SLEEP_PD_WIFI; diff --git a/components/soc/esp32/include/soc/rtc.h b/components/soc/esp32/include/soc/rtc.h index 86ca1cd881..ebdc0b6185 100644 --- a/components/soc/esp32/include/soc/rtc.h +++ b/components/soc/esp32/include/soc/rtc.h @@ -479,6 +479,11 @@ void rtc_dig_clk8m_enable(void); */ void rtc_dig_clk8m_disable(void); +/** + * @brief Get whether the rtc digital 8M clock is enabled + */ +bool rtc_dig_8m_enabled(void); + /** * @brief Calculate the real clock value after the clock calibration * @@ -528,7 +533,7 @@ typedef struct rtc_sleep_config_s { .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ .wifi_pd_en = 0, \ - .int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \ + .int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \ .rom_mem_pd_en = 0, \ .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ .wdt_flashboot_mod_en = 0, \ diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 0ea690ed9a..b5ecd9dca2 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -90,6 +90,7 @@ */ #define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 0) #define SOC_ADC_SUPPORT_RTC_CTRL 1 +#define SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256 (1) /*-------------------------- BROWNOUT CAPS -----------------------------------*/ #if SOC_CAPS_ECO_VER >= 1 diff --git a/components/soc/esp32c3/include/soc/rtc.h b/components/soc/esp32c3/include/soc/rtc.h index 7ac9f8b64c..9a0c95a210 100644 --- a/components/soc/esp32c3/include/soc/rtc.h +++ b/components/soc/esp32c3/include/soc/rtc.h @@ -590,6 +590,11 @@ void rtc_dig_clk8m_enable(void); */ void rtc_dig_clk8m_disable(void); +/** + * @brief Get whether the rtc digital 8M clock is enabled + */ +bool rtc_dig_8m_enabled(void); + /** * @brief Calculate the real clock value after the clock calibration * @@ -674,7 +679,7 @@ typedef struct { .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \ .bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \ .cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \ - .int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \ + .int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \ .dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \ .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ .wdt_flashboot_mod_en = 0, \ @@ -687,7 +692,7 @@ typedef struct { : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ : RTC_CNTL_DBIAS_SLP, \ .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ - .xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \ + .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \ .deep_slp_reject = 1, \ .light_slp_reject = 1 \ }; diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index 68e9f8306a..002c506765 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -140,6 +140,8 @@ #define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)) +#define SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256 (1) + /*-------------------------- RTCIO CAPS --------------------------------------*/ /* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported * for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */ diff --git a/components/soc/esp32s2/include/soc/rtc.h b/components/soc/esp32s2/include/soc/rtc.h index 62fafb2806..053ddeac2f 100644 --- a/components/soc/esp32s2/include/soc/rtc.h +++ b/components/soc/esp32s2/include/soc/rtc.h @@ -620,6 +620,11 @@ void rtc_dig_clk8m_enable(void); */ void rtc_dig_clk8m_disable(void); +/** + * @brief Get whether the rtc digital 8M clock is enabled + */ +bool rtc_dig_8m_enabled(void); + /** * @brief Calculate the real clock value after the clock calibration * @@ -695,7 +700,7 @@ typedef struct { .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \ - .int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \ + .int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \ .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ .wdt_flashboot_mod_en = 0, \ .dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10, \ @@ -709,7 +714,7 @@ typedef struct { : !((sleep_flags) & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_DBIAS_1V10 \ : RTC_CNTL_DBIAS_1V00, \ .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ - .xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \ + .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \ .deep_slp_reject = 1, \ .light_slp_reject = 1 \ }; diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index fcb71e0113..0967f42e75 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -63,6 +63,7 @@ #define SOC_ADC_MAX_CHANNEL_NUM (10) #define SOC_ADC_MAX_BITWIDTH (13) #define SOC_ADC_HW_CALIBRATION_V1 (1) /*!< support HW offset calibration */ +#define SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256 (1) /** diff --git a/components/soc/esp32s3/include/soc/rtc.h b/components/soc/esp32s3/include/soc/rtc.h index 929510a758..593a58613f 100644 --- a/components/soc/esp32s3/include/soc/rtc.h +++ b/components/soc/esp32s3/include/soc/rtc.h @@ -584,6 +584,11 @@ void rtc_dig_clk8m_enable(void); */ void rtc_dig_clk8m_disable(void); +/** + * @brief Get whether the rtc digital 8M clock is enabled + */ +bool rtc_dig_8m_enabled(void); + /** * @brief Calculate the real clock value after the clock calibration * From 81b98881acb2a928c69714130f50fbcc5a1bfecd Mon Sep 17 00:00:00 2001 From: jingli Date: Wed, 27 Jul 2022 18:08:26 +0800 Subject: [PATCH 2/2] esp_hw_support/sleep: fix cannot pd cpu and rc fast at the same time during light sleep Since cpu retention dma use rc fast as clk source, so rc_fast_digi will be enabled when we config to pd cpu. And cpu retention does not need rc fast keep on during light sleep. So, if we use rc_fast_digi to determine whether rc fast can be powered down, then cpu and and rc fast cannot pd at the same time. --- components/driver/ledc.c | 5 +++++ components/esp_system/sleep_modes.c | 11 +++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/components/driver/ledc.c b/components/driver/ledc.c index d8f52de20f..33480a3ee2 100644 --- a/components/driver/ledc.c +++ b/components/driver/ledc.c @@ -265,6 +265,8 @@ esp_err_t ledc_isr_register(void (*fn)(void*), void * arg, int intr_alloc_flags, } // Setting the LEDC timer divisor with the given source clock, frequency and resolution. +extern void esp_sleep_periph_use_8m(bool use_or_not); + static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_num, ledc_clk_cfg_t clk_cfg, int freq_hz, int duty_resolution) { uint32_t div_param = 0; @@ -303,6 +305,9 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n goto error; } if (speed_mode == LEDC_LOW_SPEED_MODE) { + + /* keep ESP_PD_DOMAIN_RTC8M on during light sleep */ + esp_sleep_periph_use_8m(clk_cfg == LEDC_USE_RTC8M_CLK); portENTER_CRITICAL(&ledc_spinlock); ledc_hal_set_slow_clk(&(p_ledc_obj[speed_mode]->ledc_hal), clk_cfg); portEXIT_CRITICAL(&ledc_spinlock); diff --git a/components/esp_system/sleep_modes.c b/components/esp_system/sleep_modes.c index 5e935bf314..4c67c5e6bf 100644 --- a/components/esp_system/sleep_modes.c +++ b/components/esp_system/sleep_modes.c @@ -179,6 +179,13 @@ static portMUX_TYPE spinlock_rtc_deep_sleep = portMUX_INITIALIZER_UNLOCKED; static const char *TAG = "sleep"; +static bool s_periph_use_8m_flag = false; + +void esp_sleep_periph_use_8m(bool use_or_not) +{ + s_periph_use_8m_flag = use_or_not; +} + static uint32_t get_power_down_flags(void); #if SOC_PM_SUPPORT_EXT_WAKEUP static void ext0_wakeup_prepare(void); @@ -511,10 +518,10 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags) bool rtc_using_8md256 = false; #endif //Keep the RTC8M_CLK on if the ledc low-speed channel is clocked by RTC8M_CLK in lightsleep mode - bool dig_8m_enabled = !deep_sleep && rtc_dig_8m_enabled(); + bool periph_using_8m = !deep_sleep && s_periph_use_8m_flag; //Override user-configured power modes. - if (rtc_using_8md256 || dig_8m_enabled) { + if (rtc_using_8md256 || periph_using_8m) { pd_flags &= ~RTC_SLEEP_PD_INT_8M; }