From d5d20920bbb21eac1f32ae644996485c81fe72d5 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 6 Jan 2021 16:24:40 +1100 Subject: [PATCH 1/3] esp32s2: Remove unused option CONFIG_SPIRAM_USE_AHB_DBUS3 --- components/esp32s2/spiram.c | 43 ------------------------------------- 1 file changed, 43 deletions(-) diff --git a/components/esp32s2/spiram.c b/components/esp32s2/spiram.c index e82f0c2ff2..9685dac0b4 100644 --- a/components/esp32s2/spiram.c +++ b/components/esp32s2/spiram.c @@ -135,21 +135,9 @@ void IRAM_ATTR esp_spiram_init_cache(void) Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SPIRAM_SMALL_SIZE_MAP_VADDR, SPIRAM_SMALL_SIZE_MAP_PADDR, 64, SPIRAM_SMALL_SIZE_MAP_SIZE >> 16, 0); REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DRAM1 | EXTMEM_PRO_DCACHE_MASK_DRAM0 | EXTMEM_PRO_DCACHE_MASK_DPORT); } else { -#if CONFIG_SPIRAM_USE_AHB_DBUS3// TODO Ready to remove this macro esp32s2 no AHB bus access cache - if (spiram_size <= DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE) { - /* cache size <= 14MB + 512KB, map DRAM0, DRAM1, DPORT bus, as well as data bus3 */ - Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SPIRAM_MID_SIZE_MAP_VADDR, SPIRAM_MID_SIZE_MAP_PADDR, 64, SPIRAM_MID_SIZE_MAP_SIZE >> 16, 0); - } else { - /* cache size > 14MB + 512KB, map DRAM0, DRAM1, DPORT bus, as well as data bus3 */ - Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SPIRAM_BIG_SIZE_MAP_VADDR, SPIRAM_BIG_SIZE_MAP_PADDR, 64, SPIRAM_BIG_SIZE_MAP_SIZE >> 16, 0); - } - Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SPIRAM_MID_BIG_SIZE_MAP_VADDR, SPIRAM_MID_BIG_SIZE_MAP_PADDR, 64, SPIRAM_MID_BIG_SIZE_MAP_SIZE >> 16, 0); - REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DRAM1 | EXTMEM_PRO_DCACHE_MASK_DRAM0 | EXTMEM_PRO_DCACHE_MASK_DPORT | EXTMEM_PRO_DCACHE_MASK_BUS3); -#else /* cache size > 10MB + 512KB, map DRAM0, DRAM1, DPORT bus , only remap 0x3f500000 ~ 0x3ff90000*/ Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, DPORT_CACHE_ADDRESS_LOW, SPIRAM_SMALL_SIZE_MAP_PADDR, 64, DRAM0_DRAM1_DPORT_CACHE_SIZE >> 16, 0); REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DRAM1 | EXTMEM_PRO_DCACHE_MASK_DRAM0 | EXTMEM_PRO_DCACHE_MASK_DPORT); -#endif } Cache_Resume_DCache(0); } @@ -338,36 +326,6 @@ esp_err_t esp_spiram_add_to_heapalloc(void) /* cache size <= 10MB + 512KB, map DRAM0, DRAM1, DPORT bus */ return heap_caps_add_region((intptr_t)SPIRAM_SMALL_SIZE_MAP_VADDR + size_for_flash, (intptr_t)SPIRAM_SMALL_SIZE_MAP_VADDR + SPIRAM_SMALL_SIZE_MAP_SIZE -1); } else { -#if CONFIG_SPIRAM_USE_AHB_DBUS3 //TODO - if (spiram_size <= DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE) { - /* cache size <= 14MB + 512KB, map DRAM0, DRAM1, DPORT bus, as well as data bus3 */ - if (size_for_flash <= SPIRAM_MID_SIZE_MAP_SIZE) { - esp_err_t err = heap_caps_add_region((intptr_t)SPIRAM_MID_SIZE_MAP_VADDR + size_for_flash, (intptr_t)SPIRAM_MID_SIZE_MAP_VADDR + SPIRAM_MID_SIZE_MAP_SIZE -1); - if (err) { - return err; - } - return heap_caps_add_region((intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR, (intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR + SPIRAM_MID_BIG_SIZE_MAP_SIZE -1); - } else { - return heap_caps_add_region((intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR + size_for_flash - SPIRAM_MID_SIZE_MAP_SIZE, (intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR + SPIRAM_MID_BIG_SIZE_MAP_SIZE -1); - } - } else { - if (size_for_flash <= SPIRAM_SIZE_EXC_DATA_CACHE) { - esp_err_t err = heap_caps_add_region((intptr_t)SPIRAM_BIG_SIZE_MAP_VADDR, (intptr_t)SPIRAM_BIG_SIZE_MAP_VADDR + SPIRAM_BIG_SIZE_MAP_SIZE -1); - if (err) { - return err; - } - return heap_caps_add_region((intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR, (intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR + SPIRAM_MID_BIG_SIZE_MAP_SIZE -1); - } else if (size_for_flash <= SPIRAM_SIZE_EXC_DRAM0_DRAM1_DPORT) { - esp_err_t err = heap_caps_add_region((intptr_t)SPIRAM_BIG_SIZE_MAP_VADDR + size_for_flash - SPIRAM_SIZE_EXC_DATA_CACHE, (intptr_t)SPIRAM_MID_SIZE_MAP_VADDR + SPIRAM_MID_SIZE_MAP_SIZE -1); - if (err) { - return err; - } - return heap_caps_add_region((intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR, (intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR + SPIRAM_MID_BIG_SIZE_MAP_SIZE -1); - } else { - return heap_caps_add_region((intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR + size_for_flash - SPIRAM_SIZE_EXC_DRAM0_DRAM1_DPORT, (intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR + SPIRAM_MID_BIG_SIZE_MAP_SIZE -1); - } - } -#else Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, DPORT_CACHE_ADDRESS_LOW, SPIRAM_SMALL_SIZE_MAP_PADDR, 64, DRAM0_DRAM1_DPORT_CACHE_SIZE >> 16, 0); if (size_for_flash <= SPIRAM_SIZE_EXC_DRAM0_DRAM1_DPORT) { return heap_caps_add_region((intptr_t)DPORT_CACHE_ADDRESS_LOW, (intptr_t)DPORT_CACHE_ADDRESS_LOW + DRAM0_DRAM1_DPORT_CACHE_SIZE -1); @@ -375,7 +333,6 @@ esp_err_t esp_spiram_add_to_heapalloc(void) return heap_caps_add_region((intptr_t)DPORT_CACHE_ADDRESS_LOW + size_for_flash, (intptr_t)DPORT_CACHE_ADDRESS_LOW + DRAM0_DRAM1_DPORT_CACHE_SIZE -1); } return ESP_OK; -#endif } } From 3c13a480d7f7a31a4e67e9c02aeff02a846c5289 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 6 Jan 2021 16:34:29 +1100 Subject: [PATCH 2/3] esp32s2: Simplify the code for adding spiram to heap --- components/esp32s2/spiram.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/components/esp32s2/spiram.c b/components/esp32s2/spiram.c index 9685dac0b4..242d434263 100644 --- a/components/esp32s2/spiram.c +++ b/components/esp32s2/spiram.c @@ -318,22 +318,25 @@ esp_err_t esp_spiram_add_to_heapalloc(void) { size_t spiram_size = esp_spiram_get_size(); uint32_t size_for_flash = (pages_for_flash << 16); + intptr_t vaddr; ESP_EARLY_LOGI(TAG, "Adding pool of %dK of external SPI memory to heap allocator", (spiram_size - (pages_for_flash << 16))/1024); //Add entire external RAM region to heap allocator. Heap allocator knows the capabilities of this type of memory, so there's //no need to explicitly specify them. if (spiram_size <= DRAM0_DRAM1_DPORT_CACHE_SIZE) { /* cache size <= 10MB + 512KB, map DRAM0, DRAM1, DPORT bus */ - return heap_caps_add_region((intptr_t)SPIRAM_SMALL_SIZE_MAP_VADDR + size_for_flash, (intptr_t)SPIRAM_SMALL_SIZE_MAP_VADDR + SPIRAM_SMALL_SIZE_MAP_SIZE -1); - } else { - Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, DPORT_CACHE_ADDRESS_LOW, SPIRAM_SMALL_SIZE_MAP_PADDR, 64, DRAM0_DRAM1_DPORT_CACHE_SIZE >> 16, 0); - if (size_for_flash <= SPIRAM_SIZE_EXC_DRAM0_DRAM1_DPORT) { - return heap_caps_add_region((intptr_t)DPORT_CACHE_ADDRESS_LOW, (intptr_t)DPORT_CACHE_ADDRESS_LOW + DRAM0_DRAM1_DPORT_CACHE_SIZE -1); - } else { - return heap_caps_add_region((intptr_t)DPORT_CACHE_ADDRESS_LOW + size_for_flash, (intptr_t)DPORT_CACHE_ADDRESS_LOW + DRAM0_DRAM1_DPORT_CACHE_SIZE -1); - } - return ESP_OK; + vaddr = SPIRAM_SMALL_SIZE_MAP_VADDR; + return heap_caps_add_region(vaddr + size_for_flash, vaddr + spiram_size - 1); } + + vaddr = DPORT_CACHE_ADDRESS_LOW; + Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, vaddr, SPIRAM_SMALL_SIZE_MAP_PADDR, 64, DRAM0_DRAM1_DPORT_CACHE_SIZE >> 16, 0); + if (size_for_flash <= SPIRAM_SIZE_EXC_DRAM0_DRAM1_DPORT) { + return heap_caps_add_region(vaddr, vaddr + DRAM0_DRAM1_DPORT_CACHE_SIZE - 1); + } + + // Largest size + return heap_caps_add_region(vaddr + size_for_flash, vaddr + DRAM0_DRAM1_DPORT_CACHE_SIZE -1); } From 7c55633bfb187e9190af75332de584b17d6410ae Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 6 Jan 2021 16:36:52 +1100 Subject: [PATCH 3/3] esp_common: Correctly disable ".bss segment placed in external memory" for ESP32-S2 & ESP32-S3 Support for this feature is still pending. As reported by https://github.com/espressif/esp-idf/issues/6162 --- components/esp_common/Kconfig.spiram.common | 2 +- docs/en/api-guides/external-ram.rst | 29 +++++++++-------- docs/zh_CN/api-guides/external-ram.rst | 35 ++++++++++++--------- 3 files changed, 38 insertions(+), 28 deletions(-) diff --git a/components/esp_common/Kconfig.spiram.common b/components/esp_common/Kconfig.spiram.common index b7229bd49d..e10d5cf588 100644 --- a/components/esp_common/Kconfig.spiram.common +++ b/components/esp_common/Kconfig.spiram.common @@ -92,7 +92,7 @@ config SPIRAM_MALLOC_RESERVE_INTERNAL config SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY bool "Allow .bss segment placed in external memory" default n - depends on SPIRAM + depends on SPIRAM && IDF_TARGET_ESP32 # TODO ESP32-S2 IDFGH-4320, ESP32-S3 IDF-1974 select ESP_ALLOW_BSS_SEG_EXTERNAL_MEMORY help If enabled, variables with EXT_RAM_ATTR attribute will be placed in SPIRAM instead of internal DRAM. diff --git a/docs/en/api-guides/external-ram.rst b/docs/en/api-guides/external-ram.rst index 5679b75292..bef78f97c1 100644 --- a/docs/en/api-guides/external-ram.rst +++ b/docs/en/api-guides/external-ram.rst @@ -31,10 +31,12 @@ Configuring External RAM ESP-IDF fully supports the use of external memory in applications. Once the external RAM is initialized at startup, ESP-IDF can be configured to handle it in several ways: - * :ref:`external_ram_config_memory_map` - * :ref:`external_ram_config_capability_allocator` - * :ref:`external_ram_config_malloc` (default) - * :ref:`external_ram_config_bss` +.. list:: + + * :ref:`external_ram_config_memory_map` + * :ref:`external_ram_config_capability_allocator` + * :ref:`external_ram_config_malloc` (default) + :esp32: * :ref:`external_ram_config_bss` .. _external_ram_config_memory_map: @@ -83,23 +85,24 @@ If a suitable block of preferred internal/external memory is not available, the Because some buffers can only be allocated in internal memory, a second configuration item :ref:`CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL` defines a pool of internal memory which is reserved for *only* explicitly internal allocations (such as memory for DMA use). Regular ``malloc()`` will not allocate from this pool. The :ref:`MALLOC_CAP_DMA ` and ``MALLOC_CAP_INTERNAL`` flags can be used to allocate memory from this pool. -.. _external_ram_config_bss: +.. only:: esp32 + .. _external_ram_config_bss: -Allow .bss segment placed in external memory --------------------------------------------- + Allow .bss segment placed in external memory + -------------------------------------------- -Enable this option by checking :ref:`CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY`. This configuration setting is independent of the other three. + Enable this option by checking :ref:`CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY`. This configuration setting is independent of the other three. -If enabled, a region of the address space starting from 0x3F800000 will be used to store zero-initialized data (BSS segment) from the lwIP, net80211, libpp, and bluedroid ESP-IDF libraries. + If enabled, a region of the address space starting from 0x3F800000 will be used to store zero-initialized data (BSS segment) from the lwIP, net80211, libpp, and bluedroid ESP-IDF libraries. -Additional data can be moved from the internal BSS segment to external RAM by applying the macro ``EXT_RAM_ATTR`` to any static declaration (which is not initialized to a non-zero value). + Additional data can be moved from the internal BSS segment to external RAM by applying the macro ``EXT_RAM_ATTR`` to any static declaration (which is not initialized to a non-zero value). -It is also possible to place the BSS section of a component or a library to external RAM using linker fragment scheme ``extram_bss``. + It is also possible to place the BSS section of a component or a library to external RAM using linker fragment scheme ``extram_bss``. -This option reduces the internal static memory used by the BSS segment. + This option reduces the internal static memory used by the BSS segment. -Remaining external RAM can also be added to the capability heap allocator using the method shown above. + Remaining external RAM can also be added to the capability heap allocator using the method shown above. Restrictions diff --git a/docs/zh_CN/api-guides/external-ram.rst b/docs/zh_CN/api-guides/external-ram.rst index 644deab265..b0cea63e42 100644 --- a/docs/zh_CN/api-guides/external-ram.rst +++ b/docs/zh_CN/api-guides/external-ram.rst @@ -31,10 +31,12 @@ ESP-IDF 完全支持将外部存储器集成到您的应用程序中。在启动并完成片外 RAM 初始化后，可以将 ESP-IDF 配置为以多种方式处理片外 RAM： - * :ref:`external_ram_config_memory_map` - * :ref:`external_ram_config_capability_allocator` - * :ref:`external_ram_config_malloc` （默认） - * :ref:`external_ram_config_bss` +.. list:: + + * :ref:`external_ram_config_memory_map` + * :ref:`external_ram_config_capability_allocator` + * :ref:`external_ram_config_malloc` （默认） + :esp32: * :ref:`external_ram_config_bss` .. _external_ram_config_memory_map: @@ -83,23 +85,25 @@ ESP-IDF 启动过程中，片外 RAM 被映射到以 0x3F800000 起始的数据 由于有些 Buffer 仅可在内部存储器中分配，因此需要使用第二个配置项 :ref:`CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL` 定义一个内部存储池，仅限显式的内部存储器分配使用（例如用于 DMA 的存储器）。常规 ``malloc()`` 将不会从该池中分配，但可以使用 :ref:`MALLOC_CAP_DMA ` 和 ``MALLOC_CAP_INTERNAL`` 旗标从该池中分配存储器。 -.. _external_ram_config_bss: +.. only:: esp32 + + .. _external_ram_config_bss: -允许 .bss 段放入片外存储器 ------------------------------ + 允许 .bss 段放入片外存储器 + ----------------------------- -通过检查 :ref:`CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY` 启用该选项，此选项配置与上面三个选项互不影响。 + 通过检查 :ref:`CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY` 启用该选项，此选项配置与上面三个选项互不影响。 -启用该选项后，从 0x3F800000 起始的地址空间将用于存储来自 lwip、net80211、libpp 和 bluedroid ESP-IDF 库中零初始化的数据（BSS 段）。 + 启用该选项后，从 0x3F800000 起始的地址空间将用于存储来自 lwip、net80211、libpp 和 bluedroid ESP-IDF 库中零初始化的数据（BSS 段）。 -``EXT_RAM_ATTR`` 宏应用于任何静态声明（未初始化为非零值）之后，可以将附加数据从内部 BSS 段移到片外 RAM。 + ``EXT_RAM_ATTR`` 宏应用于任何静态声明（未初始化为非零值）之后，可以将附加数据从内部 BSS 段移到片外 RAM。 -也可以使用链接器片段方案 ``extram_bss`` 将组件或库的 BSS 段放到片外 RAM 中。 + 也可以使用链接器片段方案 ``extram_bss`` 将组件或库的 BSS 段放到片外 RAM 中。 -启用此选项可以减少 BSS 段占用的内部静态存储。 + 启用此选项可以减少 BSS 段占用的内部静态存储。 -剩余的片外 RAM 也可以通过上述方法添加到堆分配器中。 + 剩余的片外 RAM 也可以通过上述方法添加到堆分配器中。 片外 RAM 使用限制 =================== @@ -114,8 +118,11 @@ ESP-IDF 启动过程中，片外 RAM 被映射到以 0x3F800000 起始的数据 * 片外 RAM 不可用作任务堆栈存储器。因此 :cpp:func:`xTaskCreate` 及类似函数将始终为堆栈和任务 TCB 分配片上储存器，而 :cpp:func:`xTaskCreateStatic` 类型的函数将检查传递的 Buffer 是否属于片上存储器。 - * 默认情况下，片外 RAM 初始化失败将终止 ESP-IDF 启动。如果想禁用此功能，可启用 :ref:`CONFIG_SPIRAM_IGNORE_NOTFOUND` 配置选项。如果启用 :ref:`CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY`，:ref:`CONFIG_SPIRAM_IGNORE_NOTFOUND` 选项将不能使用，这是因为在链接时，链接器已经向片外 RAM 分配符号。 + * 默认情况下，片外 RAM 初始化失败将终止 ESP-IDF 启动。如果想禁用此功能，可启用 :ref:`CONFIG_SPIRAM_IGNORE_NOTFOUND` 配置选项。 +.. only:: esp32 + + 如果启用 :ref:`CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY`，:ref:`CONFIG_SPIRAM_IGNORE_NOTFOUND` 选项将不能使用，这是因为在链接时，链接器已经向片外 RAM 分配符号。 .. only:: esp32