coredump: Fixes ESP-specific panic reasons handling

components/esp32/panic.c

@@ -222,6 +222,13 @@ static void setFirstBreakpoint(uint32_t pc)
 static volatile XtExcFrame * other_core_frame = NULL;
 #endif //!CONFIG_FREERTOS_UNICORE
 
+// panicHandler() gets called for when the double exception vector,
+// kernel exception vector gets used; as well as handling interrupt-based
+// faults cache error, wdt expiry. EXCAUSE register gets written with
+// one of PANIC_RSN_* values.
+// This flag indicate condition described above. Used by coredump to handle pseuso excauses properly.
+bool g_panic_pseudo_excause;
+
 void panicHandler(XtExcFrame *frame)
 {
     int core_id = xPortGetCoreID();
@@ -241,6 +248,7 @@ void panicHandler(XtExcFrame *frame)
     if (frame->exccause <= PANIC_RSN_MAX) {
         reason = reasons[frame->exccause];
     }
+    g_panic_pseudo_excause = true;
 
 #if !CONFIG_FREERTOS_UNICORE
     //Save frame for other core.

components/esp32s2beta/panic.c

@@ -302,6 +302,13 @@ static inline void printCacheError(void)
     panicPutStr("\r\n");
 }
 
+// panicHandler() gets called for when the double exception vector,
+// kernel exception vector gets used; as well as handling interrupt-based
+// faults cache error, wdt expiry. EXCAUSE register gets written with
+// one of PANIC_RSN_* values.
+// This flag indicate condition described above. Used by coredump to handle pseuso excauses properly.
+bool g_panic_pseudo_excause;
+
 void panicHandler(XtExcFrame *frame)
 {
     int core_id = xPortGetCoreID();
@@ -321,6 +328,7 @@ void panicHandler(XtExcFrame *frame)
     if (frame->exccause <= PANIC_RSN_MAX) {
         reason = reasons[frame->exccause];
     }
+    g_panic_pseudo_excause = true;
 
     if (frame->exccause == PANIC_RSN_INTWDT_CPU0) {
         esp_reset_reason_set_hint(ESP_RST_INT_WDT);

components/espcoredump/espcoredump.py

@@ -47,6 +47,7 @@ else:
     CLOSE_FDS = True
 
 INVALID_CAUSE_VALUE = 0xFFFF
+XCHAL_EXCCAUSE_NUM = 64
 
 # Exception cause dictionary to get translation of exccause register
 # From 4.4.1.5 table 4-64 Exception Causes of Xtensa
@@ -82,7 +83,17 @@ xtensa_exception_cause_dict = {
     37: ("Coprocessor5Disabled", "Coprocessor 5 instruction when cp5 disabled"),
     38: ("Coprocessor6Disabled", "Coprocessor 6 instruction when cp6 disabled"),
     39: ("Coprocessor7Disabled", "Coprocessor 7 instruction when cp7 disabled"),
-    INVALID_CAUSE_VALUE: ("InvalidCauseRegister", "Invalid EXCCAUSE register value or current task is broken and was skipped")}
+    INVALID_CAUSE_VALUE: ("InvalidCauseRegister", "Invalid EXCCAUSE register value or current task is broken and was skipped"),
+    # ESP panic pseudo reasons
+    XCHAL_EXCCAUSE_NUM + 0: ("UnknownException", "Unknown exception"),
+    XCHAL_EXCCAUSE_NUM + 1: ("DebugException", "Unhandled debug exception"),
+    XCHAL_EXCCAUSE_NUM + 2: ("DoubleException", "Double exception"),
+    XCHAL_EXCCAUSE_NUM + 3: ("KernelException", "Unhandled kernel exception"),
+    XCHAL_EXCCAUSE_NUM + 4: ("CoprocessorException", "Coprocessor exception"),
+    XCHAL_EXCCAUSE_NUM + 5: ("InterruptWDTTimoutCPU0", "Interrupt wdt timeout on CPU0"),
+    XCHAL_EXCCAUSE_NUM + 6: ("InterruptWDTTimoutCPU1", "Interrupt wdt timeout on CPU1"),
+    XCHAL_EXCCAUSE_NUM + 7: ("CacheError", "Cache disabled but cached memory region accessed"),
+}
 
 
 class ESPCoreDumpError(RuntimeError):

components/espcoredump/src/core_dump_port.c

@@ -461,6 +461,10 @@ bool esp_core_dump_check_task(void *frame,
             task->stack_start = (uint32_t)exc_frame;
         }
         exc_frame->exit = COREDUMP_CURR_TASK_MARKER;
+        extern bool g_panic_pseudo_excause;
+        if (g_panic_pseudo_excause) {
+            exc_frame->exccause += XCHAL_EXCCAUSE_NUM;
+        }
         s_extra_info.crashed_task_tcb = (uint32_t)task->tcb_addr;
     }