diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c index 7d2badf83a..cce391e45a 100644 --- a/components/bootloader_support/src/bootloader_utility.c +++ b/components/bootloader_support/src/bootloader_utility.c @@ -24,7 +24,6 @@ #include "soc/rtc.h" #include "soc/efuse_periph.h" #include "soc/rtc_periph.h" -#include "soc/timer_periph.h" #include "hal/mmu_hal.h" #include "hal/mmu_ll.h" #include "hal/cache_types.h" diff --git a/components/esp_driver_gptimer/CMakeLists.txt b/components/esp_driver_gptimer/CMakeLists.txt index 143387a4d3..55b8a07851 100644 --- a/components/esp_driver_gptimer/CMakeLists.txt +++ b/components/esp_driver_gptimer/CMakeLists.txt @@ -14,7 +14,7 @@ if(CONFIG_SOC_TIMER_SUPPORT_ETM) list(APPEND srcs "src/gptimer_etm.c") endif() -set(requires esp_pm) +set(requires esp_pm esp_hal_timg) idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${public_include} diff --git a/components/esp_driver_gptimer/linker.lf b/components/esp_driver_gptimer/linker.lf index 72f9e6eafd..80abf4c617 100644 --- a/components/esp_driver_gptimer/linker.lf +++ b/components/esp_driver_gptimer/linker.lf @@ -12,7 +12,7 @@ entries: gptimer: gptimer_stop (noflash) [mapping:gptimer_hal] -archive: libhal.a +archive: libesp_hal_timg.a entries: if GPTIMER_ISR_HANDLER_IN_IRAM = y: timer_hal: timer_hal_capture_and_get_counter_value (noflash) diff --git a/components/esp_driver_gptimer/src/gptimer_common.c b/components/esp_driver_gptimer/src/gptimer_common.c index b06f5f17c8..4152393836 100644 --- a/components/esp_driver_gptimer/src/gptimer_common.c +++ b/components/esp_driver_gptimer/src/gptimer_common.c @@ -50,8 +50,8 @@ gptimer_group_t *gptimer_acquire_group_handle(int group_id) // we need to increase/decrease the reference count before enable/disable/reset the peripheral PERIPH_RCC_ACQUIRE_ATOMIC(soc_timg_gptimer_signals[group_id][0].parent_module, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(group_id, true); - timer_ll_reset_register(group_id); + timg_ll_enable_bus_clock(group_id, true); + timg_ll_reset_register(group_id); } } ESP_LOGD(TAG, "new group (%d) @%p", group_id, group); @@ -78,7 +78,7 @@ void gptimer_release_group_handle(gptimer_group_t *group) // disable bus clock for the timer group PERIPH_RCC_RELEASE_ATOMIC(soc_timg_gptimer_signals[group_id][0].parent_module, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(group_id, false); + timg_ll_enable_bus_clock(group_id, false); } } free(group); diff --git a/components/esp_driver_gptimer/test_apps/.build-test-rules.yml b/components/esp_driver_gptimer/test_apps/.build-test-rules.yml index a48c8d7cfc..574443fadd 100644 --- a/components/esp_driver_gptimer/test_apps/.build-test-rules.yml +++ b/components/esp_driver_gptimer/test_apps/.build-test-rules.yml @@ -5,3 +5,4 @@ components/esp_driver_gptimer/test_apps/gptimer: - if: SOC_GPTIMER_SUPPORTED != 1 depends_components: - esp_driver_gptimer + - esp_hal_timg diff --git a/components/esp_hal_timg/CMakeLists.txt b/components/esp_hal_timg/CMakeLists.txt new file mode 100644 index 0000000000..2175c49abe --- /dev/null +++ b/components/esp_hal_timg/CMakeLists.txt @@ -0,0 +1,15 @@ +idf_build_get_property(target IDF_TARGET) +if(${target} STREQUAL "linux") + return() # This component is not supported by the POSIX/Linux simulator +endif() + +set(srcs) +set(public_include "include" "${target}/include") + +if(CONFIG_SOC_GPTIMER_SUPPORTED) + list(APPEND srcs "timer_hal.c" "${target}/timer_periph.c") +endif() + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS ${public_include} + REQUIRES soc hal) diff --git a/components/esp_hal_timg/README.md b/components/esp_hal_timg/README.md new file mode 100644 index 0000000000..7e05e28019 --- /dev/null +++ b/components/esp_hal_timg/README.md @@ -0,0 +1,42 @@ +# ESP Hardware Abstraction Layer for Timer Groups (`esp_hal_timg`) + +⚠️ **Notice**: This HAL component is under active development. API stability and backward-compatibility between versions are not guaranteed at this time. + +## Overview + +The `esp_hal_timg` component provides a **Hardware Abstraction Layer** for the General Purpose Timer peripherals across all ESP-IDF supported targets. It serves as a foundation for the higher-level timer drivers, offering a consistent interface to interact with timer hardware while hiding the complexities of chip-specific implementations. + +## Architecture + +The HAL architecture consists of two primary layers: + +1. **HAL Layer (Upper)**: Defines the operational sequences and data structures required to interact with timer peripherals, including: + - Initialization and deinitialization + - Timer control operations (start, stop, reload) + - Alarm and event handling + - Counter operations + +2. **Low-Level Layer (Bottom)**: Acts as a translation layer between the HAL and the register definitions in the `soc` component, handling: + - Register access abstractions + - Chip-specific register configurations + - Hardware feature compatibility + +## Features + +- Unified timer interface across all ESP chip families +- Support for different timer counting modes (up/down) +- Alarm functionality with configurable triggers +- Auto-reload capability +- ETM (Event Task Matrix) integration on supported chips +- Multiple clock source options + +## Usage + +This component is primarily used by ESP-IDF peripheral drivers such as `esp_driver_gptimer`. It is also utilized by system components like `esp_timer`. + +For advanced developers implementing custom timer solutions, the HAL functions can be used directly. However, please note that the interfaces provided by this component are internal to ESP-IDF and are subject to change. + +## Dependencies + +- `soc`: Provides chip-specific register definitions +- `hal`: Core hardware abstraction utilities and macros diff --git a/components/esp_hal_timg/esp32/include/hal/lact_ll.h b/components/esp_hal_timg/esp32/include/hal/lact_ll.h new file mode 100644 index 0000000000..c18aa71eaf --- /dev/null +++ b/components/esp_hal_timg/esp32/include/hal/lact_ll.h @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "hal/timg_ll.h" +#include "soc/timer_group_struct.h" +#include "soc/dport_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Get timer group register base address with giving group number +#define LACT_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1)) + +/** + * @brief Set clock prescale for LACT timer + * + * @param hw Timer Group register base address + * @param divider Prescale value (0 and 1 are not valid) + */ +__attribute__((always_inline)) +static inline void lact_ll_set_clock_prescale(timg_dev_t *hw, uint32_t divider) +{ + HAL_ASSERT(divider >= 2); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->lactconfig, lact_divider, divider); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32/include/hal/timer_ll.h b/components/esp_hal_timg/esp32/include/hal/timer_ll.h similarity index 72% rename from components/hal/esp32/include/hal/timer_ll.h rename to components/esp_hal_timg/esp32/include/hal/timer_ll.h index a50ce38770..ff65508326 100644 --- a/components/hal/esp32/include/hal/timer_ll.h +++ b/components/esp_hal_timg/esp32/include/hal/timer_ll.h @@ -4,9 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. -// This Low Level driver only serve the General Purpose Timer function. - #pragma once #include @@ -14,6 +11,7 @@ #include "hal/assert.h" #include "hal/misc.h" #include "hal/timer_types.h" +#include "hal/timg_ll.h" #include "soc/timer_group_struct.h" #include "soc/dport_reg.h" @@ -30,61 +28,6 @@ extern "C" { // Support APB as function clock #define TIMER_LL_FUNC_CLOCK_SUPPORT_APB 1 -/** - * @brief Enable the bus clock for timer group module - * - * @param group_id Group ID - * @param enable true to enable, false to disable - */ -static inline void _timer_ll_enable_bus_clock(int group_id, bool enable) -{ - uint32_t reg_val = DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG); - if (group_id == 0) { - reg_val &= ~DPORT_TIMERGROUP_CLK_EN; - reg_val |= enable << 13; - } else { - reg_val &= ~DPORT_TIMERGROUP1_CLK_EN; - reg_val |= enable << 15; - } - DPORT_WRITE_PERI_REG(DPORT_PERIP_CLK_EN_REG, reg_val); -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_enable_bus_clock(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_enable_bus_clock(__VA_ARGS__); \ - } while(0) - -/** - * @brief Reset the timer group module - * - * @note After reset the register, the "flash boot protection" will be enabled again. - * FLash boot protection is not used anymore after system boot up. - * This function will disable it by default in order to prevent the system from being reset unexpectedly. - * - * @param group_id Group ID - */ -static inline void _timer_ll_reset_register(int group_id) -{ - if (group_id == 0) { - DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP_RST); - DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, 0); - TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; - } else { - DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP1_RST); - DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, 0); - TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; - } -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_reset_register(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_reset_register(__VA_ARGS__); \ - } while(0) - /** * @brief Set clock source for timer * @@ -233,8 +176,8 @@ static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer __attribute__((always_inline)) static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, uint64_t alarm_value) { - hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t) (alarm_value >> 32); - hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (uint32_t) alarm_value; + hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t)(alarm_value >> 32); + hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (uint32_t)alarm_value; } /** @@ -247,8 +190,8 @@ static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, __attribute__((always_inline)) static inline void timer_ll_set_reload_value(timg_dev_t *hw, uint32_t timer_num, uint64_t load_val) { - hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t) (load_val >> 32); - hw->hw_timer[timer_num].loadlo.tx_load_lo = (uint32_t) load_val; + hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t)(load_val >> 32); + hw->hw_timer[timer_num].loadlo.tx_load_lo = (uint32_t)load_val; } /** @@ -343,19 +286,6 @@ static inline volatile void *timer_ll_get_intr_status_reg(timg_dev_t *hw) return &hw->int_st_timers.val; } -/** - * @brief Set clock prescale for LACT timer - * - * @param hw Timer Group register base address - * @param timer_num Timer number in the group - * @param divider Prescale value (0 and 1 are not valid) - */ -FORCE_INLINE_ATTR void timer_ll_set_lact_clock_prescale(timg_dev_t *hw, uint32_t divider) -{ - HAL_ASSERT(divider>=2); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->lactconfig, lact_divider, divider); -} - #ifdef __cplusplus } #endif diff --git a/components/esp_hal_timg/esp32/include/hal/timg_ll.h b/components/esp_hal_timg/esp32/include/hal/timg_ll.h new file mode 100644 index 0000000000..faeb88a2da --- /dev/null +++ b/components/esp_hal_timg/esp32/include/hal/timg_ll.h @@ -0,0 +1,78 @@ +/* + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/timer_group_struct.h" +#include "soc/dport_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the bus clock for timer group module + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void _timg_ll_enable_bus_clock(int group_id, bool enable) +{ + uint32_t reg_val = DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG); + if (group_id == 0) { + reg_val &= ~DPORT_TIMERGROUP_CLK_EN; + reg_val |= enable << 13; + } else { + reg_val &= ~DPORT_TIMERGROUP1_CLK_EN; + reg_val |= enable << 15; + } + DPORT_WRITE_PERI_REG(DPORT_PERIP_CLK_EN_REG, reg_val); +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_enable_bus_clock(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_enable_bus_clock(__VA_ARGS__); \ + } while(0) + +/** + * @brief Reset the timer group module + * + * @note After reset the register, the "flash boot protection" will be enabled again. + * FLash boot protection is not used anymore after system boot up. + * This function will disable it by default in order to prevent the system from being reset unexpectedly. + * + * @param group_id Group ID + */ +static inline void _timg_ll_reset_register(int group_id) +{ + if (group_id == 0) { + DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP_RST); + DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, 0); + TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; + } else { + DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP1_RST); + DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, 0); + TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_reset_register(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_reset_register(__VA_ARGS__); \ + } while(0) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32/timer_periph.c b/components/esp_hal_timg/esp32/timer_periph.c similarity index 100% rename from components/soc/esp32/timer_periph.c rename to components/esp_hal_timg/esp32/timer_periph.c diff --git a/components/hal/esp32c2/include/hal/timer_ll.h b/components/esp_hal_timg/esp32c2/include/hal/timer_ll.h similarity index 80% rename from components/hal/esp32c2/include/hal/timer_ll.h rename to components/esp_hal_timg/esp32c2/include/hal/timer_ll.h index 6e9430b95d..9b620f887e 100644 --- a/components/hal/esp32c2/include/hal/timer_ll.h +++ b/components/esp_hal_timg/esp32c2/include/hal/timer_ll.h @@ -4,15 +4,13 @@ * SPDX-License-Identifier: Apache-2.0 */ -// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. -// This Low Level driver only serve the General Purpose Timer function. - #pragma once #include #include "hal/assert.h" #include "hal/misc.h" #include "hal/timer_types.h" +#include "hal/timg_ll.h" #include "soc/timer_group_struct.h" #include "soc/system_struct.h" @@ -24,49 +22,6 @@ extern "C" { #define TIMER_LL_GET_HW(group_id) (&TIMERG0) #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id)) -/** - * @brief Enable the bus clock for timer group module - * - * @param group_id Group ID - * @param enable true to enable, false to disable - */ -static inline void _timer_ll_enable_bus_clock(int group_id, bool enable) -{ - (void)group_id; - SYSTEM.perip_clk_en0.timergroup_clk_en = enable; -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_enable_bus_clock(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_enable_bus_clock(__VA_ARGS__); \ - } while(0) - -/** - * @brief Reset the timer group module - * - * @note After reset the register, the "flash boot protection" will be enabled again. - * FLash boot protection is not used anymore after system boot up. - * This function will disable it by default in order to prevent the system from being reset unexpectedly. - * - * @param group_id Group ID - */ -static inline void _timer_ll_reset_register(int group_id) -{ - (void)group_id; - SYSTEM.perip_rst_en0.timergroup_rst = 1; - SYSTEM.perip_rst_en0.timergroup_rst = 0; - TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_reset_register(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_reset_register(__VA_ARGS__); \ - } while(0) - /** * @brief Set clock source for timer * @@ -215,7 +170,7 @@ static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer __attribute__((always_inline)) static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, uint64_t alarm_value) { - hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t) (alarm_value >> 32); + hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t)(alarm_value >> 32); hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (uint32_t) alarm_value; } @@ -229,7 +184,7 @@ static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, __attribute__((always_inline)) static inline void timer_ll_set_reload_value(timg_dev_t *hw, uint32_t timer_num, uint64_t load_val) { - hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t) (load_val >> 32); + hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t)(load_val >> 32); hw->hw_timer[timer_num].loadlo.tx_load_lo = (uint32_t) load_val; } diff --git a/components/esp_hal_timg/esp32c2/include/hal/timg_ll.h b/components/esp_hal_timg/esp32c2/include/hal/timg_ll.h new file mode 100644 index 0000000000..c57a836fb6 --- /dev/null +++ b/components/esp_hal_timg/esp32c2/include/hal/timg_ll.h @@ -0,0 +1,66 @@ +/* + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/timer_group_struct.h" +#include "soc/system_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the bus clock for timer group module + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void _timg_ll_enable_bus_clock(int group_id, bool enable) +{ + (void)group_id; + SYSTEM.perip_clk_en0.timergroup_clk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_enable_bus_clock(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_enable_bus_clock(__VA_ARGS__); \ + } while(0) + +/** + * @brief Reset the timer group module + * + * @note After reset the register, the "flash boot protection" will be enabled again. + * FLash boot protection is not used anymore after system boot up. + * This function will disable it by default in order to prevent the system from being reset unexpectedly. + * + * @param group_id Group ID + */ +static inline void _timg_ll_reset_register(int group_id) +{ + (void)group_id; + SYSTEM.perip_rst_en0.timergroup_rst = 1; + SYSTEM.perip_rst_en0.timergroup_rst = 0; + TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_reset_register(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_reset_register(__VA_ARGS__); \ + } while(0) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c2/timer_periph.c b/components/esp_hal_timg/esp32c2/timer_periph.c similarity index 100% rename from components/soc/esp32c2/timer_periph.c rename to components/esp_hal_timg/esp32c2/timer_periph.c diff --git a/components/hal/esp32c3/include/hal/timer_ll.h b/components/esp_hal_timg/esp32c3/include/hal/timer_ll.h similarity index 78% rename from components/hal/esp32c3/include/hal/timer_ll.h rename to components/esp_hal_timg/esp32c3/include/hal/timer_ll.h index 06a02c72c8..17581316c2 100644 --- a/components/hal/esp32c3/include/hal/timer_ll.h +++ b/components/esp_hal_timg/esp32c3/include/hal/timer_ll.h @@ -4,15 +4,13 @@ * SPDX-License-Identifier: Apache-2.0 */ -// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. -// This Low Level driver only serve the General Purpose Timer function. - #pragma once #include #include "hal/assert.h" #include "hal/misc.h" #include "hal/timer_types.h" +#include "hal/timg_ll.h" #include "soc/timer_group_struct.h" #include "soc/system_struct.h" @@ -29,57 +27,6 @@ extern "C" { // Support APB as function clock #define TIMER_LL_FUNC_CLOCK_SUPPORT_APB 1 -/** - * @brief Enable the bus clock for timer group module - * - * @param group_id Group ID - * @param enable true to enable, false to disable - */ -static inline void _timer_ll_enable_bus_clock(int group_id, bool enable) -{ - if (group_id == 0) { - SYSTEM.perip_clk_en0.reg_timergroup_clk_en = enable; - } else { - SYSTEM.perip_clk_en0.reg_timergroup1_clk_en = enable; - } -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_enable_bus_clock(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_enable_bus_clock(__VA_ARGS__); \ - } while(0) - -/** - * @brief Reset the timer group module - * - * @note After reset the register, the "flash boot protection" will be enabled again. - * FLash boot protection is not used anymore after system boot up. - * This function will disable it by default in order to prevent the system from being reset unexpectedly. - * - * @param group_id Group ID - */ -static inline void _timer_ll_reset_register(int group_id) -{ - if (group_id == 0) { - SYSTEM.perip_rst_en0.reg_timergroup_rst = 1; - SYSTEM.perip_rst_en0.reg_timergroup_rst = 0; - TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; - } else { - SYSTEM.perip_rst_en0.reg_timergroup1_rst = 1; - SYSTEM.perip_rst_en0.reg_timergroup1_rst = 0; - TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; - } -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_reset_register(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_reset_register(__VA_ARGS__); \ - } while(0) - /** * @brief Set clock source for timer * @@ -228,7 +175,7 @@ static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer __attribute__((always_inline)) static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, uint64_t alarm_value) { - hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t) (alarm_value >> 32); + hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t)(alarm_value >> 32); hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (uint32_t) alarm_value; } @@ -242,7 +189,7 @@ static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, __attribute__((always_inline)) static inline void timer_ll_set_reload_value(timg_dev_t *hw, uint32_t timer_num, uint64_t load_val) { - hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t) (load_val >> 32); + hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t)(load_val >> 32); hw->hw_timer[timer_num].loadlo.tx_load_lo = (uint32_t) load_val; } diff --git a/components/esp_hal_timg/esp32c3/include/hal/timg_ll.h b/components/esp_hal_timg/esp32c3/include/hal/timg_ll.h new file mode 100644 index 0000000000..fd7f0c7fee --- /dev/null +++ b/components/esp_hal_timg/esp32c3/include/hal/timg_ll.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/timer_group_struct.h" +#include "soc/system_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the bus clock for timer group module + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void _timg_ll_enable_bus_clock(int group_id, bool enable) +{ + if (group_id == 0) { + SYSTEM.perip_clk_en0.reg_timergroup_clk_en = enable; + } else { + SYSTEM.perip_clk_en0.reg_timergroup1_clk_en = enable; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_enable_bus_clock(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_enable_bus_clock(__VA_ARGS__); \ + } while(0) + +/** + * @brief Reset the timer group module + * + * @note After reset the register, the "flash boot protection" will be enabled again. + * FLash boot protection is not used anymore after system boot up. + * This function will disable it by default in order to prevent the system from being reset unexpectedly. + * + * @param group_id Group ID + */ +static inline void _timg_ll_reset_register(int group_id) +{ + if (group_id == 0) { + SYSTEM.perip_rst_en0.reg_timergroup_rst = 1; + SYSTEM.perip_rst_en0.reg_timergroup_rst = 0; + TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; + } else { + SYSTEM.perip_rst_en0.reg_timergroup1_rst = 1; + SYSTEM.perip_rst_en0.reg_timergroup1_rst = 0; + TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_reset_register(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_reset_register(__VA_ARGS__); \ + } while(0) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c3/timer_periph.c b/components/esp_hal_timg/esp32c3/timer_periph.c similarity index 100% rename from components/soc/esp32c3/timer_periph.c rename to components/esp_hal_timg/esp32c3/timer_periph.c diff --git a/components/hal/esp32c5/include/hal/timer_ll.h b/components/esp_hal_timg/esp32c5/include/hal/timer_ll.h similarity index 84% rename from components/hal/esp32c5/include/hal/timer_ll.h rename to components/esp_hal_timg/esp32c5/include/hal/timer_ll.h index d4c0d11101..8f2a2fd264 100644 --- a/components/hal/esp32c5/include/hal/timer_ll.h +++ b/components/esp_hal_timg/esp32c5/include/hal/timer_ll.h @@ -4,15 +4,13 @@ * SPDX-License-Identifier: Apache-2.0 */ -// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. -// This Low Level driver only serve the General Purpose Timer function. - #pragma once #include #include "hal/assert.h" #include "hal/misc.h" #include "hal/timer_types.h" +#include "hal/timg_ll.h" #include "soc/timer_group_struct.h" #include "soc/pcr_struct.h" #include "soc/soc_etm_source.h" @@ -56,57 +54,6 @@ extern "C" { }}, \ }[group][timer][event] -/** - * @brief Enable the bus clock for timer group module - * - * @param group_id Group ID - * @param enable true to enable, false to disable - */ -static inline void _timer_ll_enable_bus_clock(int group_id, bool enable) -{ - if (group_id == 0) { - PCR.timergroup0_conf.tg0_clk_en = enable; - } else { - PCR.timergroup1_conf.tg1_clk_en = enable; - } -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_enable_bus_clock(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_enable_bus_clock(__VA_ARGS__); \ - } while(0) - -/** - * @brief Reset the timer group module - * - * @note After reset the register, the "flash boot protection" will be enabled again. - * FLash boot protection is not used anymore after system boot up. - * This function will disable it by default in order to prevent the system from being reset unexpectedly. - * - * @param group_id Group ID - */ -static inline void _timer_ll_reset_register(int group_id) -{ - if (group_id == 0) { - PCR.timergroup0_conf.tg0_rst_en = 1; - PCR.timergroup0_conf.tg0_rst_en = 0; - TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; - } else { - PCR.timergroup1_conf.tg1_rst_en = 1; - PCR.timergroup1_conf.tg1_rst_en = 0; - TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; - } -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_reset_register(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_reset_register(__VA_ARGS__); \ - } while(0) - /** * @brief Set clock source for timer * diff --git a/components/esp_hal_timg/esp32c5/include/hal/timg_ll.h b/components/esp_hal_timg/esp32c5/include/hal/timg_ll.h new file mode 100644 index 0000000000..a6b0969a8f --- /dev/null +++ b/components/esp_hal_timg/esp32c5/include/hal/timg_ll.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/timer_group_struct.h" +#include "soc/pcr_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the bus clock for timer group module + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void _timg_ll_enable_bus_clock(int group_id, bool enable) +{ + if (group_id == 0) { + PCR.timergroup0_conf.tg0_clk_en = enable; + } else { + PCR.timergroup1_conf.tg1_clk_en = enable; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_enable_bus_clock(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_enable_bus_clock(__VA_ARGS__); \ + } while(0) + +/** + * @brief Reset the timer group module + * + * @note After reset the register, the "flash boot protection" will be enabled again. + * FLash boot protection is not used anymore after system boot up. + * This function will disable it by default in order to prevent the system from being reset unexpectedly. + * + * @param group_id Group ID + */ +static inline void _timg_ll_reset_register(int group_id) +{ + if (group_id == 0) { + PCR.timergroup0_conf.tg0_rst_en = 1; + PCR.timergroup0_conf.tg0_rst_en = 0; + TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; + } else { + PCR.timergroup1_conf.tg1_rst_en = 1; + PCR.timergroup1_conf.tg1_rst_en = 0; + TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_reset_register(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_reset_register(__VA_ARGS__); \ + } while(0) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/timer_periph.c b/components/esp_hal_timg/esp32c5/timer_periph.c similarity index 100% rename from components/soc/esp32c5/timer_periph.c rename to components/esp_hal_timg/esp32c5/timer_periph.c diff --git a/components/hal/esp32c6/include/hal/timer_ll.h b/components/esp_hal_timg/esp32c6/include/hal/timer_ll.h similarity index 84% rename from components/hal/esp32c6/include/hal/timer_ll.h rename to components/esp_hal_timg/esp32c6/include/hal/timer_ll.h index f75f600a0b..6be74ce00b 100644 --- a/components/hal/esp32c6/include/hal/timer_ll.h +++ b/components/esp_hal_timg/esp32c6/include/hal/timer_ll.h @@ -4,15 +4,13 @@ * SPDX-License-Identifier: Apache-2.0 */ -// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. -// This Low Level driver only serve the General Purpose Timer function. - #pragma once #include #include "hal/assert.h" #include "hal/misc.h" #include "hal/timer_types.h" +#include "hal/timg_ll.h" #include "soc/timer_group_struct.h" #include "soc/pcr_struct.h" #include "soc/soc_etm_source.h" @@ -56,57 +54,6 @@ extern "C" { }}, \ }[group][timer][event] -/** - * @brief Enable the bus clock for timer group module - * - * @param group_id Group ID - * @param enable true to enable, false to disable - */ -static inline void _timer_ll_enable_bus_clock(int group_id, bool enable) -{ - if (group_id == 0) { - PCR.timergroup0_conf.tg0_clk_en = enable; - } else { - PCR.timergroup1_conf.tg1_clk_en = enable; - } -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_enable_bus_clock(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_enable_bus_clock(__VA_ARGS__); \ - } while(0) - -/** - * @brief Reset the timer group module - * - * @note After reset the register, the "flash boot protection" will be enabled again. - * FLash boot protection is not used anymore after system boot up. - * This function will disable it by default in order to prevent the system from being reset unexpectedly. - * - * @param group_id Group ID - */ -static inline void _timer_ll_reset_register(int group_id) -{ - if (group_id == 0) { - PCR.timergroup0_conf.tg0_rst_en = 1; - PCR.timergroup0_conf.tg0_rst_en = 0; - TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; - } else { - PCR.timergroup1_conf.tg1_rst_en = 1; - PCR.timergroup1_conf.tg1_rst_en = 0; - TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; - } -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_reset_register(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_reset_register(__VA_ARGS__); \ - } while(0) - /** * @brief Set clock source for timer * diff --git a/components/esp_hal_timg/esp32c6/include/hal/timg_ll.h b/components/esp_hal_timg/esp32c6/include/hal/timg_ll.h new file mode 100644 index 0000000000..93481bfa16 --- /dev/null +++ b/components/esp_hal_timg/esp32c6/include/hal/timg_ll.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/timer_group_struct.h" +#include "soc/pcr_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the bus clock for timer group module + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void _timg_ll_enable_bus_clock(int group_id, bool enable) +{ + if (group_id == 0) { + PCR.timergroup0_conf.tg0_clk_en = enable; + } else { + PCR.timergroup1_conf.tg1_clk_en = enable; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_enable_bus_clock(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_enable_bus_clock(__VA_ARGS__); \ + } while(0) + +/** + * @brief Reset the timer group module + * + * @note After reset the register, the "flash boot protection" will be enabled again. + * FLash boot protection is not used anymore after system boot up. + * This function will disable it by default in order to prevent the system from being reset unexpectedly. + * + * @param group_id Group ID + */ +static inline void _timg_ll_reset_register(int group_id) +{ + if (group_id == 0) { + PCR.timergroup0_conf.tg0_rst_en = 1; + PCR.timergroup0_conf.tg0_rst_en = 0; + TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; + } else { + PCR.timergroup1_conf.tg1_rst_en = 1; + PCR.timergroup1_conf.tg1_rst_en = 0; + TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_reset_register(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_reset_register(__VA_ARGS__); \ + } while(0) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/timer_periph.c b/components/esp_hal_timg/esp32c6/timer_periph.c similarity index 100% rename from components/soc/esp32c6/timer_periph.c rename to components/esp_hal_timg/esp32c6/timer_periph.c diff --git a/components/hal/esp32c61/include/hal/timer_ll.h b/components/esp_hal_timg/esp32c61/include/hal/timer_ll.h similarity index 84% rename from components/hal/esp32c61/include/hal/timer_ll.h rename to components/esp_hal_timg/esp32c61/include/hal/timer_ll.h index e729081f53..d877e335e9 100644 --- a/components/hal/esp32c61/include/hal/timer_ll.h +++ b/components/esp_hal_timg/esp32c61/include/hal/timer_ll.h @@ -4,15 +4,13 @@ * SPDX-License-Identifier: Apache-2.0 */ -// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. -// This Low Level driver only serve the General Purpose Timer function. - #pragma once #include #include "hal/assert.h" #include "hal/misc.h" #include "hal/timer_types.h" +#include "hal/timg_ll.h" #include "soc/timer_group_struct.h" #include "soc/pcr_struct.h" #include "soc/soc_etm_source.h" @@ -56,57 +54,6 @@ extern "C" { }}, \ }[group][timer][event] -/** - * @brief Enable the bus clock for timer group module - * - * @param group_id Group ID - * @param enable true to enable, false to disable - */ -static inline void _timer_ll_enable_bus_clock(int group_id, bool enable) -{ - if (group_id == 0) { - PCR.timergroup0_conf.tg0_clk_en = enable; - } else { - PCR.timergroup1_conf.tg1_clk_en = enable; - } -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_enable_bus_clock(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_enable_bus_clock(__VA_ARGS__); \ - } while(0) - -/** - * @brief Reset the timer group module - * - * @note After reset the register, the "flash boot protection" will be enabled again. - * FLash boot protection is not used anymore after system boot up. - * This function will disable it by default in order to prevent the system from being reset unexpectedly. - * - * @param group_id Group ID - */ -static inline void _timer_ll_reset_register(int group_id) -{ - if (group_id == 0) { - PCR.timergroup0_conf.tg0_rst_en = 1; - PCR.timergroup0_conf.tg0_rst_en = 0; - TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; - } else { - PCR.timergroup1_conf.tg1_rst_en = 1; - PCR.timergroup1_conf.tg1_rst_en = 0; - TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; - } -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_reset_register(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_reset_register(__VA_ARGS__); \ - } while(0) - /** * @brief Set clock source for timer * diff --git a/components/esp_hal_timg/esp32c61/include/hal/timg_ll.h b/components/esp_hal_timg/esp32c61/include/hal/timg_ll.h new file mode 100644 index 0000000000..bdc60ec049 --- /dev/null +++ b/components/esp_hal_timg/esp32c61/include/hal/timg_ll.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/timer_group_struct.h" +#include "soc/pcr_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the bus clock for timer group module + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void _timg_ll_enable_bus_clock(int group_id, bool enable) +{ + if (group_id == 0) { + PCR.timergroup0_conf.tg0_clk_en = enable; + } else { + PCR.timergroup1_conf.tg1_clk_en = enable; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_enable_bus_clock(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_enable_bus_clock(__VA_ARGS__); \ + } while(0) + +/** + * @brief Reset the timer group module + * + * @note After reset the register, the "flash boot protection" will be enabled again. + * FLash boot protection is not used anymore after system boot up. + * This function will disable it by default in order to prevent the system from being reset unexpectedly. + * + * @param group_id Group ID + */ +static inline void _timg_ll_reset_register(int group_id) +{ + if (group_id == 0) { + PCR.timergroup0_conf.tg0_rst_en = 1; + PCR.timergroup0_conf.tg0_rst_en = 0; + TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; + } else { + PCR.timergroup1_conf.tg1_rst_en = 1; + PCR.timergroup1_conf.tg1_rst_en = 0; + TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_reset_register(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_reset_register(__VA_ARGS__); \ + } while(0) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/timer_periph.c b/components/esp_hal_timg/esp32c61/timer_periph.c similarity index 100% rename from components/soc/esp32c61/timer_periph.c rename to components/esp_hal_timg/esp32c61/timer_periph.c diff --git a/components/hal/esp32h2/include/hal/timer_ll.h b/components/esp_hal_timg/esp32h2/include/hal/timer_ll.h similarity index 84% rename from components/hal/esp32h2/include/hal/timer_ll.h rename to components/esp_hal_timg/esp32h2/include/hal/timer_ll.h index 12983d2902..34827327b2 100644 --- a/components/hal/esp32h2/include/hal/timer_ll.h +++ b/components/esp_hal_timg/esp32h2/include/hal/timer_ll.h @@ -4,15 +4,13 @@ * SPDX-License-Identifier: Apache-2.0 */ -// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. -// This Low Level driver only serve the General Purpose Timer function. - #pragma once #include #include "hal/assert.h" #include "hal/misc.h" #include "hal/timer_types.h" +#include "hal/timg_ll.h" #include "soc/timer_group_struct.h" #include "soc/pcr_struct.h" #include "soc/soc_etm_source.h" @@ -51,57 +49,6 @@ extern "C" { }}, \ }[group][timer][event] -/** - * @brief Enable the bus clock for timer group module - * - * @param group_id Group ID - * @param enable true to enable, false to disable - */ -static inline void _timer_ll_enable_bus_clock(int group_id, bool enable) -{ - if (group_id == 0) { - PCR.timergroup0_conf.tg0_clk_en = enable; - } else { - PCR.timergroup1_conf.tg1_clk_en = enable; - } -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_enable_bus_clock(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_enable_bus_clock(__VA_ARGS__); \ - } while(0) - -/** - * @brief Reset the timer group module - * - * @note After reset the register, the "flash boot protection" will be enabled again. - * FLash boot protection is not used anymore after system boot up. - * This function will disable it by default in order to prevent the system from being reset unexpectedly. - * - * @param group_id Group ID - */ -static inline void _timer_ll_reset_register(int group_id) -{ - if (group_id == 0) { - PCR.timergroup0_conf.tg0_rst_en = 1; - PCR.timergroup0_conf.tg0_rst_en = 0; - TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; - } else { - PCR.timergroup1_conf.tg1_rst_en = 1; - PCR.timergroup1_conf.tg1_rst_en = 0; - TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; - } -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_reset_register(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_reset_register(__VA_ARGS__); \ - } while(0) - /** * @brief Set clock source for timer * diff --git a/components/esp_hal_timg/esp32h2/include/hal/timg_ll.h b/components/esp_hal_timg/esp32h2/include/hal/timg_ll.h new file mode 100644 index 0000000000..93481bfa16 --- /dev/null +++ b/components/esp_hal_timg/esp32h2/include/hal/timg_ll.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/timer_group_struct.h" +#include "soc/pcr_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the bus clock for timer group module + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void _timg_ll_enable_bus_clock(int group_id, bool enable) +{ + if (group_id == 0) { + PCR.timergroup0_conf.tg0_clk_en = enable; + } else { + PCR.timergroup1_conf.tg1_clk_en = enable; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_enable_bus_clock(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_enable_bus_clock(__VA_ARGS__); \ + } while(0) + +/** + * @brief Reset the timer group module + * + * @note After reset the register, the "flash boot protection" will be enabled again. + * FLash boot protection is not used anymore after system boot up. + * This function will disable it by default in order to prevent the system from being reset unexpectedly. + * + * @param group_id Group ID + */ +static inline void _timg_ll_reset_register(int group_id) +{ + if (group_id == 0) { + PCR.timergroup0_conf.tg0_rst_en = 1; + PCR.timergroup0_conf.tg0_rst_en = 0; + TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; + } else { + PCR.timergroup1_conf.tg1_rst_en = 1; + PCR.timergroup1_conf.tg1_rst_en = 0; + TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_reset_register(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_reset_register(__VA_ARGS__); \ + } while(0) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/timer_periph.c b/components/esp_hal_timg/esp32h2/timer_periph.c similarity index 100% rename from components/soc/esp32h2/timer_periph.c rename to components/esp_hal_timg/esp32h2/timer_periph.c diff --git a/components/hal/esp32h21/include/hal/timer_ll.h b/components/esp_hal_timg/esp32h21/include/hal/timer_ll.h similarity index 85% rename from components/hal/esp32h21/include/hal/timer_ll.h rename to components/esp_hal_timg/esp32h21/include/hal/timer_ll.h index 693bc82513..669f35c29a 100644 --- a/components/hal/esp32h21/include/hal/timer_ll.h +++ b/components/esp_hal_timg/esp32h21/include/hal/timer_ll.h @@ -4,15 +4,13 @@ * SPDX-License-Identifier: Apache-2.0 */ -// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. -// This Low Level driver only serve the General Purpose Timer function. - #pragma once #include #include "hal/assert.h" #include "hal/misc.h" #include "hal/timer_types.h" +#include "hal/timg_ll.h" #include "soc/timer_group_struct.h" #include "soc/pcr_struct.h" #include "soc/soc_etm_source.h" @@ -56,49 +54,6 @@ extern "C" { }}, \ }[group][timer][event] -/** - * @brief Enable the bus clock for timer group module - * - * @param group_id Group ID - * @param enable true to enable, false to disable - */ -static inline void _timer_ll_enable_bus_clock(int group_id, bool enable) -{ - PCR.timergroup[group_id].timergroup_conf.tg_clk_en = enable; -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_enable_bus_clock(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_enable_bus_clock(__VA_ARGS__); \ - } while(0) - -/** - * @brief Reset the timer group module - * - * @note After reset the register, the "flash boot protection" will be enabled again. - * FLash boot protection is not used anymore after system boot up. - * This function will disable it by default in order to prevent the system from being reset unexpectedly. - * - * @param group_id Group ID - */ -static inline void _timer_ll_reset_register(int group_id) -{ - timg_dev_t *hw = TIMER_LL_GET_HW(group_id); - - PCR.timergroup[group_id].timergroup_conf.tg_rst_en = 1; - PCR.timergroup[group_id].timergroup_conf.tg_rst_en = 0; - hw->wdtconfig0.wdt_flashboot_mod_en = 0; -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_reset_register(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_reset_register(__VA_ARGS__); \ - } while(0) - /** * @brief Set clock source for timer * diff --git a/components/esp_hal_timg/esp32h21/include/hal/timg_ll.h b/components/esp_hal_timg/esp32h21/include/hal/timg_ll.h new file mode 100644 index 0000000000..da1e4d61f0 --- /dev/null +++ b/components/esp_hal_timg/esp32h21/include/hal/timg_ll.h @@ -0,0 +1,68 @@ +/* + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/timer_group_struct.h" +#include "soc/pcr_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the bus clock for timer group module + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void _timg_ll_enable_bus_clock(int group_id, bool enable) +{ + PCR.timergroup[group_id].timergroup_conf.tg_clk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_enable_bus_clock(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_enable_bus_clock(__VA_ARGS__); \ + } while(0) + +/** + * @brief Reset the timer group module + * + * @note After reset the register, the "flash boot protection" will be enabled again. + * FLash boot protection is not used anymore after system boot up. + * This function will disable it by default in order to prevent the system from being reset unexpectedly. + * + * @param group_id Group ID + */ +static inline void _timg_ll_reset_register(int group_id) +{ + PCR.timergroup[group_id].timergroup_conf.tg_rst_en = 1; + PCR.timergroup[group_id].timergroup_conf.tg_rst_en = 0; + if (group_id == 0) { + TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; + } else { + TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_reset_register(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_reset_register(__VA_ARGS__); \ + } while(0) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/timer_periph.c b/components/esp_hal_timg/esp32h21/timer_periph.c similarity index 100% rename from components/soc/esp32h21/timer_periph.c rename to components/esp_hal_timg/esp32h21/timer_periph.c diff --git a/components/hal/esp32h4/include/hal/timer_ll.h b/components/esp_hal_timg/esp32h4/include/hal/timer_ll.h similarity index 84% rename from components/hal/esp32h4/include/hal/timer_ll.h rename to components/esp_hal_timg/esp32h4/include/hal/timer_ll.h index 78714109dd..840aabe3df 100644 --- a/components/hal/esp32h4/include/hal/timer_ll.h +++ b/components/esp_hal_timg/esp32h4/include/hal/timer_ll.h @@ -4,15 +4,13 @@ * SPDX-License-Identifier: Apache-2.0 */ -// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. -// This Low Level driver only serve the General Purpose Timer function. - #pragma once #include #include "hal/assert.h" #include "hal/misc.h" #include "hal/timer_types.h" +#include "hal/timg_ll.h" #include "soc/timer_group_struct.h" #include "soc/pcr_struct.h" #include "soc/soc_etm_source.h" @@ -56,57 +54,6 @@ extern "C" { }}, \ }[group][timer][event] -/** - * @brief Enable the bus clock for timer group module - * - * @param group_id Group ID - * @param enable true to enable, false to disable - */ -static inline void _timer_ll_enable_bus_clock(int group_id, bool enable) -{ - if (group_id == 0) { - PCR.timergroup0_conf.tg0_clk_en = enable; - } else { - PCR.timergroup1_conf.tg1_clk_en = enable; - } -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_enable_bus_clock(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_enable_bus_clock(__VA_ARGS__); \ - } while(0) - -/** - * @brief Reset the timer group module - * - * @note After reset the register, the "flash boot protection" will be enabled again. - * FLash boot protection is not used anymore after system boot up. - * This function will disable it by default in order to prevent the system from being reset unexpectedly. - * - * @param group_id Group ID - */ -static inline void _timer_ll_reset_register(int group_id) -{ - if (group_id == 0) { - PCR.timergroup0_conf.tg0_rst_en = 1; - PCR.timergroup0_conf.tg0_rst_en = 0; - TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; - } else { - PCR.timergroup1_conf.tg1_rst_en = 1; - PCR.timergroup1_conf.tg1_rst_en = 0; - TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; - } -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_reset_register(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_reset_register(__VA_ARGS__); \ - } while(0) - /** * @brief Set clock source for timer * diff --git a/components/esp_hal_timg/esp32h4/include/hal/timg_ll.h b/components/esp_hal_timg/esp32h4/include/hal/timg_ll.h new file mode 100644 index 0000000000..2ff16142d9 --- /dev/null +++ b/components/esp_hal_timg/esp32h4/include/hal/timg_ll.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/timer_group_struct.h" +#include "soc/pcr_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the bus clock for timer group module + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void _timg_ll_enable_bus_clock(int group_id, bool enable) +{ + if (group_id == 0) { + PCR.timergroup0_conf.tg0_clk_en = enable; + } else { + PCR.timergroup1_conf.tg1_clk_en = enable; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_enable_bus_clock(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_enable_bus_clock(__VA_ARGS__); \ + } while(0) + +/** + * @brief Reset the timer group module + * + * @note After reset the register, the "flash boot protection" will be enabled again. + * FLash boot protection is not used anymore after system boot up. + * This function will disable it by default in order to prevent the system from being reset unexpectedly. + * + * @param group_id Group ID + */ +static inline void _timg_ll_reset_register(int group_id) +{ + if (group_id == 0) { + PCR.timergroup0_conf.tg0_rst_en = 1; + PCR.timergroup0_conf.tg0_rst_en = 0; + TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; + } else { + PCR.timergroup1_conf.tg1_rst_en = 1; + PCR.timergroup1_conf.tg1_rst_en = 0; + TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_reset_register(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_reset_register(__VA_ARGS__); \ + } while(0) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/timer_periph.c b/components/esp_hal_timg/esp32h4/timer_periph.c similarity index 100% rename from components/soc/esp32h4/timer_periph.c rename to components/esp_hal_timg/esp32h4/timer_periph.c diff --git a/components/hal/esp32p4/include/hal/timer_ll.h b/components/esp_hal_timg/esp32p4/include/hal/timer_ll.h similarity index 86% rename from components/hal/esp32p4/include/hal/timer_ll.h rename to components/esp_hal_timg/esp32p4/include/hal/timer_ll.h index 1a4f933747..b79abd92b4 100644 --- a/components/hal/esp32p4/include/hal/timer_ll.h +++ b/components/esp_hal_timg/esp32p4/include/hal/timer_ll.h @@ -4,15 +4,13 @@ * SPDX-License-Identifier: Apache-2.0 */ -// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. -// This Low Level driver only serve the General Purpose Timer function. - #pragma once #include #include "hal/assert.h" #include "hal/misc.h" #include "hal/timer_types.h" +#include "hal/timg_ll.h" #include "soc/timer_group_struct.h" #include "soc/soc_etm_source.h" #include "soc/hp_sys_clkrst_struct.h" @@ -86,57 +84,6 @@ extern "C" { }, \ }[group][timer][event] -/** - * @brief Enable the bus clock for timer group module - * - * @param group_id Group ID - * @param enable true to enable, false to disable - */ -static inline void _timer_ll_enable_bus_clock(int group_id, bool enable) -{ - if (group_id == 0) { - HP_SYS_CLKRST.soc_clk_ctrl2.reg_timergrp0_apb_clk_en = enable; - } else { - HP_SYS_CLKRST.soc_clk_ctrl2.reg_timergrp1_apb_clk_en = enable; - } -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_enable_bus_clock(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_enable_bus_clock(__VA_ARGS__); \ - } while(0) - -/** - * @brief Reset the timer group module - * - * @note After reset the register, the "flash boot protection" will be enabled again. - * FLash boot protection is not used anymore after system boot up. - * This function will disable it by default in order to prevent the system from being reset unexpectedly. - * - * @param group_id Group ID - */ -static inline void _timer_ll_reset_register(int group_id) -{ - if (group_id == 0) { - HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_timergrp0 = 1; - HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_timergrp0 = 0; - TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; - } else { - HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_timergrp1 = 1; - HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_timergrp1 = 0; - TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; - } -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_reset_register(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_reset_register(__VA_ARGS__); \ - } while(0) - /** * @brief Set clock source for timer * diff --git a/components/esp_hal_timg/esp32p4/include/hal/timg_ll.h b/components/esp_hal_timg/esp32p4/include/hal/timg_ll.h new file mode 100644 index 0000000000..79edc498ca --- /dev/null +++ b/components/esp_hal_timg/esp32p4/include/hal/timg_ll.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/timer_group_struct.h" +#include "soc/hp_sys_clkrst_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the bus clock for timer group module + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void _timg_ll_enable_bus_clock(int group_id, bool enable) +{ + if (group_id == 0) { + HP_SYS_CLKRST.soc_clk_ctrl2.reg_timergrp0_apb_clk_en = enable; + } else { + HP_SYS_CLKRST.soc_clk_ctrl2.reg_timergrp1_apb_clk_en = enable; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_enable_bus_clock(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_enable_bus_clock(__VA_ARGS__); \ + } while(0) + +/** + * @brief Reset the timer group module + * + * @note After reset the register, the "flash boot protection" will be enabled again. + * FLash boot protection is not used anymore after system boot up. + * This function will disable it by default in order to prevent the system from being reset unexpectedly. + * + * @param group_id Group ID + */ +static inline void _timg_ll_reset_register(int group_id) +{ + if (group_id == 0) { + HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_timergrp0 = 1; + HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_timergrp0 = 0; + TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; + } else { + HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_timergrp1 = 1; + HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_timergrp1 = 0; + TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_reset_register(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_reset_register(__VA_ARGS__); \ + } while(0) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/timer_periph.c b/components/esp_hal_timg/esp32p4/timer_periph.c similarity index 100% rename from components/soc/esp32p4/timer_periph.c rename to components/esp_hal_timg/esp32p4/timer_periph.c diff --git a/components/hal/esp32s2/include/hal/timer_ll.h b/components/esp_hal_timg/esp32s2/include/hal/timer_ll.h similarity index 76% rename from components/hal/esp32s2/include/hal/timer_ll.h rename to components/esp_hal_timg/esp32s2/include/hal/timer_ll.h index 1d462ee868..d6c507d30c 100644 --- a/components/hal/esp32s2/include/hal/timer_ll.h +++ b/components/esp_hal_timg/esp32s2/include/hal/timer_ll.h @@ -4,15 +4,13 @@ * SPDX-License-Identifier: Apache-2.0 */ -// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. -// This Low Level driver only serve the General Purpose Timer function. - #pragma once #include #include "hal/assert.h" #include "hal/misc.h" #include "hal/timer_types.h" +#include "hal/timg_ll.h" #include "soc/timer_group_struct.h" #include "soc/system_reg.h" @@ -29,61 +27,6 @@ extern "C" { // Support APB as function clock #define TIMER_LL_FUNC_CLOCK_SUPPORT_APB 1 -/** - * @brief Enable the bus clock for timer group module - * - * @param group_id Group ID - * @param enable true to enable, false to disable - */ -static inline void _timer_ll_enable_bus_clock(int group_id, bool enable) -{ - uint32_t reg_val = READ_PERI_REG(DPORT_PERIP_CLK_EN0_REG); - if (group_id == 0) { - reg_val &= ~DPORT_TIMERGROUP_CLK_EN_M; - reg_val |= enable << DPORT_TIMERGROUP_CLK_EN_S; - } else { - reg_val &= ~DPORT_TIMERGROUP1_CLK_EN_M; - reg_val |= enable << DPORT_TIMERGROUP1_CLK_EN_S; - } - WRITE_PERI_REG(DPORT_PERIP_CLK_EN0_REG, reg_val); -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_enable_bus_clock(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_enable_bus_clock(__VA_ARGS__); \ - } while(0) - -/** - * @brief Reset the timer group module - * - * @note After reset the register, the "flash boot protection" will be enabled again. - * FLash boot protection is not used anymore after system boot up. - * This function will disable it by default in order to prevent the system from being reset unexpectedly. - * - * @param group_id Group ID - */ -static inline void _timer_ll_reset_register(int group_id) -{ - if (group_id == 0) { - WRITE_PERI_REG(DPORT_PERIP_RST_EN0_REG, DPORT_TIMERGROUP_RST_M); - WRITE_PERI_REG(DPORT_PERIP_RST_EN0_REG, 0); - TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; - } else { - WRITE_PERI_REG(DPORT_PERIP_RST_EN0_REG, DPORT_TIMERGROUP1_RST_M); - WRITE_PERI_REG(DPORT_PERIP_RST_EN0_REG, 0); - TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; - } -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_reset_register(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_reset_register(__VA_ARGS__); \ - } while(0) - /** * @brief Set clock source for timer * @@ -235,7 +178,7 @@ static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer __attribute__((always_inline)) static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, uint64_t alarm_value) { - hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t) (alarm_value >> 32); + hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t)(alarm_value >> 32); hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (uint32_t) alarm_value; } @@ -249,7 +192,7 @@ static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, __attribute__((always_inline)) static inline void timer_ll_set_reload_value(timg_dev_t *hw, uint32_t timer_num, uint64_t load_val) { - hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t) (load_val >> 32); + hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t)(load_val >> 32); hw->hw_timer[timer_num].loadlo.tx_load_lo = (uint32_t) load_val; } diff --git a/components/esp_hal_timg/esp32s2/include/hal/timg_ll.h b/components/esp_hal_timg/esp32s2/include/hal/timg_ll.h new file mode 100644 index 0000000000..d01debeb1b --- /dev/null +++ b/components/esp_hal_timg/esp32s2/include/hal/timg_ll.h @@ -0,0 +1,78 @@ +/* + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/timer_group_struct.h" +#include "soc/system_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the bus clock for timer group module + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void _timg_ll_enable_bus_clock(int group_id, bool enable) +{ + uint32_t reg_val = READ_PERI_REG(DPORT_PERIP_CLK_EN0_REG); + if (group_id == 0) { + reg_val &= ~DPORT_TIMERGROUP_CLK_EN_M; + reg_val |= enable << DPORT_TIMERGROUP_CLK_EN_S; + } else { + reg_val &= ~DPORT_TIMERGROUP1_CLK_EN_M; + reg_val |= enable << DPORT_TIMERGROUP1_CLK_EN_S; + } + WRITE_PERI_REG(DPORT_PERIP_CLK_EN0_REG, reg_val); +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_enable_bus_clock(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_enable_bus_clock(__VA_ARGS__); \ + } while(0) + +/** + * @brief Reset the timer group module + * + * @note After reset the register, the "flash boot protection" will be enabled again. + * FLash boot protection is not used anymore after system boot up. + * This function will disable it by default in order to prevent the system from being reset unexpectedly. + * + * @param group_id Group ID + */ +static inline void _timg_ll_reset_register(int group_id) +{ + if (group_id == 0) { + WRITE_PERI_REG(DPORT_PERIP_RST_EN0_REG, DPORT_TIMERGROUP_RST_M); + WRITE_PERI_REG(DPORT_PERIP_RST_EN0_REG, 0); + TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; + } else { + WRITE_PERI_REG(DPORT_PERIP_RST_EN0_REG, DPORT_TIMERGROUP1_RST_M); + WRITE_PERI_REG(DPORT_PERIP_RST_EN0_REG, 0); + TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_reset_register(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_reset_register(__VA_ARGS__); \ + } while(0) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s2/timer_periph.c b/components/esp_hal_timg/esp32s2/timer_periph.c similarity index 100% rename from components/soc/esp32s2/timer_periph.c rename to components/esp_hal_timg/esp32s2/timer_periph.c diff --git a/components/hal/esp32s3/include/hal/timer_ll.h b/components/esp_hal_timg/esp32s3/include/hal/timer_ll.h similarity index 80% rename from components/hal/esp32s3/include/hal/timer_ll.h rename to components/esp_hal_timg/esp32s3/include/hal/timer_ll.h index fc24c28c2a..bcaaeda80d 100644 --- a/components/hal/esp32s3/include/hal/timer_ll.h +++ b/components/esp_hal_timg/esp32s3/include/hal/timer_ll.h @@ -4,15 +4,13 @@ * SPDX-License-Identifier: Apache-2.0 */ -// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. -// This Low Level driver only serve the General Purpose Timer function. - #pragma once #include #include "hal/assert.h" #include "hal/misc.h" #include "hal/timer_types.h" +#include "hal/timg_ll.h" #include "soc/timer_group_struct.h" #include "soc/system_struct.h" @@ -29,57 +27,6 @@ extern "C" { // Support APB as function clock #define TIMER_LL_FUNC_CLOCK_SUPPORT_APB 1 -/** - * @brief Enable the bus clock for timer group module - * - * @param group_id Group ID - * @param enable true to enable, false to disable - */ -static inline void _timer_ll_enable_bus_clock(int group_id, bool enable) -{ - if (group_id == 0) { - SYSTEM.perip_clk_en0.timergroup_clk_en = enable; - } else { - SYSTEM.perip_clk_en0.timergroup1_clk_en = enable; - } -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_enable_bus_clock(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_enable_bus_clock(__VA_ARGS__); \ - } while(0) - -/** - * @brief Reset the timer group module - * - * @note After reset the register, the "flash boot protection" will be enabled again. - * FLash boot protection is not used anymore after system boot up. - * This function will disable it by default in order to prevent the system from being reset unexpectedly. - * - * @param group_id Group ID - */ -static inline void _timer_ll_reset_register(int group_id) -{ - if (group_id == 0) { - SYSTEM.perip_rst_en0.timergroup_rst = 1; - SYSTEM.perip_rst_en0.timergroup_rst = 0; - TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; - } else { - SYSTEM.perip_rst_en0.timergroup1_rst = 1; - SYSTEM.perip_rst_en0.timergroup1_rst = 0; - TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; - } -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define timer_ll_reset_register(...) do { \ - (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ - _timer_ll_reset_register(__VA_ARGS__); \ - } while(0) - /** * @brief Set clock source for timer * diff --git a/components/esp_hal_timg/esp32s3/include/hal/timg_ll.h b/components/esp_hal_timg/esp32s3/include/hal/timg_ll.h new file mode 100644 index 0000000000..776a60c850 --- /dev/null +++ b/components/esp_hal_timg/esp32s3/include/hal/timg_ll.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/timer_group_struct.h" +#include "soc/system_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the bus clock for timer group module + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void _timg_ll_enable_bus_clock(int group_id, bool enable) +{ + if (group_id == 0) { + SYSTEM.perip_clk_en0.timergroup_clk_en = enable; + } else { + SYSTEM.perip_clk_en0.timergroup1_clk_en = enable; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_enable_bus_clock(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_enable_bus_clock(__VA_ARGS__); \ + } while(0) + +/** + * @brief Reset the timer group module + * + * @note After reset the register, the "flash boot protection" will be enabled again. + * FLash boot protection is not used anymore after system boot up. + * This function will disable it by default in order to prevent the system from being reset unexpectedly. + * + * @param group_id Group ID + */ +static inline void _timg_ll_reset_register(int group_id) +{ + if (group_id == 0) { + SYSTEM.perip_rst_en0.timergroup_rst = 1; + SYSTEM.perip_rst_en0.timergroup_rst = 0; + TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; + } else { + SYSTEM.perip_rst_en0.timergroup1_rst = 1; + SYSTEM.perip_rst_en0.timergroup1_rst = 0; + TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timg_ll_reset_register(...) do { \ + (void)__DECLARE_RCC_RC_ATOMIC_ENV; \ + _timg_ll_reset_register(__VA_ARGS__); \ + } while(0) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s3/timer_periph.c b/components/esp_hal_timg/esp32s3/timer_periph.c similarity index 100% rename from components/soc/esp32s3/timer_periph.c rename to components/esp_hal_timg/esp32s3/timer_periph.c diff --git a/components/hal/include/hal/timer_hal.h b/components/esp_hal_timg/include/hal/timer_hal.h similarity index 100% rename from components/hal/include/hal/timer_hal.h rename to components/esp_hal_timg/include/hal/timer_hal.h diff --git a/components/hal/include/hal/timer_types.h b/components/esp_hal_timg/include/hal/timer_types.h similarity index 100% rename from components/hal/include/hal/timer_types.h rename to components/esp_hal_timg/include/hal/timer_types.h diff --git a/components/soc/include/soc/timer_periph.h b/components/esp_hal_timg/include/soc/timer_periph.h similarity index 100% rename from components/soc/include/soc/timer_periph.h rename to components/esp_hal_timg/include/soc/timer_periph.h diff --git a/components/hal/timer_hal.c b/components/esp_hal_timg/timer_hal.c similarity index 100% rename from components/hal/timer_hal.c rename to components/esp_hal_timg/timer_hal.c diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index cbffdd85fe..ea5a6f3bcc 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -11,7 +11,7 @@ endif() set(requires soc) # only esp_hw_support/adc_share_hw_ctrl.c requires efuse component -set(priv_requires efuse spi_flash bootloader_support) +set(priv_requires efuse spi_flash bootloader_support esp_hal_timg) if(${target} STREQUAL "esp32c6") list(APPEND priv_requires hal) diff --git a/components/esp_hw_support/port/esp32/rtc_clk.c b/components/esp_hw_support/port/esp32/rtc_clk.c index 34844033ba..ae891b2c50 100644 --- a/components/esp_hw_support/port/esp32/rtc_clk.c +++ b/components/esp_hw_support/port/esp32/rtc_clk.c @@ -29,7 +29,7 @@ #include "soc/io_mux_reg.h" #ifndef BOOTLOADER_BUILD #include "esp_private/systimer.h" -#include "hal/timer_ll.h" +#include "hal/lact_ll.h" #endif #define XTAL_32K_BOOTSTRAP_TIME_US 7 @@ -379,7 +379,7 @@ void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div) /* switch clock source */ clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL); #ifndef BOOTLOADER_BUILD - timer_ll_set_lact_clock_prescale(TIMER_LL_GET_HW(LACT_MODULE), cpu_freq / LACT_TICKS_PER_US); + lact_ll_set_clock_prescale(LACT_LL_GET_HW(LACT_MODULE), cpu_freq / LACT_TICKS_PER_US); #endif rtc_clk_apb_freq_update(cpu_freq * MHZ); /* lower the voltage */ @@ -397,7 +397,7 @@ static void rtc_clk_cpu_freq_to_rc_fast(void) /* switch clock source */ clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST); #ifndef BOOTLOADER_BUILD - timer_ll_set_lact_clock_prescale(TIMER_LL_GET_HW(LACT_MODULE), SOC_CLK_RC_FAST_FREQ_APPROX / MHZ / LACT_TICKS_PER_US); + lact_ll_set_clock_prescale(LACT_LL_GET_HW(LACT_MODULE), SOC_CLK_RC_FAST_FREQ_APPROX / MHZ / LACT_TICKS_PER_US); #endif rtc_clk_apb_freq_update(SOC_CLK_RC_FAST_FREQ_APPROX); } @@ -430,7 +430,7 @@ NOINLINE_ATTR static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) uint32_t cur_freq = esp_rom_get_cpu_ticks_per_us(); int16_t delay_cycle = rtc_clk_get_lact_compensation_delay(cur_freq, cpu_freq_mhz); if (cur_freq <= 40 && delay_cycle >= 0) { - timer_ll_set_lact_clock_prescale(TIMER_LL_GET_HW(LACT_MODULE), 80 / LACT_TICKS_PER_US); + lact_ll_set_clock_prescale(LACT_LL_GET_HW(LACT_MODULE), 80 / LACT_TICKS_PER_US); for (int i = 0; i < delay_cycle; ++i) { __asm__ __volatile__("nop"); } @@ -448,7 +448,7 @@ NOINLINE_ATTR static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) for (int i = 0; i > delay_cycle; --i) { __asm__ __volatile__("nop"); } - timer_ll_set_lact_clock_prescale(TIMER_LL_GET_HW(LACT_MODULE), 80 / LACT_TICKS_PER_US); + lact_ll_set_clock_prescale(LACT_LL_GET_HW(LACT_MODULE), 80 / LACT_TICKS_PER_US); } #endif rtc_clk_wait_for_slow_cycle(); diff --git a/components/esp_hw_support/port/esp32/rtc_time.c b/components/esp_hw_support/port/esp32/rtc_time.c index 6b0025012f..67b664cb29 100644 --- a/components/esp_hw_support/port/esp32/rtc_time.c +++ b/components/esp_hw_support/port/esp32/rtc_time.c @@ -8,7 +8,7 @@ #include "esp_rom_sys.h" #include "hal/clk_tree_ll.h" #include "hal/rtc_cntl_ll.h" -#include "hal/timer_ll.h" +#include "hal/timg_ll.h" #include "soc/rtc.h" #include "soc/timer_periph.h" #include "esp_hw_log.h" @@ -201,12 +201,12 @@ static void enable_timer_group0_for_calibration(void) #ifndef BOOTLOADER_BUILD PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_TIMG0_MODULE, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(0, true); - timer_ll_reset_register(0); + timg_ll_enable_bus_clock(0, true); + timg_ll_reset_register(0); } } #else - _timer_ll_enable_bus_clock(0, true); - _timer_ll_reset_register(0); + _timg_ll_enable_bus_clock(0, true); + _timg_ll_reset_register(0); #endif } diff --git a/components/esp_hw_support/port/esp32c2/rtc_time.c b/components/esp_hw_support/port/esp32c2/rtc_time.c index baabe741b4..6048675948 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_time.c +++ b/components/esp_hw_support/port/esp32c2/rtc_time.c @@ -10,7 +10,7 @@ #include "soc/rtc_cntl_reg.h" #include "hal/clk_tree_ll.h" #include "hal/rtc_cntl_ll.h" -#include "hal/timer_ll.h" +#include "hal/timg_ll.h" #include "soc/timer_group_reg.h" #include "esp_rom_sys.h" #include "esp_private/periph_ctrl.h" @@ -68,7 +68,7 @@ static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, */ REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, 1); while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) - && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); + && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); } /* Prepare calibration */ @@ -89,7 +89,7 @@ static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles)); expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; } - uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); + uint32_t us_time_estimate = (uint32_t)(((uint64_t) slowclk_cycles) * MHZ / expected_freq); /* Start calibration */ CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); @@ -198,12 +198,12 @@ static void enable_timer_group0_for_calibration(void) #ifndef BOOTLOADER_BUILD PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_TIMG0_MODULE, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(0, true); - timer_ll_reset_register(0); + timg_ll_enable_bus_clock(0, true); + timg_ll_reset_register(0); } } #else - _timer_ll_enable_bus_clock(0, true); - _timer_ll_reset_register(0); + _timg_ll_enable_bus_clock(0, true); + _timg_ll_reset_register(0); #endif } diff --git a/components/esp_hw_support/port/esp32c3/rtc_time.c b/components/esp_hw_support/port/esp32c3/rtc_time.c index 5ec41920fa..ed33570111 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_time.c +++ b/components/esp_hw_support/port/esp32c3/rtc_time.c @@ -10,7 +10,7 @@ #include "soc/rtc_cntl_reg.h" #include "hal/clk_tree_ll.h" #include "hal/rtc_cntl_ll.h" -#include "hal/timer_ll.h" +#include "hal/timg_ll.h" #include "soc/timer_group_reg.h" #include "esp_rom_sys.h" #include "esp_private/periph_ctrl.h" @@ -89,7 +89,7 @@ static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles)); expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; } - uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); + uint32_t us_time_estimate = (uint32_t)(((uint64_t) slowclk_cycles) * MHZ / expected_freq); /* Start calibration */ CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); @@ -198,12 +198,12 @@ static void enable_timer_group0_for_calibration(void) #ifndef BOOTLOADER_BUILD PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_TIMG0_MODULE, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(0, true); - timer_ll_reset_register(0); + timg_ll_enable_bus_clock(0, true); + timg_ll_reset_register(0); } } #else - _timer_ll_enable_bus_clock(0, true); - _timer_ll_reset_register(0); + _timg_ll_enable_bus_clock(0, true); + _timg_ll_reset_register(0); #endif } diff --git a/components/esp_hw_support/port/esp32c5/rtc_time.c b/components/esp_hw_support/port/esp32c5/rtc_time.c index aeb87ddc59..cd6f45104f 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_time.c +++ b/components/esp_hw_support/port/esp32c5/rtc_time.c @@ -10,7 +10,7 @@ #include "soc/lp_timer_reg.h" #include "hal/lp_timer_hal.h" #include "hal/clk_tree_ll.h" -#include "hal/timer_ll.h" +#include "hal/timg_ll.h" #include "soc/timer_group_reg.h" #include "soc/pcr_reg.h" #include "esp_rom_sys.h" @@ -77,7 +77,7 @@ static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, */ REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, 1); while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) - && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); + && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); } /* Prepare calibration */ @@ -99,7 +99,7 @@ static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, } else { expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; } - uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); + uint32_t us_time_estimate = (uint32_t)(((uint64_t) slowclk_cycles) * MHZ / expected_freq); /* Start calibration */ CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); @@ -208,12 +208,12 @@ static void enable_timer_group0_for_calibration(void) #ifndef BOOTLOADER_BUILD PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_TIMG0_MODULE, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(0, true); - timer_ll_reset_register(0); + timg_ll_enable_bus_clock(0, true); + timg_ll_reset_register(0); } } #else - _timer_ll_enable_bus_clock(0, true); - _timer_ll_reset_register(0); + _timg_ll_enable_bus_clock(0, true); + _timg_ll_reset_register(0); #endif } diff --git a/components/esp_hw_support/port/esp32c6/rtc_time.c b/components/esp_hw_support/port/esp32c6/rtc_time.c index 4278ce3383..8bcb08a83c 100644 --- a/components/esp_hw_support/port/esp32c6/rtc_time.c +++ b/components/esp_hw_support/port/esp32c6/rtc_time.c @@ -10,7 +10,7 @@ #include "soc/pcr_reg.h" #include "hal/lp_timer_hal.h" #include "hal/clk_tree_ll.h" -#include "hal/timer_ll.h" +#include "hal/timg_ll.h" #include "soc/timer_group_reg.h" #include "esp_rom_sys.h" #include "assert.h" @@ -251,12 +251,12 @@ static void enable_timer_group0_for_calibration(void) #ifndef BOOTLOADER_BUILD PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_TIMG0_MODULE, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(0, true); - timer_ll_reset_register(0); + timg_ll_enable_bus_clock(0, true); + timg_ll_reset_register(0); } } #else - _timer_ll_enable_bus_clock(0, true); - _timer_ll_reset_register(0); + _timg_ll_enable_bus_clock(0, true); + _timg_ll_reset_register(0); #endif } diff --git a/components/esp_hw_support/port/esp32c61/rtc_time.c b/components/esp_hw_support/port/esp32c61/rtc_time.c index 3d1808bc72..30243b3cec 100644 --- a/components/esp_hw_support/port/esp32c61/rtc_time.c +++ b/components/esp_hw_support/port/esp32c61/rtc_time.c @@ -9,7 +9,7 @@ #include "soc/rtc.h" #include "hal/lp_timer_hal.h" #include "hal/clk_tree_ll.h" -#include "hal/timer_ll.h" +#include "hal/timg_ll.h" #include "soc/timer_group_reg.h" #include "soc/pcr_reg.h" #include "esp_rom_sys.h" @@ -207,12 +207,12 @@ static void enable_timer_group0_for_calibration(void) #ifndef BOOTLOADER_BUILD PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_TIMG0_MODULE, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(0, true); - timer_ll_reset_register(0); + timg_ll_enable_bus_clock(0, true); + timg_ll_reset_register(0); } } #else - _timer_ll_enable_bus_clock(0, true); - _timer_ll_reset_register(0); + _timg_ll_enable_bus_clock(0, true); + _timg_ll_reset_register(0); #endif } diff --git a/components/esp_hw_support/port/esp32h2/rtc_time.c b/components/esp_hw_support/port/esp32h2/rtc_time.c index 71fbde6dbe..1a2944a531 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_time.c +++ b/components/esp_hw_support/port/esp32h2/rtc_time.c @@ -9,7 +9,7 @@ #include "soc/rtc.h" #include "hal/lp_timer_hal.h" #include "hal/clk_tree_ll.h" -#include "hal/timer_ll.h" +#include "hal/timg_ll.h" #include "soc/timer_group_reg.h" #include "soc/pcr_reg.h" #include "esp_rom_sys.h" @@ -251,12 +251,12 @@ static void enable_timer_group0_for_calibration(void) #ifndef BOOTLOADER_BUILD PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_TIMG0_MODULE, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(0, true); - timer_ll_reset_register(0); + timg_ll_enable_bus_clock(0, true); + timg_ll_reset_register(0); } } #else - _timer_ll_enable_bus_clock(0, true); - _timer_ll_reset_register(0); + _timg_ll_enable_bus_clock(0, true); + _timg_ll_reset_register(0); #endif } diff --git a/components/esp_hw_support/port/esp32h21/rtc_time.c b/components/esp_hw_support/port/esp32h21/rtc_time.c index efab69011b..0cfb4186e8 100644 --- a/components/esp_hw_support/port/esp32h21/rtc_time.c +++ b/components/esp_hw_support/port/esp32h21/rtc_time.c @@ -9,7 +9,7 @@ #include "soc/rtc.h" #include "hal/lp_timer_hal.h" #include "hal/clk_tree_ll.h" -#include "hal/timer_ll.h" +#include "hal/timg_ll.h" #include "soc/timer_group_reg.h" #include "soc/pcr_reg.h" #include "esp_rom_sys.h" @@ -225,12 +225,12 @@ static void enable_timer_group0_for_calibration(void) #ifndef BOOTLOADER_BUILD PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_TIMG0_MODULE, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(0, true); - timer_ll_reset_register(0); + timg_ll_enable_bus_clock(0, true); + timg_ll_reset_register(0); } } #else - _timer_ll_enable_bus_clock(0, true); - _timer_ll_reset_register(0); + _timg_ll_enable_bus_clock(0, true); + _timg_ll_reset_register(0); #endif } diff --git a/components/esp_hw_support/port/esp32h4/rtc_time.c b/components/esp_hw_support/port/esp32h4/rtc_time.c index 5ad913bac3..676fa1dd3e 100644 --- a/components/esp_hw_support/port/esp32h4/rtc_time.c +++ b/components/esp_hw_support/port/esp32h4/rtc_time.c @@ -9,7 +9,7 @@ #include "soc/rtc.h" #include "hal/lp_timer_hal.h" #include "hal/clk_tree_ll.h" -#include "hal/timer_ll.h" +#include "hal/timg_ll.h" #include "soc/timer_group_reg.h" #include "esp_rom_sys.h" #include "assert.h" @@ -72,7 +72,7 @@ static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, // If the clock is already on, then do nothing bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled(); if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) { - clk_ll_xtal32k_digi_enable(); + clk_ll_xtal32k_digi_enable(); } bool rc_fast_enabled = clk_ll_rc_fast_is_enabled(); @@ -96,7 +96,7 @@ static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, */ REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, 1); while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) - && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); + && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); } /* Prepare calibration */ @@ -120,7 +120,7 @@ static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; } expected_freq /= clk_cal_divider; - uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); + uint32_t us_time_estimate = (uint32_t)(((uint64_t) slowclk_cycles) * MHZ / expected_freq); /* Start calibration */ CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); @@ -221,10 +221,15 @@ uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal __attribute__((constructor)) static void enable_timer_group0_for_calibration(void) { +#ifndef BOOTLOADER_BUILD PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_TIMG0_MODULE, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(0, true); - timer_ll_reset_register(0); + timg_ll_enable_bus_clock(0, true); + timg_ll_reset_register(0); } } +#else + _timg_ll_enable_bus_clock(0, true); + _timg_ll_reset_register(0); +#endif } diff --git a/components/esp_hw_support/port/esp32p4/rtc_time.c b/components/esp_hw_support/port/esp32p4/rtc_time.c index d61c55d96e..12d1a1ec82 100644 --- a/components/esp_hw_support/port/esp32p4/rtc_time.c +++ b/components/esp_hw_support/port/esp32p4/rtc_time.c @@ -10,7 +10,7 @@ #include "soc/rtc.h" #include "hal/lp_timer_hal.h" #include "hal/clk_tree_ll.h" -#include "hal/timer_ll.h" +#include "hal/timg_ll.h" #include "soc/hp_sys_clkrst_reg.h" #include "soc/timer_group_reg.h" #include "esp_rom_sys.h" @@ -110,7 +110,7 @@ static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, */ REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, 1); while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) - && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); + && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); } /* Prepare calibration */ @@ -125,7 +125,7 @@ static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, CLK_CAL_TIMEOUT_THRES(cal_clk_sel, slowclk_cycles)); uint32_t expected_freq = CLK_CAL_FREQ_APPROX(cal_clk_sel); assert(expected_freq); - uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); + uint32_t us_time_estimate = (uint32_t)(((uint64_t) slowclk_cycles) * MHZ / expected_freq); /* Start calibration */ CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); @@ -233,12 +233,12 @@ static void enable_timer_group0_for_calibration(void) #ifndef BOOTLOADER_BUILD PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_TIMG0_MODULE, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(0, true); - timer_ll_reset_register(0); + timg_ll_enable_bus_clock(0, true); + timg_ll_reset_register(0); } } #else - _timer_ll_enable_bus_clock(0, true); - _timer_ll_reset_register(0); + _timg_ll_enable_bus_clock(0, true); + _timg_ll_reset_register(0); #endif } diff --git a/components/esp_hw_support/port/esp32s2/rtc_time.c b/components/esp_hw_support/port/esp32s2/rtc_time.c index 7476c835a4..e74e44fb31 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_time.c +++ b/components/esp_hw_support/port/esp32s2/rtc_time.c @@ -10,7 +10,7 @@ #include "soc/rtc_cntl_reg.h" #include "hal/clk_tree_ll.h" #include "hal/rtc_cntl_ll.h" -#include "hal/timer_ll.h" +#include "hal/timg_ll.h" #include "soc/timer_group_reg.h" #include "esp_private/periph_ctrl.h" @@ -44,7 +44,7 @@ static uint32_t rtc_clk_cal_internal_oneoff(soc_clk_freq_calculation_src_t cal_c */ REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, 1); while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) - && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); + && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); } /* Prepare calibration */ @@ -65,7 +65,7 @@ static uint32_t rtc_clk_cal_internal_oneoff(soc_clk_freq_calculation_src_t cal_c REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_90K_CAL_TIMEOUT_THRES(slowclk_cycles)); expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; } - uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); + uint32_t us_time_estimate = (uint32_t)(((uint64_t) slowclk_cycles) * MHZ / expected_freq); /* Start calibration */ CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); @@ -262,12 +262,12 @@ static void enable_timer_group0_for_calibration(void) #ifndef BOOTLOADER_BUILD PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_TIMG0_MODULE, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(0, true); - timer_ll_reset_register(0); + timg_ll_enable_bus_clock(0, true); + timg_ll_reset_register(0); } } #else - _timer_ll_enable_bus_clock(0, true); - _timer_ll_reset_register(0); + _timg_ll_enable_bus_clock(0, true); + _timg_ll_reset_register(0); #endif } diff --git a/components/esp_hw_support/port/esp32s3/rtc_time.c b/components/esp_hw_support/port/esp32s3/rtc_time.c index 8348027e1a..9fa9d841f7 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_time.c +++ b/components/esp_hw_support/port/esp32s3/rtc_time.c @@ -9,7 +9,7 @@ #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" #include "hal/clk_tree_ll.h" -#include "hal/timer_ll.h" +#include "hal/timg_ll.h" #include "hal/rtc_cntl_ll.h" #include "soc/timer_group_reg.h" #include "esp_private/periph_ctrl.h" @@ -88,7 +88,7 @@ static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles)); expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; } - uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); + uint32_t us_time_estimate = (uint32_t)(((uint64_t) slowclk_cycles) * MHZ / expected_freq); /* Start calibration */ CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); @@ -197,12 +197,12 @@ static void enable_timer_group0_for_calibration(void) #ifndef BOOTLOADER_BUILD PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_TIMG0_MODULE, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(0, true); - timer_ll_reset_register(0); + timg_ll_enable_bus_clock(0, true); + timg_ll_reset_register(0); } } #else - _timer_ll_enable_bus_clock(0, true); - _timer_ll_reset_register(0); + _timg_ll_enable_bus_clock(0, true); + _timg_ll_reset_register(0); #endif } diff --git a/components/esp_system/CMakeLists.txt b/components/esp_system/CMakeLists.txt index 557f6ddc95..e052a6c581 100644 --- a/components/esp_system/CMakeLists.txt +++ b/components/esp_system/CMakeLists.txt @@ -80,6 +80,7 @@ else() # [REFACTOR-TODO] Provide system hook to release dependency reversion. # IDF-13980 esp_hal_i2c + esp_hal_timg # task_wdt_impl_timergroup.c relies on it LDFRAGMENTS "linker.lf" "app.lf") add_subdirectory(port) diff --git a/components/esp_system/int_wdt.c b/components/esp_system/int_wdt.c index bad31568f0..6d25476bbe 100644 --- a/components/esp_system/int_wdt.c +++ b/components/esp_system/int_wdt.c @@ -11,7 +11,7 @@ #include "soc/soc_caps.h" #include "hal/wdt_hal.h" #include "hal/mwdt_ll.h" -#include "hal/timer_ll.h" +#include "hal/timg_ll.h" #include "soc/system_intr.h" #include "freertos/FreeRTOS.h" #include "esp_cpu.h" @@ -144,8 +144,8 @@ void esp_int_wdt_init(void) { PERIPH_RCC_ACQUIRE_ATOMIC(IWDT_PERIPH, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(IWDT_TIMER_GROUP, true); - timer_ll_reset_register(IWDT_TIMER_GROUP); + timg_ll_enable_bus_clock(IWDT_TIMER_GROUP, true); + timg_ll_reset_register(IWDT_TIMER_GROUP); } } /* diff --git a/components/esp_system/port/soc/esp32c5/clk.c b/components/esp_system/port/soc/esp32c5/clk.c index 0db05faac6..73ef5e8599 100644 --- a/components/esp_system/port/soc/esp32c5/clk.c +++ b/components/esp_system/port/soc/esp32c5/clk.c @@ -274,8 +274,8 @@ __attribute__((weak)) void esp_perip_clk_init(void) clk_ll_enable_timergroup_rtc_calibration_clock(false); timer_ll_enable_clock(0, 0, false); timer_ll_enable_clock(1, 0, false); - _timer_ll_enable_bus_clock(0, false); - _timer_ll_enable_bus_clock(1, false); + _timg_ll_enable_bus_clock(0, false); + _timg_ll_enable_bus_clock(1, false); twaifd_ll_enable_clock(0, false); twaifd_ll_enable_bus_clock(0, false); twaifd_ll_enable_clock(1, false); diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c index 870baab647..0e20e4ab2d 100644 --- a/components/esp_system/port/soc/esp32c6/clk.c +++ b/components/esp_system/port/soc/esp32c6/clk.c @@ -251,8 +251,8 @@ __attribute__((weak)) void esp_perip_clk_init(void) ledc_ll_enable_bus_clock(false); timer_ll_enable_clock(0, 0, false); timer_ll_enable_clock(1, 0, false); - _timer_ll_enable_bus_clock(0, false); - _timer_ll_enable_bus_clock(1, false); + _timg_ll_enable_bus_clock(0, false); + _timg_ll_enable_bus_clock(1, false); twai_ll_enable_clock(0, false); twai_ll_enable_bus_clock(0, false); twai_ll_enable_clock(1, false); diff --git a/components/esp_system/port/soc/esp32h2/clk.c b/components/esp_system/port/soc/esp32h2/clk.c index 3915948a4b..203bbba9ff 100644 --- a/components/esp_system/port/soc/esp32h2/clk.c +++ b/components/esp_system/port/soc/esp32h2/clk.c @@ -246,8 +246,8 @@ __attribute__((weak)) void esp_perip_clk_init(void) ledc_ll_enable_bus_clock(false); timer_ll_enable_clock(0, 0, false); timer_ll_enable_clock(1, 0, false); - _timer_ll_enable_bus_clock(0, false); - _timer_ll_enable_bus_clock(1, false); + _timg_ll_enable_bus_clock(0, false); + _timg_ll_enable_bus_clock(1, false); twai_ll_enable_clock(0, false); twai_ll_enable_bus_clock(0, false); i2s_ll_enable_bus_clock(0, false); diff --git a/components/esp_system/port/soc/esp32p4/clk.c b/components/esp_system/port/soc/esp32p4/clk.c index 58d31e1da8..d41a7843ad 100644 --- a/components/esp_system/port/soc/esp32p4/clk.c +++ b/components/esp_system/port/soc/esp32p4/clk.c @@ -290,11 +290,11 @@ __attribute__((weak)) void esp_perip_clk_init(void) _uart_ll_enable_bus_clock(UART_NUM_4, false); _uart_ll_sclk_disable(&UART4); - _timer_ll_enable_bus_clock(0, false); + _timg_ll_enable_bus_clock(0, false); _timer_ll_enable_clock(0, 0, false); _timer_ll_enable_clock(0, 1, false); - _timer_ll_enable_bus_clock(1, false); + _timg_ll_enable_bus_clock(1, false); _timer_ll_enable_clock(1, 0, false); _timer_ll_enable_clock(1, 1, false); diff --git a/components/esp_system/task_wdt/task_wdt_impl_timergroup.c b/components/esp_system/task_wdt/task_wdt_impl_timergroup.c index dd365b79fd..ae6c0e6d58 100644 --- a/components/esp_system/task_wdt/task_wdt_impl_timergroup.c +++ b/components/esp_system/task_wdt/task_wdt_impl_timergroup.c @@ -10,7 +10,7 @@ #include "sdkconfig.h" #include "hal/wdt_hal.h" #include "hal/mwdt_ll.h" -#include "hal/timer_ll.h" +#include "hal/timg_ll.h" #include "soc/system_intr.h" #include "esp_check.h" #include "esp_err.h" @@ -113,8 +113,8 @@ esp_err_t esp_task_wdt_impl_timer_allocate(const esp_task_wdt_config_t *config, // enable bus clock for the timer group registers PERIPH_RCC_ACQUIRE_ATOMIC(TWDT_PERIPH_MODULE, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(TWDT_TIMER_GROUP, true); - timer_ll_reset_register(TWDT_TIMER_GROUP); + timg_ll_enable_bus_clock(TWDT_TIMER_GROUP, true); + timg_ll_reset_register(TWDT_TIMER_GROUP); } } wdt_hal_init(&ctx->hal, TWDT_INSTANCE, TWDT_PRESCALER, true); @@ -170,7 +170,7 @@ void esp_task_wdt_impl_timer_free(twdt_ctx_t obj) /* Disable the Timer Group module */ PERIPH_RCC_RELEASE_ATOMIC(TWDT_PERIPH_MODULE, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(TWDT_TIMER_GROUP, false); + timg_ll_enable_bus_clock(TWDT_TIMER_GROUP, false); } } diff --git a/components/esp_tee/test_apps/tee_test_fw/components/test_sec_srv/src/test_interrupt.c b/components/esp_tee/test_apps/tee_test_fw/components/test_sec_srv/src/test_interrupt.c index 17ce1321d4..f7f2c59d7e 100644 --- a/components/esp_tee/test_apps/tee_test_fw/components/test_sec_srv/src/test_interrupt.c +++ b/components/esp_tee/test_apps/tee_test_fw/components/test_sec_srv/src/test_interrupt.c @@ -77,8 +77,8 @@ static void test_timer_init(volatile uint32_t *arg) test_timer_deinit(); // Enable peripheral clock and reset hardware - _timer_ll_enable_bus_clock(group_id, true); - _timer_ll_reset_register(group_id); + _timg_ll_enable_bus_clock(group_id, true); + _timg_ll_reset_register(group_id); // Select clock source and enable module clock // Enable the default clock source PLL_F80M diff --git a/components/esp_timer/CMakeLists.txt b/components/esp_timer/CMakeLists.txt index 83317a8046..613264f171 100644 --- a/components/esp_timer/CMakeLists.txt +++ b/components/esp_timer/CMakeLists.txt @@ -21,6 +21,7 @@ else() idf_component_register(SRCS "${srcs}" INCLUDE_DIRS include + PRIV_REQUIRES esp_hal_timg PRIV_INCLUDE_DIRS private_include) # Forces the linker to include esp_timer_init.c diff --git a/components/esp_timer/src/esp_timer_impl_lac.c b/components/esp_timer/src/esp_timer_impl_lac.c index 9c0efe4c32..a6469e1962 100644 --- a/components/esp_timer/src/esp_timer_impl_lac.c +++ b/components/esp_timer/src/esp_timer_impl_lac.c @@ -20,7 +20,7 @@ #include "soc/soc.h" #include "soc/timer_group_reg.h" #include "soc/rtc.h" -#include "hal/timer_ll.h" +#include "hal/lact_ll.h" #include "freertos/FreeRTOS.h" /** @@ -226,8 +226,8 @@ esp_err_t esp_timer_impl_early_init(void) { PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_LACT, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(LACT_MODULE, true); - timer_ll_reset_register(LACT_MODULE); + timg_ll_enable_bus_clock(LACT_MODULE, true); + timg_ll_reset_register(LACT_MODULE); } } @@ -277,7 +277,7 @@ esp_err_t esp_timer_impl_init(intr_handler_t alarm_handler) */ REG_SET_BIT(INT_ENA_REG, TIMG_LACT_INT_ENA); portENTER_CRITICAL_SAFE(&s_time_update_lock); - timer_ll_set_lact_clock_prescale(TIMER_LL_GET_HW(LACT_MODULE), esp_clk_apb_freq() / MHZ / LACT_TICKS_PER_US); + lact_ll_set_clock_prescale(LACT_LL_GET_HW(LACT_MODULE), esp_clk_apb_freq() / MHZ / LACT_TICKS_PER_US); portEXIT_CRITICAL_SAFE(&s_time_update_lock); // Set the step for the sleep mode when the timer will work // from a slow_clk frequency instead of the APB frequency. @@ -308,7 +308,7 @@ void esp_timer_impl_deinit(void) s_alarm_handler = NULL; PERIPH_RCC_RELEASE_ATOMIC(PERIPH_LACT, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(LACT_MODULE, false); + timg_ll_enable_bus_clock(LACT_MODULE, false); } } } diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 9c2e267f7d..deac2de7ce 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -94,10 +94,6 @@ elseif(NOT BOOTLOADER_BUILD) list(APPEND srcs "rtc_io_hal.c") endif() - if(CONFIG_SOC_GPTIMER_SUPPORTED) - list(APPEND srcs "timer_hal.c") - endif() - if(CONFIG_SOC_LEDC_SUPPORTED) list(APPEND srcs "ledc_hal.c" "ledc_hal_iram.c") endif() diff --git a/components/hal/esp32h4/include/hal/mwdt_ll.h b/components/hal/esp32h4/include/hal/mwdt_ll.h index a1cfd5410f..128830b73b 100644 --- a/components/hal/esp32h4/include/hal/mwdt_ll.h +++ b/components/hal/esp32h4/include/hal/mwdt_ll.h @@ -15,7 +15,6 @@ extern "C" { #include #include -#include "soc/timer_periph.h" #include "soc/timer_group_struct.h" #include "soc/pcr_struct.h" #include "hal/wdt_types.h" diff --git a/components/hal/test_apps/tee/components/pms_and_cpu_intr/src/cpu_intr/test_interrupt.c b/components/hal/test_apps/tee/components/pms_and_cpu_intr/src/cpu_intr/test_interrupt.c index 0cbfd3630c..1cd72c097d 100644 --- a/components/hal/test_apps/tee/components/pms_and_cpu_intr/src/cpu_intr/test_interrupt.c +++ b/components/hal/test_apps/tee/components/pms_and_cpu_intr/src/cpu_intr/test_interrupt.c @@ -81,8 +81,8 @@ static void test_timer_init(int mode, volatile uint32_t *arg) test_timer_deinit(); // Enable peripheral clock and reset hardware - _timer_ll_enable_bus_clock(group_id, true); - _timer_ll_reset_register(group_id); + _timg_ll_enable_bus_clock(group_id, true); + _timg_ll_reset_register(group_id); // Select clock source and enable module clock // Enable the default clock source PLL_F80M diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt index ec29c8f22f..7d34586b46 100644 --- a/components/soc/CMakeLists.txt +++ b/components/soc/CMakeLists.txt @@ -132,10 +132,6 @@ if(CONFIG_SOC_TEMP_SENSOR_SUPPORTED) list(APPEND srcs "${target_folder}/temperature_sensor_periph.c") endif() -if(CONFIG_SOC_GPTIMER_SUPPORTED) - list(APPEND srcs "${target_folder}/timer_periph.c") -endif() - if(CONFIG_SOC_LCDCAM_SUPPORTED OR CONFIG_SOC_I2S_SUPPORTS_LCD_CAMERA) list(APPEND srcs "${target_folder}/lcd_periph.c") endif() diff --git a/components/soc/esp32c5/system_retention_periph.c b/components/soc/esp32c5/system_retention_periph.c index a1b78a03cb..0b6143e029 100644 --- a/components/soc/esp32c5/system_retention_periph.c +++ b/components/soc/esp32c5/system_retention_periph.c @@ -6,7 +6,6 @@ #include "soc/regdma.h" #include "soc/system_periph_retention.h" -#include "soc/timer_periph.h" #include "soc/uart_reg.h" #include "soc/systimer_reg.h" #include "soc/timer_group_reg.h" diff --git a/components/soc/esp32c6/system_retention_periph.c b/components/soc/esp32c6/system_retention_periph.c index 25f1b093d3..d3ebf10144 100644 --- a/components/soc/esp32c6/system_retention_periph.c +++ b/components/soc/esp32c6/system_retention_periph.c @@ -6,7 +6,6 @@ #include "soc/regdma.h" #include "soc/system_periph_retention.h" -#include "soc/timer_periph.h" #include "soc/uart_reg.h" #include "soc/systimer_reg.h" #include "soc/timer_group_reg.h" diff --git a/components/soc/esp32c61/system_retention_periph.c b/components/soc/esp32c61/system_retention_periph.c index d0237b4493..a25afa10c2 100644 --- a/components/soc/esp32c61/system_retention_periph.c +++ b/components/soc/esp32c61/system_retention_periph.c @@ -6,7 +6,6 @@ #include "soc/regdma.h" #include "soc/system_periph_retention.h" -#include "soc/timer_periph.h" #include "soc/uart_reg.h" #include "soc/systimer_reg.h" #include "soc/timer_group_reg.h" diff --git a/components/soc/esp32h2/system_retention_periph.c b/components/soc/esp32h2/system_retention_periph.c index 463a401f92..d312932781 100644 --- a/components/soc/esp32h2/system_retention_periph.c +++ b/components/soc/esp32h2/system_retention_periph.c @@ -6,7 +6,6 @@ #include "soc/regdma.h" #include "soc/system_periph_retention.h" -#include "soc/timer_periph.h" #include "soc/uart_reg.h" #include "soc/systimer_reg.h" #include "soc/timer_group_reg.h" diff --git a/components/soc/esp32h21/system_retention_periph.c b/components/soc/esp32h21/system_retention_periph.c index e32b2b2d98..4c24c50b05 100644 --- a/components/soc/esp32h21/system_retention_periph.c +++ b/components/soc/esp32h21/system_retention_periph.c @@ -6,7 +6,6 @@ #include "soc/regdma.h" #include "soc/system_periph_retention.h" -#include "soc/timer_periph.h" #include "soc/uart_reg.h" #include "soc/systimer_reg.h" #include "soc/timer_group_reg.h" diff --git a/components/soc/esp32h4/system_retention_periph.c b/components/soc/esp32h4/system_retention_periph.c index 97baa156ce..77f49ebb4c 100644 --- a/components/soc/esp32h4/system_retention_periph.c +++ b/components/soc/esp32h4/system_retention_periph.c @@ -6,7 +6,6 @@ #include "soc/regdma.h" #include "soc/system_periph_retention.h" -#include "soc/timer_periph.h" #include "soc/uart_reg.h" #include "soc/systimer_reg.h" #include "soc/timer_group_reg.h" diff --git a/components/soc/esp32p4/system_retention_periph.c b/components/soc/esp32p4/system_retention_periph.c index 87d94fc0fc..082c5b2d75 100644 --- a/components/soc/esp32p4/system_retention_periph.c +++ b/components/soc/esp32p4/system_retention_periph.c @@ -20,7 +20,6 @@ #include "soc/spi1_mem_s_reg.h" #include "soc/systimer_reg.h" #include "soc/timer_group_reg.h" -#include "soc/timer_periph.h" #include "soc/uart_reg.h" #include "esp32p4/rom/cache.h" #include "soc/pvt_reg.h" diff --git a/docs/doxygen/Doxyfile b/docs/doxygen/Doxyfile index c8dc338ec4..f1f6c238f6 100644 --- a/docs/doxygen/Doxyfile +++ b/docs/doxygen/Doxyfile @@ -161,6 +161,7 @@ INPUT = \ $(PROJECT_PATH)/components/esp_eth/include/esp_eth.h \ $(PROJECT_PATH)/components/esp_event/include/esp_event_base.h \ $(PROJECT_PATH)/components/esp_event/include/esp_event.h \ + $(PROJECT_PATH)/components/esp_hal_timg/include/hal/timer_types.h \ $(PROJECT_PATH)/components/esp_hal_i2c/include/hal/i2c_types.h \ $(PROJECT_PATH)/components/esp_http_client/include/esp_http_client.h \ $(PROJECT_PATH)/components/esp_http_server/include/esp_http_server.h \ @@ -264,7 +265,6 @@ INPUT = \ $(PROJECT_PATH)/components/hal/include/hal/spi_flash_types.h \ $(PROJECT_PATH)/components/hal/include/hal/spi_types.h \ $(PROJECT_PATH)/components/hal/include/hal/temperature_sensor_types.h \ - $(PROJECT_PATH)/components/hal/include/hal/timer_types.h \ $(PROJECT_PATH)/components/hal/include/hal/twai_types.h \ $(PROJECT_PATH)/components/hal/include/hal/uart_types.h \ $(PROJECT_PATH)/components/hal/include/hal/efuse_hal.h \ diff --git a/examples/peripherals/.build-test-rules.yml b/examples/peripherals/.build-test-rules.yml index 7e82e76923..66d5dee20c 100644 --- a/examples/peripherals/.build-test-rules.yml +++ b/examples/peripherals/.build-test-rules.yml @@ -479,18 +479,21 @@ examples/peripherals/timer_group/gptimer: - if: SOC_GPTIMER_SUPPORTED != 1 depends_components: - esp_driver_gptimer + - esp_hal_timg examples/peripherals/timer_group/gptimer_capture_hc_sr04: disable: - if: SOC_ETM_SUPPORTED != 1 or SOC_TIMER_SUPPORT_ETM != 1 depends_components: - esp_driver_gptimer + - esp_hal_timg examples/peripherals/timer_group/wiegand_interface: disable: - if: SOC_GPTIMER_SUPPORTED != 1 or IDF_TARGET in ["esp32c2"] depends_components: - esp_driver_gptimer + - esp_hal_timg examples/peripherals/touch_sensor: disable: