diff --git a/components/esp_hw_support/include/esp_private/sar_periph_ctrl.h b/components/esp_hw_support/include/esp_private/sar_periph_ctrl.h
new file mode 100644
index 0000000000..35c48ba6ff
--- /dev/null
+++ b/components/esp_hw_support/include/esp_private/sar_periph_ctrl.h
@@ -0,0 +1,29 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * SAR related peripherals are interdependent. This file
+ * provides a united control to these registers, as multiple
+ * components require these controls.
+ *
+ * See target/sar_periph_ctrl.c to know involved peripherals
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Initialise SAR related peripheral register settings
+ * Should only be used when running into app stage
+ */
+void sar_periph_ctrl_init(void);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/esp_hw_support/port/esp32/CMakeLists.txt b/components/esp_hw_support/port/esp32/CMakeLists.txt
index a5e40f7b0e..40ac8b9367 100644
--- a/components/esp_hw_support/port/esp32/CMakeLists.txt
+++ b/components/esp_hw_support/port/esp32/CMakeLists.txt
@@ -11,7 +11,8 @@ set(srcs
     "chip_info.c")
 
 if(NOT BOOTLOADER_BUILD)
-    list(APPEND srcs "cache_sram_mmu.c")
+    list(APPEND srcs "cache_sram_mmu.c"
+                     "sar_periph_ctrl.c")
 endif()
 
 add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
diff --git a/components/esp_hw_support/port/esp32/rtc_init.c b/components/esp_hw_support/port/esp32/rtc_init.c
index 4b9472ff97..45f20b2814 100644
--- a/components/esp_hw_support/port/esp32/rtc_init.c
+++ b/components/esp_hw_support/port/esp32/rtc_init.c
@@ -12,6 +12,9 @@
 #include "soc/dport_reg.h"
 #include "hal/efuse_ll.h"
 #include "soc/gpio_periph.h"
+#ifndef BOOTLOADER_BUILD
+#include "esp_private/sar_periph_ctrl.h"
+#endif
 
 
 void rtc_init(rtc_config_t cfg)
@@ -94,6 +97,11 @@ void rtc_init(rtc_config_t cfg)
 
     REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
     REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
+
+#ifndef BOOTLOADER_BUILD
+    //initialise SAR related peripheral register settings
+    sar_periph_ctrl_init();
+#endif
 }
 
 rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
diff --git a/components/esp_hw_support/port/esp32/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32/sar_periph_ctrl.c
new file mode 100644
index 0000000000..34b694d93f
--- /dev/null
+++ b/components/esp_hw_support/port/esp32/sar_periph_ctrl.c
@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * SAR related peripherals are interdependent. This file
+ * provides a united control to these registers, as multiple
+ * components require these controls.
+ *
+ * Related peripherals are:
+ * - ADC
+ * - PWDET
+ */
+
+#include "sdkconfig.h"
+#include "freertos/FreeRTOS.h"
+#include "esp_private/sar_periph_ctrl.h"
+#include "hal/sar_ctrl_ll.h"
+
+extern portMUX_TYPE rtc_spinlock;
+
+void sar_periph_ctrl_init(void)
+{
+    //Put SAR control mux to ON state
+    sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_ON);
+
+    //Add other periph power control initialisation here
+}
+
+void sar_periph_ctrl_power_disable(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
diff --git a/components/esp_hw_support/port/esp32c2/CMakeLists.txt b/components/esp_hw_support/port/esp32c2/CMakeLists.txt
index 315e233fc7..df1877dec3 100644
--- a/components/esp_hw_support/port/esp32c2/CMakeLists.txt
+++ b/components/esp_hw_support/port/esp32c2/CMakeLists.txt
@@ -4,8 +4,13 @@ set(srcs "rtc_clk_init.c"
          "rtc_pm.c"
          "rtc_sleep.c"
          "rtc_time.c"
-         "chip_info.c"
-         )
+         "chip_info.c")
+
+if(NOT BOOTLOADER_BUILD)
+
+    list(APPEND srcs "sar_periph_ctrl.c")
+
+endif()
 
 add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
 
diff --git a/components/esp_hw_support/port/esp32c2/rtc_init.c b/components/esp_hw_support/port/esp32c2/rtc_init.c
index 5c9124d132..e8ec002a09 100644
--- a/components/esp_hw_support/port/esp32c2/rtc_init.c
+++ b/components/esp_hw_support/port/esp32c2/rtc_init.c
@@ -21,6 +21,9 @@
 #include "esp_hw_log.h"
 #include "esp_efuse.h"
 #include "esp_efuse_table.h"
+#ifndef BOOTLOADER_BUILD
+#include "esp_private/sar_periph_ctrl.h"
+#endif
 
 static const char *TAG = "rtc_init";
 
@@ -121,6 +124,11 @@ void rtc_init(rtc_config_t cfg)
     REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
     REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
     REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 1);
+
+#ifndef BOOTLOADER_BUILD
+    //initialise SAR related peripheral register settings
+    sar_periph_ctrl_init();
+#endif
 }
 
 rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
diff --git a/components/esp_hw_support/port/esp32c2/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32c2/sar_periph_ctrl.c
new file mode 100644
index 0000000000..b0acdf96cd
--- /dev/null
+++ b/components/esp_hw_support/port/esp32c2/sar_periph_ctrl.c
@@ -0,0 +1,38 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * SAR related peripherals are interdependent. This file
+ * provides a united control to these registers, as multiple
+ * components require these controls.
+ *
+ * Related peripherals are:
+ * - ADC
+ * - PWDET
+ * - Temp Sensor
+ */
+
+#include "sdkconfig.h"
+#include "freertos/FreeRTOS.h"
+#include "esp_private/sar_periph_ctrl.h"
+#include "hal/sar_ctrl_ll.h"
+
+extern portMUX_TYPE rtc_spinlock;
+
+void sar_periph_ctrl_init(void)
+{
+    //Put SAR control mux to FSM state
+    sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
+
+    //Add other periph power control initialisation here
+}
+
+void sar_periph_ctrl_power_disable(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
diff --git a/components/esp_hw_support/port/esp32c3/CMakeLists.txt b/components/esp_hw_support/port/esp32c3/CMakeLists.txt
index dac547e54d..ab7b6676a6 100644
--- a/components/esp_hw_support/port/esp32c3/CMakeLists.txt
+++ b/components/esp_hw_support/port/esp32c3/CMakeLists.txt
@@ -4,12 +4,12 @@ set(srcs "rtc_clk_init.c"
          "rtc_pm.c"
          "rtc_sleep.c"
          "rtc_time.c"
-         "chip_info.c"
-         )
+         "chip_info.c")
 
 if(NOT BOOTLOADER_BUILD)
     list(APPEND srcs "esp_crypto_lock.c"
-                     "esp_ds.c")
+                     "esp_ds.c"
+                     "sar_periph_ctrl.c")
 
     # init constructor for wifi
     list(APPEND srcs "adc2_init_cal.c")
diff --git a/components/esp_hw_support/port/esp32c3/rtc_init.c b/components/esp_hw_support/port/esp32c3/rtc_init.c
index 6884aff4d1..b69171a04e 100644
--- a/components/esp_hw_support/port/esp32c3/rtc_init.c
+++ b/components/esp_hw_support/port/esp32c3/rtc_init.c
@@ -21,6 +21,9 @@
 #include "esp_hw_log.h"
 #include "esp_efuse.h"
 #include "esp_efuse_table.h"
+#ifndef BOOTLOADER_BUILD
+#include "esp_private/sar_periph_ctrl.h"
+#endif
 
 static const char *TAG = "rtc_init";
 
@@ -156,6 +159,11 @@ void rtc_init(rtc_config_t cfg)
     REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
     REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
     REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 1);
+
+#ifndef BOOTLOADER_BUILD
+    //initialise SAR related peripheral register settings
+    sar_periph_ctrl_init();
+#endif
 }
 
 rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
diff --git a/components/esp_hw_support/port/esp32c3/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32c3/sar_periph_ctrl.c
new file mode 100644
index 0000000000..b0acdf96cd
--- /dev/null
+++ b/components/esp_hw_support/port/esp32c3/sar_periph_ctrl.c
@@ -0,0 +1,38 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * SAR related peripherals are interdependent. This file
+ * provides a united control to these registers, as multiple
+ * components require these controls.
+ *
+ * Related peripherals are:
+ * - ADC
+ * - PWDET
+ * - Temp Sensor
+ */
+
+#include "sdkconfig.h"
+#include "freertos/FreeRTOS.h"
+#include "esp_private/sar_periph_ctrl.h"
+#include "hal/sar_ctrl_ll.h"
+
+extern portMUX_TYPE rtc_spinlock;
+
+void sar_periph_ctrl_init(void)
+{
+    //Put SAR control mux to FSM state
+    sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
+
+    //Add other periph power control initialisation here
+}
+
+void sar_periph_ctrl_power_disable(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
diff --git a/components/esp_hw_support/port/esp32c6/CMakeLists.txt b/components/esp_hw_support/port/esp32c6/CMakeLists.txt
index 95caea4b5e..5a783cd05f 100644
--- a/components/esp_hw_support/port/esp32c6/CMakeLists.txt
+++ b/components/esp_hw_support/port/esp32c6/CMakeLists.txt
@@ -4,13 +4,13 @@ set(srcs "rtc_clk_init.c"
         #  "rtc_pm.c" // TODO: IDF-5645
         #  "rtc_sleep.c" // TODO: IDF-5645
          "rtc_time.c"
-         "chip_info.c"
-         )
+         "chip_info.c")
 
 if(NOT BOOTLOADER_BUILD)
     # list(APPEND srcs "esp_hmac.c" // TODO: IDF-5355
     #                  "esp_crypto_lock.c"
     #                  "esp_ds.c") // TODO: IDF-5360
+    list(APPEND srcs "sar_periph_ctrl.c")
 
     if(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE)
         list(APPEND srcs "esp_memprot.c" "../esp_memprot_conv.c")
diff --git a/components/esp_hw_support/port/esp32c6/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32c6/sar_periph_ctrl.c
new file mode 100644
index 0000000000..8cb3fce969
--- /dev/null
+++ b/components/esp_hw_support/port/esp32c6/sar_periph_ctrl.c
@@ -0,0 +1,29 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * SAR related peripherals are interdependent. This file
+ * provides a united control to these registers, as multiple
+ * components require these controls.
+ *
+ * Related peripherals are:
+ * - ADC
+ * - PWDET
+ */
+
+#include "sdkconfig.h"
+#include "freertos/FreeRTOS.h"
+#include "esp_private/sar_periph_ctrl.h"
+
+void sar_periph_ctrl_init(void)
+{
+    //TODO: IDF-6124
+}
+
+void sar_periph_ctrl_power_disable(void)
+{
+    //TODO: IDF-6124
+}
diff --git a/components/esp_hw_support/port/esp32h2/CMakeLists.txt b/components/esp_hw_support/port/esp32h2/CMakeLists.txt
index f0b7582a6d..4d50f8cf38 100644
--- a/components/esp_hw_support/port/esp32h2/CMakeLists.txt
+++ b/components/esp_hw_support/port/esp32h2/CMakeLists.txt
@@ -4,12 +4,12 @@ set(srcs "rtc_clk_init.c"
          "rtc_pm.c"
          "rtc_sleep.c"
          "rtc_time.c"
-         "chip_info.c"
-         )
+         "chip_info.c")
 
 if(NOT BOOTLOADER_BUILD)
     list(APPEND srcs "esp_crypto_lock.c"
-                     "esp_ds.c")
+                     "esp_ds.c"
+                     "sar_periph_ctrl.c")
 
     if(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE)
         list(APPEND srcs "esp_memprot.c" "../esp_memprot_conv.c")
diff --git a/components/esp_hw_support/port/esp32h2/rtc_init.c b/components/esp_hw_support/port/esp32h2/rtc_init.c
index 975b5bf85e..80adb0ffff 100644
--- a/components/esp_hw_support/port/esp32h2/rtc_init.c
+++ b/components/esp_hw_support/port/esp32h2/rtc_init.c
@@ -20,6 +20,9 @@
 #include "esp_efuse_table.h"
 #include "i2c_pmu.h"
 #include "soc/clkrst_reg.h"
+#ifndef BOOTLOADER_BUILD
+#include "esp_private/sar_periph_ctrl.h"
+#endif
 
 void pmu_ctl(void);
 void dcdc_ctl(uint32_t mode);
@@ -135,6 +138,11 @@ void rtc_init(rtc_config_t cfg)
     }
     /* config dcdc frequency */
     REG_SET_FIELD(RTC_CNTL_DCDC_CTRL0_REG, RTC_CNTL_FSW_DCDC, RTC_CNTL_DCDC_FREQ_DEFAULT);
+
+#ifndef BOOTLOADER_BUILD
+    //initialise SAR related peripheral register settings
+    sar_periph_ctrl_init();
+#endif
 }
 
 void pmu_ctl(void)
diff --git a/components/esp_hw_support/port/esp32h2/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32h2/sar_periph_ctrl.c
new file mode 100644
index 0000000000..989608de64
--- /dev/null
+++ b/components/esp_hw_support/port/esp32h2/sar_periph_ctrl.c
@@ -0,0 +1,30 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * SAR related peripherals are interdependent. This file
+ * provides a united control to these registers, as multiple
+ * components require these controls.
+ *
+ * Related peripherals are:
+ * - ADC
+ * - PWDET
+ * - Temp Sensor
+ */
+
+#include "sdkconfig.h"
+#include "freertos/FreeRTOS.h"
+#include "esp_private/sar_periph_ctrl.h"
+
+void sar_periph_ctrl_init(void)
+{
+    //TODO: IDF-6123
+}
+
+void sar_periph_ctrl_power_disable(void)
+{
+    //TODO: IDF-6123
+}
diff --git a/components/esp_hw_support/port/esp32s2/CMakeLists.txt b/components/esp_hw_support/port/esp32s2/CMakeLists.txt
index 4a286ad2aa..cd16ce998b 100644
--- a/components/esp_hw_support/port/esp32s2/CMakeLists.txt
+++ b/components/esp_hw_support/port/esp32s2/CMakeLists.txt
@@ -8,13 +8,13 @@ set(srcs
     "rtc_pm.c"
     "rtc_sleep.c"
     "rtc_time.c"
-    "chip_info.c"
-    )
+    "chip_info.c")
 
 if(NOT BOOTLOADER_BUILD)
     list(APPEND srcs "memprot.c"
                      "esp_crypto_lock.c"
-                     "esp_ds.c")
+                     "esp_ds.c"
+                     "sar_periph_ctrl.c")
 
     # init constructor for wifi
     list(APPEND srcs "adc2_init_cal.c")
diff --git a/components/esp_hw_support/port/esp32s2/rtc_init.c b/components/esp_hw_support/port/esp32s2/rtc_init.c
index 8ae329581c..18437d7a09 100644
--- a/components/esp_hw_support/port/esp32s2/rtc_init.c
+++ b/components/esp_hw_support/port/esp32s2/rtc_init.c
@@ -18,6 +18,9 @@
 #include "esp_hw_log.h"
 #include "esp_efuse.h"
 #include "esp_efuse_table.h"
+#ifndef BOOTLOADER_BUILD
+#include "esp_private/sar_periph_ctrl.h"
+#endif
 
 __attribute__((unused)) static const char *TAG = "rtc_init";
 
@@ -163,6 +166,11 @@ void rtc_init(rtc_config_t cfg)
 
     REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
     REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
+
+#ifndef BOOTLOADER_BUILD
+    //initialise SAR related peripheral register settings
+    sar_periph_ctrl_init();
+#endif
 }
 
 rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
diff --git a/components/esp_hw_support/port/esp32s2/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32s2/sar_periph_ctrl.c
new file mode 100644
index 0000000000..b0acdf96cd
--- /dev/null
+++ b/components/esp_hw_support/port/esp32s2/sar_periph_ctrl.c
@@ -0,0 +1,38 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * SAR related peripherals are interdependent. This file
+ * provides a united control to these registers, as multiple
+ * components require these controls.
+ *
+ * Related peripherals are:
+ * - ADC
+ * - PWDET
+ * - Temp Sensor
+ */
+
+#include "sdkconfig.h"
+#include "freertos/FreeRTOS.h"
+#include "esp_private/sar_periph_ctrl.h"
+#include "hal/sar_ctrl_ll.h"
+
+extern portMUX_TYPE rtc_spinlock;
+
+void sar_periph_ctrl_init(void)
+{
+    //Put SAR control mux to FSM state
+    sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
+
+    //Add other periph power control initialisation here
+}
+
+void sar_periph_ctrl_power_disable(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
diff --git a/components/esp_hw_support/port/esp32s3/CMakeLists.txt b/components/esp_hw_support/port/esp32s3/CMakeLists.txt
index 18d8718097..378b7915d5 100644
--- a/components/esp_hw_support/port/esp32s3/CMakeLists.txt
+++ b/components/esp_hw_support/port/esp32s3/CMakeLists.txt
@@ -8,12 +8,12 @@ set(srcs
     "rtc_pm.c"
     "rtc_sleep.c"
     "rtc_time.c"
-    "chip_info.c"
-   )
+    "chip_info.c")
 
 if(NOT BOOTLOADER_BUILD)
     list(APPEND srcs "esp_ds.c"
-                     "esp_crypto_lock.c")
+                     "esp_crypto_lock.c"
+                     "sar_periph_ctrl.c")
 
     if(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE)
         list(APPEND srcs "esp_memprot.c" "../esp_memprot_conv.c")
diff --git a/components/esp_hw_support/port/esp32s3/rtc_init.c b/components/esp_hw_support/port/esp32s3/rtc_init.c
index b4e364594f..864047748d 100644
--- a/components/esp_hw_support/port/esp32s3/rtc_init.c
+++ b/components/esp_hw_support/port/esp32s3/rtc_init.c
@@ -25,6 +25,9 @@
 #include "esp_efuse_table.h"
 #include "esp_private/spi_flash_os.h"
 #include "hal/efuse_hal.h"
+#ifndef BOOTLOADER_BUILD
+#include "esp_private/sar_periph_ctrl.h"
+#endif
 
 #define RTC_CNTL_MEM_FORCE_NOISO (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO)
 
@@ -196,6 +199,11 @@ void rtc_init(rtc_config_t cfg)
 
     REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
     REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
+
+#ifndef BOOTLOADER_BUILD
+    //initialise SAR related peripheral register settings
+    sar_periph_ctrl_init();
+#endif
 }
 
 rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
diff --git a/components/esp_hw_support/port/esp32s3/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32s3/sar_periph_ctrl.c
new file mode 100644
index 0000000000..b0acdf96cd
--- /dev/null
+++ b/components/esp_hw_support/port/esp32s3/sar_periph_ctrl.c
@@ -0,0 +1,38 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * SAR related peripherals are interdependent. This file
+ * provides a united control to these registers, as multiple
+ * components require these controls.
+ *
+ * Related peripherals are:
+ * - ADC
+ * - PWDET
+ * - Temp Sensor
+ */
+
+#include "sdkconfig.h"
+#include "freertos/FreeRTOS.h"
+#include "esp_private/sar_periph_ctrl.h"
+#include "hal/sar_ctrl_ll.h"
+
+extern portMUX_TYPE rtc_spinlock;
+
+void sar_periph_ctrl_init(void)
+{
+    //Put SAR control mux to FSM state
+    sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
+
+    //Add other periph power control initialisation here
+}
+
+void sar_periph_ctrl_power_disable(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
diff --git a/components/hal/esp32/include/hal/sar_ctrl_ll.h b/components/hal/esp32/include/hal/sar_ctrl_ll.h
new file mode 100644
index 0000000000..a4046036e3
--- /dev/null
+++ b/components/hal/esp32/include/hal/sar_ctrl_ll.h
@@ -0,0 +1,56 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * SAR related peripherals are interdependent.
+ * Related peripherals are:
+ * - ADC
+ * - PWDET
+ *
+ * All of above peripherals require SAR to work correctly.
+ * As SAR has some registers that will influence above mentioned peripherals.
+ * This file gives an abstraction for such registers
+ */
+
+#pragma once
+
+#include <stdlib.h>
+#include "soc/sens_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef enum {
+    SAR_CTRL_LL_POWER_FSM,     //SAR power controlled by FSM
+    SAR_CTRL_LL_POWER_ON,      //SAR power on
+    SAR_CTRL_LL_POWER_OFF,     //SAR power off
+} sar_ctrl_ll_power_t;
+
+/*---------------------------------------------------------------
+                    SAR power control
+---------------------------------------------------------------*/
+/**
+ * Set SAR power mode
+ *
+ * @param mode  See `sar_ctrl_ll_power_t`
+ */
+static inline void sar_ctrl_ll_set_power_mode(sar_ctrl_ll_power_t mode)
+{
+    if (mode == SAR_CTRL_LL_POWER_FSM) {
+        SENS.sar_meas_wait2.force_xpd_sar = 0x0;
+    } else if (mode == SAR_CTRL_LL_POWER_ON) {
+        SENS.sar_meas_wait2.force_xpd_sar = 0x3;
+    } else {
+        SENS.sar_meas_wait2.force_xpd_sar = 0x2;
+    }
+}
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32c2/include/hal/sar_ctrl_ll.h b/components/hal/esp32c2/include/hal/sar_ctrl_ll.h
new file mode 100644
index 0000000000..1809ecd661
--- /dev/null
+++ b/components/hal/esp32c2/include/hal/sar_ctrl_ll.h
@@ -0,0 +1,57 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * SAR related peripherals are interdependent.
+ * Related peripherals are:
+ * - ADC
+ * - PWDET
+ * - Temp Sensor
+ *
+ * All of above peripherals require SAR to work correctly.
+ * As SAR has some registers that will influence above mentioned peripherals.
+ * This file gives an abstraction for such registers
+ */
+
+#pragma once
+
+#include <stdlib.h>
+#include "soc/rtc_cntl_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef enum {
+    SAR_CTRL_LL_POWER_FSM,     //SAR power controlled by FSM
+    SAR_CTRL_LL_POWER_ON,      //SAR power on
+    SAR_CTRL_LL_POWER_OFF,     //SAR power off
+} sar_ctrl_ll_power_t;
+
+/*---------------------------------------------------------------
+                    SAR power control
+---------------------------------------------------------------*/
+/**
+ * Set SAR power mode
+ *
+ * @param mode  See `sar_ctrl_ll_power_t`
+ */
+static inline void sar_ctrl_ll_set_power_mode(sar_ctrl_ll_power_t mode)
+{
+    if (mode == SAR_CTRL_LL_POWER_FSM) {
+        RTCCNTL.sensor_ctrl.force_xpd_sar = 0x0;
+    } else if (mode == SAR_CTRL_LL_POWER_ON) {
+        RTCCNTL.sensor_ctrl.force_xpd_sar = 0x3;
+    } else {
+        RTCCNTL.sensor_ctrl.force_xpd_sar = 0x2;
+    }
+}
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32c3/include/hal/sar_ctrl_ll.h b/components/hal/esp32c3/include/hal/sar_ctrl_ll.h
new file mode 100644
index 0000000000..1809ecd661
--- /dev/null
+++ b/components/hal/esp32c3/include/hal/sar_ctrl_ll.h
@@ -0,0 +1,57 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * SAR related peripherals are interdependent.
+ * Related peripherals are:
+ * - ADC
+ * - PWDET
+ * - Temp Sensor
+ *
+ * All of above peripherals require SAR to work correctly.
+ * As SAR has some registers that will influence above mentioned peripherals.
+ * This file gives an abstraction for such registers
+ */
+
+#pragma once
+
+#include <stdlib.h>
+#include "soc/rtc_cntl_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef enum {
+    SAR_CTRL_LL_POWER_FSM,     //SAR power controlled by FSM
+    SAR_CTRL_LL_POWER_ON,      //SAR power on
+    SAR_CTRL_LL_POWER_OFF,     //SAR power off
+} sar_ctrl_ll_power_t;
+
+/*---------------------------------------------------------------
+                    SAR power control
+---------------------------------------------------------------*/
+/**
+ * Set SAR power mode
+ *
+ * @param mode  See `sar_ctrl_ll_power_t`
+ */
+static inline void sar_ctrl_ll_set_power_mode(sar_ctrl_ll_power_t mode)
+{
+    if (mode == SAR_CTRL_LL_POWER_FSM) {
+        RTCCNTL.sensor_ctrl.force_xpd_sar = 0x0;
+    } else if (mode == SAR_CTRL_LL_POWER_ON) {
+        RTCCNTL.sensor_ctrl.force_xpd_sar = 0x3;
+    } else {
+        RTCCNTL.sensor_ctrl.force_xpd_sar = 0x2;
+    }
+}
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32c6/include/hal/sar_ctrl_ll.h b/components/hal/esp32c6/include/hal/sar_ctrl_ll.h
new file mode 100644
index 0000000000..68b6a482fe
--- /dev/null
+++ b/components/hal/esp32c6/include/hal/sar_ctrl_ll.h
@@ -0,0 +1,50 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * SAR related peripherals are interdependent.
+ * Related peripherals are:
+ * - ADC
+ * - PWDET
+ *
+ * All of above peripherals require SAR to work correctly.
+ * As SAR has some registers that will influence above mentioned peripherals.
+ * This file gives an abstraction for such registers
+ */
+
+#pragma once
+
+#include <stdlib.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef enum {
+    SAR_CTRL_LL_POWER_FSM,     //SAR power controlled by FSM
+    SAR_CTRL_LL_POWER_ON,      //SAR power on
+    SAR_CTRL_LL_POWER_OFF,     //SAR power off
+} sar_ctrl_ll_power_t;
+
+/*---------------------------------------------------------------
+                    SAR power control
+---------------------------------------------------------------*/
+/**
+ * Set SAR power mode
+ *
+ * @param mode  See `sar_ctrl_ll_power_t`
+ */
+static inline void sar_ctrl_ll_set_power_mode(sar_ctrl_ll_power_t mode)
+{
+    //TODO: IDF-6124
+    abort();
+}
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32h2/include/hal/sar_ctrl_ll.h b/components/hal/esp32h2/include/hal/sar_ctrl_ll.h
new file mode 100644
index 0000000000..e4e3222cf0
--- /dev/null
+++ b/components/hal/esp32h2/include/hal/sar_ctrl_ll.h
@@ -0,0 +1,51 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * SAR related peripherals are interdependent.
+ * Related peripherals are:
+ * - ADC
+ * - PWDET
+ * - Temp Sensor
+ *
+ * All of above peripherals require SAR to work correctly.
+ * As SAR has some registers that will influence above mentioned peripherals.
+ * This file gives an abstraction for such registers
+ */
+
+#pragma once
+
+#include <stdlib.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef enum {
+    SAR_CTRL_LL_POWER_FSM,     //SAR power controlled by FSM
+    SAR_CTRL_LL_POWER_ON,      //SAR power on
+    SAR_CTRL_LL_POWER_OFF,     //SAR power off
+} sar_ctrl_ll_power_t;
+
+/*---------------------------------------------------------------
+                    SAR power control
+---------------------------------------------------------------*/
+/**
+ * Set SAR power mode
+ *
+ * @param mode  See `sar_ctrl_ll_power_t`
+ */
+static inline void sar_ctrl_ll_set_power_mode(sar_ctrl_ll_power_t mode)
+{
+    //TODO: IDF-6123
+    abort();
+}
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32s2/include/hal/sar_ctrl_ll.h b/components/hal/esp32s2/include/hal/sar_ctrl_ll.h
new file mode 100644
index 0000000000..d8583133e1
--- /dev/null
+++ b/components/hal/esp32s2/include/hal/sar_ctrl_ll.h
@@ -0,0 +1,57 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * SAR related peripherals are interdependent.
+ * Related peripherals are:
+ * - ADC
+ * - PWDET
+ * - Temp Sensor
+ *
+ * All of above peripherals require SAR to work correctly.
+ * As SAR has some registers that will influence above mentioned peripherals.
+ * This file gives an abstraction for such registers
+ */
+
+#pragma once
+
+#include <stdlib.h>
+#include "soc/sens_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef enum {
+    SAR_CTRL_LL_POWER_FSM,     //SAR power controlled by FSM
+    SAR_CTRL_LL_POWER_ON,      //SAR power on
+    SAR_CTRL_LL_POWER_OFF,     //SAR power off
+} sar_ctrl_ll_power_t;
+
+/*---------------------------------------------------------------
+                    SAR power control
+---------------------------------------------------------------*/
+/**
+ * Set SAR power mode
+ *
+ * @param mode  See `sar_ctrl_ll_power_t`
+ */
+static inline void sar_ctrl_ll_set_power_mode(sar_ctrl_ll_power_t mode)
+{
+    if (mode == SAR_CTRL_LL_POWER_FSM) {
+        SENS.sar_power_xpd_sar.force_xpd_sar = 0x0;
+    } else if (mode == SAR_CTRL_LL_POWER_ON) {
+        SENS.sar_power_xpd_sar.force_xpd_sar = 0x3;
+    } else {
+        SENS.sar_power_xpd_sar.force_xpd_sar = 0x2;
+    }
+}
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32s3/include/hal/sar_ctrl_ll.h b/components/hal/esp32s3/include/hal/sar_ctrl_ll.h
new file mode 100644
index 0000000000..d8583133e1
--- /dev/null
+++ b/components/hal/esp32s3/include/hal/sar_ctrl_ll.h
@@ -0,0 +1,57 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * SAR related peripherals are interdependent.
+ * Related peripherals are:
+ * - ADC
+ * - PWDET
+ * - Temp Sensor
+ *
+ * All of above peripherals require SAR to work correctly.
+ * As SAR has some registers that will influence above mentioned peripherals.
+ * This file gives an abstraction for such registers
+ */
+
+#pragma once
+
+#include <stdlib.h>
+#include "soc/sens_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef enum {
+    SAR_CTRL_LL_POWER_FSM,     //SAR power controlled by FSM
+    SAR_CTRL_LL_POWER_ON,      //SAR power on
+    SAR_CTRL_LL_POWER_OFF,     //SAR power off
+} sar_ctrl_ll_power_t;
+
+/*---------------------------------------------------------------
+                    SAR power control
+---------------------------------------------------------------*/
+/**
+ * Set SAR power mode
+ *
+ * @param mode  See `sar_ctrl_ll_power_t`
+ */
+static inline void sar_ctrl_ll_set_power_mode(sar_ctrl_ll_power_t mode)
+{
+    if (mode == SAR_CTRL_LL_POWER_FSM) {
+        SENS.sar_power_xpd_sar.force_xpd_sar = 0x0;
+    } else if (mode == SAR_CTRL_LL_POWER_ON) {
+        SENS.sar_power_xpd_sar.force_xpd_sar = 0x3;
+    } else {
+        SENS.sar_power_xpd_sar.force_xpd_sar = 0x2;
+    }
+}
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h
index 2df1be7bb5..dc8cf3316f 100644
--- a/components/soc/esp32s2/include/soc/soc_caps.h
+++ b/components/soc/esp32s2/include/soc/soc_caps.h
@@ -246,7 +246,6 @@
 #define SOC_RTCIO_HOLD_SUPPORTED 1
 #define SOC_RTCIO_WAKE_SUPPORTED 1
 
-
 /*-------------------------- Sigma Delta Modulator CAPS -----------------*/
 #define SOC_SDM_GROUPS             1U
 #define SOC_SDM_CHANNELS_PER_GROUP 8