diff --git a/components/esp_hw_support/sleep_gpio.c b/components/esp_hw_support/sleep_gpio.c
index 5c75c44bfb..87726d1150 100644
--- a/components/esp_hw_support/sleep_gpio.c
+++ b/components/esp_hw_support/sleep_gpio.c
@@ -62,20 +62,6 @@ void esp_sleep_config_gpio_isolate(void)
         }
     }
 
-#if CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM
-    int32_t mspi_io_cs1_io_num = esp_mspi_get_io(ESP_MSPI_IO_CS1);
-    if (GPIO_IS_VALID_GPIO(mspi_io_cs1_io_num)) {
-        gpio_sleep_set_pull_mode(mspi_io_cs1_io_num, GPIO_PULLUP_ONLY);
-    }
-#endif // CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM
-
-#if CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
-    int32_t mspi_io_cs0_io_num = esp_mspi_get_io(ESP_MSPI_IO_CS0);
-    if (GPIO_IS_VALID_GPIO(mspi_io_cs0_io_num)) {
-        gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_CS0), GPIO_PULLUP_ONLY);
-    }
-#endif // CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
-
 #if CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU
     gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_CLK), GPIO_PULLUP_ONLY);
     gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_Q),   GPIO_PULLUP_ONLY);
@@ -103,6 +89,21 @@ void esp_sleep_enable_gpio_switch(bool enable)
     ESP_EARLY_LOGI(TAG, "%s automatic switching of GPIO sleep configuration", enable ? "Enable" : "Disable");
     for (gpio_num_t gpio_num = GPIO_NUM_0; gpio_num < GPIO_NUM_MAX; gpio_num++) {
         if (GPIO_IS_VALID_GPIO(gpio_num)) {
+            /* If the PSRAM is disable in ESP32xx chips equipped with PSRAM, there will be a large current leakage. */
+#if CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM
+            if (gpio_num == esp_mspi_get_io(ESP_MSPI_IO_CS1)) {
+                gpio_sleep_sel_dis(gpio_num);
+                continue;
+            }
+#endif // CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM
+
+#if CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
+            if (gpio_num == esp_mspi_get_io(ESP_MSPI_IO_CS0)) {
+                gpio_sleep_sel_dis(gpio_num);
+                continue;
+            }
+#endif // CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
+
             if (enable) {
                 gpio_sleep_sel_en(gpio_num);
             } else {
@@ -189,13 +190,9 @@ void esp_deep_sleep_wakeup_io_reset(void)
 #if CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND || CONFIG_PM_SLP_DISABLE_GPIO
 ESP_SYSTEM_INIT_FN(esp_sleep_startup_init, SECONDARY, BIT(0), 105)
 {
-/* If the TOP domain is powered off, the GPIO will also be powered off during sleep,
-   and all configurations in the sleep state of GPIO will not take effect.*/
-#if !CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
     // Configure to isolate (disable the Input/Output/Pullup/Pulldown
     // function of the pin) all GPIO pins in sleep state
     esp_sleep_config_gpio_isolate();
-#endif
     // Enable automatic switching of GPIO configuration
     esp_sleep_enable_gpio_switch(true);
     return ESP_OK;
diff --git a/components/hal/esp32c61/include/hal/uart_ll.h b/components/hal/esp32c61/include/hal/uart_ll.h
index c14dea7524..6e5a0a208f 100644
--- a/components/hal/esp32c61/include/hal/uart_ll.h
+++ b/components/hal/esp32c61/include/hal/uart_ll.h
@@ -31,7 +31,7 @@ extern "C" {
 // Get UART hardware instance with giving uart num
 #define UART_LL_GET_HW(num) (((num) == UART_NUM_0) ? (&UART0) : (&UART1))
 
-#define UART_LL_MIN_WAKEUP_THRESH (2)
+#define UART_LL_MIN_WAKEUP_THRESH (3)
 #define UART_LL_INTR_MASK         (0x7ffff) //All interrupt mask
 
 #define UART_LL_FSM_IDLE                       (0x0)