diff --git a/components/bootloader_support/src/bootloader_random_esp32c5.c b/components/bootloader_support/src/bootloader_random_esp32c5.c
index e973d99043..688a7619ec 100644
--- a/components/bootloader_support/src/bootloader_random_esp32c5.c
+++ b/components/bootloader_support/src/bootloader_random_esp32c5.c
@@ -10,6 +10,8 @@
 #include "hal/adc_types.h"
 #include "esp_private/regi2c_ctrl.h"
 
+#define I2C_SAR_ADC_INIT_CODE_VAL 2150
+
 void bootloader_random_enable(void)
 {
     adc_ll_reset_register();
@@ -29,8 +31,8 @@ void bootloader_random_enable(void)
     ANALOG_CLOCK_ENABLE();
 
     adc_ll_regi2c_init();
-    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
-    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
 
     adc_digi_pattern_config_t pattern_config = {};
     pattern_config.unit = ADC_UNIT_1;
diff --git a/components/bootloader_support/src/bootloader_random_esp32c6.c b/components/bootloader_support/src/bootloader_random_esp32c6.c
index efd6ab384a..de45f07c32 100644
--- a/components/bootloader_support/src/bootloader_random_esp32c6.c
+++ b/components/bootloader_support/src/bootloader_random_esp32c6.c
@@ -10,6 +10,8 @@
 #include "hal/adc_types.h"
 #include "esp_private/regi2c_ctrl.h"
 
+#define I2C_SAR_ADC_INIT_CODE_VAL 2150
+
 void bootloader_random_enable(void)
 {
     adc_ll_reset_register();
@@ -29,8 +31,8 @@ void bootloader_random_enable(void)
     ANALOG_CLOCK_ENABLE();
 
     adc_ll_regi2c_init();
-    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
-    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
 
     adc_digi_pattern_config_t pattern_config = {};
     pattern_config.unit = ADC_UNIT_2;
diff --git a/components/bootloader_support/src/bootloader_random_esp32c61.c b/components/bootloader_support/src/bootloader_random_esp32c61.c
index 7bc9322c94..1f1e2ad9ff 100644
--- a/components/bootloader_support/src/bootloader_random_esp32c61.c
+++ b/components/bootloader_support/src/bootloader_random_esp32c61.c
@@ -10,6 +10,8 @@
 #include "hal/adc_types.h"
 #include "esp_private/regi2c_ctrl.h"
 
+#define I2C_SAR_ADC_INIT_CODE_VAL 2150
+
 void bootloader_random_enable(void)
 {
     adc_ll_reset_register();
@@ -29,8 +31,8 @@ void bootloader_random_enable(void)
     ANALOG_CLOCK_ENABLE();
 
     adc_ll_regi2c_init();
-    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
-    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
 
     adc_digi_pattern_config_t pattern_config = {};
     pattern_config.unit = ADC_UNIT_1;
diff --git a/components/bootloader_support/src/bootloader_random_esp32h2.c b/components/bootloader_support/src/bootloader_random_esp32h2.c
index 3c6ba78987..4c4f5155a7 100644
--- a/components/bootloader_support/src/bootloader_random_esp32h2.c
+++ b/components/bootloader_support/src/bootloader_random_esp32h2.c
@@ -10,6 +10,8 @@
 #include "hal/adc_types.h"
 #include "esp_private/regi2c_ctrl.h"
 
+#define I2C_SAR_ADC_INIT_CODE_VAL 2150
+
 void bootloader_random_enable(void)
 {
     adc_ll_reset_register();
@@ -29,8 +31,8 @@ void bootloader_random_enable(void)
     ANALOG_CLOCK_ENABLE();
 
     adc_ll_regi2c_init();
-    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
-    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
 
     adc_digi_pattern_config_t pattern_config = {};
     pattern_config.atten = ADC_ATTEN_DB_2_5;
diff --git a/components/bootloader_support/src/bootloader_random_esp32p4.c b/components/bootloader_support/src/bootloader_random_esp32p4.c
index 5fdcb42bcb..baa1effa57 100644
--- a/components/bootloader_support/src/bootloader_random_esp32p4.c
+++ b/components/bootloader_support/src/bootloader_random_esp32p4.c
@@ -1,108 +1,72 @@
 /*
  * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
+*
+* SPDX-License-Identifier: Apache-2.0
+*/
+#include "sdkconfig.h"
 #include "bootloader_random.h"
-#include "soc/soc.h"
-#include "soc/adc_reg.h"
-#include "soc/pmu_reg.h"
-#include "soc/regi2c_saradc.h"
-#include "soc/hp_sys_clkrst_reg.h"
-#include "soc/lp_adc_reg.h"
-#include "esp_private/regi2c_ctrl.h"
-#include "esp_rom_regi2c.h"
+#include "hal/regi2c_ctrl_ll.h"
+#include "hal/adc_ll.h"
+#include "hal/adc_types.h"
 
-// TODO IDF-6497: once ADC API is supported, use the API instead of defining functions and constants here
+#include "esp_private/periph_ctrl.h"
+#include "esp_private/adc_share_hw_ctrl.h"
 
 #define I2C_SAR_ADC_INIT_CODE_VAL 2166
 
-typedef struct {
-    int atten;
-    int channel;
-} pattern_item;
-
-typedef struct {
-    pattern_item item[4];
-} pattern_table;
-
-static void adc1_fix_initcode_set(uint32_t initcode_value)
-{
-    uint32_t msb = initcode_value >> 8;
-    uint32_t lsb = initcode_value & 0xff;
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
-}
-
-//total 4 tables
-static void hpadc_sar1_pattern_table_cfg(unsigned int table_idx, pattern_table table)
-{
-    uint32_t wdata = 0;
-    wdata = (table.item[0].channel << 20 | table.item[0].atten << 18 |
-            table.item[1].channel << 14|table.item[1].atten << 12 |
-            table.item[2].channel << 8 |table.item[2].atten << 6 |
-            table.item[3].channel << 2 |table.item[3].atten);
-    WRITE_PERI_REG(ADC_SAR1_PATT_TAB1_REG + table_idx * 4, wdata);
-}
-
 void bootloader_random_enable(void)
 {
-    pattern_table sar1_table[4] = {};
-    uint32_t pattern_len = 0;
+    _adc_ll_reset_register();
+    _adc_ll_enable_bus_clock(true);
 
-    SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_ADC_APB_CLK_EN);
-    SET_PERI_REG_MASK(HP_SYS_CLKRST_PERI_CLK_CTRL23_REG, HP_SYS_CLKRST_REG_ADC_CLK_EN);
+    adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
+    adc_ll_digi_controller_clk_div(0, 0, 0);
 
-    SET_PERI_REG_MASK(RTCADC_MEAS1_MUX_REG, RTCADC_SAR1_DIG_FORCE);
-    SET_PERI_REG_MASK(PMU_RF_PWC_REG,PMU_XPD_PERIF_I2C);
-
-    uint32_t sar1_clk_div_num = GET_PERI_REG_BITS2((HP_SYS_CLKRST_PERI_CLK_CTRL24_REG),
-            (HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_M),
-            (HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_S));
-
-    SET_PERI_REG_MASK(ADC_CTRL_REG_REG, ADC_START_FORCE); //start force 1
+    // some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
+#ifndef BOOTLOADER_BUILD
+    regi2c_saradc_enable();
+#else
+    regi2c_ctrl_ll_i2c_sar_periph_enable();
+#endif
 
     // enable analog i2c master clock for RNG runtime
     ANALOG_CLOCK_ENABLE();
 
-    adc1_fix_initcode_set(I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_regi2c_init();
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
 
-    //  cfg pattern table
-    sar1_table[0].item[0].channel = 10; //rand() % 6;
-    sar1_table[0].item[0].atten = 3;
-    sar1_table[0].item[1].channel = 10;
-    sar1_table[0].item[1].atten = 3;
-    sar1_table[0].item[2].channel = 10;
-    sar1_table[0].item[2].atten = 3;
-    sar1_table[0].item[3].channel = 10;
-    sar1_table[0].item[3].atten = 3;
+    adc_digi_pattern_config_t pattern_config = {};
+    pattern_config.unit = ADC_UNIT_1;
+    pattern_config.atten = ADC_ATTEN_DB_12;
+    pattern_config.channel = ADC_CHANNEL_10;
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 0, pattern_config);
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 1, pattern_config);
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 2, pattern_config);
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 3, pattern_config);
+    adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, 1);
 
-    hpadc_sar1_pattern_table_cfg(0, sar1_table[0]);
-    SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_SAR1_PATT_LEN, pattern_len, ADC_SAR1_PATT_LEN_S);
+    adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_DIG);
+    adc_ll_digi_set_power_manage(ADC_UNIT_1, ADC_LL_POWER_SW_ON);
 
-    SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_XPD_SAR1_FORCE, 3, ADC_XPD_SAR1_FORCE_S);
-    SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_XPD_SAR2_FORCE, 3, ADC_XPD_SAR2_FORCE_S);
-
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_ENT_VDD_GRP1, 1);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_DTEST_VDD_GRP1, 0);
-
-    CLEAR_PERI_REG_MASK(ADC_CTRL_REG_REG, ADC_START_FORCE);
-    SET_PERI_REG_MASK(ADC_CTRL2_REG, ADC_TIMER_EN);
-    SET_PERI_REG_BITS(ADC_CTRL2_REG, ADC_TIMER_TARGET, sar1_clk_div_num * 25, ADC_TIMER_TARGET_S);
-
-    while (GET_PERI_REG_MASK(ADC_INT_RAW_REG, ADC_SAR1_DONE_INT_RAW) == 0) { }
-
-    SET_PERI_REG_MASK(ADC_INT_CLR_REG, ADC_APB_SARADC1_DONE_INT_CLR);
+    adc_ll_digi_set_clk_div(15);
+    adc_ll_digi_set_trigger_interval(100);
+    adc_ll_digi_trigger_enable();
 }
 
 void bootloader_random_disable(void)
 {
+    adc_ll_digi_trigger_disable();
+    adc_ll_digi_reset_pattern_table();
+    adc_ll_set_calibration_param(ADC_UNIT_1, 0x0);
+    adc_ll_set_calibration_param(ADC_UNIT_2, 0x0);
+    adc_ll_regi2c_adc_deinit();
+
+#ifndef BOOTLOADER_BUILD
+    regi2c_saradc_disable();
+#endif
+
     // disable analog i2c master clock
     ANALOG_CLOCK_DISABLE();
-
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0);
-
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_ENT_VDD_GRP1, 0);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_DTEST_VDD_GRP1, 0);
+    adc_ll_digi_controller_clk_div(4, 0, 0);
+    adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
 }
diff --git a/components/hal/esp32c5/include/hal/adc_ll.h b/components/hal/esp32c5/include/hal/adc_ll.h
index 716669bb5d..91f82a0f37 100644
--- a/components/hal/esp32c5/include/hal/adc_ll.h
+++ b/components/hal/esp32c5/include/hal/adc_ll.h
@@ -139,6 +139,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
  *
  * @param div Division factor.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
@@ -188,6 +189,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
  * @param adc_n ADC unit.
  * @param patt_len Items range: 1 ~ 8.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
 {
     APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_len = patt_len - 1;
@@ -203,6 +205,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
  * @param pattern_index Items index. Range: 0 ~ 7.
  * @param pattern Stored conversion rules.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
 {
     uint32_t tab;
@@ -275,6 +278,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
  * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
  * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_target = cycle;
@@ -283,6 +287,7 @@ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 /**
  * Enable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_enable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 1;
@@ -291,6 +296,7 @@ static inline void adc_ll_digi_trigger_enable(void)
 /**
  * Disable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_disable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 0;
@@ -304,6 +310,7 @@ static inline void adc_ll_digi_trigger_disable(void)
  * @param div_b Division factor. Range: 1 ~ 63.
  * @param div_a Division factor. Range: 0 ~ 63.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num);
@@ -316,6 +323,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
  *
  * @param clk_src clock source for ADC digital controller.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
 {
     switch (clk_src) {
@@ -570,6 +578,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
  * @brief Enable the ADC APB clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_bus_clock(bool enable)
 {
     PCR.saradc_conf.saradc_reg_clk_en = enable;
@@ -579,6 +588,7 @@ static inline void adc_ll_enable_bus_clock(bool enable)
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
@@ -587,6 +597,7 @@ static inline void adc_ll_enable_func_clock(bool enable)
 /**
  * @brief Reset ADC module
  */
+__attribute__((always_inline))
 static inline void adc_ll_reset_register(void)
 {
     PCR.saradc_conf.saradc_rst_en = 1;
diff --git a/components/hal/esp32c6/include/hal/adc_ll.h b/components/hal/esp32c6/include/hal/adc_ll.h
index 589bb46829..a79fec376a 100644
--- a/components/hal/esp32c6/include/hal/adc_ll.h
+++ b/components/hal/esp32c6/include/hal/adc_ll.h
@@ -138,6 +138,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
  *
  * @param div Division factor.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
@@ -187,6 +188,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
  * @param adc_n ADC unit.
  * @param patt_len Items range: 1 ~ 8.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
 {
     APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_len = patt_len - 1;
@@ -202,6 +204,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
  * @param pattern_index Items index. Range: 0 ~ 7.
  * @param pattern Stored conversion rules.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
 {
     uint32_t tab;
@@ -274,6 +277,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
  * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
  * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_target = cycle;
@@ -282,6 +286,7 @@ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 /**
  * Enable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_enable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 1;
@@ -290,6 +295,7 @@ static inline void adc_ll_digi_trigger_enable(void)
 /**
  * Disable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_disable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 0;
@@ -303,6 +309,7 @@ static inline void adc_ll_digi_trigger_disable(void)
  * @param div_b Division factor. Range: 1 ~ 63.
  * @param div_a Division factor. Range: 0 ~ 63.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num);
@@ -315,6 +322,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
  *
  * @param clk_src clock source for ADC digital controller.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
 {
     switch (clk_src) {
@@ -569,6 +577,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
  * @brief Enable the ADC clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_bus_clock(bool enable)
 {
     PCR.saradc_conf.saradc_reg_clk_en = enable;
@@ -578,6 +587,7 @@ static inline void adc_ll_enable_bus_clock(bool enable)
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
@@ -586,6 +596,7 @@ static inline void adc_ll_enable_func_clock(bool enable)
 /**
  * @brief Reset ADC module
  */
+__attribute__((always_inline))
 static inline void adc_ll_reset_register(void)
 {
     PCR.saradc_conf.saradc_rst_en = 1;
diff --git a/components/hal/esp32c61/include/hal/adc_ll.h b/components/hal/esp32c61/include/hal/adc_ll.h
index 36df5fcd8d..b83a9851e2 100644
--- a/components/hal/esp32c61/include/hal/adc_ll.h
+++ b/components/hal/esp32c61/include/hal/adc_ll.h
@@ -139,6 +139,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
  *
  * @param div Division factor.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
@@ -188,6 +189,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
  * @param adc_n ADC unit.
  * @param patt_len Items range: 1 ~ 8.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
 {
     ADC.saradc_ctrl.saradc_sar_patt_len = patt_len - 1;
@@ -203,6 +205,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
  * @param pattern_index Items index. Range: 0 ~ 7.
  * @param pattern Stored conversion rules.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
 {
     uint32_t tab;
@@ -277,6 +280,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
  * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
  * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 {
     ADC.saradc_ctrl2.saradc_timer_target = cycle;
@@ -285,6 +289,7 @@ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 /**
  * Enable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_enable(void)
 {
     ADC.saradc_ctrl2.saradc_timer_en = 1;
@@ -293,6 +298,7 @@ static inline void adc_ll_digi_trigger_enable(void)
 /**
  * Disable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_disable(void)
 {
     ADC.saradc_ctrl2.saradc_timer_en = 0;
@@ -306,6 +312,7 @@ static inline void adc_ll_digi_trigger_disable(void)
  * @param div_b Division factor. Range: 1 ~ 63.
  * @param div_a Division factor. Range: 0 ~ 63.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num);
@@ -318,6 +325,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
  *
  * @param clk_src clock source for ADC digital controller.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
 {
     switch (clk_src) {
@@ -572,6 +580,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
  * @brief Enable the ADC APB clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_bus_clock(bool enable)
 {
     PCR.saradc_conf.saradc_reg_clk_en = enable;
@@ -581,6 +590,7 @@ static inline void adc_ll_enable_bus_clock(bool enable)
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
@@ -589,6 +599,7 @@ static inline void adc_ll_enable_func_clock(bool enable)
 /**
  * @brief Reset ADC module
  */
+__attribute__((always_inline))
 static inline void adc_ll_reset_register(void)
 {
     PCR.saradc_conf.saradc_rst_en = 1;
diff --git a/components/hal/esp32h2/include/hal/adc_ll.h b/components/hal/esp32h2/include/hal/adc_ll.h
index b7742f2ea1..5c457b14ec 100644
--- a/components/hal/esp32h2/include/hal/adc_ll.h
+++ b/components/hal/esp32h2/include/hal/adc_ll.h
@@ -139,6 +139,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
  *
  * @param div Division factor.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
@@ -188,6 +189,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
  * @param adc_n ADC unit.
  * @param patt_len Items range: 1 ~ 8.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
 {
     APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_len = patt_len - 1;
@@ -203,6 +205,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
  * @param pattern_index Items index. Range: 0 ~ 7.
  * @param pattern Stored conversion rules.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
 {
     uint32_t tab;
@@ -275,6 +278,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
  * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
  * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_target = cycle;
@@ -283,6 +287,7 @@ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 /**
  * Enable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_enable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 1;
@@ -291,6 +296,7 @@ static inline void adc_ll_digi_trigger_enable(void)
 /**
  * Disable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_disable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 0;
@@ -304,6 +310,7 @@ static inline void adc_ll_digi_trigger_disable(void)
  * @param div_b Division factor. Range: 1 ~ 63.
  * @param div_a Division factor. Range: 0 ~ 63.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num);
@@ -316,6 +323,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
  *
  * @param clk_src clock source for ADC digital controller.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
 {
     switch (clk_src) {
@@ -570,6 +578,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
  * @brief Enable the ADC clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_bus_clock(bool enable)
 {
     PCR.saradc_conf.saradc_reg_clk_en = enable;
@@ -579,6 +588,7 @@ static inline void adc_ll_enable_bus_clock(bool enable)
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
@@ -587,6 +597,7 @@ static inline void adc_ll_enable_func_clock(bool enable)
 /**
  * @brief Reset ADC module
  */
+__attribute__((always_inline))
 static inline void adc_ll_reset_register(void)
 {
     PCR.saradc_conf.saradc_rst_en = 1;
diff --git a/components/hal/esp32p4/include/hal/adc_ll.h b/components/hal/esp32p4/include/hal/adc_ll.h
index 20d94c8df0..e6bc2c3e32 100644
--- a/components/hal/esp32p4/include/hal/adc_ll.h
+++ b/components/hal/esp32p4/include/hal/adc_ll.h
@@ -145,6 +145,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
  *
  * @param div Division factor.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
@@ -202,6 +203,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
  * @param div_b Division factor. Range: 1 ~ 63.
  * @param div_a Division factor. Range: 0 ~ 63.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl23, reg_adc_clk_div_num, div_num);
@@ -214,6 +216,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
  *
  * @param clk_src clock source for ADC digital controller.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
 {
     switch (clk_src) {
@@ -326,6 +329,7 @@ static inline void adc_ll_digi_filter_enable(adc_digi_iir_filter_t idx, adc_unit
  * @param adc_n ADC unit.
  * @param patt_len Items range: 1 ~ 16.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
 {
     if (adc_n == ADC_UNIT_1) {
@@ -345,6 +349,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
  * @param pattern_index Items index. Range: 0 ~ 11.
  * @param pattern Stored conversion rules.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
 {
     uint32_t tab;
@@ -366,6 +371,18 @@ static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t patt
     }
 }
 
+
+/**
+ * Rest pattern table to default value
+ */
+static inline void adc_ll_digi_reset_pattern_table(void)
+{
+    for(int i = 0; i < 4; i++) {
+        ADC.sar1_patt_tab[i].sar1_patt_tab = 0xffffff;
+        ADC.sar2_patt_tab[i].sar2_patt_tab = 0xffffff;
+    }
+}
+
 /**
  * Reset the pattern table pointer, then take the measurement rule from table header in next measurement.
  *
@@ -404,6 +421,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
  * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
  * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 {
     ADC.ctrl2.timer_target = cycle;
@@ -448,6 +466,7 @@ static inline void adc_ll_digi_reset(void)
 /**
  * Enable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_enable(void)
 {
     ADC.ctrl2.timer_sel = 1;
@@ -457,6 +476,7 @@ static inline void adc_ll_digi_trigger_enable(void)
 /**
  * Disable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_disable(void)
 {
     ADC.ctrl2.timer_en = 0;
@@ -514,24 +534,26 @@ static inline void _adc_ll_sar2_clock_force_en(bool enable)
  * @brief Enable the ADC clock
  * @param enable true to enable, false to disable
  */
-static inline void adc_ll_enable_bus_clock(bool enable)
+__attribute__((always_inline))
+static inline void _adc_ll_enable_bus_clock(bool enable)
 {
     HP_SYS_CLKRST.soc_clk_ctrl2.reg_adc_apb_clk_en = enable;
     HP_SYS_CLKRST.peri_clk_ctrl23.reg_adc_clk_en = enable;
 }
 // HP_SYS_CLKRST.soc_clk_ctrl2 are shared registers, so this function must be used in an atomic way
-#define adc_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; adc_ll_enable_bus_clock(__VA_ARGS__)
+#define adc_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _adc_ll_enable_bus_clock(__VA_ARGS__)
 
 /**
  * @brief Reset ADC module
  */
-static inline void adc_ll_reset_register(void)
+__attribute__((always_inline))
+static inline void _adc_ll_reset_register(void)
 {
     HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_adc = 1;
     HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_adc = 0;
 }
 //  HP_SYS_CLKRST.hp_rst_en2 is a shared register, so this function must be used in an atomic way
-#define adc_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; adc_ll_reset_register(__VA_ARGS__)
+#define adc_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _adc_ll_reset_register(__VA_ARGS__)
 
 
 
@@ -541,6 +563,7 @@ static inline void adc_ll_reset_register(void)
  * @param adc_n ADC unit.
  * @param manage Set ADC power status.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_power_manage(adc_unit_t adc_n, adc_ll_power_t manage)
 {
     if (adc_n == ADC_UNIT_1) {
@@ -747,6 +770,48 @@ static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param
     }
 }
 
+/**
+ * Set the SAR DTEST param
+ *
+ * @param param DTEST value
+ */
+__attribute__((always_inline))
+static inline void adc_ll_set_dtest_param(uint32_t param)
+{
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_DTEST_VDD_GRP1, param);
+}
+
+/**
+ * Set the SAR ENT param
+ *
+ * @param param ENT value
+ */
+__attribute__((always_inline))
+static inline void adc_ll_set_ent_param(uint32_t param)
+{
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_ENT_VDD_GRP1, param);
+}
+
+/**
+ * Init regi2c SARADC registers
+ */
+__attribute__((always_inline))
+static inline void adc_ll_regi2c_init(void)
+{
+    adc_ll_set_dtest_param(0);
+    adc_ll_set_ent_param(1);
+}
+
+/**
+ * Deinit regi2c SARADC registers
+ */
+__attribute__((always_inline))
+static inline void adc_ll_regi2c_adc_deinit(void)
+{
+    adc_ll_set_dtest_param(0);
+    adc_ll_set_ent_param(0);
+}
+
 /*---------------------------------------------------------------
                     Oneshot Read
 ---------------------------------------------------------------*/
diff --git a/components/hal/include/hal/adc_types.h b/components/hal/include/hal/adc_types.h
index 833aa1ceab..56f673fa04 100644
--- a/components/hal/include/hal/adc_types.h
+++ b/components/hal/include/hal/adc_types.h
@@ -38,6 +38,7 @@ typedef enum {
     ADC_CHANNEL_7,     ///< ADC channel
     ADC_CHANNEL_8,     ///< ADC channel
     ADC_CHANNEL_9,     ///< ADC channel
+    ADC_CHANNEL_10,    ///< ADC channel
 } adc_channel_t;
 
 /**