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refactor(cam): rename IRAM-Safe to Cache-Safe

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This commit is contained in:
armando
2025-03-07 11:35:51 +08:00
parent 241389134b
commit 737a858dab
6 changed files with 34 additions and 17 deletions
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18
components/esp_driver_cam/Kconfig
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@ -2,8 +2,8 @@ menu "ESP-Driver:Camera Controller Configurations"
depends on SOC_MIPI_CSI_SUPPORTED || SOC_LCDCAM_CAM_SUPPORTED
config CAM_CTLR_MIPI_CSI_ISR_IRAM_SAFE
bool "CSI ISR IRAM-Safe"
config CAM_CTLR_MIPI_CSI_ISR_CACHE_SAFE
bool "CSI ISR Cache-Safe"
depends on SOC_MIPI_CSI_SUPPORTED
default n
select DW_GDMA_ISR_IRAM_SAFE
@ -11,22 +11,22 @@ menu "ESP-Driver:Camera Controller Configurations"
select DW_GDMA_SETTER_FUNC_IN_IRAM
select DW_GDMA_GETTER_FUNC_IN_IRAM
help
Ensure the CSI driver ISR is IRAM-Safe. When enabled, the ISR handler
Ensure the CSI driver ISR is Cache-Safe. When enabled, the ISR handler
will be available when the cache is disabled.
config CAM_CTLR_ISP_DVP_ISR_IRAM_SAFE # IDF-10093
bool "ISP_DVP ISR IRAM-Safe"
config CAM_CTLR_ISP_DVP_ISR_CACHE_SAFE # IDF-10093
bool "ISP_DVP ISR Cache-Safe"
default n
select DW_GDMA_ISR_IRAM_SAFE
select DW_GDMA_CTRL_FUNC_IN_IRAM
select DW_GDMA_SETTER_FUNC_IN_IRAM
select DW_GDMA_GETTER_FUNC_IN_IRAM
help
Ensure the ISP_DVP driver ISR is IRAM-Safe. When enabled, the ISR handler
Ensure the ISP_DVP driver ISR is Cache-Safe. When enabled, the ISR handler
will be available when the cache is disabled.
config CAM_CTLR_DVP_CAM_ISR_IRAM_SAFE
bool "DVP ISR IRAM-Safe"
config CAM_CTLR_DVP_CAM_ISR_CACHE_SAFE
bool "DVP ISR Cache-Safe"
depends on SOC_LCDCAM_CAM_SUPPORTED
default n
select DW_GDMA_ISR_IRAM_SAFE
@ -34,7 +34,7 @@ menu "ESP-Driver:Camera Controller Configurations"
select DW_GDMA_SETTER_FUNC_IN_IRAM
select DW_GDMA_GETTER_FUNC_IN_IRAM
help
Ensure the DVP driver ISR is IRAM-Safe. When enabled, the ISR handler
Ensure the DVP driver ISR is Cache-Safe. When enabled, the ISR handler
will be available when the cache is disabled.
endmenu # ESP Camera Controller Configurations

4
components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c
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@ -25,7 +25,7 @@
#include "esp_private/esp_cache_private.h"
#include "esp_cache.h"
#if CONFIG_CAM_CTLR_MIPI_CSI_ISR_IRAM_SAFE
#if CONFIG_CAM_CTLR_MIPI_CSI_ISR_CACHE_SAFE
#define CSI_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
#else
#define CSI_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
@ -374,7 +374,7 @@ esp_err_t s_register_event_callbacks(esp_cam_ctlr_handle_t handle, const esp_cam
csi_controller_t *ctlr = __containerof(handle, csi_controller_t, base);
ESP_RETURN_ON_FALSE(ctlr->csi_fsm == CSI_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "driver starts already, not allow cbs register");
#if CONFIG_CAM_CTLR_MIPI_CSI_ISR_IRAM_SAFE
#if CONFIG_CAM_CTLR_MIPI_CSI_ISR_CACHE_SAFE
if (cbs->on_get_new_trans) {
ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_get_new_trans), ESP_ERR_INVALID_ARG, TAG, "on_get_new_trans callback not in IRAM");
}

4
components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c
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@ -23,7 +23,7 @@
#include "esp_private/esp_cam_dvp.h"
#include "../../dvp_share_ctrl.h"
#ifdef CONFIG_CAM_CTLR_DVP_CAM_ISR_IRAM_SAFE
#ifdef CONFIG_CAM_CTLR_DVP_CAM_ISR_CACHE_SAFE
#define CAM_DVP_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
#else
#define CAM_DVP_MEM_ALLOC_CAPS (MALLOC_CAP_DEFAULT)
@ -573,7 +573,7 @@ static esp_err_t esp_cam_ctlr_dvp_cam_register_event_callbacks(esp_cam_ctlr_hand
ESP_RETURN_ON_FALSE(cbs->on_trans_finished, ESP_ERR_INVALID_ARG, TAG, "invalid argument: on_trans_finished is null");
ESP_RETURN_ON_FALSE(cbs->on_get_new_trans || !ctlr->bk_buffer_dis, ESP_ERR_INVALID_ARG, TAG, "invalid argument: on_get_new_trans is null");
#if CONFIG_CAM_CTLR_DVP_CAM_ISR_IRAM_SAFE
#if CONFIG_CAM_CTLR_DVP_CAM_ISR_CACHE_SAFE
if (cbs->on_get_new_trans) {
ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_get_new_trans), ESP_ERR_INVALID_ARG, TAG, "on_get_new_trans callback not in IRAM");
}

4
components/esp_driver_cam/isp_dvp/src/esp_cam_ctlr_isp_dvp.c
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@ -31,7 +31,7 @@
#include "esp_cam_ctlr_isp_dvp.h"
#include "../../dvp_share_ctrl.h"
#if CONFIG_CAM_CTLR_ISP_DVP_ISR_IRAM_SAFE
#if CONFIG_CAM_CTLR_ISP_DVP_ISR_CACHE_SAFE
#define ISP_DVP_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
#else
#define ISP_DVP_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
@ -262,7 +262,7 @@ static esp_err_t s_isp_dvp_register_event_callbacks(esp_cam_ctlr_handle_t handle
isp_dvp_controller_t *dvp_ctlr = __containerof(handle, isp_dvp_controller_t, base);
ESP_RETURN_ON_FALSE(dvp_ctlr->fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller isn't in init state");
#if CONFIG_CAM_CTLR_ISP_DVP_ISR_IRAM_SAFE
#if CONFIG_CAM_CTLR_ISP_DVP_ISR_CACHE_SAFE
if (cbs->on_get_new_trans) {
ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_get_new_trans), ESP_ERR_INVALID_ARG, TAG, "on_get_new_trans callback not in IRAM");
}

6
components/esp_driver_cam/sdkconfig.rename Normal file
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@ -0,0 +1,6 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_CAM_CTLR_MIPI_CSI_ISR_IRAM_SAFE CONFIG_CAM_CTLR_MIPI_CSI_ISR_CACHE_SAFE
CONFIG_CAM_CTLR_ISP_DVP_ISR_IRAM_SAFE CONFIG_CAM_CTLR_ISP_DVP_ISR_CACHE_SAFE
CONFIG_CAM_CTLR_DVP_CAM_ISR_IRAM_SAFE CONFIG_CAM_CTLR_DVP_CAM_ISR_CACHE_SAFE

15
docs/en/api-reference/peripherals/camera_driver.rst
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@ -134,8 +134,12 @@ The factory function :cpp:func:`esp_cam_new_csi_ctlr` and :cpp:func:`esp_cam_ctl
Kconfig Options
^^^^^^^^^^^^^^^
- :ref:`CONFIG_CAM_CTLR_MIPI_CSI_ISR_IRAM_SAFE` controls whether the default ISR handler should be masked when the cache is disabled
The following Kconfig options affect the behavior of the interrupt handler when cache is disabled:
.. list::
:SOC_MIPI_CSI_SUPPORTED: - :ref:`CONFIG_CAM_CTLR_MIPI_CSI_ISR_CACHE_SAFE`, see :ref:`cam-thread-safety` for more details.
:SOC_ISP_DVP_SUPPORTED: - :ref:`CONFIG_CAM_CTLR_ISP_DVP_ISR_CACHE_SAFE`, see :ref:`cam-thread-safety` for more details.
.. _cam-iram-safe:
@ -144,7 +148,14 @@ IRAM Safe
By default, the CSI interrupt will be deferred when the cache is disabled because of writing or erasing the flash.
There is a Kconfig option :ref:`CONFIG_CAM_CTLR_MIPI_CSI_ISR_IRAM_SAFE` that:
There are Kconfig options
.. list::
:SOC_MIPI_CSI_SUPPORTED: - :ref:`CONFIG_CAM_CTLR_MIPI_CSI_ISR_CACHE_SAFE`
:SOC_ISP_DVP_SUPPORTED: - :ref:`CONFIG_CAM_CTLR_ISP_DVP_ISR_CACHE_SAFE`
that
- Enables the interrupt being serviced even when the cache is disabled
- Places all functions that used by the ISR into IRAM