diff --git a/components/esp_system/port/soc/esp32s3/system_internal.c b/components/esp_system/port/soc/esp32s3/system_internal.c
index e797c12efc..635d80cb4c 100644
--- a/components/esp_system/port/soc/esp32s3/system_internal.c
+++ b/components/esp_system/port/soc/esp32s3/system_internal.c
@@ -1,6 +1,6 @@
 
 /*
- * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -102,10 +102,6 @@ void IRAM_ATTR esp_restart_noos(void)
     }
 #endif
 
-    // Disable cache
-    Cache_Disable_ICache();
-    Cache_Disable_DCache();
-
     // Reset and stall the other CPU.
     // CPU must be reset before stalling, in case it was running a s32c1i
     // instruction. This would cause memory pool to be locked by arbiter
@@ -117,6 +113,10 @@ void IRAM_ATTR esp_restart_noos(void)
     esp_cpu_stall(other_core_id);
 #endif
 
+    // Disable cache
+    Cache_Disable_ICache();
+    Cache_Disable_DCache();
+
     // 2nd stage bootloader reconfigures SPI flash signals.
     // Reset them to the defaults expected by ROM.
     WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);