From 2a815e90374d1017f8d9723547d1f28e58bb396a Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Wed, 2 Jul 2025 11:47:47 +0800 Subject: [PATCH 1/2] fix(esp_hw_support): fix assert when changing 8MD256 RTC slow clock source during OTA --- components/esp_hw_support/sleep_modes.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 7d25c4314f..f793a314a0 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -2263,6 +2263,16 @@ esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain, esp_sleep_pd_option_ return ESP_OK; } +static const char* s_submode2str[] = { + [ESP_SLEEP_RTC_USE_RC_FAST_MODE] = "ESP_SLEEP_RTC_USE_RC_FAST_MODE", + [ESP_SLEEP_DIG_USE_RC_FAST_MODE] = "ESP_SLEEP_DIG_USE_RC_FAST_MODE", + [ESP_SLEEP_USE_ADC_TSEN_MONITOR_MODE] = "ESP_SLEEP_USE_ADC_TSEN_MONITOR_MODE", + [ESP_SLEEP_ULTRA_LOW_MODE] = "ESP_SLEEP_ULTRA_LOW_MODE", + [ESP_SLEEP_RTC_FAST_USE_XTAL_MODE] = "ESP_SLEEP_RTC_FAST_USE_XTAL_MODE", + [ESP_SLEEP_DIG_USE_XTAL_MODE] = "ESP_SLEEP_DIG_USE_XTAL_MODE", + [ESP_SLEEP_LP_USE_XTAL_MODE] = "ESP_SLEEP_LP_USE_XTAL_MODE", +}; + esp_err_t esp_sleep_sub_mode_config(esp_sleep_sub_mode_t mode, bool activate) { if (mode >= ESP_SLEEP_MODE_MAX) { @@ -2275,7 +2285,10 @@ esp_err_t esp_sleep_sub_mode_config(esp_sleep_sub_mode_t mode, bool activate) } else { s_sleep_sub_mode_ref_cnt[mode]--; } - assert(s_sleep_sub_mode_ref_cnt[mode] >= 0); + if (s_sleep_sub_mode_ref_cnt[mode] < 0) { + ESP_EARLY_LOGW(TAG, "%s disabled multiple times!! (If this log appears only once after OTA upgrade, it can be ignored.)", s_submode2str[mode]); + s_sleep_sub_mode_ref_cnt[mode] = 0; + } portEXIT_CRITICAL_SAFE(&s_config.lock); return ESP_OK; } @@ -2296,15 +2309,7 @@ int32_t* esp_sleep_sub_mode_dump_config(FILE *stream) { if (stream) { for (uint32_t mode = 0; mode < ESP_SLEEP_MODE_MAX; mode++) { fprintf(stream, LOG_COLOR_I "%s : %s (cnt = %" PRId32 ")\n" LOG_RESET_COLOR, - (const char*[]){ - [ESP_SLEEP_RTC_USE_RC_FAST_MODE] = "ESP_SLEEP_RTC_USE_RC_FAST_MODE", - [ESP_SLEEP_DIG_USE_RC_FAST_MODE] = "ESP_SLEEP_DIG_USE_RC_FAST_MODE", - [ESP_SLEEP_USE_ADC_TSEN_MONITOR_MODE] = "ESP_SLEEP_USE_ADC_TSEN_MONITOR_MODE", - [ESP_SLEEP_ULTRA_LOW_MODE] = "ESP_SLEEP_ULTRA_LOW_MODE", - [ESP_SLEEP_RTC_FAST_USE_XTAL_MODE] = "ESP_SLEEP_RTC_FAST_USE_XTAL_MODE", - [ESP_SLEEP_DIG_USE_XTAL_MODE] = "ESP_SLEEP_DIG_USE_XTAL_MODE", - [ESP_SLEEP_LP_USE_XTAL_MODE] = "ESP_SLEEP_LP_USE_XTAL_MODE", - }[mode], + s_submode2str[mode], s_sleep_sub_mode_ref_cnt[mode] ? "ENABLED" : "DISABLED", s_sleep_sub_mode_ref_cnt[mode]); } From 1de92b2e7024c05977027133c1c1860103b26b46 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Fri, 18 Jul 2025 15:28:57 +0800 Subject: [PATCH 2/2] fix(esp_hw_support): enable ESP_SLEEP_RTC_FAST_USE_XTAL_MODE only once in RTC_FAST selection --- components/esp_system/port/soc/esp32c5/clk.c | 4 +++- components/esp_system/port/soc/esp32p4/clk.c | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/components/esp_system/port/soc/esp32c5/clk.c b/components/esp_system/port/soc/esp32c5/clk.c index 836286748c..717b079d9d 100644 --- a/components/esp_system/port/soc/esp32c5/clk.c +++ b/components/esp_system/port/soc/esp32c5/clk.c @@ -64,7 +64,9 @@ __attribute__((weak)) void esp_clk_init(void) rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST); #elif CONFIG_RTC_FAST_CLK_SRC_XTAL rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_XTAL); - esp_sleep_sub_mode_config(ESP_SLEEP_RTC_FAST_USE_XTAL_MODE, true); + if (esp_sleep_sub_mode_dump_config(NULL)[ESP_SLEEP_RTC_FAST_USE_XTAL_MODE] == 0) { + esp_sleep_sub_mode_config(ESP_SLEEP_RTC_FAST_USE_XTAL_MODE, true); + } #else #error "No RTC fast clock source configured" #endif diff --git a/components/esp_system/port/soc/esp32p4/clk.c b/components/esp_system/port/soc/esp32p4/clk.c index 54f6a3c266..22225e1abf 100644 --- a/components/esp_system/port/soc/esp32p4/clk.c +++ b/components/esp_system/port/soc/esp32p4/clk.c @@ -93,7 +93,9 @@ __attribute__((weak)) void esp_clk_init(void) rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST); #elif CONFIG_RTC_FAST_CLK_SRC_XTAL rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_XTAL); - esp_sleep_sub_mode_config(ESP_SLEEP_RTC_FAST_USE_XTAL_MODE, true); + if (esp_sleep_sub_mode_dump_config(NULL)[ESP_SLEEP_RTC_FAST_USE_XTAL_MODE] == 0) { + esp_sleep_sub_mode_config(ESP_SLEEP_RTC_FAST_USE_XTAL_MODE, true); + } #else #error "No RTC fast clock source configured" #endif