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uart: move frequency of clock sources out of HAL

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This commit is contained in:
Michael (XIAO Xufeng)
2022-07-28 10:47:13 +08:00
parent f8bcec07fa
commit 746f4b814c
26 changed files with 172 additions and 167 deletions
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29
components/hal/esp32c2/include/hal/uart_ll.h
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@@ -11,7 +11,6 @@
#pragma once
#include "hal/uart_types.h"
#include "soc/uart_periph.h"
#include "hal/clk_tree_ll.h"
#ifdef __cplusplus
extern "C" {
@@ -142,38 +141,18 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk)
}
}
/**
* @brief Get the UART source clock frequency.
*
* @param hw Beginning address of the peripheral registers.
*
* @return Current source clock frequency
*/
static inline uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw)
{
switch (hw->clk_conf.sclk_sel) {
default:
case 1:
return APB_CLK_FREQ;
case 2:
return RTC_CLK_FREQ;
case 3:
return clk_ll_xtal_load_freq_mhz() * MHZ;
}
}
/**
* @brief Configure the baud-rate.
*
* @param hw Beginning address of the peripheral registers.
* @param baud The baud rate to be set.
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return None
*/
static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud)
static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
uint32_t sclk_freq = uart_ll_get_sclk_freq(hw);
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
int sclk_div = DIV_UP(sclk_freq, max_div * baud);
@@ -190,12 +169,12 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud)
* @brief Get the current baud-rate.
*
* @param hw Beginning address of the peripheral registers.
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return The current baudrate
*/
static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw)
static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
{
uint32_t sclk_freq = uart_ll_get_sclk_freq(hw);
typeof(hw->clk_div) div_reg = hw->clk_div;
return ((sclk_freq << 4)) / (((div_reg.div_int << 4) | div_reg.div_frag) * (hw->clk_conf.sclk_div_num + 1));
}