From 4ca115be9891c5abf510016fe3cd1c382f6ed4cd Mon Sep 17 00:00:00 2001 From: Armando Date: Fri, 25 Feb 2022 13:41:02 +0800 Subject: [PATCH 1/2] adc: fix adc digital not reset issue --- components/driver/adc.c | 4 +++- .../hal/esp32s2/include/hal/clk_gate_ll.h | 22 ++++++++----------- .../hal/esp32s3/include/hal/clk_gate_ll.h | 4 ++++ tools/ci/check_copyright_ignore.txt | 1 - 4 files changed, 16 insertions(+), 15 deletions(-) diff --git a/components/driver/adc.c b/components/driver/adc.c index 1488a9755d..06ef9b1840 100644 --- a/components/driver/adc.c +++ b/components/driver/adc.c @@ -284,8 +284,10 @@ esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config) }; adc_hal_context_config(&s_adc_digi_ctx->hal, &config); - //enable SARADC module clock + //enable ADC digital part periph_module_enable(PERIPH_SARADC_MODULE); + //reset ADC digital part + periph_module_reset(PERIPH_SARADC_MODULE); #if SOC_ADC_CALIBRATION_V1_SUPPORTED adc_hal_calibration_init(ADC_NUM_1); diff --git a/components/hal/esp32s2/include/hal/clk_gate_ll.h b/components/hal/esp32s2/include/hal/clk_gate_ll.h index 7a2bbe6cf2..cde957997f 100644 --- a/components/hal/esp32s2/include/hal/clk_gate_ll.h +++ b/components/hal/esp32s2/include/hal/clk_gate_ll.h @@ -1,16 +1,8 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -29,6 +21,8 @@ extern "C" { static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph) { switch (periph) { + case PERIPH_SARADC_MODULE: + return DPORT_APB_SARADC_CLK_EN; case PERIPH_LEDC_MODULE: return DPORT_LEDC_CLK_EN; case PERIPH_UART0_MODULE: @@ -99,6 +93,8 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en (void)enable; // unused switch (periph) { + case PERIPH_SARADC_MODULE: + return DPORT_APB_SARADC_RST; case PERIPH_LEDC_MODULE: return DPORT_LEDC_RST; case PERIPH_UART0_MODULE: diff --git a/components/hal/esp32s3/include/hal/clk_gate_ll.h b/components/hal/esp32s3/include/hal/clk_gate_ll.h index 01f684732f..a3b5afbe00 100644 --- a/components/hal/esp32s3/include/hal/clk_gate_ll.h +++ b/components/hal/esp32s3/include/hal/clk_gate_ll.h @@ -21,6 +21,8 @@ extern "C" { static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph) { switch (periph) { + case PERIPH_SARADC_MODULE: + return SYSTEM_APB_SARADC_CLK_EN; case PERIPH_RMT_MODULE: return SYSTEM_RMT_CLK_EN; case PERIPH_LEDC_MODULE: @@ -103,6 +105,8 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph) static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool enable) { switch (periph) { + case PERIPH_SARADC_MODULE: + return SYSTEM_APB_SARADC_RST; case PERIPH_RMT_MODULE: return SYSTEM_RMT_RST; case PERIPH_LEDC_MODULE: diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index 020430934f..d6d26e36ea 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -887,7 +887,6 @@ components/hal/esp32s2/brownout_hal.c components/hal/esp32s2/cp_dma_hal.c components/hal/esp32s2/include/hal/adc_hal_conf.h components/hal/esp32s2/include/hal/aes_ll.h -components/hal/esp32s2/include/hal/clk_gate_ll.h components/hal/esp32s2/include/hal/cp_dma_hal.h components/hal/esp32s2/include/hal/cp_dma_ll.h components/hal/esp32s2/include/hal/cpu_ll.h From e66f59ae0bd22db7643e76cc325790100727aa58 Mon Sep 17 00:00:00 2001 From: Armando Date: Fri, 25 Feb 2022 13:41:30 +0800 Subject: [PATCH 2/2] rng: fix rng adc digital inpu not disabled issue --- .../src/bootloader_random_esp32s3.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/components/bootloader_support/src/bootloader_random_esp32s3.c b/components/bootloader_support/src/bootloader_random_esp32s3.c index 3f80020c2c..2953db4917 100644 --- a/components/bootloader_support/src/bootloader_random_esp32s3.c +++ b/components/bootloader_support/src/bootloader_random_esp32s3.c @@ -74,6 +74,7 @@ void bootloader_random_enable(void) REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); } +//TODO: IDF-4714 void bootloader_random_disable(void) { /* Restore internal I2C bus state */ @@ -82,13 +83,19 @@ void bootloader_random_disable(void) REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); - /* Restore SARADC to default mode */ - CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE); - SET_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_APB_SARADC_CLK_EN); - REG_SET_FIELD(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0); - CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN); + //Stop SAR ADC clock CLEAR_PERI_REG_MASK(SENS_SAR_PERI_CLK_GATE_CONF_REG, SENS_SARADC_CLK_EN); + //Power off SAR ADC + REG_SET_FIELD(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0); + //return to ADC RTC controller + CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE); + //Invalidate ADC digital trigger timer + CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN); + + //Disable ADC digital part CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_APB_SARADC_CLK_EN); + //Hold reset bit for ADC digital part + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_APB_SARADC_RST); /* Note: the 8M CLK entropy source continues running even after this function is called, but as mentioned above it's better to enable Wi-Fi or BT or call bootloader_random_enable()