esp32s2: IRAM/DRAM memory protection

* new mem_prot API
* mem_prot on & locked by default (see Kconfig)
* feature activated in start_cpu0_default()

JIRA IDF-1355

components/esp32/cache_err_int.c

@@ -33,13 +33,13 @@
 void esp_cache_err_int_init(void)
 {
     uint32_t core_id = xPortGetCoreID();
-    ESP_INTR_DISABLE(ETS_CACHEERR_INUM);
+    ESP_INTR_DISABLE(ETS_MEMACCESS_ERR_INUM);
 
     // We do not register a handler for the interrupt because it is interrupt
     // level 4 which is not serviceable from C. Instead, xtensa_vectors.S has
     // a call to the panic handler for
     // this interrupt.
-    intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
+    intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_MEMACCESS_ERR_INUM);
 
     // Enable invalid cache access interrupt when the cache is disabled.
     // When the interrupt happens, we can not determine the CPU where the
@@ -67,7 +67,7 @@ void esp_cache_err_int_init(void)
             DPORT_CACHE_IA_INT_APP_IRAM0 |
             DPORT_CACHE_IA_INT_APP_IRAM1);
     }
-    ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
+    ESP_INTR_ENABLE(ETS_MEMACCESS_ERR_INUM);
 }
 
 int IRAM_ATTR esp_cache_err_get_cpuid(void)

components/esp32/include/esp32/cache_err_int.h

@@ -17,7 +17,7 @@
  * @brief initialize cache invalid access interrupt
  *
  * This function enables cache invalid access interrupt source and connects it
- * to interrupt input number ETS_CACHEERR_INUM (see soc/soc.h). It is called
+ * to interrupt input number ETS_MEMACCESS_ERR_INUM (see soc/soc.h). It is called
  * from the startup code.
  */
 void esp_cache_err_int_init(void);