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feat(power_glich): support power_glitch of esp32c5_eco1 and above, eco32c61 eco2 and above

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This commit is contained in:
chaijie@espressif.com
2024-11-26 17:11:25 +08:00
committed by BOT
parent 7bca1fe76f
commit 74c34669f0
7 changed files with 58 additions and 32 deletions
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6
components/bootloader_support/src/esp32c5/bootloader_esp32c5.c
View File

@@ -94,11 +94,7 @@ static inline void bootloader_ana_reset_config(void)
{
//Enable BOD reset (mode1)
brownout_ll_ana_reset_enable(true);
if (efuse_hal_chip_revision() == 0) {
// decrease power glitch reset voltage to avoid start the glitch reset
uint8_t power_glitch_dref = 0;
bootloader_power_glitch_reset_config(true, power_glitch_dref);
}
bootloader_power_glitch_reset_config(true);
}
esp_err_t bootloader_init(void)

20
components/bootloader_support/src/esp32c5/bootloader_soc.c
View File

@@ -17,18 +17,18 @@ void bootloader_ana_clock_glitch_reset_config(bool enable)
(void)enable;
}
void bootloader_power_glitch_reset_config(bool enable, uint8_t dref)
void bootloader_power_glitch_reset_config(bool enable)
{
assert(dref < 8);
REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);
//only detect VDDPST POWER GLITCH
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PERIF, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_XTAL, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PLL, 0);
REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);//default val for chip from ECO1
if (enable) {
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PERIF, dref);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_VDDPST, dref);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_XTAL, dref);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLL, dref);
REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0xf);
REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0xf);//default val for chip from ECO1
} else {
REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0);
}