Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master'

G0: RISC-V targets have now an independent G0 layer

See merge request espressif/esp-idf!17926

components/esp_hw_support/port/esp32c2/private_include/regi2c_saradc.h

@@ -6,74 +6,4 @@
 
 #pragma once
 
-/**
+#include "soc/regi2c_saradc.h"
- * @file regi2c_saradc.h
- * @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC.
- *
- * This file lists register fields of SAR, located on an internal configuration
- * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
- * function in adc_ll.h.
- */
-
-#define I2C_SAR_ADC            0X69
-#define I2C_SAR_ADC_HOSTID     0
-
-#define ADC_SAR1_ENCAL_GND_ADDR 0x7
-#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
-#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
-
-#define ADC_SAR2_ENCAL_GND_ADDR 0x7
-#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
-#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
-
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
-
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR  0x0
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB  0x7
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB  0x0
-
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
-
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR  0x3
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB  0x7
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB  0x0
-
-#define ADC_SAR1_DREF_ADDR  0x2
-#define ADC_SAR1_DREF_ADDR_MSB  0x6
-#define ADC_SAR1_DREF_ADDR_LSB  0x4
-
-#define ADC_SAR2_DREF_ADDR  0x5
-#define ADC_SAR2_DREF_ADDR_MSB  0x6
-#define ADC_SAR2_DREF_ADDR_LSB  0x4
-
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
-
-#define ADC_SARADC_DTEST_RTC_ADDR 0x7
-#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1
-#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0
-
-#define ADC_SARADC_ENT_TSENS_ADDR 0x7
-#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2
-#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2
-
-#define ADC_SARADC_ENT_RTC_ADDR 0x7
-#define ADC_SARADC_ENT_RTC_ADDR_MSB 3
-#define ADC_SARADC_ENT_RTC_ADDR_LSB 3
-
-#define ADC_SARADC1_ENCAL_REF_ADDR 0x7
-#define ADC_SARADC1_ENCAL_REF_ADDR_MSB 4
-#define ADC_SARADC1_ENCAL_REF_ADDR_LSB 4
-
-#define ADC_SARADC2_ENCAL_REF_ADDR 0x7
-#define ADC_SARADC2_ENCAL_REF_ADDR_MSB 6
-#define ADC_SARADC2_ENCAL_REF_ADDR_LSB 6
-
-#define I2C_SARADC_TSENS_DAC 0x6
-#define I2C_SARADC_TSENS_DAC_MSB 3
-#define I2C_SARADC_TSENS_DAC_LSB 0

components/esp_hw_support/port/esp32c3/private_include/regi2c_saradc.h

@@ -6,74 +6,4 @@
 
 #pragma once
 
-/**
+#include "soc/regi2c_saradc.h"
- * @file regi2c_saradc.h
- * @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC.
- *
- * This file lists register fields of SAR, located on an internal configuration
- * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
- * function in adc_ll.h.
- */
-
-#define I2C_SAR_ADC            0X69
-#define I2C_SAR_ADC_HOSTID     0
-
-#define ADC_SAR1_ENCAL_GND_ADDR 0x7
-#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
-#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
-
-#define ADC_SAR2_ENCAL_GND_ADDR 0x7
-#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
-#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
-
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
-
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR  0x0
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB  0x7
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB  0x0
-
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
-
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR  0x3
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB  0x7
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB  0x0
-
-#define ADC_SAR1_DREF_ADDR  0x2
-#define ADC_SAR1_DREF_ADDR_MSB  0x6
-#define ADC_SAR1_DREF_ADDR_LSB  0x4
-
-#define ADC_SAR2_DREF_ADDR  0x5
-#define ADC_SAR2_DREF_ADDR_MSB  0x6
-#define ADC_SAR2_DREF_ADDR_LSB  0x4
-
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
-
-#define ADC_SARADC_DTEST_RTC_ADDR 0x7
-#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1
-#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0
-
-#define ADC_SARADC_ENT_TSENS_ADDR 0x7
-#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2
-#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2
-
-#define ADC_SARADC_ENT_RTC_ADDR 0x7
-#define ADC_SARADC_ENT_RTC_ADDR_MSB 3
-#define ADC_SARADC_ENT_RTC_ADDR_LSB 3
-
-#define ADC_SARADC1_ENCAL_REF_ADDR 0x7
-#define ADC_SARADC1_ENCAL_REF_ADDR_MSB 4
-#define ADC_SARADC1_ENCAL_REF_ADDR_LSB 4
-
-#define ADC_SARADC2_ENCAL_REF_ADDR 0x7
-#define ADC_SARADC2_ENCAL_REF_ADDR_MSB 6
-#define ADC_SARADC2_ENCAL_REF_ADDR_LSB 6
-
-#define I2C_SARADC_TSENS_DAC 0x6
-#define I2C_SARADC_TSENS_DAC_MSB 3
-#define I2C_SARADC_TSENS_DAC_LSB 0

components/esp_hw_support/port/esp32h2/private_include/regi2c_saradc.h

@@ -6,74 +6,4 @@
 
 #pragma once
 
-/**
+#include "soc/regi2c_saradc.h"
- * @file regi2c_saradc.h
- * @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC.
- *
- * This file lists register fields of SAR, located on an internal configuration
- * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
- * function in adc_ll.h.
- */
-
-#define I2C_SAR_ADC            0X69
-#define I2C_SAR_ADC_HOSTID     0
-
-#define ADC_SAR1_ENCAL_GND_ADDR 0x7
-#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
-#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
-
-#define ADC_SAR2_ENCAL_GND_ADDR 0x7
-#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
-#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
-
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
-
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR  0x0
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB  0x7
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB  0x0
-
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
-
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR  0x3
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB  0x7
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB  0x0
-
-#define ADC_SAR1_DREF_ADDR  0x2
-#define ADC_SAR1_DREF_ADDR_MSB  0x6
-#define ADC_SAR1_DREF_ADDR_LSB  0x4
-
-#define ADC_SAR2_DREF_ADDR  0x5
-#define ADC_SAR2_DREF_ADDR_MSB  0x6
-#define ADC_SAR2_DREF_ADDR_LSB  0x4
-
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
-
-#define ADC_SARADC_DTEST_RTC_ADDR 0x7
-#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1
-#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0
-
-#define ADC_SARADC_ENT_TSENS_ADDR 0x7
-#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2
-#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2
-
-#define ADC_SARADC_ENT_RTC_ADDR 0x7
-#define ADC_SARADC_ENT_RTC_ADDR_MSB 3
-#define ADC_SARADC_ENT_RTC_ADDR_LSB 3
-
-#define ADC_SARADC1_ENCAL_REF_ADDR 0x7
-#define ADC_SARADC1_ENCAL_REF_ADDR_MSB 4
-#define ADC_SARADC1_ENCAL_REF_ADDR_LSB 4
-
-#define ADC_SARADC2_ENCAL_REF_ADDR 0x7
-#define ADC_SARADC2_ENCAL_REF_ADDR_MSB 6
-#define ADC_SARADC2_ENCAL_REF_ADDR_LSB 6
-
-#define I2C_SARADC_TSENS_DAC 0x6
-#define I2C_SARADC_TSENS_DAC_MSB 3
-#define I2C_SARADC_TSENS_DAC_LSB 0

components/hal/esp32c2/brownout_hal.c

@@ -8,9 +8,9 @@
 #include "hal/brownout_hal.h"
 #include "soc/rtc_cntl_struct.h"
 #include "soc/rtc_cntl_reg.h"
-#include "esp_private/regi2c_ctrl.h"
-#include "regi2c_brownout.h"
 #include "esp_attr.h"
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_brownout.h"
 
 
 void brownout_hal_config(const brownout_hal_config_t *cfg)

components/hal/esp32c2/include/hal/adc_ll.h

@@ -17,9 +17,8 @@
 #include "hal/misc.h"
 #include "hal/adc_types.h"
 #include "hal/adc_types_private.h"
-
+#include "hal/regi2c_ctrl.h"
-#include "esp_private/regi2c_ctrl.h"
+#include "soc/regi2c_saradc.h"
-#include "regi2c_saradc.h"
 
 #ifdef __cplusplus
 extern "C" {

components/hal/esp32c2/include/hal/gdma_ll.h

@@ -5,6 +5,7 @@
  */
 #pragma once
 
+#include <stddef.h> /* Required for NULL constant */
 #include <stdint.h>
 #include <stdbool.h>
 #include "soc/gdma_struct.h"

components/hal/esp32c3/brownout_hal.c

@@ -8,10 +8,9 @@
 #include "hal/brownout_hal.h"
 #include "soc/rtc_cntl_struct.h"
 #include "soc/rtc_cntl_reg.h"
-#include "esp_private/regi2c_ctrl.h"
-#include "regi2c_brownout.h"
 #include "esp_attr.h"
-
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_brownout.h"
 
 void brownout_hal_config(const brownout_hal_config_t *cfg)
 {

components/hal/esp32c3/include/hal/adc_ll.h

@@ -18,9 +18,9 @@
 #include "hal/assert.h"
 #include "hal/adc_types.h"
 #include "hal/adc_types_private.h"
+#include "hal/regi2c_ctrl.h"
 
-#include "esp_private/regi2c_ctrl.h"
+#include "soc/regi2c_saradc.h"
-#include "regi2c_saradc.h"
 
 #ifdef __cplusplus
 extern "C" {

components/hal/esp32c3/include/hal/gdma_ll.h

@@ -5,6 +5,7 @@
  */
 #pragma once
 
+#include <stddef.h> /* Required for NULL constant */
 #include <stdint.h>
 #include <stdbool.h>
 #include "soc/gdma_struct.h"

components/hal/esp32h2/brownout_hal.c

@@ -9,9 +9,9 @@
 #include "soc/rtc_cntl_struct.h"
 #include "soc/rtc_cntl_reg.h"
 #include "i2c_pmu.h"
-#include "esp_private/regi2c_ctrl.h"
-#include "regi2c_brownout.h"
 #include "esp_attr.h"
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_brownout.h"
 
 
 void brownout_hal_config(const brownout_hal_config_t *cfg)

components/hal/esp32h2/include/hal/adc_ll.h

@@ -17,9 +17,9 @@
 #include "soc/rtc_cntl_struct.h"
 #include "soc/rtc_cntl_reg.h"
 #include "hal/misc.h"
+#include "hal/regi2c_ctrl.h"
 
-#include "esp_private/regi2c_ctrl.h"
+#include "soc/regi2c_saradc.h"
-#include "regi2c_saradc.h"
 
 #ifdef __cplusplus
 extern "C" {

components/hal/esp32h2/include/hal/gdma_ll.h

@@ -5,6 +5,7 @@
  */
 #pragma once
 
+#include <stddef.h> /* Required for NULL constant */
 #include <stdint.h>
 #include <stdbool.h>
 #include "soc/gdma_struct.h"

components/hal/include/hal/rtc_io_hal.h

@@ -15,6 +15,8 @@
 #pragma once
 
 #include <esp_err.h>
+#include "sdkconfig.h"
+
 #if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C2
 #include "soc/soc_caps.h"
 #include "hal/rtc_io_ll.h"

components/hal/platform_port/include/hal/regi2c_ctrl.h

@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#if __has_include("esp_private/regi2c_ctrl.h")
+    #include "esp_private/regi2c_ctrl.h"
+#else
+    #include "esp_rom_regi2c.h"
+    #define REGI2C_WRITE_MASK(block, reg_add, indata) esp_rom_regi2c_write_mask(block, block##_HOSTID,  reg_add,  reg_add##_MSB,  reg_add##_LSB,  indata)
+#endif

components/hal/spi_flash_hal.c

@@ -30,7 +30,7 @@ static uint32_t get_flash_clock_divider(const spi_flash_hal_config_t *cfg)
     // round down flash frequency to keep it safe.
     int best_div = 0;
     if (clk_source < cfg->freq_mhz) {
-        ESP_LOGE(TAG, "Target frequency %dMHz higher than supported.", cfg->freq_mhz);
+        HAL_LOGE(TAG, "Target frequency %dMHz higher than supported.", cfg->freq_mhz);
         abort();
     }
 #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3

components/riscv/CMakeLists.txt

@@ -9,7 +9,7 @@ endif()
 if(BOOTLOADER_BUILD)
     set(priv_requires soc)
 else()
-    set(priv_requires soc freertos)
+    set(priv_requires soc)
     set(srcs
         "instruction_decode.c"
         "interrupt.c"

components/soc/esp32c2/include/soc/regi2c_saradc.h

@@ -0,0 +1,79 @@
+/*
+ * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+/**
+ * @file regi2c_saradc.h
+ * @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC.
+ *
+ * This file lists register fields of SAR, located on an internal configuration
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
+ * function in adc_ll.h.
+ */
+
+#define I2C_SAR_ADC            0X69
+#define I2C_SAR_ADC_HOSTID     0
+
+#define ADC_SAR1_ENCAL_GND_ADDR 0x7
+#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
+#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
+
+#define ADC_SAR2_ENCAL_GND_ADDR 0x7
+#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
+#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
+
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
+
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR  0x0
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB  0x7
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB  0x0
+
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
+
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR  0x3
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB  0x7
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB  0x0
+
+#define ADC_SAR1_DREF_ADDR  0x2
+#define ADC_SAR1_DREF_ADDR_MSB  0x6
+#define ADC_SAR1_DREF_ADDR_LSB  0x4
+
+#define ADC_SAR2_DREF_ADDR  0x5
+#define ADC_SAR2_DREF_ADDR_MSB  0x6
+#define ADC_SAR2_DREF_ADDR_LSB  0x4
+
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
+
+#define ADC_SARADC_DTEST_RTC_ADDR 0x7
+#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1
+#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0
+
+#define ADC_SARADC_ENT_TSENS_ADDR 0x7
+#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2
+#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2
+
+#define ADC_SARADC_ENT_RTC_ADDR 0x7
+#define ADC_SARADC_ENT_RTC_ADDR_MSB 3
+#define ADC_SARADC_ENT_RTC_ADDR_LSB 3
+
+#define ADC_SARADC1_ENCAL_REF_ADDR 0x7
+#define ADC_SARADC1_ENCAL_REF_ADDR_MSB 4
+#define ADC_SARADC1_ENCAL_REF_ADDR_LSB 4
+
+#define ADC_SARADC2_ENCAL_REF_ADDR 0x7
+#define ADC_SARADC2_ENCAL_REF_ADDR_MSB 6
+#define ADC_SARADC2_ENCAL_REF_ADDR_LSB 6
+
+#define I2C_SARADC_TSENS_DAC 0x6
+#define I2C_SARADC_TSENS_DAC_MSB 3
+#define I2C_SARADC_TSENS_DAC_LSB 0

components/soc/esp32c3/include/soc/regi2c_saradc.h

@@ -0,0 +1,79 @@
+/*
+ * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+/**
+ * @file regi2c_saradc.h
+ * @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC.
+ *
+ * This file lists register fields of SAR, located on an internal configuration
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
+ * function in adc_ll.h.
+ */
+
+#define I2C_SAR_ADC            0X69
+#define I2C_SAR_ADC_HOSTID     0
+
+#define ADC_SAR1_ENCAL_GND_ADDR 0x7
+#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
+#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
+
+#define ADC_SAR2_ENCAL_GND_ADDR 0x7
+#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
+#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
+
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
+
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR  0x0
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB  0x7
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB  0x0
+
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
+
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR  0x3
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB  0x7
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB  0x0
+
+#define ADC_SAR1_DREF_ADDR  0x2
+#define ADC_SAR1_DREF_ADDR_MSB  0x6
+#define ADC_SAR1_DREF_ADDR_LSB  0x4
+
+#define ADC_SAR2_DREF_ADDR  0x5
+#define ADC_SAR2_DREF_ADDR_MSB  0x6
+#define ADC_SAR2_DREF_ADDR_LSB  0x4
+
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
+
+#define ADC_SARADC_DTEST_RTC_ADDR 0x7
+#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1
+#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0
+
+#define ADC_SARADC_ENT_TSENS_ADDR 0x7
+#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2
+#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2
+
+#define ADC_SARADC_ENT_RTC_ADDR 0x7
+#define ADC_SARADC_ENT_RTC_ADDR_MSB 3
+#define ADC_SARADC_ENT_RTC_ADDR_LSB 3
+
+#define ADC_SARADC1_ENCAL_REF_ADDR 0x7
+#define ADC_SARADC1_ENCAL_REF_ADDR_MSB 4
+#define ADC_SARADC1_ENCAL_REF_ADDR_LSB 4
+
+#define ADC_SARADC2_ENCAL_REF_ADDR 0x7
+#define ADC_SARADC2_ENCAL_REF_ADDR_MSB 6
+#define ADC_SARADC2_ENCAL_REF_ADDR_LSB 6
+
+#define I2C_SARADC_TSENS_DAC 0x6
+#define I2C_SARADC_TSENS_DAC_MSB 3
+#define I2C_SARADC_TSENS_DAC_LSB 0

components/soc/esp32h2/include/soc/regi2c_brownout.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */

components/soc/esp32h2/include/soc/regi2c_saradc.h

@@ -0,0 +1,79 @@
+/*
+ * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+/**
+ * @file regi2c_saradc.h
+ * @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC.
+ *
+ * This file lists register fields of SAR, located on an internal configuration
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
+ * function in adc_ll.h.
+ */
+
+#define I2C_SAR_ADC            0X69
+#define I2C_SAR_ADC_HOSTID     0
+
+#define ADC_SAR1_ENCAL_GND_ADDR 0x7
+#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
+#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
+
+#define ADC_SAR2_ENCAL_GND_ADDR 0x7
+#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
+#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
+
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
+
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR  0x0
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB  0x7
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB  0x0
+
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
+
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR  0x3
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB  0x7
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB  0x0
+
+#define ADC_SAR1_DREF_ADDR  0x2
+#define ADC_SAR1_DREF_ADDR_MSB  0x6
+#define ADC_SAR1_DREF_ADDR_LSB  0x4
+
+#define ADC_SAR2_DREF_ADDR  0x5
+#define ADC_SAR2_DREF_ADDR_MSB  0x6
+#define ADC_SAR2_DREF_ADDR_LSB  0x4
+
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
+
+#define ADC_SARADC_DTEST_RTC_ADDR 0x7
+#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1
+#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0
+
+#define ADC_SARADC_ENT_TSENS_ADDR 0x7
+#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2
+#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2
+
+#define ADC_SARADC_ENT_RTC_ADDR 0x7
+#define ADC_SARADC_ENT_RTC_ADDR_MSB 3
+#define ADC_SARADC_ENT_RTC_ADDR_LSB 3
+
+#define ADC_SARADC1_ENCAL_REF_ADDR 0x7
+#define ADC_SARADC1_ENCAL_REF_ADDR_MSB 4
+#define ADC_SARADC1_ENCAL_REF_ADDR_LSB 4
+
+#define ADC_SARADC2_ENCAL_REF_ADDR 0x7
+#define ADC_SARADC2_ENCAL_REF_ADDR_MSB 6
+#define ADC_SARADC2_ENCAL_REF_ADDR_LSB 6
+
+#define I2C_SARADC_TSENS_DAC 0x6
+#define I2C_SARADC_TSENS_DAC_MSB 3
+#define I2C_SARADC_TSENS_DAC_LSB 0

tools/cmake/component_deps.dot.in

@@ -11,7 +11,6 @@ subgraph cluster_g0 {
     esp_common;
     esp_rom;
     ${CONFIG_IDF_TARGET_ARCH};
-    ${CONFIG_IDF_TARGET};
 }
 
 subgraph cluster_g1 {

tools/find_build_apps/common.py

@@ -256,7 +256,8 @@ class BuildItem(object):
 
         map_file = find_first_match('*.map', self.build_path)
         if not map_file:
-            raise ValueError('.map file not found under "{}"'.format(self.build_path))
+            logging.info('.map file not found under "{}"'.format(self.build_path))
+            return None
 
         size_json_fp = os.path.join(self.build_path, SIZE_JSON_FN)
         idf_size_args = [
@@ -271,7 +272,8 @@ class BuildItem(object):
 
     def write_size_info(self, size_info_fs):
         if not self.size_json_fp or (not os.path.exists(self.size_json_fp)):
-            raise OSError('Run get_size_json_fp() for app {} after built binary'.format(self.app_dir))
+            logging.info(f'No size info found for app {self._app_name}')
+            return
         size_info_dict = {
             'app_name': self._app_name,
             'config_name': self.config_name,

tools/test_apps/system/g0_components/CMakeLists.txt

@@ -0,0 +1,55 @@
+# For more information about build system see
+# https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/build-system.html
+# The following five lines of boilerplate have to be in your project's
+# CMakeLists in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.5)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+
+# As this G0 example is not runnable as-is, the map file generated won't some important
+# sections. Thus, in order to prevent IDF from generating a map file at all, specify
+# null device as the destination file.
+if(WIN32)
+    idf_build_set_property(LINK_OPTIONS "-Wl,--Map=NUL" APPEND)
+else()
+    idf_build_set_property(LINK_OPTIONS "-Wl,--Map=/dev/null" APPEND)
+endif()
+
+# Force this project to use only G0 components
+set(all_g0_components esp_rom soc hal esp_common main)  # also <arch>, i.e. xtensa or riscv, will be added below
+set(COMPONENTS ${all_g0_components})
+
+# By default, common components include some G1+ components. Override common components to only have G0 ones
+idf_build_set_property(__COMPONENT_REQUIRES_COMMON "${all_g0_components}")
+# Generate a graph to visually see the dependencies between G0 and G1+ (if any)
+idf_build_set_property(__BUILD_COMPONENT_DEPGRAPH_ENABLED 1)
+
+project(g0_components)
+
+# As a workaround for ESP32-C2, we need to define the MMU page size here, until MMU hal-driver
+# is refactored
+if(CONFIG_IDF_TARGET_ESP32C2)
+    idf_build_set_property(C_COMPILE_OPTIONS "-DCONFIG_MMU_PAGE_SIZE=64" APPEND)
+endif()
+
+# Now that the project has been initialized, let's check which components it is using
+# The following variable lists all the components that shall be used by this project
+set(expected_components
+    ${COMPONENTS}
+    ${CONFIG_IDF_TARGET_ARCH}   # xtensa or riscv
+    )
+
+# Do not include libc into the build, we don't have any libC in G0
+set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -nostdlib")
+
+# Get all the components that were required to initialize this project
+idf_build_get_property(build_components BUILD_COMPONENTS)
+
+# Sort lists to be able to compare them literally
+list(SORT expected_components)
+list(SORT build_components)
+if(NOT "${expected_components}" STREQUAL "${build_components}")
+    message(FATAL_ERROR "Unexpected components list in G0 build\n"
+                        "Expected: ${expected_components}\n"
+                        "Actual: ${build_components}")
+endif()

tools/test_apps/system/g0_components/README.md

@@ -0,0 +1,33 @@
+| Supported Targets | ESP32-C3 | ESP32-C2 | ESP32-H2 |
+| ----------------- | -------- | -------- | -------- |
+
+All Xtensa based targets (ESP32, ESP32-S2, ESP32-S3) are currently not supported by this test, because their components having dependencies on G1+ components.
+
+# "G0"-components-only app
+
+This test application will compile ESP-IDF and this test's main component with G0 components only. The goal is to make sure that no G0 component depends
+on G1 or higher component.
+
+Currently, this test only supports RISC-V based targets as Xtensa ones still have some G0 components depending on G1+ components.
+
+Compiling this test with an Xtensa based target will result in a CMake error, showing all the non-G0 components included in the build file generation.
+
+The purpose of this example is to make sure that any modification to ESP-IDF doesn't violate the G0-G1+ dependency rule.
+
+# Using this test app
+
+Set the target to a RISC-V based, `esp32c3` for example:
+```bash
+idf.py set-target esp32c3
+```
+
+Then, trigger the build:
+```bash
+idf.py build
+```
+
+Build should be successful if there is no dependency problem between G0 and upper layers. 
+
+# Component dependencies graph (`component_deps.dot`)
+
+When this project is configured, `component_deps.dot` file in the build directory is generated. This file contains a Graphviz graph showing the component dependencies. You can visualize this graph (using `dot` tool or online at https://dreampuf.github.io/GraphvizOnline/) to see why an extra component got added. You can also build the project for the base branch, to compare the graph to a known good one.

tools/test_apps/system/g0_components/main/CMakeLists.txt

@@ -0,0 +1,2 @@
+idf_component_register(SRCS "g0_components.c"
+                    INCLUDE_DIRS ".")

tools/test_apps/system/g0_components/main/g0_components.c

@@ -0,0 +1,11 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdio.h>
+
+void app_main(void)
+{
+
+}