spi_flash: added programming guide for ESP-IDF vs ESP-ROM flash driver

docs/en/api-reference/peripherals/spi_flash/index.rst

@@ -250,6 +250,20 @@ Additionally, all API functions are protected with a mutex (``s_flash_op_mutex``
 
 In a single core environment (:ref:`CONFIG_FREERTOS_UNICORE` enabled), you need to disable both caches, so that no inter-CPU communication can take place.
 
+
+.. toctree::
+    :hidden:
+
+    spi_flash_idf_vs_rom
+
+.. only:: CONFIG_ESP_ROM_HAS_SPI_FLASH
+
+    ESP-IDF vs Chip-ROM SPI Flash Driver
+    ------------------------------------
+
+    Refer to :doc:`spi_flash_idf_vs_rom`.
+
+
 API Reference - SPI Flash
 -------------------------
 

docs/en/api-reference/peripherals/spi_flash/spi_flash_idf_vs_rom.rst

@@ -0,0 +1,37 @@
+SPI Flash API ESP-IDF version vs Chip-ROM version
+=================================================
+
+.. toctree::
+   :maxdepth: 1
+
+There is a set of SPI Flash drivers in Chip-ROM which you can use by enabling  :ref:`CONFIG_SPI_FLASH_ROM_IMPL`. Most of the ESP-IDF SPI Flash driver code are in internal RAM, therefore enabling this option will free some internal RAM usage. Note if you enable this option, this means some SPI Flash driver features and bugfixes that are done in ESP-IDF might not be included in the Chip-ROM version.
+
+
+Feature Supported by ESP-IDF but not in Chip-ROM
+------------------------------------------------
+
+.. list::
+
+    - Octal Flash chip support. See :ref:`oct-flash-doc` for details.
+    - 32-bit-address support for GD25Q256. See :ref:`32-bit-flash-doc` for details.
+    - TH Flash chip support.
+    - Kconfig option :ref:`CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED`.
+    - :ref:`CONFIG_SPI_FLASH_VERIFY_WRITE`, enabling this option helps you detect bad writing.
+    - :ref:`CONFIG_SPI_FLASH_LOG_FAILED_WRITE`, enabling this option will print the bad writing.
+    - :ref:`CONFIG_SPI_FLASH_WARN_SETTING_ZERO_TO_ONE`, enabling this option will check if you're writing zero to one.
+    :esp32h2 or esp32c6: - Flash MMAP driver isn't ready in Chip-ROM.
+
+
+Bugfixes Introduced in ESP-IDF but not in Chip-ROM
+--------------------------------------------------
+
+.. list::
+
+    - Detected Flash physical size correctly, for larger than 256MBit Flash chips. (Commit ID: b4964279d44f73cce7cfd5cf684567fbdfd6fd9e)
+    :esp32c3: - Improved SPI1 cs setup timing, otherwise issue may happen on ZB32Q128. (Commit ID: 08f1bbe0c75382f1702e40c941e93314285105d4)
+    :esp32s3: - Fixed issue that 4-line Flash encryption cannot work normally when 8-line PSRAM enabled. (Commit ID: 683d92bc884e0f2a7eebea40a551cf05f0c28256)
+    :esp32s2: - Fixed issue that only 4MB virtual address ranges can be mapped to read-only data on Flash.
+    :esp32s3: - Fixed issue that only 128KB virtual address ranges can be mapped to instructions on Flash.
+    :esp32s3: - Fixed issue that only 16MB virtual address ranges can be mapped to read-only data on Flash.
+    :esp32c3: - Fixed issue that only 128KB virtual address ranges can be mapped to instructions on Flash.
+    :esp32c2: - Fixed issue that only at most 128KB virtual address ranges can be mapped to instructions on Flash.

docs/en/api-reference/peripherals/spi_flash/spi_flash_optional_feature.rst

@@ -59,6 +59,8 @@ Flash Chips List:
 6. XMC
 7. BOYA
 
+.. _hpm-doc:
+
 High performance mode
 ---------------------
 
@@ -83,6 +85,9 @@ Flash Chips (name & ID) List:
 
     It is hard to create several strategies to cover all situations, so all flash chips using HPM need to be supported explicitly. Therefore, if you try to use a flash not listed as supported under high performance mode, it might cause some error. So, when you try to use the flash chip beyond supported list, please test properly.
 
+
+.. _oct-flash-doc:
+
 OPI flash support
 -----------------
 
@@ -102,6 +107,9 @@ Flash Chips List:
 
 1. MX25UM25645G
 
+
+.. _32-bit-flash-doc:
+
 32-bit Address Flash Chips
 --------------------------