From 023bbe5cb195c1b5e748f020c718c0c3b047a528 Mon Sep 17 00:00:00 2001 From: songruojing Date: Tue, 12 Oct 2021 11:37:17 +0800 Subject: [PATCH] esp_system: fix the bug that some peripheral clocks are being disabled during cpu reset for esp32s2, c3, s3 --- components/esp_rom/include/esp32c3/rom/rtc.h | 4 ++-- components/esp_system/port/soc/esp32/clk.c | 4 ++-- components/esp_system/port/soc/esp32c3/clk.c | 9 ++++----- components/esp_system/port/soc/esp32s2/clk.c | 7 ++++--- components/esp_system/port/soc/esp32s3/clk.c | 6 ++++-- 5 files changed, 16 insertions(+), 14 deletions(-) diff --git a/components/esp_rom/include/esp32c3/rom/rtc.h b/components/esp_rom/include/esp32c3/rom/rtc.h index ef0c5daaba..8c9be5ea26 100644 --- a/components/esp_rom/include/esp32c3/rom/rtc.h +++ b/components/esp_rom/include/esp32c3/rom/rtc.h @@ -93,8 +93,8 @@ typedef enum { RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/ RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/ RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/ - TG1WDT_CPU_RESET = 17, /**<11, Time Group1 reset CPU*/ - SUPER_WDT_RESET = 18, /**<11, super watchdog reset digital core and rtc module*/ + TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/ + SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/ } RESET_REASON; typedef enum { diff --git a/components/esp_system/port/soc/esp32/clk.c b/components/esp_system/port/soc/esp32/clk.c index 720c0e9b26..ca55a5f4e2 100644 --- a/components/esp_system/port/soc/esp32/clk.c +++ b/components/esp_system/port/soc/esp32/clk.c @@ -225,9 +225,9 @@ __attribute__((weak)) void esp_perip_clk_init(void) /* For reason that only reset CPU, do not disable the clocks * that have been enabled before reset. */ - if ((rst_reas[0] >= TGWDT_CPU_RESET && rst_reas[0] <= RTCWDT_CPU_RESET) + if ((rst_reas[0] == TGWDT_CPU_RESET || rst_reas[0] == SW_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) #if !CONFIG_FREERTOS_UNICORE - || (rst_reas[1] >= TGWDT_CPU_RESET && rst_reas[1] <= RTCWDT_CPU_RESET) + || (rst_reas[1] == TGWDT_CPU_RESET || rst_reas[1] == SW_CPU_RESET || rst_reas[1] == RTCWDT_CPU_RESET) #endif ) { common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG); diff --git a/components/esp_system/port/soc/esp32c3/clk.c b/components/esp_system/port/soc/esp32c3/clk.c index 8e2b443b86..d3b63ef5e7 100644 --- a/components/esp_system/port/soc/esp32c3/clk.c +++ b/components/esp_system/port/soc/esp32c3/clk.c @@ -223,12 +223,11 @@ __attribute__((weak)) void esp_perip_clk_init(void) /* For reason that only reset CPU, do not disable the clocks * that have been enabled before reset. */ - /* For reason that only reset CPU, do not disable the clocks - * that have been enabled before reset. - */ - if ((rst_reas[0] >= TG0WDT_CPU_RESET && rst_reas[0] <= TG0WDT_CPU_RESET && rst_reas[0] != RTCWDT_BROWN_OUT_RESET) + if ((rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == RTC_SW_CPU_RESET || + rst_reas[0] == RTCWDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET) #if !CONFIG_FREERTOS_UNICORE - || (rst_reas[1] >= TG0WDT_CPU_RESET && rst_reas[1] <= RTCWDT_CPU_RESET) + || (rst_reas[1] == TG0WDT_CPU_RESET || rst_reas[1] == RTC_SW_CPU_RESET || + rst_reas[1] == RTCWDT_CPU_RESET || rst_reas[1] == TG1WDT_CPU_RESET) #endif ) { common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG); diff --git a/components/esp_system/port/soc/esp32s2/clk.c b/components/esp_system/port/soc/esp32s2/clk.c index 688e0ec076..358991d308 100644 --- a/components/esp_system/port/soc/esp32s2/clk.c +++ b/components/esp_system/port/soc/esp32s2/clk.c @@ -219,9 +219,10 @@ __attribute__((weak)) void esp_perip_clk_init(void) /* For reason that only reset CPU, do not disable the clocks * that have been enabled before reset. */ - if (rst_reas[0] >= TG0WDT_CPU_RESET && - rst_reas[0] <= TG0WDT_CPU_RESET && - rst_reas[0] != RTCWDT_BROWN_OUT_RESET) { + if (rst_reas[0] == TG0WDT_CPU_RESET || + rst_reas[0] == RTC_SW_CPU_RESET || + rst_reas[0] == RTCWDT_CPU_RESET || + rst_reas[0] == TG1WDT_CPU_RESET) { common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG); hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN1_REG); wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG); diff --git a/components/esp_system/port/soc/esp32s3/clk.c b/components/esp_system/port/soc/esp32s3/clk.c index 05b9df6bde..f7f2aa7089 100644 --- a/components/esp_system/port/soc/esp32s3/clk.c +++ b/components/esp_system/port/soc/esp32s3/clk.c @@ -221,9 +221,11 @@ __attribute__((weak)) void esp_perip_clk_init(void) /* For reason that only reset CPU, do not disable the clocks * that have been enabled before reset. */ - if ((rst_reas[0] >= TG0WDT_CPU_RESET && rst_reas[0] <= TG0WDT_CPU_RESET && rst_reas[0] != RTCWDT_BROWN_OUT_RESET) + if ((rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == RTC_SW_CPU_RESET || + rst_reas[0] == RTCWDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET) #if !CONFIG_FREERTOS_UNICORE - || (rst_reas[1] >= TG0WDT_CPU_RESET && rst_reas[1] <= RTCWDT_CPU_RESET) + || (rst_reas[1] == TG0WDT_CPU_RESET || rst_reas[1] == RTC_SW_CPU_RESET || + rst_reas[1] == RTCWDT_CPU_RESET || rst_reas[1] == TG1WDT_CPU_RESET) #endif ) { common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);