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unit_test: support reference clock, test delay function

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This commit is contained in:
morris
2020-08-13 11:56:52 +08:00
parent e90dbe29cb
commit 75a372a9f0
8 changed files with 3058 additions and 2308 deletions
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7
components/esp_timer/test/test_esp_timer.c
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@@ -6,7 +6,6 @@
#include "esp_timer.h" #include "esp_timer.h"
#include "esp_timer_impl.h" #include "esp_timer_impl.h"
#include "unity.h" #include "unity.h"
#include "soc/frc_timer_reg.h"
#include "soc/timer_group_reg.h" #include "soc/timer_group_reg.h"
#include "esp_heap_caps.h" #include "esp_heap_caps.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
@@ -16,6 +15,10 @@
#include "esp_freertos_hooks.h" #include "esp_freertos_hooks.h"
#include "esp_rom_sys.h" #include "esp_rom_sys.h"
#if CONFIG_ESP_TIMER_IMPL_FRC2
#include "soc/frc_timer_reg.h"
#endif
#ifdef CONFIG_ESP_TIMER_PROFILING #ifdef CONFIG_ESP_TIMER_PROFILING
#define WITH_PROFILING 1 #define WITH_PROFILING 1
#endif #endif
@@ -855,6 +858,7 @@ TEST_CASE("Test case when esp_timer_impl_set_alarm needs set timer < now_time",
TEST_ASSERT(alarm_reg <= (count_reg + offset)); TEST_ASSERT(alarm_reg <= (count_reg + offset));
} }
#ifdef CONFIG_ESP_TIMER_IMPL_FRC2
TEST_CASE("Test esp_timer_impl_set_alarm when the counter is near an overflow value", "[esp_timer]") TEST_CASE("Test esp_timer_impl_set_alarm when the counter is near an overflow value", "[esp_timer]")
{ {
for (int i = 0; i < 1024; ++i) { for (int i = 0; i < 1024; ++i) {
@@ -864,3 +868,4 @@ TEST_CASE("Test esp_timer_impl_set_alarm when the counter is near an overflow va
esp_timer_impl_set_alarm(1); // timestamp is expired esp_timer_impl_set_alarm(1); // timestamp is expired
} }
} }
#endif

55
components/hal/esp32s3/include/hal/rmt_ll.h
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@@ -17,6 +17,7 @@
extern "C" { extern "C" {
#endif #endif
#include <stdint.h>
#include <stdbool.h> #include <stdbool.h>
#include "soc/rmt_struct.h" #include "soc/rmt_struct.h"
#include "soc/rmt_caps.h" #include "soc/rmt_caps.h"
@@ -24,6 +25,16 @@ extern "C" {
#define RMT_LL_HW_BASE (&RMT) #define RMT_LL_HW_BASE (&RMT)
#define RMT_LL_MEM_BASE (&RMTMEM) #define RMT_LL_MEM_BASE (&RMTMEM)
static inline void rmt_ll_set_sclk(rmt_dev_t *dev, uint32_t source, uint32_t div_num, uint32_t div_frac_a, uint32_t div_frac_b)
{
dev->sys_conf.sclk_active = 0;
dev->sys_conf.sclk_sel = source;
dev->sys_conf.sclk_div_num = div_num;
dev->sys_conf.sclk_div_a = div_frac_a;
dev->sys_conf.sclk_div_b = div_frac_b;
dev->sys_conf.sclk_active = 1;
}
static inline void rmt_ll_enable_drive_clock(rmt_dev_t *dev, bool enable) static inline void rmt_ll_enable_drive_clock(rmt_dev_t *dev, bool enable)
{ {
dev->sys_conf.clk_en = enable; // register clock gating dev->sys_conf.clk_en = enable; // register clock gating
@@ -38,14 +49,20 @@ static inline void rmt_ll_reset_counter_clock_div(rmt_dev_t *dev, uint32_t chann
static inline void rmt_ll_reset_tx_pointer(rmt_dev_t *dev, uint32_t channel) static inline void rmt_ll_reset_tx_pointer(rmt_dev_t *dev, uint32_t channel)
{ {
dev->tx_conf[channel].apb_mem_rst = 1;
dev->tx_conf[channel].mem_rd_rst = 1;
} }
static inline void rmt_ll_reset_rx_pointer(rmt_dev_t *dev, uint32_t channel) static inline void rmt_ll_reset_rx_pointer(rmt_dev_t *dev, uint32_t channel)
{ {
dev->rx_conf[channel].conf1.apb_mem_rst = 1;
dev->rx_conf[channel].conf1.mem_wr_rst = 1;
} }
static inline void rmt_ll_start_tx(rmt_dev_t *dev, uint32_t channel) static inline void rmt_ll_start_tx(rmt_dev_t *dev, uint32_t channel)
{ {
dev->tx_conf[channel].conf_update = 1;
dev->tx_conf[channel].tx_start = 1;
} }
static inline void rmt_ll_stop_tx(rmt_dev_t *dev, uint32_t channel) static inline void rmt_ll_stop_tx(rmt_dev_t *dev, uint32_t channel)
@@ -72,6 +89,7 @@ static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev)
static inline void rmt_ll_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num) static inline void rmt_ll_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
{ {
dev->tx_conf[channel].mem_size = block_num;
} }
static inline uint32_t rmt_ll_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) static inline uint32_t rmt_ll_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
@@ -81,11 +99,12 @@ static inline uint32_t rmt_ll_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
static inline void rmt_ll_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) static inline void rmt_ll_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
{ {
dev->tx_conf[channel].div_cnt = div;
} }
static inline uint32_t rmt_ll_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel) static inline uint32_t rmt_ll_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
{ {
return 256; return dev->tx_conf[channel].div_cnt;
} }
static inline void rmt_ll_enable_tx_pingpong(rmt_dev_t *dev, bool enable) static inline void rmt_ll_enable_tx_pingpong(rmt_dev_t *dev, bool enable)
@@ -117,6 +136,7 @@ static inline uint32_t rmt_ll_get_mem_owner(rmt_dev_t *dev, uint32_t channel)
static inline void rmt_ll_enable_tx_loop(rmt_dev_t *dev, uint32_t channel, bool enable) static inline void rmt_ll_enable_tx_loop(rmt_dev_t *dev, uint32_t channel, bool enable)
{ {
dev->tx_conf[channel].tx_conti_mode = enable;
} }
static inline bool rmt_ll_is_tx_loop_enabled(rmt_dev_t *dev, uint32_t channel) static inline bool rmt_ll_is_tx_loop_enabled(rmt_dev_t *dev, uint32_t channel)
@@ -126,23 +146,23 @@ static inline bool rmt_ll_is_tx_loop_enabled(rmt_dev_t *dev, uint32_t channel)
static inline void rmt_ll_set_tx_loop_count(rmt_dev_t *dev, uint32_t channel, uint32_t count) static inline void rmt_ll_set_tx_loop_count(rmt_dev_t *dev, uint32_t channel, uint32_t count)
{ {
dev->tx_lim_ch[channel].tx_loop_num = count; dev->tx_lim[channel].tx_loop_num = count;
} }
static inline void rmt_ll_reset_tx_loop(rmt_dev_t *dev, uint32_t channel) static inline void rmt_ll_reset_tx_loop(rmt_dev_t *dev, uint32_t channel)
{ {
dev->tx_lim_ch[channel].loop_count_reset = 1; dev->tx_lim[channel].loop_count_reset = 1;
dev->tx_lim_ch[channel].loop_count_reset = 0; dev->tx_lim[channel].loop_count_reset = 0;
} }
static inline void rmt_ll_enable_tx_loop_count(rmt_dev_t *dev, uint32_t channel, bool enable) static inline void rmt_ll_enable_tx_loop_count(rmt_dev_t *dev, uint32_t channel, bool enable)
{ {
dev->tx_lim_ch[channel].tx_loop_cnt_en = enable; dev->tx_lim[channel].tx_loop_cnt_en = enable;
} }
static inline void rmt_ll_enable_tx_sync(rmt_dev_t *dev, bool enable) static inline void rmt_ll_enable_tx_sync(rmt_dev_t *dev, bool enable)
{ {
dev->tx_sim.en = enable; dev->tx_sim.tx_sim_en = enable;
} }
static inline void rmt_ll_add_channel_to_group(rmt_dev_t *dev, uint32_t channel) static inline void rmt_ll_add_channel_to_group(rmt_dev_t *dev, uint32_t channel)
@@ -175,30 +195,32 @@ static inline uint32_t rmt_ll_get_counter_clock_src(rmt_dev_t *dev, uint32_t cha
static inline void rmt_ll_enable_tx_idle(rmt_dev_t *dev, uint32_t channel, bool enable) static inline void rmt_ll_enable_tx_idle(rmt_dev_t *dev, uint32_t channel, bool enable)
{ {
dev->tx_conf[channel].idle_out_en = enable;
} }
static inline bool rmt_ll_is_tx_idle_enabled(rmt_dev_t *dev, uint32_t channel) static inline bool rmt_ll_is_tx_idle_enabled(rmt_dev_t *dev, uint32_t channel)
{ {
return false; return dev->tx_conf[channel].idle_out_en;
} }
static inline void rmt_ll_set_tx_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) static inline void rmt_ll_set_tx_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{ {
dev->tx_conf[channel].idle_out_lv = level;
} }
static inline uint32_t rmt_ll_get_tx_idle_level(rmt_dev_t *dev, uint32_t channel) static inline uint32_t rmt_ll_get_tx_idle_level(rmt_dev_t *dev, uint32_t channel)
{ {
return 0; return dev->tx_conf[channel].idle_out_lv;
} }
static inline uint32_t rmt_ll_get_channel_status(rmt_dev_t *dev, uint32_t channel) static inline uint32_t rmt_ll_get_channel_status(rmt_dev_t *dev, uint32_t channel)
{ {
return dev->status_ch[channel].val; return 0;
} }
static inline void rmt_ll_set_tx_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit) static inline void rmt_ll_set_tx_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
{ {
dev->tx_lim_ch[channel].limit = limit; dev->tx_lim[channel].limit = limit;
} }
static inline void rmt_ll_set_rx_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit) static inline void rmt_ll_set_rx_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
@@ -316,34 +338,39 @@ static inline void rmt_ll_set_tx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t
{ {
// In case the compiler optimise a 32bit instruction (e.g. s32i) into two 16bit instruction (e.g. s16i, which is not allowed to access a register) // In case the compiler optimise a 32bit instruction (e.g. s32i) into two 16bit instruction (e.g. s16i, which is not allowed to access a register)
// We take care of the "read-modify-write" procedure by ourselves. // We take care of the "read-modify-write" procedure by ourselves.
typeof(dev->carrier_duty_ch[0]) reg; typeof(dev->tx_carrier[0]) reg;
reg.high = high_ticks; reg.high = high_ticks;
reg.low = low_ticks; reg.low = low_ticks;
dev->carrier_duty_ch[channel].val = reg.val; dev->tx_carrier[channel].val = reg.val;
} }
static inline void rmt_ll_set_rx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) static inline void rmt_ll_set_rx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
{ {
typeof(dev->rx_carrier[0]) reg;
reg.high_thres = high_ticks;
reg.low_thres = low_ticks;
dev->rx_carrier[channel].val = reg.val;
} }
static inline void rmt_ll_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks) static inline void rmt_ll_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
{ {
*high_ticks = dev->carrier_duty_ch[channel].high;
*low_ticks = dev->carrier_duty_ch[channel].low;
} }
static inline void rmt_ll_enable_carrier(rmt_dev_t *dev, uint32_t channel, bool enable) static inline void rmt_ll_enable_carrier(rmt_dev_t *dev, uint32_t channel, bool enable)
{ {
dev->tx_conf[channel].carrier_en = enable;
} }
static inline void rmt_ll_set_carrier_on_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) static inline void rmt_ll_set_carrier_on_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{ {
dev->tx_conf[channel].carrier_out_lv = level;
} }
// set true, enable carrier in all RMT state (idle, reading, sending) // set true, enable carrier in all RMT state (idle, reading, sending)
// set false, enable carrier only in sending state (i.e. there're effective data in RAM to be sent) // set false, enable carrier only in sending state (i.e. there're effective data in RAM to be sent)
static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t channel, bool enable) static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t channel, bool enable)
{ {
dev->tx_conf[channel].carrier_eff_en = !enable;
} }
static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off) static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off)

1
components/hal/include/hal/rmt_hal.h
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@@ -17,6 +17,7 @@
extern "C" { extern "C" {
#endif #endif
#include <stdint.h>
#include "soc/rmt_struct.h" #include "soc/rmt_struct.h"
#include "soc/rmt_caps.h" #include "soc/rmt_caps.h"

16
components/idf_test/include/esp32s3/idf_performance_target.h
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@@ -15,3 +15,19 @@
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30
#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B
#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B (309*1000)
#endif
#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB
#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB (1697*1000)
#endif
#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE
#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE 76600
#endif
// floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround)
#define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70
#define IDF_PERFORMANCE_MAX_CYCLES_PER_SQRT 140

4810
components/soc/soc/esp32s3/include/soc/rmt_reg.h
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File diff suppressed because it is too large Load Diff

472
components/soc/soc/esp32s3/include/soc/rmt_struct.h
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@@ -17,314 +17,322 @@
extern "C" { extern "C" {
#endif #endif
#include <stdint.h>
typedef volatile struct { typedef volatile struct {
uint32_t data_ch[8]; /**/ uint32_t data_ch[8];
union { union {
struct { struct {
uint32_t mem_raddr_ex: 10; uint32_t tx_start : 1;
uint32_t reserved10: 1; uint32_t mem_rd_rst : 1;
uint32_t waddr: 10; uint32_t apb_mem_rst : 1;
uint32_t reserved21: 1; uint32_t tx_conti_mode : 1;
uint32_t state: 3; uint32_t mem_tx_wrap_en : 1;
uint32_t mem_empty: 1; uint32_t idle_out_lv : 1;
uint32_t apb_mem_wr_err: 1; uint32_t idle_out_en : 1;
uint32_t reserved27: 5; uint32_t tx_stop : 1;
uint32_t div_cnt : 8;
uint32_t mem_size : 4;
uint32_t carrier_eff_en : 1;
uint32_t carrier_en : 1;
uint32_t carrier_out_lv : 1;
uint32_t afifo_rst : 1;
uint32_t conf_update : 1;
uint32_t reserved25 : 7;
}; };
uint32_t val; uint32_t val;
} status_ch[8]; } tx_conf[4];
struct {
union {
struct {
uint32_t div_cnt : 8;
uint32_t idle_thres : 15;
uint32_t reserved23 : 1;
uint32_t mem_size : 4;
uint32_t carrier_en : 1;
uint32_t carrier_out_lv : 1;
uint32_t reserved30 : 2;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t rx_en : 1;
uint32_t mem_wr_rst : 1;
uint32_t apb_mem_rst : 1;
uint32_t mem_owner : 1;
uint32_t rx_filter_en : 1;
uint32_t rx_filter_thres : 8;
uint32_t mem_rx_wrap_en : 1;
uint32_t afifo_rst : 1;
uint32_t conf_update : 1;
uint32_t reserved16 : 16;
};
uint32_t val;
} conf1;
} rx_conf[4];
union { union {
struct { struct {
uint32_t ch0_tx_end: 1; uint32_t mem_raddr_ex : 10;
uint32_t ch1_tx_end: 1; uint32_t reserved10 : 1;
uint32_t ch2_tx_end: 1; uint32_t apb_mem_waddr : 10;
uint32_t ch3_tx_end: 1; uint32_t reserved21 : 1;
uint32_t ch0_err: 1; uint32_t state : 3;
uint32_t ch1_err: 1; uint32_t mem_empty : 1;
uint32_t ch2_err: 1; uint32_t apb_mem_wr_err : 1;
uint32_t ch3_err: 1; uint32_t reserved27 : 5;
uint32_t ch0_tx_thr_event: 1; };
uint32_t ch1_tx_thr_event: 1; uint32_t val;
uint32_t ch2_tx_thr_event: 1; } tx_status[4];
uint32_t ch3_tx_thr_event: 1; union {
uint32_t ch0_tx_loop: 1; struct {
uint32_t ch1_tx_loop: 1; uint32_t mem_waddr_ex : 10;
uint32_t ch2_tx_loop: 1; uint32_t reserved10 : 1;
uint32_t ch3_tx_loop: 1; uint32_t apb_mem_raddr : 10;
uint32_t ch4_rx_end: 1; uint32_t reserved21 : 1;
uint32_t ch5_rx_end: 1; uint32_t state : 3;
uint32_t ch6_rx_end: 1; uint32_t mem_owner_err : 1;
uint32_t ch7_rx_end: 1; uint32_t mem_full : 1;
uint32_t ch4_err: 1; uint32_t apb_mem_rd_err : 1;
uint32_t ch5_err: 1; uint32_t reserved27 : 4;
uint32_t ch6_err: 1; };
uint32_t ch7_err: 1; uint32_t val;
uint32_t ch4_rx_thr_event: 1; } rx_status[4];
uint32_t ch5_rx_thr_event: 1; union {
uint32_t ch6_rx_thr_event: 1; struct {
uint32_t ch7_rx_thr_event: 1; uint32_t ch0_tx_end : 1;
uint32_t reserved28: 4; uint32_t ch1_tx_end : 1;
uint32_t ch2_tx_end : 1;
uint32_t ch3_tx_end : 1;
uint32_t ch0_err : 1;
uint32_t ch1_err : 1;
uint32_t ch2_err : 1;
uint32_t ch3_err : 1;
uint32_t ch0_tx_thr_event : 1;
uint32_t ch1_tx_thr_event : 1;
uint32_t ch2_tx_thr_event : 1;
uint32_t ch3_tx_thr_event : 1;
uint32_t ch0_tx_loop : 1;
uint32_t ch1_tx_loop : 1;
uint32_t ch2_tx_loop : 1;
uint32_t ch3_tx_loop : 1;
uint32_t ch4_rx_end : 1;
uint32_t ch5_rx_end : 1;
uint32_t ch6_rx_end : 1;
uint32_t ch7_rx_end : 1;
uint32_t ch4_err : 1;
uint32_t ch5_err : 1;
uint32_t ch6_err : 1;
uint32_t ch7_err : 1;
uint32_t ch4_rx_thr_event : 1;
uint32_t ch5_rx_thr_event : 1;
uint32_t ch6_rx_thr_event : 1;
uint32_t ch7_rx_thr_event : 1;
uint32_t reserved28 : 4;
}; };
uint32_t val; uint32_t val;
} int_raw; } int_raw;
union { union {
struct { struct {
uint32_t ch0_tx_end: 1; uint32_t ch0_tx_end : 1;
uint32_t ch1_tx_end: 1; uint32_t ch1_tx_end : 1;
uint32_t ch2_tx_end: 1; uint32_t ch2_tx_end : 1;
uint32_t ch3_tx_end: 1; uint32_t ch3_tx_end : 1;
uint32_t ch0_err: 1; uint32_t ch0_err : 1;
uint32_t ch1_err: 1; uint32_t ch1_err : 1;
uint32_t ch2_err: 1; uint32_t ch2_err : 1;
uint32_t ch3_err: 1; uint32_t ch3_err : 1;
uint32_t ch0_tx_thr_event: 1; uint32_t ch0_tx_thr_event : 1;
uint32_t ch1_tx_thr_event: 1; uint32_t ch1_tx_thr_event : 1;
uint32_t ch2_tx_thr_event: 1; uint32_t ch2_tx_thr_event : 1;
uint32_t ch3_tx_thr_event: 1; uint32_t ch3_tx_thr_event : 1;
uint32_t ch0_tx_loop: 1; uint32_t ch0_tx_loop : 1;
uint32_t ch1_tx_loop: 1; uint32_t ch1_tx_loop : 1;
uint32_t ch2_tx_loop: 1; uint32_t ch2_tx_loop : 1;
uint32_t ch3_tx_loop: 1; uint32_t ch3_tx_loop : 1;
uint32_t ch4_rx_end: 1; uint32_t ch4_rx_end : 1;
uint32_t ch5_rx_end: 1; uint32_t ch5_rx_end : 1;
uint32_t ch6_rx_end: 1; uint32_t ch6_rx_end : 1;
uint32_t ch7_rx_end: 1; uint32_t ch7_rx_end : 1;
uint32_t ch4_err: 1; uint32_t ch4_err : 1;
uint32_t ch5_err: 1; uint32_t ch5_err : 1;
uint32_t ch6_err: 1; uint32_t ch6_err : 1;
uint32_t ch7_err: 1; uint32_t ch7_err : 1;
uint32_t ch4_rx_thr_event: 1; uint32_t ch4_rx_thr_event : 1;
uint32_t ch5_rx_thr_event: 1; uint32_t ch5_rx_thr_event : 1;
uint32_t ch6_rx_thr_event: 1; uint32_t ch6_rx_thr_event : 1;
uint32_t ch7_rx_thr_event: 1; uint32_t ch7_rx_thr_event : 1;
uint32_t reserved28: 4; uint32_t reserved28 : 4;
}; };
uint32_t val; uint32_t val;
} int_st; } int_st;
union { union {
struct { struct {
uint32_t ch0_tx_end: 1; uint32_t ch0_tx_end : 1;
uint32_t ch1_tx_end: 1; uint32_t ch1_tx_end : 1;
uint32_t ch2_tx_end: 1; uint32_t ch2_tx_end : 1;
uint32_t ch3_tx_end: 1; uint32_t ch3_tx_end : 1;
uint32_t ch0_err: 1; uint32_t ch0_err : 1;
uint32_t ch1_err: 1; uint32_t ch1_err : 1;
uint32_t ch2_err: 1; uint32_t ch2_err : 1;
uint32_t ch3_err: 1; uint32_t ch3_err : 1;
uint32_t ch0_tx_thr_event: 1; uint32_t ch0_tx_thr_event : 1;
uint32_t ch1_tx_thr_event: 1; uint32_t ch1_tx_thr_event : 1;
uint32_t ch2_tx_thr_event: 1; uint32_t ch2_tx_thr_event : 1;
uint32_t ch3_tx_thr_event: 1; uint32_t ch3_tx_thr_event : 1;
uint32_t ch0_tx_loop: 1; uint32_t ch0_tx_loop : 1;
uint32_t ch1_tx_loop: 1; uint32_t ch1_tx_loop : 1;
uint32_t ch2_tx_loop: 1; uint32_t ch2_tx_loop : 1;
uint32_t ch3_tx_loop: 1; uint32_t ch3_tx_loop : 1;
uint32_t ch4_rx_end: 1; uint32_t ch4_rx_end : 1;
uint32_t ch5_rx_end: 1; uint32_t ch5_rx_end : 1;
uint32_t ch6_rx_end: 1; uint32_t ch6_rx_end : 1;
uint32_t ch7_rx_end: 1; uint32_t ch7_rx_end : 1;
uint32_t ch4_err: 1; uint32_t ch4_err : 1;
uint32_t ch5_err: 1; uint32_t ch5_err : 1;
uint32_t ch6_err: 1; uint32_t ch6_err : 1;
uint32_t ch7_err: 1; uint32_t ch7_err : 1;
uint32_t ch4_rx_thr_event: 1; uint32_t ch4_rx_thr_event : 1;
uint32_t ch5_rx_thr_event: 1; uint32_t ch5_rx_thr_event : 1;
uint32_t ch6_rx_thr_event: 1; uint32_t ch6_rx_thr_event : 1;
uint32_t ch7_rx_thr_event: 1; uint32_t ch7_rx_thr_event : 1;
uint32_t reserved28: 4; uint32_t reserved28 : 4;
}; };
uint32_t val; uint32_t val;
} int_ena; } int_ena;
union { union {
struct { struct {
uint32_t ch0_tx_end: 1; uint32_t ch0_tx_end : 1;
uint32_t ch1_tx_end: 1; uint32_t ch1_tx_end : 1;
uint32_t ch2_tx_end: 1; uint32_t ch2_tx_end : 1;
uint32_t ch3_tx_end: 1; uint32_t ch3_tx_end : 1;
uint32_t ch0_err: 1; uint32_t ch0_err : 1;
uint32_t ch1_err: 1; uint32_t ch1_err : 1;
uint32_t ch2_err: 1; uint32_t ch2_err : 1;
uint32_t ch3_err: 1; uint32_t ch3_err : 1;
uint32_t ch0_tx_thr_event: 1; uint32_t ch0_tx_thr_event : 1;
uint32_t ch1_tx_thr_event: 1; uint32_t ch1_tx_thr_event : 1;
uint32_t ch2_tx_thr_event: 1; uint32_t ch2_tx_thr_event : 1;
uint32_t ch3_tx_thr_event: 1; uint32_t ch3_tx_thr_event : 1;
uint32_t ch0_tx_loop: 1; uint32_t ch0_tx_loop : 1;
uint32_t ch1_tx_loop: 1; uint32_t ch1_tx_loop : 1;
uint32_t ch2_tx_loop: 1; uint32_t ch2_tx_loop : 1;
uint32_t ch3_tx_loop: 1; uint32_t ch3_tx_loop : 1;
uint32_t ch4_rx_end: 1; uint32_t ch4_rx_end : 1;
uint32_t ch5_rx_end: 1; uint32_t ch5_rx_end : 1;
uint32_t ch6_rx_end: 1; uint32_t ch6_rx_end : 1;
uint32_t ch7_rx_end: 1; uint32_t ch7_rx_end : 1;
uint32_t ch4_err: 1; uint32_t ch4_err : 1;
uint32_t ch5_err: 1; uint32_t ch5_err : 1;
uint32_t ch6_err: 1; uint32_t ch6_err : 1;
uint32_t ch7_err: 1; uint32_t ch7_err : 1;
uint32_t ch4_rx_thr_event: 1; uint32_t ch4_rx_thr_event : 1;
uint32_t ch5_rx_thr_event: 1; uint32_t ch5_rx_thr_event : 1;
uint32_t ch6_rx_thr_event: 1; uint32_t ch6_rx_thr_event : 1;
uint32_t ch7_rx_thr_event: 1; uint32_t ch7_rx_thr_event : 1;
uint32_t reserved28: 4; uint32_t reserved28 : 4;
}; };
uint32_t val; uint32_t val;
} int_clr; } int_clr;
union { union {
struct { struct {
uint32_t low: 16; uint32_t low : 16;
uint32_t high: 16; uint32_t high : 16;
}; };
uint32_t val; uint32_t val;
} carrier_duty_ch[8]; } tx_carrier[4];
union { union {
struct { struct {
uint32_t carrier_low_thres_ch4: 16; uint32_t low_thres : 16;
uint32_t carrier_high_thres_ch4: 16; uint32_t high_thres : 16;
}; };
uint32_t val; uint32_t val;
} ch4_rx_carrier_rm; } rx_carrier[4];
union { union {
struct { struct {
uint32_t carrier_low_thres_ch5: 16; uint32_t limit : 9;
uint32_t carrier_high_thres_ch5: 16; uint32_t tx_loop_num : 10;
uint32_t tx_loop_cnt_en : 1;
uint32_t loop_count_reset : 1;
uint32_t reserved21 : 11;
}; };
uint32_t val; uint32_t val;
} ch5_rx_carrier_rm; } tx_lim[4];
union { union {
struct { struct {
uint32_t carrier_low_thres_ch6: 16; uint32_t rx_lim : 9;
uint32_t carrier_high_thres_ch6: 16; uint32_t reserved9 : 23;
}; };
uint32_t val; uint32_t val;
} ch6_rx_carrier_rm; } rx_lim[4];
union { union {
struct { struct {
uint32_t carrier_low_thres_ch7: 16; uint32_t fifo_mask : 1;
uint32_t carrier_high_thres_ch7: 16; uint32_t mem_clk_force_on : 1;
}; uint32_t mem_force_pd : 1;
uint32_t val; uint32_t mem_force_pu : 1;
} ch7_rx_carrier_rm; uint32_t sclk_div_num : 8;
union { uint32_t sclk_div_a : 6;
struct { uint32_t sclk_div_b : 6;
uint32_t limit: 9; uint32_t sclk_sel : 2;
uint32_t tx_loop_num: 10; uint32_t sclk_active : 1;
uint32_t tx_loop_cnt_en: 1; uint32_t reserved27 : 4;
uint32_t loop_count_reset: 1; uint32_t clk_en : 1;
uint32_t reserved21: 11;
};
uint32_t val;
} tx_lim_ch[8];
union {
struct {
uint32_t rx_lim_ch4: 9;
uint32_t reserved9: 23;
};
uint32_t val;
} ch4_rx_lim;
union {
struct {
uint32_t rx_lim_ch5: 9;
uint32_t reserved9: 23;
};
uint32_t val;
} ch5_rx_lim;
union {
struct {
uint32_t rx_lim_ch6: 9;
uint32_t reserved9: 23;
};
uint32_t val;
} ch6_rx_lim;
union {
struct {
uint32_t rx_lim_ch7: 9;
uint32_t reserved9: 23;
};
uint32_t val;
} ch7_rx_lim;
union {
struct {
uint32_t fifo_mask: 1;
uint32_t mem_clk_force_on: 1;
uint32_t mem_force_pd: 1;
uint32_t mem_force_pu: 1;
uint32_t sclk_div_num: 8;
uint32_t sclk_div_a: 6;
uint32_t sclk_div_b: 6;
uint32_t sclk_sel: 2;
uint32_t sclk_active: 1;
uint32_t reserved27: 4;
uint32_t clk_en: 1;
}; };
uint32_t val; uint32_t val;
} sys_conf; } sys_conf;
union { union {
struct { struct {
uint32_t ch0: 1; uint32_t tx_sim_ch0 : 1;
uint32_t ch1: 1; uint32_t tx_sim_ch1 : 1;
uint32_t ch2: 1; uint32_t tx_sim_ch2 : 1;
uint32_t ch3: 1; uint32_t tx_sim_ch3 : 1;
uint32_t en: 1; uint32_t tx_sim_en : 1;
uint32_t reserved5: 27; uint32_t reserved5 : 27;
}; };
uint32_t val; uint32_t val;
} tx_sim; } tx_sim;
union { union {
struct { struct {
uint32_t ch0: 1; uint32_t ref_cnt_rst_ch0 : 1;
uint32_t ch1: 1; uint32_t ref_cnt_rst_ch1 : 1;
uint32_t ch2: 1; uint32_t ref_cnt_rst_ch2 : 1;
uint32_t ch3: 1; uint32_t ref_cnt_rst_ch3 : 1;
uint32_t ch4: 1; uint32_t ref_cnt_rst_ch4 : 1;
uint32_t ch5: 1; uint32_t ref_cnt_rst_ch5 : 1;
uint32_t ch6: 1; uint32_t ref_cnt_rst_ch6 : 1;
uint32_t ch7: 1; uint32_t ref_cnt_rst_ch7 : 1;
uint32_t reserved8: 24; uint32_t reserved8 : 24;
}; };
uint32_t val; uint32_t val;
} ref_cnt_rst; } ref_cnt_rst;
union { union {
struct { struct {
uint32_t date: 28; uint32_t date : 28;
uint32_t reserved28: 4; uint32_t reserved28 : 4;
}; };
uint32_t val; uint32_t val;
} date; } date;
} rmt_dev_t; } rmt_dev_t;
extern rmt_dev_t RMT;
typedef struct { typedef struct {
union { union {
struct { struct {
uint32_t duration0 :15; uint32_t duration0 : 15;
uint32_t level0 :1; uint32_t level0 : 1;
uint32_t duration1 :15; uint32_t duration1 : 15;
uint32_t level1 :1; uint32_t level1 : 1;
}; };
uint32_t val; uint32_t val;
}; };
} rmt_item32_t; } rmt_item32_t;
typedef struct { extern rmt_dev_t RMT;
union {
struct {
uint16_t duration :15;
uint16_t level :1;
};
uint16_t val;
};
} rmt_item16_t;
//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
typedef volatile struct { typedef volatile struct {
struct { struct {
union { union {
rmt_item32_t data32[64]; rmt_item32_t data32[48];
rmt_item16_t data16[128];
}; };
} chan[4]; } chan[8];
} rmt_mem_t; } rmt_mem_t;
extern rmt_mem_t RMTMEM; extern rmt_mem_t RMTMEM;

3
tools/unit-test-app/components/test_utils/include/test_utils.h
View File

@@ -20,9 +20,10 @@
#include "sdkconfig.h" #include "sdkconfig.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "freertos/task.h" #include "freertos/task.h"
#include "unity.h"
/* include performance pass standards header file */ /* include performance pass standards header file */
#include "idf_performance.h" #include "idf_performance.h"
#include "idf_performance_target.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {

2
tools/unit-test-app/components/test_utils/ref_clock.c
View File

@@ -77,7 +77,7 @@ void ref_clock_init(void)
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
rmt_ll_set_counter_clock_src(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, 0); // select REF_TICK (1MHz) rmt_ll_set_counter_clock_src(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, 0); // select REF_TICK (1MHz)
#else #else
// TODO: configure RMT module clock source to fixed 1MHz rmt_ll_set_sclk(s_rmt_hal.regs, 3, 39, 0, 0); // XTAL(40MHz), rmt_sclk => 1MHz (40/(1+39))
#endif #endif
rmt_hal_set_counter_clock(&s_rmt_hal, REF_CLOCK_RMT_CHANNEL, 1000000, 1000000); // counter clock: 1MHz rmt_hal_set_counter_clock(&s_rmt_hal, REF_CLOCK_RMT_CHANNEL, 1000000, 1000000); // counter clock: 1MHz
rmt_ll_enable_tx_idle(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, true); // enable idle output rmt_ll_enable_tx_idle(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, true); // enable idle output