diff --git a/components/esp32/cpu_start.c b/components/esp32/cpu_start.c
index 61fefd5b17..96a65a0774 100644
--- a/components/esp32/cpu_start.c
+++ b/components/esp32/cpu_start.c
@@ -253,6 +253,11 @@ void IRAM_ATTR call_start_cpu0()
        fail initializing it properly. */
     heap_caps_init();
 
+    for (int i = 0; i < 64; i++) {
+        ets_printf(((i+1)%8) ? DRAM_STR("%08x ") : DRAM_STR("%08x\n"), *(((volatile uint32_t *)SOC_RTC_DATA_LOW) + i));
+        *(((volatile uint32_t *)SOC_RTC_DATA_LOW) + i) = 0;
+    }
+
     ESP_EARLY_LOGI(TAG, "Pro cpu start user code");
     start_cpu0();
 }
diff --git a/components/esp32/dport_panic_highint_hdl.S b/components/esp32/dport_panic_highint_hdl.S
index 5e6a271097..5283d4df07 100644
--- a/components/esp32/dport_panic_highint_hdl.S
+++ b/components/esp32/dport_panic_highint_hdl.S
@@ -230,6 +230,24 @@ xt_highint5:
     .align      4
 .handle_livelock_int:
 
+    movi    a0, SOC_RTC_DATA_LOW
+    movi    a5, _l4_intr_livelock_sync
+    l32i    a5, a5, 0
+    s32i    a5, a0, 0
+    memw
+    movi    a5, _l4_intr_livelock_sync
+    l32i    a5, a5, 4
+    s32i    a5, a0, 4
+    memw
+    movi    a5, _l4_intr_livelock_app
+    l32i    a5, a5, 0
+    s32i    a5, a0, 8
+    memw
+    movi    a5, _l4_intr_livelock_counter
+    l32i    a5, a5, 0
+    s32i    a5, a0, 12
+    memw
+
     getcoreid   a5
 
     /* Save A2, A3, A4 so we can use those registers */