From 63ac5e4a991942f350ae124551276e84b736ca55 Mon Sep 17 00:00:00 2001 From: jiangguangming Date: Thu, 21 Apr 2022 23:26:56 +0800 Subject: [PATCH 1/4] mmu: add ll func used to invalidate the mmu entry --- components/hal/esp32/include/hal/mmu_ll.h | 28 ++++++++++++++++++++- components/hal/esp32c2/include/hal/mmu_ll.h | 14 +++++++++++ components/hal/esp32c3/include/hal/mmu_ll.h | 14 +++++++++++ components/hal/esp32h2/include/hal/mmu_ll.h | 14 +++++++++++ components/hal/esp32s2/include/hal/mmu_ll.h | 15 +++++++++++ components/hal/esp32s3/include/hal/mmu_ll.h | 15 +++++++++++ components/soc/esp32/include/soc/mmu.h | 22 ++++++---------- tools/ci/check_copyright_ignore.txt | 1 - 8 files changed, 107 insertions(+), 16 deletions(-) diff --git a/components/hal/esp32/include/hal/mmu_ll.h b/components/hal/esp32/include/hal/mmu_ll.h index d5ffc7e143..c7772c4fee 100644 --- a/components/hal/esp32/include/hal/mmu_ll.h +++ b/components/hal/esp32/include/hal/mmu_ll.h @@ -11,7 +11,8 @@ #include "soc/ext_mem_defs.h" #include "hal/assert.h" #include "hal/mmu_types.h" - +#include "soc/mmu.h" +#include "soc/dport_access.h" #ifdef __cplusplus extern "C" { @@ -68,6 +69,31 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t (ADDRESS_IN_DROM0_CACHE(vaddr_start) && ADDRESS_IN_DROM0_CACHE(vaddr_end)); } +/** + * Set MMU table entry as invalid + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + */ +__attribute__((always_inline)) +static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) +{ + HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); + + DPORT_INTERRUPT_DISABLE(); + switch (mmu_id) { + case MMU_TABLE_PRO: + DPORT_WRITE_PERI_REG((uint32_t)&SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[entry_id], SOC_MMU_INVALID_ENTRY_VAL); + break; + case MMU_TABLE_APP: + DPORT_WRITE_PERI_REG((uint32_t)&SOC_MMU_DPORT_APP_FLASH_MMU_TABLE[entry_id], SOC_MMU_INVALID_ENTRY_VAL); + break; + default: + HAL_ASSERT(false && "invalid mmu_id"); + } + DPORT_INTERRUPT_RESTORE(); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c2/include/hal/mmu_ll.h b/components/hal/esp32c2/include/hal/mmu_ll.h index d632b80229..510a72bc1a 100644 --- a/components/hal/esp32c2/include/hal/mmu_ll.h +++ b/components/hal/esp32c2/include/hal/mmu_ll.h @@ -147,6 +147,20 @@ static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32 *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID; } +/** + * Set MMU table entry as invalid + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + */ +__attribute__((always_inline)) +static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) +{ + (void)mmu_id; + HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); + + *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; +} #ifdef __cplusplus } diff --git a/components/hal/esp32c3/include/hal/mmu_ll.h b/components/hal/esp32c3/include/hal/mmu_ll.h index a65d781ecc..dae0f1cc69 100644 --- a/components/hal/esp32c3/include/hal/mmu_ll.h +++ b/components/hal/esp32c3/include/hal/mmu_ll.h @@ -114,6 +114,20 @@ static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32 *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID; } +/** + * Set MMU table entry as invalid + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + */ +__attribute__((always_inline)) +static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) +{ + (void)mmu_id; + HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); + + *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; +} #ifdef __cplusplus } diff --git a/components/hal/esp32h2/include/hal/mmu_ll.h b/components/hal/esp32h2/include/hal/mmu_ll.h index 855589fbfa..617a753655 100644 --- a/components/hal/esp32h2/include/hal/mmu_ll.h +++ b/components/hal/esp32h2/include/hal/mmu_ll.h @@ -114,6 +114,20 @@ static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32 *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID; } +/** + * Set MMU table entry as invalid + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + */ +__attribute__((always_inline)) +static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) +{ + (void)mmu_id; + HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); + + *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; +} #ifdef __cplusplus } diff --git a/components/hal/esp32s2/include/hal/mmu_ll.h b/components/hal/esp32s2/include/hal/mmu_ll.h index 47b7a08b5f..14f776a7ea 100644 --- a/components/hal/esp32s2/include/hal/mmu_ll.h +++ b/components/hal/esp32s2/include/hal/mmu_ll.h @@ -138,6 +138,21 @@ static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32 *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | MMU_VALID; } +/** + * Set MMU table entry as invalid + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + */ +__attribute__((always_inline)) +static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) +{ + (void)mmu_id; + HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); + + *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s3/include/hal/mmu_ll.h b/components/hal/esp32s3/include/hal/mmu_ll.h index f1ef83b7df..aedc9c750c 100644 --- a/components/hal/esp32s3/include/hal/mmu_ll.h +++ b/components/hal/esp32s3/include/hal/mmu_ll.h @@ -114,6 +114,21 @@ static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32 *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | MMU_VALID; } +/** + * Set MMU table entry as invalid + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + */ +__attribute__((always_inline)) +static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) +{ + (void)mmu_id; + HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); + + *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; +} + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32/include/soc/mmu.h b/components/soc/esp32/include/soc/mmu.h index bde6995516..d0fba26a46 100644 --- a/components/soc/esp32/include/soc/mmu.h +++ b/components/soc/esp32/include/soc/mmu.h @@ -1,16 +1,9 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + #pragma once #include @@ -31,7 +24,8 @@ extern "C" { #define SOC_MMU_INVALID_ENTRY_VAL DPORT_FLASH_MMU_TABLE_INVALID_VAL #define SOC_MMU_ADDR_MASK DPORT_MMU_ADDRESS_MASK #define SOC_MMU_PAGE_IN_FLASH(page) (page) -#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE ((volatile uint32_t*) 0x3FF10000) +#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE DPORT_PRO_FLASH_MMU_TABLE +#define SOC_MMU_DPORT_APP_FLASH_MMU_TABLE DPORT_APP_FLASH_MMU_TABLE #define SOC_MMU_VADDR1_START_ADDR SOC_IROM_MASK_LOW #define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE ((SOC_MMU_VADDR1_FIRST_USABLE_ADDR - SOC_MMU_VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_IROM0_PAGES_START) #define SOC_MMU_VADDR0_START_ADDR SOC_DROM_LOW diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index b474f4e34d..8e6bea359a 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -1242,7 +1242,6 @@ components/soc/esp32/include/soc/i2c_struct.h components/soc/esp32/include/soc/io_mux_reg.h components/soc/esp32/include/soc/ledc_reg.h components/soc/esp32/include/soc/ledc_struct.h -components/soc/esp32/include/soc/mmu.h components/soc/esp32/include/soc/nrx_reg.h components/soc/esp32/include/soc/pid.h components/soc/esp32/include/soc/reset_reasons.h From 2764cd56821ef72dd3f32acdf6b4aa7f58ceb5c6 Mon Sep 17 00:00:00 2001 From: Armando Date: Thu, 21 Apr 2022 21:55:44 +0800 Subject: [PATCH 2/4] mmu: simplify mmu_hal_init --- components/hal/esp32/include/hal/mmu_ll.h | 25 ++++++++++++++----- components/hal/esp32c2/include/hal/mmu_ll.h | 13 ++++++++++ components/hal/esp32c3/include/hal/mmu_ll.h | 13 ++++++++++ components/hal/esp32h2/include/hal/mmu_ll.h | 13 ++++++++++ components/hal/esp32s2/include/hal/mmu_ll.h | 13 ++++++++++ components/hal/esp32s3/include/hal/mmu_ll.h | 13 ++++++++++ components/hal/mmu_hal.c | 15 ++--------- .../soc/esp32/include/soc/ext_mem_defs.h | 6 +++++ 8 files changed, 92 insertions(+), 19 deletions(-) diff --git a/components/hal/esp32/include/hal/mmu_ll.h b/components/hal/esp32/include/hal/mmu_ll.h index c7772c4fee..9e52d374ad 100644 --- a/components/hal/esp32/include/hal/mmu_ll.h +++ b/components/hal/esp32/include/hal/mmu_ll.h @@ -9,10 +9,10 @@ #pragma once #include "soc/ext_mem_defs.h" +#include "soc/dport_reg.h" +#include "soc/dport_access.h" #include "hal/assert.h" #include "hal/mmu_types.h" -#include "soc/mmu.h" -#include "soc/dport_access.h" #ifdef __cplusplus extern "C" { @@ -82,11 +82,11 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) DPORT_INTERRUPT_DISABLE(); switch (mmu_id) { - case MMU_TABLE_PRO: - DPORT_WRITE_PERI_REG((uint32_t)&SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[entry_id], SOC_MMU_INVALID_ENTRY_VAL); + case 0: + DPORT_WRITE_PERI_REG((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id], DPORT_FLASH_MMU_TABLE_INVALID_VAL); break; - case MMU_TABLE_APP: - DPORT_WRITE_PERI_REG((uint32_t)&SOC_MMU_DPORT_APP_FLASH_MMU_TABLE[entry_id], SOC_MMU_INVALID_ENTRY_VAL); + case 1: + DPORT_WRITE_PERI_REG((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[entry_id], DPORT_FLASH_MMU_TABLE_INVALID_VAL); break; default: HAL_ASSERT(false && "invalid mmu_id"); @@ -94,6 +94,19 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) DPORT_INTERRUPT_RESTORE(); } +/** + * Unmap all the items in the MMU table + * + * @param mmu_id MMU ID + */ +__attribute__((always_inline)) +static inline void mmu_ll_unmap_all(uint32_t mmu_id) +{ + for (int i = 0; i < MMU_MAX_ENTRY_NUM; i++) { + mmu_ll_set_entry_invalid(mmu_id, i); + } +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c2/include/hal/mmu_ll.h b/components/hal/esp32c2/include/hal/mmu_ll.h index 510a72bc1a..c206b411ae 100644 --- a/components/hal/esp32c2/include/hal/mmu_ll.h +++ b/components/hal/esp32c2/include/hal/mmu_ll.h @@ -162,6 +162,19 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; } +/** + * Unmap all the items in the MMU table + * + * @param mmu_id MMU ID + */ +__attribute__((always_inline)) +static inline void mmu_ll_unmap_all(uint32_t mmu_id) +{ + for (int i = 0; i < MMU_MAX_ENTRY_NUM; i++) { + mmu_ll_set_entry_invalid(mmu_id, i); + } +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c3/include/hal/mmu_ll.h b/components/hal/esp32c3/include/hal/mmu_ll.h index dae0f1cc69..7b5e038552 100644 --- a/components/hal/esp32c3/include/hal/mmu_ll.h +++ b/components/hal/esp32c3/include/hal/mmu_ll.h @@ -129,6 +129,19 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; } +/** + * Unmap all the items in the MMU table + * + * @param mmu_id MMU ID + */ +__attribute__((always_inline)) +static inline void mmu_ll_unmap_all(uint32_t mmu_id) +{ + for (int i = 0; i < MMU_MAX_ENTRY_NUM; i++) { + mmu_ll_set_entry_invalid(mmu_id, i); + } +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h2/include/hal/mmu_ll.h b/components/hal/esp32h2/include/hal/mmu_ll.h index 617a753655..7a930e38df 100644 --- a/components/hal/esp32h2/include/hal/mmu_ll.h +++ b/components/hal/esp32h2/include/hal/mmu_ll.h @@ -129,6 +129,19 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; } +/** + * Unmap all the items in the MMU table + * + * @param mmu_id MMU ID + */ +__attribute__((always_inline)) +static inline void mmu_ll_unmap_all(uint32_t mmu_id) +{ + for (int i = 0; i < MMU_MAX_ENTRY_NUM; i++) { + mmu_ll_set_entry_invalid(mmu_id, i); + } +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s2/include/hal/mmu_ll.h b/components/hal/esp32s2/include/hal/mmu_ll.h index 14f776a7ea..22fcf20781 100644 --- a/components/hal/esp32s2/include/hal/mmu_ll.h +++ b/components/hal/esp32s2/include/hal/mmu_ll.h @@ -153,6 +153,19 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; } +/** + * Unmap all the items in the MMU table + * + * @param mmu_id MMU ID + */ +__attribute__((always_inline)) +static inline void mmu_ll_unmap_all(uint32_t mmu_id) +{ + for (int i = 0; i < MMU_MAX_ENTRY_NUM; i++) { + mmu_ll_set_entry_invalid(mmu_id, i); + } +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s3/include/hal/mmu_ll.h b/components/hal/esp32s3/include/hal/mmu_ll.h index aedc9c750c..8b3c29e8a6 100644 --- a/components/hal/esp32s3/include/hal/mmu_ll.h +++ b/components/hal/esp32s3/include/hal/mmu_ll.h @@ -129,6 +129,19 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; } +/** + * Unmap all the items in the MMU table + * + * @param mmu_id MMU ID + */ +__attribute__((always_inline)) +static inline void mmu_ll_unmap_all(uint32_t mmu_id) +{ + for (int i = 0; i < MMU_MAX_ENTRY_NUM; i++) { + mmu_ll_set_entry_invalid(mmu_id, i); + } +} + #ifdef __cplusplus } #endif diff --git a/components/hal/mmu_hal.c b/components/hal/mmu_hal.c index 3931ddb22d..d3560aa04c 100644 --- a/components/hal/mmu_hal.c +++ b/components/hal/mmu_hal.c @@ -30,20 +30,9 @@ void mmu_hal_init(void) { -#if CONFIG_IDF_TARGET_ESP32 - mmu_init(0); + mmu_ll_unmap_all(0); #if !CONFIG_FREERTOS_UNICORE - /** - * The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are necessary to work around a hardware bug. - * See ESP32 Errata 3.1 - */ - DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR); - mmu_init(1); - DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR); -#endif - -#else //!esp32 - Cache_MMU_Init(); + mmu_ll_unmap_all(1); #endif } diff --git a/components/soc/esp32/include/soc/ext_mem_defs.h b/components/soc/esp32/include/soc/ext_mem_defs.h index 2fe9e40e96..a2f6849c8c 100644 --- a/components/soc/esp32/include/soc/ext_mem_defs.h +++ b/components/soc/esp32/include/soc/ext_mem_defs.h @@ -37,6 +37,12 @@ extern "C" { #define ADDRESS_IN_DRAM1_CACHE(vaddr) ADDRESS_IN_BUS(DRAM1_CACHE, vaddr) #define ADDRESS_IN_DROM0_CACHE(vaddr) ADDRESS_IN_BUS(DROM0_CACHE, vaddr) +/** + * Max MMU entry num. + * `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.: + * 256 * 64KB, means MMU can map 16MB at most + */ +#define MMU_MAX_ENTRY_NUM 256 #ifdef __cplusplus } From e09787d85136f52333bb39fd97ca31394508ff16 Mon Sep 17 00:00:00 2001 From: Armando Date: Tue, 26 Apr 2022 23:18:18 +0800 Subject: [PATCH 3/4] mmu: fix macro MMU_ENTRY_NUM and add new macro MMU_MAX_PADDR_PAGE_NUM --- components/hal/esp32/include/hal/mmu_ll.h | 4 ++-- components/hal/esp32c2/include/hal/mmu_ll.h | 6 +++--- components/hal/esp32c3/include/hal/mmu_ll.h | 6 +++--- components/hal/esp32h2/include/hal/mmu_ll.h | 6 +++--- components/hal/esp32s2/include/hal/mmu_ll.h | 6 +++--- components/hal/esp32s3/include/hal/mmu_ll.h | 6 +++--- components/hal/mmu_hal.c | 2 +- components/soc/esp32/include/soc/ext_mem_defs.h | 8 ++------ components/soc/esp32c2/include/soc/ext_mem_defs.h | 13 ++++++------- components/soc/esp32c3/include/soc/ext_mem_defs.h | 11 ++++++----- components/soc/esp32h2/include/soc/ext_mem_defs.h | 10 ++++++---- components/soc/esp32s2/include/soc/ext_mem_defs.h | 11 +++++++---- components/soc/esp32s3/include/soc/ext_mem_defs.h | 10 ++++++---- 13 files changed, 51 insertions(+), 48 deletions(-) diff --git a/components/hal/esp32/include/hal/mmu_ll.h b/components/hal/esp32/include/hal/mmu_ll.h index 9e52d374ad..ed67b21948 100644 --- a/components/hal/esp32/include/hal/mmu_ll.h +++ b/components/hal/esp32/include/hal/mmu_ll.h @@ -78,7 +78,7 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t __attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) { - HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); + HAL_ASSERT(entry_id < MMU_ENTRY_NUM); DPORT_INTERRUPT_DISABLE(); switch (mmu_id) { @@ -102,7 +102,7 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) __attribute__((always_inline)) static inline void mmu_ll_unmap_all(uint32_t mmu_id) { - for (int i = 0; i < MMU_MAX_ENTRY_NUM; i++) { + for (int i = 0; i < MMU_ENTRY_NUM; i++) { mmu_ll_set_entry_invalid(mmu_id, i); } } diff --git a/components/hal/esp32c2/include/hal/mmu_ll.h b/components/hal/esp32c2/include/hal/mmu_ll.h index c206b411ae..030d5d3ba4 100644 --- a/components/hal/esp32c2/include/hal/mmu_ll.h +++ b/components/hal/esp32c2/include/hal/mmu_ll.h @@ -142,7 +142,7 @@ static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32 { (void)mmu_id; HAL_ASSERT(target == MMU_TARGET_FLASH0); - HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); + HAL_ASSERT(entry_id < MMU_ENTRY_NUM); *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID; } @@ -157,7 +157,7 @@ __attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) { (void)mmu_id; - HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); + HAL_ASSERT(entry_id < MMU_ENTRY_NUM); *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; } @@ -170,7 +170,7 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) __attribute__((always_inline)) static inline void mmu_ll_unmap_all(uint32_t mmu_id) { - for (int i = 0; i < MMU_MAX_ENTRY_NUM; i++) { + for (int i = 0; i < MMU_ENTRY_NUM; i++) { mmu_ll_set_entry_invalid(mmu_id, i); } } diff --git a/components/hal/esp32c3/include/hal/mmu_ll.h b/components/hal/esp32c3/include/hal/mmu_ll.h index 7b5e038552..f648bef369 100644 --- a/components/hal/esp32c3/include/hal/mmu_ll.h +++ b/components/hal/esp32c3/include/hal/mmu_ll.h @@ -109,7 +109,7 @@ static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32 { (void)mmu_id; HAL_ASSERT(target == MMU_TARGET_FLASH0); - HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); + HAL_ASSERT(entry_id < MMU_ENTRY_NUM); *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID; } @@ -124,7 +124,7 @@ __attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) { (void)mmu_id; - HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); + HAL_ASSERT(entry_id < MMU_ENTRY_NUM); *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; } @@ -137,7 +137,7 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) __attribute__((always_inline)) static inline void mmu_ll_unmap_all(uint32_t mmu_id) { - for (int i = 0; i < MMU_MAX_ENTRY_NUM; i++) { + for (int i = 0; i < MMU_ENTRY_NUM; i++) { mmu_ll_set_entry_invalid(mmu_id, i); } } diff --git a/components/hal/esp32h2/include/hal/mmu_ll.h b/components/hal/esp32h2/include/hal/mmu_ll.h index 7a930e38df..33ba1d9489 100644 --- a/components/hal/esp32h2/include/hal/mmu_ll.h +++ b/components/hal/esp32h2/include/hal/mmu_ll.h @@ -109,7 +109,7 @@ static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32 { (void)mmu_id; HAL_ASSERT(target == MMU_TARGET_FLASH0); - HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); + HAL_ASSERT(entry_id < MMU_ENTRY_NUM); *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID; } @@ -124,7 +124,7 @@ __attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) { (void)mmu_id; - HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); + HAL_ASSERT(entry_id < MMU_ENTRY_NUM); *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; } @@ -137,7 +137,7 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) __attribute__((always_inline)) static inline void mmu_ll_unmap_all(uint32_t mmu_id) { - for (int i = 0; i < MMU_MAX_ENTRY_NUM; i++) { + for (int i = 0; i < MMU_ENTRY_NUM; i++) { mmu_ll_set_entry_invalid(mmu_id, i); } } diff --git a/components/hal/esp32s2/include/hal/mmu_ll.h b/components/hal/esp32s2/include/hal/mmu_ll.h index 22fcf20781..7829ae8954 100644 --- a/components/hal/esp32s2/include/hal/mmu_ll.h +++ b/components/hal/esp32s2/include/hal/mmu_ll.h @@ -132,7 +132,7 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target) { (void)mmu_id; - HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); + HAL_ASSERT(entry_id < MMU_ENTRY_NUM); uint32_t target_code = (target == MMU_TARGET_FLASH0) ? MMU_ACCESS_FLASH : MMU_ACCESS_SPIRAM; *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | MMU_VALID; @@ -148,7 +148,7 @@ __attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) { (void)mmu_id; - HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); + HAL_ASSERT(entry_id < MMU_ENTRY_NUM); *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; } @@ -161,7 +161,7 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) __attribute__((always_inline)) static inline void mmu_ll_unmap_all(uint32_t mmu_id) { - for (int i = 0; i < MMU_MAX_ENTRY_NUM; i++) { + for (int i = 0; i < MMU_ENTRY_NUM; i++) { mmu_ll_set_entry_invalid(mmu_id, i); } } diff --git a/components/hal/esp32s3/include/hal/mmu_ll.h b/components/hal/esp32s3/include/hal/mmu_ll.h index 8b3c29e8a6..b09ab67912 100644 --- a/components/hal/esp32s3/include/hal/mmu_ll.h +++ b/components/hal/esp32s3/include/hal/mmu_ll.h @@ -108,7 +108,7 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target) { (void)mmu_id; - HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); + HAL_ASSERT(entry_id < MMU_ENTRY_NUM); uint32_t target_code = (target == MMU_TARGET_FLASH0) ? MMU_ACCESS_FLASH : MMU_ACCESS_SPIRAM; *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | MMU_VALID; @@ -124,7 +124,7 @@ __attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) { (void)mmu_id; - HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); + HAL_ASSERT(entry_id < MMU_ENTRY_NUM); *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; } @@ -137,7 +137,7 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) __attribute__((always_inline)) static inline void mmu_ll_unmap_all(uint32_t mmu_id) { - for (int i = 0; i < MMU_MAX_ENTRY_NUM; i++) { + for (int i = 0; i < MMU_ENTRY_NUM; i++) { mmu_ll_set_entry_invalid(mmu_id, i); } } diff --git a/components/hal/mmu_hal.c b/components/hal/mmu_hal.c index d3560aa04c..5cfc8d79c1 100644 --- a/components/hal/mmu_hal.c +++ b/components/hal/mmu_hal.c @@ -83,7 +83,7 @@ void mmu_hal_map_region(uint32_t mmu_id, mmu_target_t mem_type, uint32_t vaddr, uint32_t page_size_in_bytes = mmu_hal_pages_to_bytes(mmu_id, 1); HAL_ASSERT(vaddr % page_size_in_bytes == 0); HAL_ASSERT(paddr % page_size_in_bytes == 0); - HAL_ASSERT((paddr + len) <= mmu_hal_pages_to_bytes(mmu_id, MMU_MAX_ENTRY_NUM)); + HAL_ASSERT((paddr + len) <= mmu_hal_pages_to_bytes(mmu_id, MMU_MAX_PADDR_PAGE_NUM)); HAL_ASSERT(mmu_ll_check_valid_ext_vaddr_region(mmu_id, vaddr, len)); uint32_t page_num = (len + page_size_in_bytes - 1) / page_size_in_bytes; diff --git a/components/soc/esp32/include/soc/ext_mem_defs.h b/components/soc/esp32/include/soc/ext_mem_defs.h index a2f6849c8c..abe9eb6c50 100644 --- a/components/soc/esp32/include/soc/ext_mem_defs.h +++ b/components/soc/esp32/include/soc/ext_mem_defs.h @@ -37,12 +37,8 @@ extern "C" { #define ADDRESS_IN_DRAM1_CACHE(vaddr) ADDRESS_IN_BUS(DRAM1_CACHE, vaddr) #define ADDRESS_IN_DROM0_CACHE(vaddr) ADDRESS_IN_BUS(DROM0_CACHE, vaddr) -/** - * Max MMU entry num. - * `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.: - * 256 * 64KB, means MMU can map 16MB at most - */ -#define MMU_MAX_ENTRY_NUM 256 +//MMU entry num +#define MMU_ENTRY_NUM 256 #ifdef __cplusplus } diff --git a/components/soc/esp32c2/include/soc/ext_mem_defs.h b/components/soc/esp32c2/include/soc/ext_mem_defs.h index 535bbfcdc0..4e843972f2 100644 --- a/components/soc/esp32c2/include/soc/ext_mem_defs.h +++ b/components/soc/esp32c2/include/soc/ext_mem_defs.h @@ -42,9 +42,6 @@ extern "C" { #define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE) #define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE) -//IDF-3821 -// #define MMU_SIZE 0x100 - #define CACHE_IBUS 0 #define CACHE_IBUS_MMU_START 0 #define CACHE_IBUS_MMU_END 0x100 @@ -95,16 +92,18 @@ extern "C" { */ #define INVALID_PHY_PAGE 0x7f /** - * Max MMU entry num. - * `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.: - * 64 * 64KB, means MMU can map 4MB at most + * Max MMU available paddr page num. + * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * 64 * 64KB, means MMU can support 4MB paddr at most */ -#define MMU_MAX_ENTRY_NUM 64 +#define MMU_MAX_PADDR_PAGE_NUM 64 /** * This is the mask used for mapping. e.g.: * 0x4200_0000 & MMU_VADDR_MASK */ #define MMU_VADDR_MASK ((0x100000 << (MMU_PAGE_MODE)) - 1) +//MMU entry num +#define MMU_ENTRY_NUM 64 #define BUS_PMS_MASK 0xffffff diff --git a/components/soc/esp32c3/include/soc/ext_mem_defs.h b/components/soc/esp32c3/include/soc/ext_mem_defs.h index e409bbe7a7..ec78bf6d35 100644 --- a/components/soc/esp32c3/include/soc/ext_mem_defs.h +++ b/components/soc/esp32c3/include/soc/ext_mem_defs.h @@ -86,17 +86,18 @@ extern "C" { */ #define INVALID_PHY_PAGE 0xffff /** - * Max MMU entry num. - * `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.: - * 256 * 64KB, means MMU can map 16MB at most + * Max MMU available paddr page num. + * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * 256 * 64KB, means MMU can support 16MB paddr at most */ -#define MMU_MAX_ENTRY_NUM 256 +#define MMU_MAX_PADDR_PAGE_NUM 256 /** * This is the mask used for mapping. e.g.: * 0x4200_0000 & MMU_VADDR_MASK */ #define MMU_VADDR_MASK 0x7FFFFF - +//MMU entry num +#define MMU_ENTRY_NUM 128 #define CACHE_ICACHE_LOW_SHIFT 0 #define CACHE_ICACHE_HIGH_SHIFT 2 diff --git a/components/soc/esp32h2/include/soc/ext_mem_defs.h b/components/soc/esp32h2/include/soc/ext_mem_defs.h index f2eae6a6f7..137b3ee1da 100644 --- a/components/soc/esp32h2/include/soc/ext_mem_defs.h +++ b/components/soc/esp32h2/include/soc/ext_mem_defs.h @@ -86,16 +86,18 @@ extern "C" { */ #define INVALID_PHY_PAGE 0xffff /** - * Max MMU entry num. - * `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.: - * 256 * 64KB, means MMU can map 16MB at most + * Max MMU available paddr page num. + * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * 256 * 64KB, means MMU can support 16MB paddr at most */ -#define MMU_MAX_ENTRY_NUM 256 +#define MMU_MAX_PADDR_PAGE_NUM 256 /** * This is the mask used for mapping. e.g.: * 0x4200_0000 & MMU_VADDR_MASK */ #define MMU_VADDR_MASK 0x7fffff +//MMU entry num +#define MMU_ENTRY_NUM 128 #define CACHE_ICACHE_LOW_SHIFT 0 #define CACHE_ICACHE_HIGH_SHIFT 2 diff --git a/components/soc/esp32s2/include/soc/ext_mem_defs.h b/components/soc/esp32s2/include/soc/ext_mem_defs.h index 3859ba5f7f..39ada481e4 100644 --- a/components/soc/esp32s2/include/soc/ext_mem_defs.h +++ b/components/soc/esp32s2/include/soc/ext_mem_defs.h @@ -111,16 +111,19 @@ extern "C" { */ #define MMU_VALID_VAL_MASK 0x3fff /** - * Max MMU entry num. - * `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.: - * 16384 * 64KB, means MMU can map 1GB at most + * Max MMU available paddr page num. + * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * 16384 * 64KB, means MMU can support 1GB paddr at most */ -#define MMU_MAX_ENTRY_NUM 16384 +#define MMU_MAX_PADDR_PAGE_NUM 16384 /** * This is the mask used for mapping. e.g.: * 0x4200_0000 & MMU_VADDR_MASK */ #define MMU_VADDR_MASK 0x3FFFFF +//MMU entry num +#define MMU_ENTRY_NUM 384 + #define BUS_NUM_MASK 0x3 #define CACHE_MEMORY_BANK_SIZE 8192 diff --git a/components/soc/esp32s3/include/soc/ext_mem_defs.h b/components/soc/esp32s3/include/soc/ext_mem_defs.h index 1a0e90ae8e..1e66716601 100644 --- a/components/soc/esp32s3/include/soc/ext_mem_defs.h +++ b/components/soc/esp32s3/include/soc/ext_mem_defs.h @@ -86,16 +86,18 @@ extern "C" { */ #define INVALID_PHY_PAGE 0xffff /** - * Max MMU entry num. - * `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.: - * 16384 * 64KB, means MMU can map 1GB at most + * Max MMU available paddr page num. + * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * 16384 * 64KB, means MMU can support 1GB paddr at most */ -#define MMU_MAX_ENTRY_NUM 16384 +#define MMU_MAX_PADDR_PAGE_NUM 16384 /** * This is the mask used for mapping. e.g.: * 0x4200_0000 & MMU_VADDR_MASK */ #define MMU_VADDR_MASK 0x1FFFFFF +//MMU entry num +#define MMU_ENTRY_NUM 512 #define CACHE_ICACHE_LOW_SHIFT 0 #define CACHE_ICACHE_HIGH_SHIFT 2 From b748a4fe5eac5486372b0e9b9af58489e4a85225 Mon Sep 17 00:00:00 2001 From: Armando Date: Mon, 25 Apr 2022 21:49:35 +0800 Subject: [PATCH 4/4] mmu: improve vaddr range check --- components/hal/esp32/include/hal/cache_ll.h | 4 ++-- components/hal/esp32s3/include/hal/cache_ll.h | 4 ++-- components/soc/esp32/include/soc/ext_mem_defs.h | 2 +- components/soc/esp32c2/include/soc/ext_mem_defs.h | 2 +- components/soc/esp32c3/include/soc/ext_mem_defs.h | 2 +- components/soc/esp32h2/include/soc/ext_mem_defs.h | 2 +- components/soc/esp32s2/include/soc/ext_mem_defs.h | 2 +- components/soc/esp32s3/include/soc/ext_mem_defs.h | 2 +- 8 files changed, 10 insertions(+), 10 deletions(-) diff --git a/components/hal/esp32/include/hal/cache_ll.h b/components/hal/esp32/include/hal/cache_ll.h index a2e750e006..2241d99779 100644 --- a/components/hal/esp32/include/hal/cache_ll.h +++ b/components/hal/esp32/include/hal/cache_ll.h @@ -49,10 +49,10 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v mask |= (vaddr_end >= IRAM1_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0; mask |= (vaddr_end >= IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0; } else if (vaddr_start >= DRAM1_CACHE_ADDRESS_LOW) { - HAL_ASSERT(vaddr_end < DRAM1_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, see `ext_mem_defs.h` + HAL_ASSERT(vaddr_end <= DRAM1_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, see `ext_mem_defs.h` mask |= CACHE_BUS_DBUS1; } else if (vaddr_start >= DROM0_CACHE_ADDRESS_LOW) { - HAL_ASSERT(vaddr_end < DROM0_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, see `ext_mem_defs.h` + HAL_ASSERT(vaddr_end <= DROM0_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, see `ext_mem_defs.h` mask |= CACHE_BUS_DBUS0; } else { HAL_ASSERT(false); diff --git a/components/hal/esp32s3/include/hal/cache_ll.h b/components/hal/esp32s3/include/hal/cache_ll.h index 45812aaaef..6831b872b9 100644 --- a/components/hal/esp32s3/include/hal/cache_ll.h +++ b/components/hal/esp32s3/include/hal/cache_ll.h @@ -42,9 +42,9 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v cache_bus_mask_t mask = 0; uint32_t vaddr_end = vaddr_start + len; - if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) { + if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end <= IRAM0_CACHE_ADDRESS_HIGH) { mask |= CACHE_BUS_IBUS0; //Both cores have their own IBUS0 - } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH) { + } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end <= DRAM0_CACHE_ADDRESS_HIGH) { mask |= CACHE_BUS_DBUS0; //Both cores have their own DBUS0 } else { HAL_ASSERT(0); //Out of region diff --git a/components/soc/esp32/include/soc/ext_mem_defs.h b/components/soc/esp32/include/soc/ext_mem_defs.h index abe9eb6c50..704e81d28b 100644 --- a/components/soc/esp32/include/soc/ext_mem_defs.h +++ b/components/soc/esp32/include/soc/ext_mem_defs.h @@ -30,7 +30,7 @@ extern "C" { #define DROM0_CACHE_ADDRESS_HIGH 0x3F800000 -#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) +#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH) #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) #define ADDRESS_IN_IRAM1_CACHE(vaddr) ADDRESS_IN_BUS(IRAM1_CACHE, vaddr) #define ADDRESS_IN_IROM0_CACHE(vaddr) ADDRESS_IN_BUS(IROM0_CACHE, vaddr) diff --git a/components/soc/esp32c2/include/soc/ext_mem_defs.h b/components/soc/esp32c2/include/soc/ext_mem_defs.h index 4e843972f2..62612ba96f 100644 --- a/components/soc/esp32c2/include/soc/ext_mem_defs.h +++ b/components/soc/esp32c2/include/soc/ext_mem_defs.h @@ -32,7 +32,7 @@ extern "C" { #define ESP_CACHE_TEMP_ADDR 0x3C000000 #define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) -#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) +#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH) #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) diff --git a/components/soc/esp32c3/include/soc/ext_mem_defs.h b/components/soc/esp32c3/include/soc/ext_mem_defs.h index ec78bf6d35..e75b025c5b 100644 --- a/components/soc/esp32c3/include/soc/ext_mem_defs.h +++ b/components/soc/esp32c3/include/soc/ext_mem_defs.h @@ -27,7 +27,7 @@ extern "C" { #define ESP_CACHE_TEMP_ADDR 0x3C000000 #define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) -#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) +#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH) #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) diff --git a/components/soc/esp32h2/include/soc/ext_mem_defs.h b/components/soc/esp32h2/include/soc/ext_mem_defs.h index 137b3ee1da..77b541d1b6 100644 --- a/components/soc/esp32h2/include/soc/ext_mem_defs.h +++ b/components/soc/esp32h2/include/soc/ext_mem_defs.h @@ -27,7 +27,7 @@ extern "C" { #define ESP_CACHE_TEMP_ADDR 0x3C000000 #define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) -#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) +#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH) #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) diff --git a/components/soc/esp32s2/include/soc/ext_mem_defs.h b/components/soc/esp32s2/include/soc/ext_mem_defs.h index 39ada481e4..06ec81e38c 100644 --- a/components/soc/esp32s2/include/soc/ext_mem_defs.h +++ b/components/soc/esp32s2/include/soc/ext_mem_defs.h @@ -43,7 +43,7 @@ extern "C" { #define DPORT_CACHE_ADDRESS_HIGH 0x3f800000 #define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) -#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) +#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH) #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) diff --git a/components/soc/esp32s3/include/soc/ext_mem_defs.h b/components/soc/esp32s3/include/soc/ext_mem_defs.h index 1e66716601..6c9222f24c 100644 --- a/components/soc/esp32s3/include/soc/ext_mem_defs.h +++ b/components/soc/esp32s3/include/soc/ext_mem_defs.h @@ -26,7 +26,7 @@ extern "C" { #define ESP_CACHE_TEMP_ADDR 0x3C800000 #define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) -#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) +#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH) #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)