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refactor(isp): use hw auto clock control mode for pipelines

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This commit is contained in:
Armando
2025-01-16 11:19:53 +08:00
parent ae85fe9b08
commit 775e4d584c
10 changed files with 66 additions and 67 deletions
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3
components/esp_driver_isp/src/isp_ae.c
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@@ -101,6 +101,7 @@ esp_err_t esp_isp_new_ae_controller(isp_proc_handle_t isp_proc, const esp_isp_ae
ESP_GOTO_ON_ERROR(intr_priority != isp_proc->intr_priority, err2, TAG, "intr_priority error");
ESP_GOTO_ON_ERROR(esp_isp_register_isr(ae_ctlr->isp_proc, ISP_SUBMODULE_AE), err2, TAG, "fail to register ISR");
isp_ll_ae_set_clk_ctrl_mode(isp_proc->hal.hw, ISP_LL_PIPELINE_CLK_CTRL_AUTO);
isp_ll_ae_set_sample_point(isp_proc->hal.hw, ae_config->sample_point);
isp_ll_ae_enable(isp_proc->hal.hw, false);
isp_hal_ae_window_config(&isp_proc->hal, &ae_config->window);
@@ -141,7 +142,6 @@ esp_err_t esp_isp_ae_controller_enable(isp_ae_ctlr_t ae_ctlr)
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&ae_ctlr->fsm, &expected_fsm, ISP_FSM_ENABLE),
ESP_ERR_INVALID_STATE, TAG, "controller not in init state");
isp_ll_ae_clk_enable(ae_ctlr->isp_proc->hal.hw, true);
isp_ll_enable_intr(ae_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_AE_MASK, true);
isp_ll_ae_enable(ae_ctlr->isp_proc->hal.hw, true);
@@ -155,7 +155,6 @@ esp_err_t esp_isp_ae_controller_disable(isp_ae_ctlr_t ae_ctlr)
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&ae_ctlr->fsm, &expected_fsm, ISP_FSM_INIT),
ESP_ERR_INVALID_STATE, TAG, "controller not in enable state");
isp_ll_ae_clk_enable(ae_ctlr->isp_proc->hal.hw, false);
isp_ll_enable_intr(ae_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_AE_MASK, false);
isp_ll_ae_enable(ae_ctlr->isp_proc->hal.hw, false);
esp_intr_disable(ae_ctlr->intr_handle);