From 74e9376022df544dd0680d1ef7b549979716a668 Mon Sep 17 00:00:00 2001
From: Ivan Grokhotkov <ivan@espressif.com>
Date: Thu, 16 Jun 2022 15:28:21 +0200
Subject: [PATCH] esp_system: fix garbled UART output on startup on esp32s2

Closes https://github.com/espressif/esp-idf/issues/9168
---
 components/esp_system/port/soc/esp32s2/clk.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/components/esp_system/port/soc/esp32s2/clk.c b/components/esp_system/port/soc/esp32s2/clk.c
index 68ad39c120..f1eb0bee55 100644
--- a/components/esp_system/port/soc/esp32s2/clk.c
+++ b/components/esp_system/port/soc/esp32s2/clk.c
@@ -71,6 +71,12 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
     soc_reset_reason_t rst_reas = esp_rom_get_reset_reason(0);
     if (rst_reas == RESET_REASON_CHIP_POWER_ON) {
         cfg.cali_ocode = 1;
+        /* Ocode calibration will switch to XTAL frequency, need to wait for UART FIFO
+         * to be empty, to avoid garbled output.
+         */
+        if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
+            esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+        }
     }
     rtc_init(cfg);