From cb6b14a0f8f6d9ec70cab5ac93cd8436c94a5dc0 Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Thu, 18 May 2023 17:17:04 +0800 Subject: [PATCH] doc: Update efuse info files --- docs/docs_not_updated/esp32c6.txt | 3 - docs/docs_not_updated/esp32h2.txt | 4 - .../system/inc/espefuse_summary_ESP32-C2.rst | 142 +++---- .../system/inc/espefuse_summary_ESP32-C3.rst | 288 +++++++------- .../system/inc/espefuse_summary_ESP32-C6.rst | 287 ++++++++------ .../system/inc/espefuse_summary_ESP32-H2.rst | 184 ++++++++- .../system/inc/espefuse_summary_ESP32-S2.rst | 297 +++++++------- .../system/inc/espefuse_summary_ESP32-S3.rst | 327 ++++++++------- .../system/inc/espefuse_summary_ESP32.rst | 155 +++++--- .../system/inc/revisions_ESP32-C6.rst | 12 +- .../system/inc/revisions_ESP32-H2.rst | 14 +- .../system/inc/show-efuse-table_ESP32-C2.rst | 160 +++++--- .../system/inc/show-efuse-table_ESP32-C3.rst | 322 ++++++++------- .../system/inc/show-efuse-table_ESP32-C6.rst | 286 +++++++------- .../system/inc/show-efuse-table_ESP32-H2.rst | 175 +++++++- .../system/inc/show-efuse-table_ESP32-S2.rst | 326 +++++++++------ .../system/inc/show-efuse-table_ESP32-S3.rst | 372 +++++++++++------- .../system/inc/show-efuse-table_ESP32.rst | 163 +++++--- .../system/inc/espefuse_summary_ESP32-H2.rst | 4 +- .../system/inc/revisions_ESP32-H2.rst | 7 +- .../system/inc/show-efuse-table_ESP32-H2.rst | 5 +- 21 files changed, 2162 insertions(+), 1371 deletions(-) diff --git a/docs/docs_not_updated/esp32c6.txt b/docs/docs_not_updated/esp32c6.txt index 0dd3a56037..98aba46483 100644 --- a/docs/docs_not_updated/esp32c6.txt +++ b/docs/docs_not_updated/esp32c6.txt @@ -34,12 +34,9 @@ api-reference/network/esp_wifi api-reference/network/index api-reference/system/ulp_macros api-reference/system/ulp -api-reference/system/efuse api-reference/system/ulp_instruction_set api-reference/system/power_management -api-reference/system/inc/show-efuse-table_ESP32-C6 api-reference/system/inc/power_management_esp32s2_and_later -api-reference/system/inc/espefuse_summary_ESP32-C6 api-reference/system/ulp-risc-v api-reference/bluetooth api-reference/bluetooth/esp_spp diff --git a/docs/docs_not_updated/esp32h2.txt b/docs/docs_not_updated/esp32h2.txt index f7f241b0c0..25c6e62e9f 100644 --- a/docs/docs_not_updated/esp32h2.txt +++ b/docs/docs_not_updated/esp32h2.txt @@ -58,15 +58,11 @@ api-reference/network/esp_smartconfig api-reference/network/esp_wifi api-reference/network/index api-reference/system/sleep_modes -api-reference/system/efuse api-reference/system/chip_revision api-reference/system/esp_timer api-reference/system/system_time api-reference/system/power_management api-reference/system/inc/power_management_esp32 -api-reference/system/inc/espefuse_summary_ESP32-H2 -api-reference/system/inc/revisions_ESP32-H2 -api-reference/system/inc/show-efuse-table_ESP32-H2 api-reference/system/inc/power_management_esp32s2_and_later api-reference/bluetooth/esp_spp api-reference/bluetooth/esp_l2cap_bt diff --git a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C2.rst b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C2.rst index c520cb9e98..a28b334470 100644 --- a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C2.rst +++ b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C2.rst @@ -2,82 +2,88 @@ espefuse.py -p PORT summary - Connecting................... + espefuse.py v4.6-dev + Connecting.... Detecting chip type... ESP32-C2 - espefuse.py v4.1 - + === Run "summary" command === EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) ---------------------------------------------------------------------------------------- - Adc_Calib fuses: - ADC_CALIBRATION_0 (BLOCK2) = 0 R/W (0b0000000000000000000000) - ADC_CALIBRATION_1 (BLOCK2) = 0 R/W (0x00000000) - ADC_CALIBRATION_2 (BLOCK2) = 0 R/W (0x00000000) - + Calibration fuses: + OCODE (BLOCK2) OCode = 78 R/W (0b1001110) + TEMP_CALIB (BLOCK2) Temperature calibration data = -7.4 R/W (0b101001010) + ADC1_INIT_CODE_ATTEN0 (BLOCK2) ADC1 init code at atten0 = 28 R/W (0x07) + ADC1_INIT_CODE_ATTEN3 (BLOCK2) ADC1 init code at atten3 = 0 R/W (0b10000) + ADC1_CAL_VOL_ATTEN0 (BLOCK2) ADC1 calibration voltage at atten0 = -44 R/W (0x8b) + ADC1_CAL_VOL_ATTEN3 (BLOCK2) ADC1 calibration voltage at atten3 = 16 R/W (0b000100) + DIG_DBIAS_HVT (BLOCK2) BLOCK2 digital dbias when hvt = -16 R/W (0b10100) + DIG_LDO_SLP_DBIAS2 (BLOCK2) BLOCK2 DIG_LDO_DBG0_DBIAS2 = -8 R/W (0b1000010) + DIG_LDO_SLP_DBIAS26 (BLOCK2) BLOCK2 DIG_LDO_DBG0_DBIAS26 = 24 R/W (0x06) + DIG_LDO_ACT_DBIAS26 (BLOCK2) BLOCK2 DIG_LDO_ACT_DBIAS26 = 16 R/W (0b000100) + DIG_LDO_ACT_STEPD10 (BLOCK2) BLOCK2 DIG_LDO_ACT_STEPD10 = 12 R/W (0x3) + RTC_LDO_SLP_DBIAS13 (BLOCK2) BLOCK2 DIG_LDO_SLP_DBIAS13 = 88 R/W (0b0010110) + RTC_LDO_SLP_DBIAS29 (BLOCK2) BLOCK2 DIG_LDO_SLP_DBIAS29 = 96 R/W (0b000011000) + RTC_LDO_SLP_DBIAS31 (BLOCK2) BLOCK2 DIG_LDO_SLP_DBIAS31 = 4 R/W (0b000001) + RTC_LDO_ACT_DBIAS31 (BLOCK2) BLOCK2 DIG_LDO_ACT_DBIAS31 = 24 R/W (0b000110) + RTC_LDO_ACT_DBIAS13 (BLOCK2) BLOCK2 DIG_LDO_ACT_DBIAS13 = 72 R/W (0x12) + Config fuses: - UART_PRINT_CONTROL (BLOCK0) Set UART boot message output mode = Force print R/W (0b00) - FORCE_SEND_RESUME (BLOCK0) Force ROM code to send a resume cmd during SPI boo = False R/W (0b0) - t - DIS_DIRECT_BOOT (BLOCK0) Disable direct_boot mode = False R/W (0b0) - - Efuse fuses: - WR_DIS (BLOCK0) Disables programming of individual eFuses = 0 R/W (0x00) - RD_DIS (BLOCK0) Disables software reading from BLOCK3 = 0 R/W (0b00) - - Flash Config fuses: - FLASH_TPUW (BLOCK0) Configures flash startup delay after SoC power-up, = 0 R/W (0x0) - unit is (ms/2). When the value is 15, delay is 7. - 5 ms - + WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00) + RD_DIS (BLOCK0) Disable reading from BlOCK3 = 0 R/W (0b00) + UART_PRINT_CONTROL (BLOCK0) Set the default UARTboot message output mode = Enable R/W (0b00) + DIS_DIRECT_BOOT (BLOCK0) This bit set means disable direct_boot mode = False R/W (0b0) + + Flash fuses: + FORCE_SEND_RESUME (BLOCK0) Set this bit to force ROM code to send a resume co = False R/W (0b0) + mmand during SPI boot + FLASH_TPUW (BLOCK0) Configures flash waiting time after power-up; in u = 0 R/W (0x0) + nit of ms. If the value is less than 15; the waiti + ng time is the configurable value. Otherwise; the + waiting time is twice the configurable value + Identity fuses: - SECURE_VERSION (BLOCK0) Secure version (anti-rollback feature) = 0 R/W (0x0) - CUSTOM_MAC_USED (BLOCK0) Enable CUSTOM_MAC programming = False R/W (0b0) - CUSTOM_MAC (BLOCK1) Custom MAC addr - = 00:00:00:00:00:00 (OK) R/W - MAC (BLOCK2) Factory MAC Address - = 94:b5:55:80:00:d0 (OK) R/W - WAFER_VERSION (BLOCK2) WAFER version = (revision 0) R/W (0b000) - PKG_VERSION (BLOCK2) Package version = ESP32-C2 R/W (0b000) - BLOCK2_VERSION (BLOCK2) Version of BLOCK2 = No calibration R/W (0b000) - - Jtag Config fuses: - DIS_PAD_JTAG (BLOCK0) Permanently disable JTAG access via padsUSB JTAG i = False R/W (0b0) - s controlled separately - - Ldo fuses: - LDO_VOL_BIAS_CONFIG_LOW (BLOCK2) = 0 R/W (0b000) - LDO_VOL_BIAS_CONFIG_HIGH (BLOCK2) = 0 R/W (0b000000000000000000000000000) - - Pvt fuses: - PVT_LOW (BLOCK2) = 0 R/W (0b00000) - PVT_HIGH (BLOCK2) = 0 R/W (0b0000000000) - - Rf fuses: - RF_REF_I_BIAS_CONFIG (BLOCK2) = 0 R/W (0b000) - + DISABLE_WAFER_VERSION_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0) + DISABLE_BLK_VERSION_MAJOR (BLOCK0) Disables check of blk version major = False R/W (0b0) + WAFER_VERSION_MINOR (BLOCK2) WAFER_VERSION_MINOR = 2 R/W (0x2) + WAFER_VERSION_MAJOR (BLOCK2) WAFER_VERSION_MAJOR = 1 R/W (0b01) + PKG_VERSION (BLOCK2) EFUSE_PKG_VERSION = 1 R/W (0b001) + BLK_VERSION_MINOR (BLOCK2) Minor version of BLOCK2 = With calib R/W (0b001) + BLK_VERSION_MAJOR (BLOCK2) Major version of BLOCK2 = 0 R/W (0b00) + + Jtag fuses: + DIS_PAD_JTAG (BLOCK0) Set this bit to disable pad jtag = False R/W (0b0) + + Mac fuses: + CUSTOM_MAC_USED (BLOCK0) True if MAC_CUSTOM is burned = False R/W (0b0) + CUSTOM_MAC (BLOCK1) Custom MAC address + = 00:00:00:00:00:00 (OK) R/W + MAC (BLOCK2) MAC address + = 08:3a:8d:5c:4b:94 (OK) R/W + Security fuses: - DIS_DOWNLOAD_ICACHE (BLOCK0) Disables iCache in download mode = False R/W (0b0) - DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Disables flash encryption in Download boot modes = False R/W (0b0) - SPI_BOOT_CRYPT_CNT (BLOCK0) Enables encryption and decryption, when an SPI boo = Disable R/W (0b000) - t mode is set. Enabled when 1 or 3 bits are set,dis - abled otherwise + DIS_DOWNLOAD_ICACHE (BLOCK0) The bit be set to disable icache in download mode = False R/W (0b0) + DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) The bit be set to disable manual encryption = False R/W (0b0) + SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) + and disables otherwise XTS_KEY_LENGTH_256 (BLOCK0) Flash encryption key length = 128 bits key R/W (0b0) - DIS_DOWNLOAD_MODE (BLOCK0) Disables all Download boot modes = False R/W (0b0) - ENABLE_SECURITY_DOWNLOAD (BLOCK0) Enables secure UART download mode (read/write flas = False R/W (0b0) - h only) - SECURE_BOOT_EN (BLOCK0) Configures secure boot = Flase R/W (0b0) + DIS_DOWNLOAD_MODE (BLOCK0) Set this bit to disable download mode (boot_mode[3 = False R/W (0b0) + :0] = 0; 1; 2; 4; 5; 6; 7) + ENABLE_SECURITY_DOWNLOAD (BLOCK0) Set this bit to enable secure UART download mode = False R/W (0b0) + SECURE_BOOT_EN (BLOCK0) The bit be set to enable secure boot = False R/W (0b0) + SECURE_VERSION (BLOCK0) Secure version for anti-rollback = 0 R/W (0x0) BLOCK_KEY0 (BLOCK3) BLOCK_KEY0 - 256-bits. 256-bit key of Flash Encryp - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - tion + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + tion BLOCK_KEY0_LOW_128 (BLOCK3) BLOCK_KEY0 - lower 128-bits. 128-bit key of Flash - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - Encryption + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Encryption BLOCK_KEY0_HI_128 (BLOCK3) BLOCK_KEY0 - higher 128-bits. 128-bits key of Secu - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - re Boot. - - Wdt Config fuses: - WDT_DELAY_SEL (BLOCK0) RTC WDT timeout threshold = 0 R/W (0b00) + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + re Boot + + Wdt fuses: + WDT_DELAY_SEL (BLOCK0) RTC watchdog timeout threshold; in unit of slow cl = 40000 R/W (0b00) + ock cycle To get a dump for all eFuse registers. @@ -86,15 +92,15 @@ To get a dump for all eFuse registers. espefuse.py -p PORT dump - Connecting.............. + espefuse.py v4.6-dev + Connecting.... Detecting chip type... ESP32-C2 BLOCK0 (BLOCK0 ) [0 ] read_regs: 00000000 00000000 BLOCK1 (BLOCK1 ) [1 ] read_regs: 00000000 00000000 00000000 - BLOCK2 (BLOCK2 ) [2 ] read_regs: 558000d0 000094b5 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK2 (BLOCK2 ) [2 ] read_regs: 8d5c4b94 8252083a 5c01e953 80d0a824 c0860b18 00006890 00000000 4b000000 BLOCK_KEY0 (BLOCK3 ) [3 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 BLOCK0 (BLOCK0 ) [0 ] err__regs: 00000000 00000000 EFUSE_RD_RS_ERR_REG 0x00000000 - espefuse.py v4.1 === Run "dump" command === diff --git a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C3.rst b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C3.rst index dd678f5551..dc7e60e3f5 100644 --- a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C3.rst +++ b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C3.rst @@ -2,139 +2,157 @@ espefuse.py -p PORT summary - Connecting.... + espefuse.py v4.6-dev + Connecting.... Detecting chip type... ESP32-C3 - espefuse.py v3.1-dev - EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) + + === Run "summary" command === + EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) ---------------------------------------------------------------------------------------- + Calibration fuses: + K_RTC_LDO (BLOCK1) BLOCK1 K_RTC_LDO = -36 R/W (0b1001001) + K_DIG_LDO (BLOCK1) BLOCK1 K_DIG_LDO = -64 R/W (0b1010000) + V_RTC_DBIAS20 (BLOCK1) BLOCK1 voltage of rtc dbias20 = -40 R/W (0x8a) + V_DIG_DBIAS20 (BLOCK1) BLOCK1 voltage of digital dbias20 = -76 R/W (0x93) + DIG_DBIAS_HVT (BLOCK1) BLOCK1 digital dbias when hvt = -28 R/W (0b10111) + THRES_HVT (BLOCK1) BLOCK1 pvt threshold when hvt = 2000 R/W (0b0111110100) + TEMP_CALIB (BLOCK2) Temperature calibration data = -7.2 R/W (0b101001000) + OCODE (BLOCK2) ADC OCode = 78 R/W (0x4e) + ADC1_INIT_CODE_ATTEN0 (BLOCK2) ADC1 init code at atten0 = 1560 R/W (0b0110000110) + ADC1_INIT_CODE_ATTEN1 (BLOCK2) ADC1 init code at atten1 = -108 R/W (0b1000011011) + ADC1_INIT_CODE_ATTEN2 (BLOCK2) ADC1 init code at atten2 = -232 R/W (0b1000111010) + ADC1_INIT_CODE_ATTEN3 (BLOCK2) ADC1 init code at atten3 = -696 R/W (0b1010101110) + ADC1_CAL_VOL_ATTEN0 (BLOCK2) ADC1 calibration voltage at atten0 = -212 R/W (0b1000110101) + ADC1_CAL_VOL_ATTEN1 (BLOCK2) ADC1 calibration voltage at atten1 = 52 R/W (0b0000001101) + ADC1_CAL_VOL_ATTEN2 (BLOCK2) ADC1 calibration voltage at atten2 = -152 R/W (0b1000100110) + ADC1_CAL_VOL_ATTEN3 (BLOCK2) ADC1 calibration voltage at atten3 = -284 R/W (0b1001000111) + Config fuses: - DIS_ICACHE (BLOCK0) Disables ICache = False R/W (0b0) - DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0) - DIS_FORCE_DOWNLOAD (BLOCK0) Disables forcing chip into Download mode = False R/W (0b0) - DIS_CAN (BLOCK0) Disables the TWAI Controller hardware = False R/W (0b0) - VDD_SPI_AS_GPIO (BLOCK0) Set this bit to vdd spi pin function as gpio = False R/W (0b0) - BTLC_GPIO_ENABLE (BLOCK0) Enable btlc gpio = 0 R/W (0b00) - POWERGLITCH_EN (BLOCK0) Set this bit to enable power glitch function = False R/W (0b0) - POWER_GLITCH_DSENSE (BLOCK0) Sample delay configuration of power glitch = 0 R/W (0b00) - DIS_DIRECT_BOOT (BLOCK0) Disables direct boot mode = False R/W (0b0) - DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Selects the default UART for printing boot msg = UART0 R/W (0b0) - UART_PRINT_CONTROL (BLOCK0) Sets the default UART boot message output mode = Enabled R/W (0b00) - FORCE_SEND_RESUME (BLOCK0) Force ROM code to send a resume command during SPI = False R/W (0b0) - bootduring SPI boot - BLOCK_USR_DATA (BLOCK3) User data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - - Efuse fuses: - WR_DIS (BLOCK0) Disables programming of individual eFuses = 0 R/W (0x00000000) - RD_DIS (BLOCK0) Disables software reading from BLOCK4-10 = 0 R/W (0b0000000) - - Flash Config fuses: - FLASH_TPUW (BLOCK0) Configures flash startup delay after SoC power-up, = 0 R/W (0x0) - unit is (ms/2). When the value is 15, delay is 7. - 5 ms - FLASH_ECC_MODE (BLOCK0) Set this bit to set flsah ecc mode. - = flash ecc 16to18 byte mode R/W (0b0) - FLASH_TYPE (BLOCK0) Selects SPI flash type = 4 data lines R/W (0b0) - FLASH_PAGE_SIZE (BLOCK0) Flash page size = 0 R/W (0b00) - FLASH_ECC_EN (BLOCK0) Enable ECC for flash boot = False R/W (0b0) - + WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000) + RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000) + DIS_ICACHE (BLOCK0) Set this bit to disable Icache = False R/W (0b0) + DIS_TWAI (BLOCK0) Set this bit to disable CAN function = False R/W (0b0) + DIS_DIRECT_BOOT (BLOCK0) Disable direct boot mode = False R/W (0b0) + UART_PRINT_CONTROL (BLOCK0) Set the default UARTboot message output mode = Enable R/W (0b00) + ERR_RST_ENABLE (BLOCK0) Use BLOCK0 to check error record registers = with check R/W (0b1) + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Flash fuses: + FLASH_TPUW (BLOCK0) Configures flash waiting time after power-up; in u = 0 R/W (0x0) + nit of ms. If the value is less than 15; the waiti + ng time is the configurable value; Otherwise; the + waiting time is twice the configurable value + FORCE_SEND_RESUME (BLOCK0) Set this bit to force ROM code to send a resume co = False R/W (0b0) + mmand during SPI boot + Identity fuses: - SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) - ure) - MAC (BLOCK1) Factory MAC Address - = 7c:df:a1:40:40:08: (OK) R/W - WAFER_VERSION (BLOCK1) WAFER version = (revision 0) R/W (0b000) - PKG_VERSION (BLOCK1) Package version = ESP32-C3 R/W (0x0) - BLOCK1_VERSION (BLOCK1) BLOCK1 efuse version = 0 R/W (0b000) - OPTIONAL_UNIQUE_ID (BLOCK2)(0 errors): Optional unique 128-bit ID - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK2_VERSION (BLOCK2) Version of BLOCK2 = No calibration R/W (0b000) - CUSTOM_MAC (BLOCK3) Custom MAC Address - = 00:00:00:00:00:00 (OK) R/W - - Jtag Config fuses: - JTAG_SEL_ENABLE (BLOCK0) Set this bit to enable selection between usb_to_jt = False R/W (0b0) - ag and pad_to_jtag through strapping gpio10 when b - oth reg_dis_usb_jtag and reg_dis_pad_jtag are equa - l to 0. - SOFT_DIS_JTAG (BLOCK0) Software disables JTAG. When software disabled, JT = 0 R/W (0b000) - AG can be activated temporarily by HMAC peripheral - DIS_PAD_JTAG (BLOCK0) Permanently disable JTAG access via pads. USB JTAG = False R/W (0b0) - is controlled separately. - + DISABLE_WAFER_VERSION_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0) + DISABLE_BLK_VERSION_MAJOR (BLOCK0) Disables check of blk version major = False R/W (0b0) + WAFER_VERSION_MINOR_LO (BLOCK1) WAFER_VERSION_MINOR least significant bits = 3 R/W (0b011) + PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000) + BLK_VERSION_MINOR (BLOCK1) BLK_VERSION_MINOR = 2 R/W (0b010) + WAFER_VERSION_MINOR_HI (BLOCK1) WAFER_VERSION_MINOR most significant bit = False R/W (0b0) + WAFER_VERSION_MAJOR (BLOCK1) WAFER_VERSION_MAJOR = 0 R/W (0b00) + OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID + = 25 60 04 96 c3 fd 41 6f be ed 2c 51 1d e3 7e 21 R/W + BLK_VERSION_MAJOR (BLOCK2) BLK_VERSION_MAJOR of BLOCK2 = With calibration R/W (0b01) + WAFER_VERSION_MINOR (BLOCK0) calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI = 3 R/W (0x3) + << 3 + WAFER_VERSION_MINOR_LO (read only) + + Jtag fuses: + SOFT_DIS_JTAG (BLOCK0) Set these bits to disable JTAG in the soft way (od = 0 R/W (0b000) + d number 1 means disable ). JTAG can be enabled in + HMAC module + DIS_PAD_JTAG (BLOCK0) Set this bit to disable JTAG in the hard way. JTAG = False R/W (0b0) + is disabled permanently + + Mac fuses: + MAC (BLOCK1) MAC address + = 58:cf:79:0f:96:8c (OK) R/W + CUSTOM_MAC (BLOCK3) Custom MAC address + = 00:00:00:00:00:00 (OK) R/W + Security fuses: - DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Disables flash encryption when in download boot mo = False R/W (0b0) - des - SPI_BOOT_CRYPT_CNT (BLOCK0) Enables encryption and decryption, when an SPI boo = Disable R/W (0b000) - t mode is set. Enabled when 1 or 3 bits are set,di - sabled otherwise - SECURE_BOOT_KEY_REVOKE0 (BLOCK0) If set, revokes use of secure boot key digest 0 = False R/W (0b0) - SECURE_BOOT_KEY_REVOKE1 (BLOCK0) If set, revokes use of secure boot key digest 1 = False R/W (0b0) - SECURE_BOOT_KEY_REVOKE2 (BLOCK0) If set, revokes use of secure boot key digest 2 = False R/W (0b0) - KEY_PURPOSE_0 (BLOCK0) KEY0 purpose = USER R/W (0x0) - KEY_PURPOSE_1 (BLOCK0) KEY1 purpose = USER R/W (0x0) - KEY_PURPOSE_2 (BLOCK0) KEY2 purpose = USER R/W (0x0) - KEY_PURPOSE_3 (BLOCK0) KEY3 purpose = USER R/W (0x0) - KEY_PURPOSE_4 (BLOCK0) KEY4 purpose = USER R/W (0x0) - KEY_PURPOSE_5 (BLOCK0) KEY5 purpose = USER R/W (0x0) - SECURE_BOOT_EN (BLOCK0) Enables secure boot = False R/W (0b0) - SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Enables aggressive secure boot key revocation mode = False R/W (0b0) - DIS_DOWNLOAD_MODE (BLOCK0) Disables all Download boot modes = False R/W (0b0) - ENABLE_SECURITY_DOWNLOAD (BLOCK0) Enables secure UART download mode (read/write flas = False R/W (0b0) - h only) - BLOCK_KEY0 (BLOCK4)(0 errors): - Purpose: USER - Encryption key0 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY1 (BLOCK5)(0 errors): - Purpose: USER - Encryption key1 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY2 (BLOCK6)(0 errors): - Purpose: USER - Encryption key2 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY3 (BLOCK7)(0 errors): - Purpose: USER - Encryption key3 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY4 (BLOCK8)(0 errors): - Purpose: USER - Encryption key4 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY5 (BLOCK9)(0 errors): - Purpose: USER - Encryption key5 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_SYS_DATA2 (BLOCK10)(0 errors): System data (part 2) - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - - Spi_Pad_Config fuses: - SPI_PAD_CONFIG_CLK (BLOCK1) SPI CLK pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_Q (BLOCK1) SPI Q (D1) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D (BLOCK1) SPI D (D0) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_CS (BLOCK1) SPI CS pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_HD (BLOCK1) SPI HD (D3) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_WP (BLOCK1) SPI WP (D2) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_DQS (BLOCK1) SPI DQS pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D4 (BLOCK1) SPI D4 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D5 (BLOCK1) SPI D5 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D6 (BLOCK1) SPI D6 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D7 (BLOCK1) SPI D7 pad = 0 R/W (0b000000) - - Usb Config fuses: - DIS_USB_JTAG (BLOCK0) Disables USB JTAG. JTAG access via pads is control = False R/W (0b0) - led separately - DIS_USB_DEVICE (BLOCK0) Disables USB DEVICE = False R/W (0b0) - DIS_USB (BLOCK0) Disables the USB OTG hardware = False R/W (0b0) - USB_EXCHG_PINS (BLOCK0) Exchanges USB D+ and D- pins = False R/W (0b0) - DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Disables download through USB-Serial-JTAG = False R/W (0b0) - - Vdd_Spi Config fuses: - PIN_POWER_SELECTION (BLOCK0) GPIO33-GPIO37 power supply selection in ROM code = VDD3P3_CPU R/W (0b0) - - Wdt Config fuses: - WDT_DELAY_SEL (BLOCK0) Selects RTC WDT timeout threshold at startup = False R/W (0b0) + DIS_DOWNLOAD_ICACHE (BLOCK0) Set this bit to disable Icache in download mode (b = False R/W (0b0) + oot_mode[3:0] is 0; 1; 2; 3; 6; 7) + DIS_FORCE_DOWNLOAD (BLOCK0) Set this bit to disable the function that forces c = False R/W (0b0) + hip into download mode + DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Set this bit to disable flash encryption when in d = False R/W (0b0) + ownload boot modes + SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) + and disables otherwise + SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) + KEY_PURPOSE_0 (BLOCK0) Purpose of Key0 = USER R/W (0x0) + KEY_PURPOSE_1 (BLOCK0) Purpose of Key1 = USER R/W (0x0) + KEY_PURPOSE_2 (BLOCK0) Purpose of Key2 = USER R/W (0x0) + KEY_PURPOSE_3 (BLOCK0) Purpose of Key3 = USER R/W (0x0) + KEY_PURPOSE_4 (BLOCK0) Purpose of Key4 = USER R/W (0x0) + KEY_PURPOSE_5 (BLOCK0) Purpose of Key5 = USER R/W (0x0) + SECURE_BOOT_EN (BLOCK0) Set this bit to enable secure boot = False R/W (0b0) + SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Set this bit to enable revoking aggressive secure = False R/W (0b0) + boot + DIS_DOWNLOAD_MODE (BLOCK0) Set this bit to disable download mode (boot_mode[3 = False R/W (0b0) + :0] = 0; 1; 2; 3; 6; 7) + ENABLE_SECURITY_DOWNLOAD (BLOCK0) Set this bit to enable secure UART download mode = False R/W (0b0) + SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) + ure) + BLOCK_KEY0 (BLOCK4) + Purpose: USER + Key0 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY1 (BLOCK5) + Purpose: USER + Key1 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY2 (BLOCK6) + Purpose: USER + Key2 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY3 (BLOCK7) + Purpose: USER + Key3 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY4 (BLOCK8) + Purpose: USER + Key4 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY5 (BLOCK9) + Purpose: USER + Key5 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Spi Pad fuses: + SPI_PAD_CONFIG_CLK (BLOCK1) SPI PAD CLK = 0 R/W (0b000000) + SPI_PAD_CONFIG_Q (BLOCK1) SPI PAD Q(D1) = 0 R/W (0b000000) + SPI_PAD_CONFIG_D (BLOCK1) SPI PAD D(D0) = 0 R/W (0b000000) + SPI_PAD_CONFIG_CS (BLOCK1) SPI PAD CS = 0 R/W (0b000000) + SPI_PAD_CONFIG_HD (BLOCK1) SPI PAD HD(D3) = 0 R/W (0b000000) + SPI_PAD_CONFIG_WP (BLOCK1) SPI PAD WP(D2) = 0 R/W (0b000000) + SPI_PAD_CONFIG_DQS (BLOCK1) SPI PAD DQS = 0 R/W (0b000000) + SPI_PAD_CONFIG_D4 (BLOCK1) SPI PAD D4 = 0 R/W (0b000000) + SPI_PAD_CONFIG_D5 (BLOCK1) SPI PAD D5 = 0 R/W (0b000000) + SPI_PAD_CONFIG_D6 (BLOCK1) SPI PAD D6 = 0 R/W (0b000000) + SPI_PAD_CONFIG_D7 (BLOCK1) SPI PAD D7 = 0 R/W (0b000000) + + Usb fuses: + DIS_USB_JTAG (BLOCK0) Set this bit to disable function of usb switch to = False R/W (0b0) + jtag in module of usb device + DIS_USB_SERIAL_JTAG (BLOCK0) USB-Serial-JTAG = Enable R/W (0b0) + USB_EXCHG_PINS (BLOCK0) Set this bit to exchange USB D+ and D- pins = False R/W (0b0) + DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) USB printing = Enable R/W (0b0) + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Disable UART download mode through USB-Serial-JTAG = False R/W (0b0) + + Vdd fuses: + VDD_SPI_AS_GPIO (BLOCK0) Set this bit to vdd spi pin function as gpio = False R/W (0b0) + + Wdt fuses: + WDT_DELAY_SEL (BLOCK0) RTC watchdog timeout threshold; in unit of slow cl = 40000 R/W (0b00) + ock cycle To get a dump for all eFuse registers. @@ -143,11 +161,12 @@ To get a dump for all eFuse registers. espefuse.py -p PORT dump + espefuse.py v4.6-dev Connecting.... Detecting chip type... ESP32-C3 - BLOCK0 ( ) [0 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 - MAC_SPI_8M_0 (BLOCK1 ) [1 ] read_regs: a1404008 00007cdf 00000000 00000000 00000000 00000000 - BLOCK_SYS_DATA (BLOCK2 ) [2 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK0 ( ) [0 ] read_regs: 00000000 00000000 00000000 00000000 80000000 00000000 + MAC_SPI_8M_0 (BLOCK1 ) [1 ] read_regs: 790f968c 000058cf 00000000 020c0000 715424e0 0047d2f2 + BLOCK_SYS_DATA (BLOCK2 ) [2 ] read_regs: 96046025 6f41fdc3 512cedbe 217ee31d d864ea41 5aba3a86 1e260363 00000009 BLOCK_USR_DATA (BLOCK3 ) [3 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 BLOCK_KEY0 (BLOCK4 ) [4 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 BLOCK_KEY1 (BLOCK5 ) [5 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 @@ -156,4 +175,9 @@ To get a dump for all eFuse registers. BLOCK_KEY4 (BLOCK8 ) [8 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 BLOCK_KEY5 (BLOCK9 ) [9 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 BLOCK_SYS_DATA2 (BLOCK10 ) [10] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 - espefuse.py v3.1-dev + + BLOCK0 ( ) [0 ] err__regs: 00000000 00000000 00000000 00000000 00000000 00000000 + EFUSE_RD_RS_ERR0_REG 0x00000000 + EFUSE_RD_RS_ERR1_REG 0x00000000 + + === Run "dump" command === diff --git a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C6.rst b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C6.rst index eae9d3c08e..2bbe02776c 100644 --- a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C6.rst +++ b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C6.rst @@ -2,150 +2,183 @@ espefuse.py -p PORT summary + espefuse.py v4.6-dev Connecting.... Detecting chip type... ESP32-C6 - + === Run "summary" command === EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) ---------------------------------------------------------------------------------------- Config fuses: - DIS_ICACHE (BLOCK0) Disables ICache = False R/W (0b0) - DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0) - DIS_FORCE_DOWNLOAD (BLOCK0) Disables forcing chip into Download mode = False R/W (0b0) - DIS_SPI_DOWNLOAD_MSPI (BLOCK0) SPI0 controller is disabled in boot_mode_download = False R/W (0b0) - DIS_CAN (BLOCK0) Disables the TWAI Controller hardware = False R/W (0b0) - VDD_SPI_AS_GPIO (BLOCK0) Set this bit to vdd spi pin function as gpio = False R/W (0b0) - BTLC_GPIO_ENABLE (BLOCK0) Enable btlc gpio = 0 R/W (0b00) - POWERGLITCH_EN (BLOCK0) Set this bit to enable power glitch function = False R/W (0b0) - POWER_GLITCH_DSENSE (BLOCK0) Sample delay configuration of power glitch = 0 R/W (0b00) - DIS_DIRECT_BOOT (BLOCK0) Disables direct boot mode = False R/W (0b0) - UART_PRINT_CHANNEL (BLOCK0) Selects the default UART for printing boot msg = UART0 R/W (0b0) - UART_PRINT_CONTROL (BLOCK0) Sets the default UART boot message output mode = Enabled R/W (0b00) - FORCE_SEND_RESUME (BLOCK0) Force ROM code to send a resume command during SPI = False R/W (0b0) - bootduring SPI boot + WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000) + RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000) + SWAP_UART_SDIO_EN (BLOCK0) Represents whether pad of uart and sdio is swapped = False R/W (0b0) + or not. 1: swapped. 0: not swapped + DIS_ICACHE (BLOCK0) Represents whether icache is disabled or enabled. = False R/W (0b0) + 1: disabled. 0: enabled + DIS_TWAI (BLOCK0) Represents whether TWAI function is disabled or en = False R/W (0b0) + abled. 1: disabled. 0: enabled + DIS_DIRECT_BOOT (BLOCK0) Represents whether direct boot mode is disabled or = False R/W (0b0) + enabled. 1: disabled. 0: enabled + UART_PRINT_CONTROL (BLOCK0) Set the default UARTboot message output mode = Enable R/W (0b00) + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Flash fuses: + FLASH_TPUW (BLOCK0) Represents the flash waiting time after power-up; = 0 R/W (0x0) + in unit of ms. When the value less than 15; the wa + iting time is the programmed value. Otherwise; the + waiting time is 2 times the programmed value + FORCE_SEND_RESUME (BLOCK0) Represents whether ROM code is forced to send a re = False R/W (0b0) + sume command during SPI boot. 1: forced. 0:not for + ced + FLASH_CAP (BLOCK1) = 0 R/W (0b000) + FLASH_TEMP (BLOCK1) = 0 R/W (0b00) + FLASH_VENDOR (BLOCK1) = 0 R/W (0b000) + + Identity fuses: DISABLE_WAFER_VERSION_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0) DISABLE_BLK_VERSION_MAJOR (BLOCK0) Disables check of blk version major = False R/W (0b0) - BLOCK_USR_DATA (BLOCK3) User data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - - Efuse fuses: - WR_DIS (BLOCK0) Disables programming of individual eFuses = 0 R/W (0x00000000) - RD_DIS (BLOCK0) Disables software reading from BLOCK4-10 = 0 R/W (0b0000000) - - Flash Config fuses: - FLASH_TPUW (BLOCK0) Configures flash startup delay after SoC power-up, = 0 R/W (0x0) - unit is (ms/2). When the value is 15, delay is 7. - 5 ms - FLASH_ECC_MODE (BLOCK0) Set this bit to set flsah ecc mode. - = flash ecc 16to18 byte mode R/W (0b0) - FLASH_TYPE (BLOCK0) Selects SPI flash type = 4 data lines R/W (0b0) - FLASH_PAGE_SIZE (BLOCK0) Flash page size = 0 R/W (0b00) - FLASH_ECC_EN (BLOCK0) Enable ECC for flash boot = False R/W (0b0) - - Identity fuses: - SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) - ure) - MAC (BLOCK1) Factory MAC Address - = 60:55:f9:f6:03:24 (OK) R/W - WAFER_VERSION_MINOR_LO (BLOCK1) WAFER_VERSION_MINOR least significant bits = 0 R/W (0b000) - PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000) - BLK_VERSION_MINOR (BLOCK1) BLOCK version minor = 0 R/W (0b000) - WAFER_VERSION_MINOR_HI (BLOCK1) WAFER_VERSION_MINOR most significant bits = 0 R/W (0b0) - WAFER_VERSION_MAJOR (BLOCK1) WAFER_VERSION_MAJOR = 0 R/W (0b00) + WAFER_VERSION_MINOR (BLOCK1) = 1 R/W (0x1) + WAFER_VERSION_MAJOR (BLOCK1) = 0 R/W (0b00) + PKG_VERSION (BLOCK1) Package version = 1 R/W (0b001) + BLK_VERSION_MINOR (BLOCK1) BLK_VERSION_MINOR of BLOCK2 = 0 R/W (0b000) + BLK_VERSION_MAJOR (BLOCK1) BLK_VERSION_MAJOR of BLOCK2 = 0 R/W (0b00) OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLK_VERSION_MAJOR (BLOCK2) BLOCK version major = No calibration R/W (0b00) - CUSTOM_MAC (BLOCK3) Custom MAC Address - = 00:00:00:00:00:00 (OK) R/W - WAFER_VERSION_MINOR (BLOCK0) calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI = 0 R/W (0x0) - << 3 + WAFER_VERSION_MINOR_LO (read only) - - Jtag Config fuses: - JTAG_SEL_ENABLE (BLOCK0) Set this bit to enable selection between usb_to_jt = False R/W (0b0) - ag and pad_to_jtag through strapping gpio10 when b - oth reg_dis_usb_jtag and reg_dis_pad_jtag are equa - l to 0. - SOFT_DIS_JTAG (BLOCK0) Software disables JTAG. When software disabled, JT = 0 R/W (0b000) - AG can be activated temporarily by HMAC peripheral - DIS_PAD_JTAG (BLOCK0) Permanently disable JTAG access via pads. USB JTAG = False R/W (0b0) - is controlled separately. - + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Jtag fuses: + JTAG_SEL_ENABLE (BLOCK0) Represents whether the selection between usb_to_jt = False R/W (0b0) + ag and pad_to_jtag through strapping gpio15 when b + oth EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are + equal to 0 is enabled or disabled. 1: enabled. 0: + disabled + SOFT_DIS_JTAG (BLOCK0) Represents whether JTAG is disabled in soft way. O = 0 R/W (0b000) + dd number: disabled. Even number: enabled + DIS_PAD_JTAG (BLOCK0) Represents whether JTAG is disabled in the hard wa = False R/W (0b0) + y(permanently). 1: disabled. 0: enabled + + Mac fuses: + MAC (BLOCK1) MAC address + = 60:55:f9:f7:52:9c (OK) R/W + MAC_EXT (BLOCK1) Stores the extended bits of MAC address = 00:00 (OK) R/W + CUSTOM_MAC (BLOCK3) Custom MAC + = 00:00:00:00:00:00 (OK) R/W + Security fuses: - DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Disables flash encryption when in download boot mo = False R/W (0b0) - des - SPI_BOOT_CRYPT_CNT (BLOCK0) Enables encryption and decryption, when an SPI boo = Disable R/W (0b000) - t mode is set. Enabled when 1 or 3 bits are set,di - sabled otherwise - SECURE_BOOT_KEY_REVOKE0 (BLOCK0) If set, revokes use of secure boot key digest 0 = False R/W (0b0) - SECURE_BOOT_KEY_REVOKE1 (BLOCK0) If set, revokes use of secure boot key digest 1 = False R/W (0b0) - SECURE_BOOT_KEY_REVOKE2 (BLOCK0) If set, revokes use of secure boot key digest 2 = False R/W (0b0) - KEY_PURPOSE_0 (BLOCK0) KEY0 purpose = USER R/W (0x0) - KEY_PURPOSE_1 (BLOCK0) KEY1 purpose = USER R/W (0x0) - KEY_PURPOSE_2 (BLOCK0) KEY2 purpose = USER R/W (0x0) - KEY_PURPOSE_3 (BLOCK0) KEY3 purpose = USER R/W (0x0) - KEY_PURPOSE_4 (BLOCK0) KEY4 purpose = USER R/W (0x0) - KEY_PURPOSE_5 (BLOCK0) KEY5 purpose = USER R/W (0x0) - SECURE_BOOT_EN (BLOCK0) Enables secure boot = False R/W (0b0) - SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Enables aggressive secure boot key revocation mode = False R/W (0b0) - DIS_DOWNLOAD_MODE (BLOCK0) Disables all Download boot modes = False R/W (0b0) - ENABLE_SECURITY_DOWNLOAD (BLOCK0) Enables secure UART download mode (read/write flas = False R/W (0b0) - h only) - SECURE_BOOT_DISABLE_FAST_WAKE (BLOCK0) FAST VERIFY ON WAKE is disabled or enabled when = False R/W (0b0) - Secure Boot is enabled - SEC_DPA_LEVEL (BLOCK0) Configures the clock random divide mode to = 0 R/W (0b00) - determine the DPA security level - CRYPT_DPA_ENABLE (BLOCK0) Defense against DPA attack is enabled = True R/W (0b1) + DIS_DOWNLOAD_ICACHE (BLOCK0) Represents whether icache is disabled or enabled i = False R/W (0b0) + n Download mode. 1: disabled. 0: enabled + DIS_FORCE_DOWNLOAD (BLOCK0) Represents whether the function that forces chip i = False R/W (0b0) + nto download mode is disabled or enabled. 1: disab + led. 0: enabled + SPI_DOWNLOAD_MSPI_DIS (BLOCK0) Represents whether SPI0 controller during boot_mod = False R/W (0b0) + e_download is disabled or enabled. 1: disabled. 0: + enabled + DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Represents whether flash encrypt function is disab = False R/W (0b0) + led or enabled(except in SPI boot mode). 1: disabl + ed. 0: enabled + SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) + and disables otherwise + SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) + KEY_PURPOSE_0 (BLOCK0) Represents the purpose of Key0 = USER R/W (0x0) + KEY_PURPOSE_1 (BLOCK0) Represents the purpose of Key1 = USER R/W (0x0) + KEY_PURPOSE_2 (BLOCK0) Represents the purpose of Key2 = USER R/W (0x0) + KEY_PURPOSE_3 (BLOCK0) Represents the purpose of Key3 = USER R/W (0x0) + KEY_PURPOSE_4 (BLOCK0) Represents the purpose of Key4 = USER R/W (0x0) + KEY_PURPOSE_5 (BLOCK0) Represents the purpose of Key5 = USER R/W (0x0) + SEC_DPA_LEVEL (BLOCK0) Represents the spa secure level by configuring the = 0 R/W (0b00) + clock random divide mode + CRYPT_DPA_ENABLE (BLOCK0) Represents whether anti-dpa attack is enabled. 1:e = False R/W (0b0) + nabled. 0: disabled + SECURE_BOOT_EN (BLOCK0) Represents whether secure boot is enabled or disab = False R/W (0b0) + led. 1: enabled. 0: disabled + SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Represents whether revoking aggressive secure boot = False R/W (0b0) + is enabled or disabled. 1: enabled. 0: disabled + DIS_DOWNLOAD_MODE (BLOCK0) Represents whether Download mode is disabled or en = False R/W (0b0) + abled. 1: disabled. 0: enabled + ENABLE_SECURITY_DOWNLOAD (BLOCK0) Represents whether security download is enabled or = False R/W (0b0) + disabled. 1: enabled. 0: disabled + SECURE_VERSION (BLOCK0) Represents the version used by ESP-IDF anti-rollba = 0 R/W (0x0000) + ck feature + SECURE_BOOT_DISABLE_FAST_WAKE (BLOCK0) Represents whether FAST VERIFY ON WAKE is disabled = False R/W (0b0) + or enabled when Secure Boot is enabled. 1: disabl + ed. 0: enabled BLOCK_KEY0 (BLOCK4) - Purpose: USER - Encryption key0 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Purpose: USER + Key0 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY1 (BLOCK5) - Purpose: USER - Encryption key1 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Purpose: USER + Key1 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY2 (BLOCK6) - Purpose: USER - Encryption key2 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Purpose: USER + Key2 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY3 (BLOCK7) - Purpose: USER - Encryption key3 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Purpose: USER + Key3 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY4 (BLOCK8) - Purpose: USER - Encryption key4 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Purpose: USER + Key4 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY5 (BLOCK9) - Purpose: USER - Encryption key5 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_SYS_DATA2 (BLOCK10) System data (part 2) - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Purpose: USER + Key5 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Usb fuses: + DIS_USB_JTAG (BLOCK0) Represents whether the function of usb switch to j = False R/W (0b0) + tag is disabled or enabled. 1: disabled. 0: enable + d + DIS_USB_SERIAL_JTAG (BLOCK0) Represents whether USB-Serial-JTAG is disabled or = False R/W (0b0) + enabled. 1: disabled. 0: enabled + USB_EXCHG_PINS (BLOCK0) Represents whether the D+ and D- pins is exchanged = False R/W (0b0) + . 1: exchanged. 0: not exchanged + DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Represents whether print from USB-Serial-JTAG is d = False R/W (0b0) + isabled or enabled. 1: disabled. 0: enabled + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Represents whether the USB-Serial-JTAG download fu = False R/W (0b0) + nction is disabled or enabled. 1: disabled. 0: ena + bled + + Vdd fuses: + VDD_SPI_AS_GPIO (BLOCK0) Represents whether vdd spi pin is functioned as gp = False R/W (0b0) + io. 1: functioned. 0: not functioned + + Wdt fuses: + WDT_DELAY_SEL (BLOCK0) Represents whether RTC watchdog timeout threshold = 0 R/W (0b00) + is selected at startup. 1: selected. 0: not select + ed - Spi_Pad_Config fuses: - SPI_PAD_CONFIG_CLK (BLOCK1) SPI CLK pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_Q (BLOCK1) SPI Q (D1) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D (BLOCK1) SPI D (D0) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_CS (BLOCK1) SPI CS pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_HD (BLOCK1) SPI HD (D3) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_WP (BLOCK1) SPI WP (D2) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_DQS (BLOCK1) SPI DQS pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D4 (BLOCK1) SPI D4 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D5 (BLOCK1) SPI D5 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D6 (BLOCK1) SPI D6 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D7 (BLOCK1) SPI D7 pad = 0 R/W (0b000000) - Usb Config fuses: - DIS_USB_JTAG (BLOCK0) Disables USB JTAG. JTAG access via pads is control = False R/W (0b0) - led separately - DIS_USB_DEVICE (BLOCK0) Disables USB DEVICE = False R/W (0b0) - DIS_USB (BLOCK0) Disables the USB OTG hardware = False R/W (0b0) - USB_EXCHG_PINS (BLOCK0) Exchanges USB D+ and D- pins = False R/W (0b0) - DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) USB-Serial-JTAG during ROM boot is disabled = False R/W (0b0) - DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) USB-Serial-JTAG download function is disabled = False R/W (0b0) +To get a dump for all eFuse registers. - Vdd_Spi Config fuses: - PIN_POWER_SELECTION (BLOCK0) GPIO33-GPIO37 power supply selection in ROM code = VDD3P3_CPU R/W (0b0) +.. code-block:: none - Wdt Config fuses: - WDT_DELAY_SEL (BLOCK0) Selects RTC WDT timeout threshold at startup = False R/W (0b0) + espefuse.py -p PORT dump + + espefuse.py v4.6-dev + Connecting.... + Detecting chip type... ESP32-C6 + BLOCK0 ( ) [0 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 + MAC_SPI_8M_0 (BLOCK1 ) [1 ] read_regs: f9f7529c 00006055 00000000 01040000 00000000 00000000 + BLOCK_SYS_DATA (BLOCK2 ) [2 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_USR_DATA (BLOCK3 ) [3 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_KEY0 (BLOCK4 ) [4 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_KEY1 (BLOCK5 ) [5 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_KEY2 (BLOCK6 ) [6 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_KEY3 (BLOCK7 ) [7 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_KEY4 (BLOCK8 ) [8 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_KEY5 (BLOCK9 ) [9 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_SYS_DATA2 (BLOCK10 ) [10] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + + BLOCK0 ( ) [0 ] err__regs: 00000000 00000000 00000000 00000000 00000000 00000000 + EFUSE_RD_RS_ERR0_REG 0x00000000 + EFUSE_RD_RS_ERR1_REG 0x00000000 + + === Run "dump" command === diff --git a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-H2.rst b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-H2.rst index e5a43ee310..42c24c6d27 100644 --- a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-H2.rst +++ b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-H2.rst @@ -1,3 +1,185 @@ .. code-block:: none - TO BE UPDATED + espefuse.py -p PORT summary + + espefuse.py v4.6-dev + Connecting.... + Detecting chip type... ESP32-H2 + + === Run "summary" command === + EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) + ---------------------------------------------------------------------------------------- + Config fuses: + WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000) + RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000) + DIS_ICACHE (BLOCK0) Represents whether icache is disabled or enabled. = False R/W (0b0) + 1: disabled. 0: enabled + POWERGLITCH_EN (BLOCK0) Represents whether power glitch function is enable = False R/W (0b0) + d. 1: enabled. 0: disabled + DIS_TWAI (BLOCK0) Represents whether TWAI function is disabled or en = False R/W (0b0) + abled. 1: disabled. 0: enabled + DIS_DIRECT_BOOT (BLOCK0) Represents whether direct boot mode is disabled or = False R/W (0b0) + enabled. 1: disabled. 0: enabled + UART_PRINT_CONTROL (BLOCK0) Set the default UARTboot message output mode = Enable R/W (0b00) + HYS_EN_PAD0 (BLOCK0) Set bits to enable hysteresis function of PAD0~5 = 0 R/W (0b000000) + HYS_EN_PAD1 (BLOCK0) Set bits to enable hysteresis function of PAD6~27 = 0 R/W (0b0000000000000000000000) + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Flash fuses: + FLASH_TPUW (BLOCK0) Represents the flash waiting time after power-up; = 0 R/W (0x0) + in unit of ms. When the value less than 15; the wa + iting time is the programmed value. Otherwise; the + waiting time is 2 times the programmed value + FORCE_SEND_RESUME (BLOCK0) Represents whether ROM code is forced to send a re = False R/W (0b0) + sume command during SPI boot. 1: forced. 0:not for + ced + FLASH_CAP (BLOCK1) = 0 R/W (0b000) + FLASH_TEMP (BLOCK1) = 0 R/W (0b00) + FLASH_VENDOR (BLOCK1) = 0 R/W (0b000) + + Identity fuses: + WAFER_VERSION_MINOR (BLOCK1) = 0 R/W (0b000) + WAFER_VERSION_MAJOR (BLOCK1) = 0 R/W (0b00) + DISABLE_WAFER_VERSION_MAJOR (BLOCK1) Disables check of wafer version major = False R/W (0b0) + PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000) + OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLK_VERSION_MINOR (BLOCK2) BLK_VERSION_MINOR of BLOCK2 = 0 R/W (0b000) + BLK_VERSION_MAJOR (BLOCK2) BLK_VERSION_MAJOR of BLOCK2 = 0 R/W (0b00) + DISABLE_BLK_VERSION_MAJOR (BLOCK2) Disables check of blk version major = False R/W (0b0) + + Jtag fuses: + JTAG_SEL_ENABLE (BLOCK0) Set this bit to enable selection between usb_to_jt = False R/W (0b0) + ag and pad_to_jtag through strapping gpio25 when b + oth EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are + equal to 0 + SOFT_DIS_JTAG (BLOCK0) Represents whether JTAG is disabled in soft way. O = 0 R/W (0b000) + dd number: disabled. Even number: enabled + DIS_PAD_JTAG (BLOCK0) Represents whether JTAG is disabled in the hard wa = False R/W (0b0) + y(permanently). 1: disabled. 0: enabled + + Mac fuses: + MAC (BLOCK1) MAC address + = 60:55:f9:f7:2c:a2:ff:fe (OK) R/W + MAC_EXT (BLOCK1) Stores the extended bits of MAC address = ff:fe (OK) R/W + CUSTOM_MAC (BLOCK3) Custom MAC + = 00:00:00:00:00:00:ff:fe (OK) R/W + + Security fuses: + DIS_FORCE_DOWNLOAD (BLOCK0) Represents whether the function that forces chip i = False R/W (0b0) + nto download mode is disabled or enabled. 1: disab + led. 0: enabled + SPI_DOWNLOAD_MSPI_DIS (BLOCK0) Represents whether SPI0 controller during boot_mod = False R/W (0b0) + e_download is disabled or enabled. 1: disabled. 0: + enabled + DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Represents whether flash encrypt function is disab = False R/W (0b0) + led or enabled(except in SPI boot mode). 1: disabl + ed. 0: enabled + SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) + and disables otherwise + SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) + KEY_PURPOSE_0 (BLOCK0) Represents the purpose of Key0 = USER R/W (0x0) + KEY_PURPOSE_1 (BLOCK0) Represents the purpose of Key1 = USER R/W (0x0) + KEY_PURPOSE_2 (BLOCK0) Represents the purpose of Key2 = USER R/W (0x0) + KEY_PURPOSE_3 (BLOCK0) Represents the purpose of Key3 = USER R/W (0x0) + KEY_PURPOSE_4 (BLOCK0) Represents the purpose of Key4 = USER R/W (0x0) + KEY_PURPOSE_5 (BLOCK0) Represents the purpose of Key5 = USER R/W (0x0) + SEC_DPA_LEVEL (BLOCK0) Represents the spa secure level by configuring the = 0 R/W (0b00) + clock random divide mode + ECDSA_FORCE_USE_HARDWARE_K (BLOCK0) Represents whether hardware random number k is for = False R/W (0b0) + ced used in ESDCA. 1: force used. 0: not force use + d + CRYPT_DPA_ENABLE (BLOCK0) Represents whether anti-dpa attack is enabled. 1:e = False R/W (0b0) + nabled. 0: disabled + SECURE_BOOT_EN (BLOCK0) Represents whether secure boot is enabled or disab = False R/W (0b0) + led. 1: enabled. 0: disabled + SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Represents whether revoking aggressive secure boot = False R/W (0b0) + is enabled or disabled. 1: enabled. 0: disabled + DIS_DOWNLOAD_MODE (BLOCK0) Represents whether Download mode is disabled or en = False R/W (0b0) + abled. 1: disabled. 0: enabled + ENABLE_SECURITY_DOWNLOAD (BLOCK0) Represents whether security download is enabled or = False R/W (0b0) + disabled. 1: enabled. 0: disabled + SECURE_VERSION (BLOCK0) Represents the version used by ESP-IDF anti-rollba = 0 R/W (0x0000) + ck feature + SECURE_BOOT_DISABLE_FAST_WAKE (BLOCK0) Represents whether FAST VERIFY ON WAKE is disabled = False R/W (0b0) + or enabled when Secure Boot is enabled. 1: disabl + ed. 0: enabled + BLOCK_KEY0 (BLOCK4) + Purpose: USER + Key0 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY1 (BLOCK5) + Purpose: USER + Key1 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY2 (BLOCK6) + Purpose: USER + Key2 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY3 (BLOCK7) + Purpose: USER + Key3 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY4 (BLOCK8) + Purpose: USER + Key4 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY5 (BLOCK9) + Purpose: USER + Key5 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Usb fuses: + DIS_USB_JTAG (BLOCK0) Represents whether the function of usb switch to j = False R/W (0b0) + tag is disabled or enabled. 1: disabled. 0: enable + d + USB_EXCHG_PINS (BLOCK0) Represents whether the D+ and D- pins is exchanged = False R/W (0b0) + . 1: exchanged. 0: not exchanged + DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Set this bit to disable USB-Serial-JTAG print duri = False R/W (0b0) + ng rom boot + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Represents whether the USB-Serial-JTAG download fu = False R/W (0b0) + nction is disabled or enabled. 1: disabled. 0: ena + bled + + Vdd fuses: + VDD_SPI_AS_GPIO (BLOCK0) Represents whether vdd spi pin is functioned as gp = False R/W (0b0) + io. 1: functioned. 0: not functioned + + Wdt fuses: + WDT_DELAY_SEL (BLOCK0) Represents whether RTC watchdog timeout threshold = 0 R/W (0b00) + is selected at startup. 1: selected. 0: not select + ed + + +To get a dump for all eFuse registers. + +.. code-block:: none + + espefuse.py -p PORT dump + + espefuse.py dump + espefuse.py v4.6-dev + Connecting.... + Detecting chip type... ESP32-H2 + BLOCK0 ( ) [0 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 + MAC_SPI_8M_0 (BLOCK1 ) [1 ] read_regs: f9f72ca2 fffe6055 00000000 00000000 00000000 00000000 + BLOCK_SYS_DATA (BLOCK2 ) [2 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_USR_DATA (BLOCK3 ) [3 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_KEY0 (BLOCK4 ) [4 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_KEY1 (BLOCK5 ) [5 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_KEY2 (BLOCK6 ) [6 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_KEY3 (BLOCK7 ) [7 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_KEY4 (BLOCK8 ) [8 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_KEY5 (BLOCK9 ) [9 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_SYS_DATA2 (BLOCK10 ) [10] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + + BLOCK0 ( ) [0 ] err__regs: 00000000 00000000 00000000 00000000 00000000 00000000 + EFUSE_RD_RS_ERR0_REG 0x00000000 + EFUSE_RD_RS_ERR1_REG 0x00000000 + + === Run "dump" command === diff --git a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S2.rst b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S2.rst index ab6a8d4f10..ae7c134ea5 100644 --- a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S2.rst +++ b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S2.rst @@ -2,167 +2,171 @@ espefuse.py -p PORT summary + espefuse.py v4.6-dev Connecting.... + Detecting chip type... Unsupported detection protocol, switching and trying again... Detecting chip type... ESP32-S2 - espefuse.py v3.1-dev - EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) + + === Run "summary" command === + EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) ---------------------------------------------------------------------------------------- - Calibration fuses: - TEMP_SENSOR_CAL (BLOCK2) Temperature calibration = -9.200000000000001 R/W (0b101011100) - ADC1_MODE0_D2 (BLOCK2) ADC1 calibration 1 = -28 R/W (0x87) - ADC1_MODE1_D2 (BLOCK2) ADC1 calibration 2 = -28 R/W (0x87) - ADC1_MODE2_D2 (BLOCK2) ADC1 calibration 3 = -28 R/W (0x87) - ADC1_MODE3_D2 (BLOCK2) ADC1 calibration 4 = -24 R/W (0x86) - ADC2_MODE0_D2 (BLOCK2) ADC2 calibration 5 = 12 R/W (0x03) - ADC2_MODE1_D2 (BLOCK2) ADC2 calibration 6 = 8 R/W (0x02) - ADC2_MODE2_D2 (BLOCK2) ADC2 calibration 7 = 12 R/W (0x03) - ADC2_MODE3_D2 (BLOCK2) ADC2 calibration 8 = 16 R/W (0x04) - ADC1_MODE0_D1 (BLOCK2) ADC1 calibration 9 = -20 R/W (0b100101) - ADC1_MODE1_D1 (BLOCK2) ADC1 calibration 10 = -12 R/W (0b100011) - ADC1_MODE2_D1 (BLOCK2) ADC1 calibration 11 = -12 R/W (0b100011) - ADC1_MODE3_D1 (BLOCK2) ADC1 calibration 12 = -4 R/W (0b100001) - ADC2_MODE0_D1 (BLOCK2) ADC2 calibration 13 = -12 R/W (0b100011) - ADC2_MODE1_D1 (BLOCK2) ADC2 calibration 14 = -8 R/W (0b100010) - ADC2_MODE2_D1 (BLOCK2) ADC2 calibration 15 = -8 R/W (0b100010) - ADC2_MODE3_D1 (BLOCK2) ADC2 calibration 16 = -4 R/W (0b100001) - Config fuses: - DIS_RTC_RAM_BOOT (BLOCK0) Disables boot from RTC RAM = False R/W (0b0) - DIS_ICACHE (BLOCK0) Disables ICache = False R/W (0b0) - DIS_DCACHE (BLOCK0) Disables DCache = False R/W (0b0) - DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0) - DIS_DOWNLOAD_DCACHE (BLOCK0) Disables Dcache when SoC is in Download mode = False R/W (0b0) - DIS_FORCE_DOWNLOAD (BLOCK0) Disables forcing chip into Download mode = False R/W (0b0) - DIS_CAN (BLOCK0) Disables the TWAI Controller hardware = False R/W (0b0) - DIS_BOOT_REMAP (BLOCK0) Disables capability to Remap RAM to ROM address sp = False R/W (0b0) - ace - FLASH_TPUW (BLOCK0) Configures flash startup delay after SoC power-up, = 0 R/W (0x0) - unit is (ms/2). When the value is 15, delay is 7. - 5 ms - DIS_LEGACY_SPI_BOOT (BLOCK0) Disables Legacy SPI boot mode = False R/W (0b0) - UART_PRINT_CHANNEL (BLOCK0) Selects the default UART for printing boot msg = UART0 R/W (0b0) - DIS_USB_DOWNLOAD_MODE (BLOCK0) Disables use of USB in UART download boot mode = False R/W (0b0) - UART_PRINT_CONTROL (BLOCK0) Sets the default UART boot message output mode = Enabled R/W (0b00) - FLASH_TYPE (BLOCK0) Selects SPI flash type = 4 data lines R/W (0b0) - FORCE_SEND_RESUME (BLOCK0) Forces ROM code to send an SPI flash resume comman = False R/W (0b0) - d during SPI boot - BLOCK_USR_DATA (BLOCK3) User data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - - Efuse fuses: - WR_DIS (BLOCK0) Disables programming of individual eFuses = 0 R/W (0x00000000) - RD_DIS (BLOCK0) Disables software reading from BLOCK4-10 = 0 R/W (0b0000000) - + WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000) + RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000) + DIS_ICACHE (BLOCK0) Set this bit to disable Icache = False R/W (0b0) + DIS_DCACHE (BLOCK0) Set this bit to disable Dcache = False R/W (0b0) + DIS_TWAI (BLOCK0) Set this bit to disable the TWAI Controller functi = False R/W (0b0) + on + DIS_BOOT_REMAP (BLOCK0) Disables capability to Remap RAM to ROM address sp = False R/W (0b0) + ace + DIS_LEGACY_SPI_BOOT (BLOCK0) Set this bit to disable Legacy SPI boot mode = False R/W (0b0) + UART_PRINT_CHANNEL (BLOCK0) Selects the default UART for printing boot message = UART0 R/W (0b0) + s + UART_PRINT_CONTROL (BLOCK0) Set the default UART boot message output mode = Enable R/W (0b00) + PIN_POWER_SELECTION (BLOCK0) Set default power supply for GPIO33-GPIO37; set wh = VDD3P3_CPU R/W (0b0) + en SPI flash is initialized + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Flash fuses: + FLASH_TPUW (BLOCK0) Configures flash startup delay after SoC power-up; = 0 R/W (0x0) + in unit of (ms/2). When the value is 15; delay is + 7.5 ms + FLASH_TYPE (BLOCK0) SPI flash type = 4 data lines R/W (0b0) + FORCE_SEND_RESUME (BLOCK0) If set; forces ROM code to send an SPI flash resum = False R/W (0b0) + e command during SPI boot + FLASH_VERSION (BLOCK1) Flash version = 2 R/W (0x2) + Identity fuses: - BLOCK0_VERSION (BLOCK0) BLOCK0 efuse version = 0 R/W (0b00) - SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) - ure) - MAC (BLOCK1) Factory MAC Address - = 7c:df:a1:00:3a:6e: (OK) R/W - WAFER_VERSION (BLOCK1) WAFER version = A R/W (0b000) - PKG_VERSION (BLOCK1) Package version - = ESP32-S2, QFN 7x7 56 pins R/W (0x0) - BLOCK1_VERSION (BLOCK1) BLOCK1 efuse version = 0 R/W (0b000) - OPTIONAL_UNIQUE_ID (BLOCK2)(0 errors): Optional unique 128-bit ID - = 7d 33 b8 bb 0b 13 b3 c8 71 37 0e e8 7c ab d5 92 R/W - BLOCK2_VERSION (BLOCK2) Version of BLOCK2 = With calibration R/W (0b001) - CUSTOM_MAC (BLOCK3) Custom MAC Address - = 00:00:00:00:00:00 (OK) R/W - + BLOCK0_VERSION (BLOCK0) BLOCK0 efuse version = 0 R/W (0b00) + DISABLE_WAFER_VERSION_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0) + DISABLE_BLK_VERSION_MAJOR (BLOCK0) Disables check of blk version major = False R/W (0b0) + WAFER_VERSION_MAJOR (BLOCK1) WAFER_VERSION_MAJOR = 1 R/W (0b01) + WAFER_VERSION_MINOR_HI (BLOCK1) WAFER_VERSION_MINOR most significant bit = False R/W (0b0) + BLK_VERSION_MAJOR (BLOCK1) BLK_VERSION_MAJOR = 0 R/W (0b00) + PSRAM_VERSION (BLOCK1) PSRAM version = 1 R/W (0x1) + PKG_VERSION (BLOCK1) Package version = 0 R/W (0x0) + WAFER_VERSION_MINOR_LO (BLOCK1) WAFER_VERSION_MINOR least significant bits = 0 R/W (0b000) + OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID + = ea 0e c6 f1 01 f2 38 82 e9 98 5b 59 81 fe 00 02 R/W + BLK_VERSION_MINOR (BLOCK2) BLK_VERSION_MINOR of BLOCK2 = ADC calib V2 R/W (0b010) + WAFER_VERSION_MINOR (BLOCK0) calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI = 0 R/W (0x0) + << 3 + WAFER_VERSION_MINOR_LO (read only) + + Jtag fuses: + SOFT_DIS_JTAG (BLOCK0) Software disables JTAG. When software disabled; JT = False R/W (0b0) + AG can be activated temporarily by HMAC peripheral + HARD_DIS_JTAG (BLOCK0) Hardware disables JTAG permanently = False R/W (0b0) + + Mac fuses: + MAC (BLOCK1) MAC address + = 58:cf:79:b3:b9:54 (OK) R/W + CUSTOM_MAC (BLOCK3) Custom MAC + = 00:00:00:00:00:00 (OK) R/W + Security fuses: - SOFT_DIS_JTAG (BLOCK0) Software disables JTAG. When software disabled, JT = False R/W (0b0) - AG can be activated temporarily by HMAC peripheral - HARD_DIS_JTAG (BLOCK0) Hardware disables JTAG permanently = False R/W (0b0) - DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Disables flash encryption when in download boot mo = False R/W (0b0) - des - SPI_BOOT_CRYPT_CNT (BLOCK0) Enables encryption and decryption, when an SPI boo = Disable R/W (0b000) - t mode is set. Enabled when 1 or 3 bits are set,di - sabled otherwise - SECURE_BOOT_KEY_REVOKE0 (BLOCK0) If set, revokes use of secure boot key digest 0 = False R/W (0b0) - SECURE_BOOT_KEY_REVOKE1 (BLOCK0) If set, revokes use of secure boot key digest 1 = False R/W (0b0) - SECURE_BOOT_KEY_REVOKE2 (BLOCK0) If set, revokes use of secure boot key digest 2 = False R/W (0b0) - KEY_PURPOSE_0 (BLOCK0) KEY0 purpose = USER R/W (0x0) - KEY_PURPOSE_1 (BLOCK0) KEY1 purpose = USER R/W (0x0) - KEY_PURPOSE_2 (BLOCK0) KEY2 purpose = USER R/W (0x0) - KEY_PURPOSE_3 (BLOCK0) KEY3 purpose = USER R/W (0x0) - KEY_PURPOSE_4 (BLOCK0) KEY4 purpose = USER R/W (0x0) - KEY_PURPOSE_5 (BLOCK0) KEY5 purpose = USER R/W (0x0) - SECURE_BOOT_EN (BLOCK0) Enables secure boot = False R/W (0b0) - SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Enables aggressive secure boot key revocation mode = False R/W (0b0) - DIS_DOWNLOAD_MODE (BLOCK0) Disables all Download boot modes = False R/W (0b0) - ENABLE_SECURITY_DOWNLOAD (BLOCK0) Enables secure UART download mode (read/write flas = False R/W (0b0) - h only) - BLOCK_KEY0 (BLOCK4)(0 errors): - Purpose: USER - Encryption key0 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY1 (BLOCK5)(0 errors): - Purpose: USER - Encryption key1 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY2 (BLOCK6)(0 errors): - Purpose: USER - Encryption key2 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY3 (BLOCK7)(0 errors): - Purpose: USER - Encryption key3 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY4 (BLOCK8)(0 errors): - Purpose: USER - Encryption key4 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY5 (BLOCK9)(0 errors): - Purpose: USER - Encryption key5 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_SYS_DATA2 (BLOCK10) System data (part 2) - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - - Spi_Pad_Config fuses: - SPI_PAD_CONFIG_CLK (BLOCK1) SPI CLK pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_Q (BLOCK1) SPI Q (D1) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D (BLOCK1) SPI D (D0) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_CS (BLOCK1) SPI CS pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_HD (BLOCK1) SPI HD (D3) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_WP (BLOCK1) SPI WP (D2) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_DQS (BLOCK1) SPI DQS pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D4 (BLOCK1) SPI D4 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D5 (BLOCK1) SPI D5 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D6 (BLOCK1) SPI D6 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D7 (BLOCK1) SPI D7 pad = 0 R/W (0b000000) - - Usb Config fuses: - DIS_USB (BLOCK0) Disables the USB OTG hardware = False R/W (0b0) - USB_EXCHG_PINS (BLOCK0) Exchanges USB D+ and D- pins = False R/W (0b0) - EXT_PHY_ENABLE (BLOCK0) Enables external USB PHY = False R/W (0b0) - USB_FORCE_NOPERSIST (BLOCK0) Forces to set USB BVALID to 1 = False R/W (0b0) - - Vdd_Spi Config fuses: - VDD_SPI_FORCE (BLOCK0) Force using VDD_SPI_XPD and VDD_SPI_TIEH to config = False R/W (0b0) - ure VDD_SPI LDO - VDD_SPI_XPD (BLOCK0) The VDD_SPI regulator is powered on = False R/W (0b0) - VDD_SPI_TIEH (BLOCK0) The VDD_SPI power supply voltage at reset = Connect to 1.8V LDO R/W (0b0) - PIN_POWER_SELECTION (BLOCK0) Sets default power supply for GPIO33..37, set when = VDD3P3_CPU R/W (0b0) - SPI flash is initialized - - Wdt Config fuses: - WDT_DELAY_SEL (BLOCK0) Selects RTC WDT timeout threshold at startup = 0 R/W (0b00) - + DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0) + DIS_DOWNLOAD_DCACHE (BLOCK0) Disables Dcache when SoC is in Download mode = False R/W (0b0) + DIS_FORCE_DOWNLOAD (BLOCK0) Set this bit to disable the function that forces c = False R/W (0b0) + hip into download mode + DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Disables flash encryption when in download boot mo = False R/W (0b0) + des + SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) + and disabled otherwise + SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) + KEY_PURPOSE_0 (BLOCK0) Purpose of KEY0 = USER R/W (0x0) + KEY_PURPOSE_1 (BLOCK0) Purpose of KEY1 = USER R/W (0x0) + KEY_PURPOSE_2 (BLOCK0) Purpose of KEY2 = USER R/W (0x0) + KEY_PURPOSE_3 (BLOCK0) Purpose of KEY3 = USER R/W (0x0) + KEY_PURPOSE_4 (BLOCK0) Purpose of KEY4 = USER R/W (0x0) + KEY_PURPOSE_5 (BLOCK0) Purpose of KEY5 = USER R/W (0x0) + SECURE_BOOT_EN (BLOCK0) Set this bit to enable secure boot = False R/W (0b0) + SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Set this bit to enable aggressive secure boot key = False R/W (0b0) + revocation mode + DIS_DOWNLOAD_MODE (BLOCK0) Set this bit to disable all download boot modes = False R/W (0b0) + ENABLE_SECURITY_DOWNLOAD (BLOCK0) Set this bit to enable secure UART download mode ( = False R/W (0b0) + read/write flash only) + SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) + ure) + BLOCK_KEY0 (BLOCK4) + Purpose: USER + Key0 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY1 (BLOCK5) + Purpose: USER + Key1 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY2 (BLOCK6) + Purpose: USER + Key2 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY3 (BLOCK7) + Purpose: USER + Key3 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY4 (BLOCK8) + Purpose: USER + Key4 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY5 (BLOCK9) + Purpose: USER + Key5 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Spi Pad fuses: + SPI_PAD_CONFIG_CLK (BLOCK1) SPI_PAD_configure CLK = 0 R/W (0b000000) + SPI_PAD_CONFIG_Q (BLOCK1) SPI_PAD_configure Q(D1) = 0 R/W (0b000000) + SPI_PAD_CONFIG_D (BLOCK1) SPI_PAD_configure D(D0) = 0 R/W (0b000000) + SPI_PAD_CONFIG_CS (BLOCK1) SPI_PAD_configure CS = 0 R/W (0b000000) + SPI_PAD_CONFIG_HD (BLOCK1) SPI_PAD_configure HD(D3) = 0 R/W (0b000000) + SPI_PAD_CONFIG_WP (BLOCK1) SPI_PAD_configure WP(D2) = 0 R/W (0b000000) + SPI_PAD_CONFIG_DQS (BLOCK1) SPI_PAD_configure DQS = 0 R/W (0b000000) + SPI_PAD_CONFIG_D4 (BLOCK1) SPI_PAD_configure D4 = 0 R/W (0b000000) + SPI_PAD_CONFIG_D5 (BLOCK1) SPI_PAD_configure D5 = 0 R/W (0b000000) + SPI_PAD_CONFIG_D6 (BLOCK1) SPI_PAD_configure D6 = 0 R/W (0b000000) + SPI_PAD_CONFIG_D7 (BLOCK1) SPI_PAD_configure D7 = 0 R/W (0b000000) + + Usb fuses: + DIS_USB (BLOCK0) Set this bit to disable USB OTG function = False R/W (0b0) + USB_EXCHG_PINS (BLOCK0) Set this bit to exchange USB D+ and D- pins = False R/W (0b0) + USB_EXT_PHY_ENABLE (BLOCK0) Set this bit to enable external USB PHY = False R/W (0b0) + USB_FORCE_NOPERSIST (BLOCK0) If set; forces USB BVALID to 1 = False R/W (0b0) + DIS_USB_DOWNLOAD_MODE (BLOCK0) Set this bit to disable use of USB OTG in UART dow = False R/W (0b0) + nload boot mode + + Vdd fuses: + VDD_SPI_XPD (BLOCK0) If VDD_SPI_FORCE is 1; this value determines if th = False R/W (0b0) + e VDD_SPI regulator is powered on + VDD_SPI_TIEH (BLOCK0) If VDD_SPI_FORCE is 1; determines VDD_SPI voltage + = VDD_SPI connects to 1.8 V LDO R/W (0b0) + VDD_SPI_FORCE (BLOCK0) Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TI = False R/W (0b0) + EH to configure VDD_SPI LDO + + Wdt fuses: + WDT_DELAY_SEL (BLOCK0) RTC watchdog timeout threshold; in unit of slow cl = 40000 R/W (0b00) + ock cycle + Flash voltage (VDD_SPI) determined by GPIO45 on reset (GPIO45=High: VDD_SPI pin is powered from internal 1.8V LDO GPIO45=Low or NC: VDD_SPI pin is powered directly from VDD3P3_RTC_IO via resistor Rspi. Typically this voltage is 3.3 V). + To get a dump for all eFuse registers. .. code-block:: none espefuse.py -p PORT dump + espefuse.py v4.6-dev Connecting.... + Detecting chip type... Unsupported detection protocol, switching and trying again... Detecting chip type... ESP32-S2 BLOCK0 ( ) [0 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 - MAC_SPI_8M_0 (BLOCK1 ) [1 ] read_regs: a1003a6e 00007cdf 00000000 00000000 00000000 00000000 - BLOCK_SYS_DATA (BLOCK2 ) [2 ] read_regs: bbb8337d c8b3130b e80e3771 92d5ab7c 8787ae10 02038687 38e50403 8628a386 + MAC_SPI_8M_0 (BLOCK1 ) [1 ] read_regs: 79b3b954 000058cf 00000000 10440000 00000000 00000000 + BLOCK_SYS_DATA (BLOCK2 ) [2 ] read_regs: f1c60eea 8238f201 595b98e9 0200fe81 1c549f24 88491102 06461421 070c2083 BLOCK_USR_DATA (BLOCK3 ) [3 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 BLOCK_KEY0 (BLOCK4 ) [4 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 BLOCK_KEY1 (BLOCK5 ) [5 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 @@ -171,4 +175,9 @@ To get a dump for all eFuse registers. BLOCK_KEY4 (BLOCK8 ) [8 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 BLOCK_KEY5 (BLOCK9 ) [9 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 BLOCK_SYS_DATA2 (BLOCK10 ) [10] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 - espefuse.py v3.1-dev + + BLOCK0 ( ) [0 ] err__regs: 00000000 00000000 00000000 00000000 00000000 00000000 + EFUSE_RD_RS_ERR0_REG 0x00000000 + EFUSE_RD_RS_ERR1_REG 0x00000000 + + === Run "dump" command === diff --git a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S3.rst b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S3.rst index 81494ec8df..8127bea3be 100644 --- a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S3.rst +++ b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S3.rst @@ -2,165 +2,205 @@ espefuse.py -p PORT summary + espefuse.py v4.6-dev Connecting.... Detecting chip type... ESP32-S3 - espefuse.py v3.1-dev - EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) + + === Run "summary" command === + EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) ---------------------------------------------------------------------------------------- Calibration fuses: - TEMP_SENSOR_CAL (BLOCK2) Temperature calibration = -9.200000000000001 R/W (0b101011100) - ADC1_MODE0_D2 (BLOCK2) ADC1 calibration 1 = -28 R/W (0x87) - ADC1_MODE1_D2 (BLOCK2) ADC1 calibration 2 = -28 R/W (0x87) - ADC1_MODE2_D2 (BLOCK2) ADC1 calibration 3 = -28 R/W (0x87) - ADC1_MODE3_D2 (BLOCK2) ADC1 calibration 4 = -24 R/W (0x86) - ADC2_MODE0_D2 (BLOCK2) ADC2 calibration 5 = 12 R/W (0x03) - ADC2_MODE1_D2 (BLOCK2) ADC2 calibration 6 = 8 R/W (0x02) - ADC2_MODE2_D2 (BLOCK2) ADC2 calibration 7 = 12 R/W (0x03) - ADC2_MODE3_D2 (BLOCK2) ADC2 calibration 8 = 16 R/W (0x04) - ADC1_MODE0_D1 (BLOCK2) ADC1 calibration 9 = -20 R/W (0b100101) - ADC1_MODE1_D1 (BLOCK2) ADC1 calibration 10 = -12 R/W (0b100011) - ADC1_MODE2_D1 (BLOCK2) ADC1 calibration 11 = -12 R/W (0b100011) - ADC1_MODE3_D1 (BLOCK2) ADC1 calibration 12 = -4 R/W (0b100001) - ADC2_MODE0_D1 (BLOCK2) ADC2 calibration 13 = -12 R/W (0b100011) - ADC2_MODE1_D1 (BLOCK2) ADC2 calibration 14 = -8 R/W (0b100010) - ADC2_MODE2_D1 (BLOCK2) ADC2 calibration 15 = -8 R/W (0b100010) - ADC2_MODE3_D1 (BLOCK2) ADC2 calibration 16 = -4 R/W (0b100001) - + K_RTC_LDO (BLOCK1) BLOCK1 K_RTC_LDO = 12 R/W (0b0000011) + K_DIG_LDO (BLOCK1) BLOCK1 K_DIG_LDO = -28 R/W (0b1000111) + V_RTC_DBIAS20 (BLOCK1) BLOCK1 voltage of rtc dbias20 = 20 R/W (0x05) + V_DIG_DBIAS20 (BLOCK1) BLOCK1 voltage of digital dbias20 = -44 R/W (0x8b) + DIG_DBIAS_HVT (BLOCK1) BLOCK1 digital dbias when hvt = -36 R/W (0b11001) + ADC2_CAL_VOL_ATTEN3 (BLOCK1) ADC2 calibration voltage at atten3 = -24 R/W (0b100110) + TEMP_CALIB (BLOCK2) Temperature calibration data = -10.9 R/W (0b101101101) + OCODE (BLOCK2) ADC OCode = 88 R/W (0x58) + ADC1_INIT_CODE_ATTEN0 (BLOCK2) ADC1 init code at atten0 = 432 R/W (0x6c) + ADC1_INIT_CODE_ATTEN1 (BLOCK2) ADC1 init code at atten1 = -16 R/W (0b100100) + ADC1_INIT_CODE_ATTEN2 (BLOCK2) ADC1 init code at atten2 = 88 R/W (0b010110) + ADC1_INIT_CODE_ATTEN3 (BLOCK2) ADC1 init code at atten3 = 0 R/W (0b100000) + ADC2_INIT_CODE_ATTEN0 (BLOCK2) ADC2 init code at atten0 = -72 R/W (0x92) + ADC2_INIT_CODE_ATTEN1 (BLOCK2) ADC2 init code at atten1 = -16 R/W (0b100100) + ADC2_INIT_CODE_ATTEN2 (BLOCK2) ADC2 init code at atten2 = 48 R/W (0b001100) + ADC2_INIT_CODE_ATTEN3 (BLOCK2) ADC2 init code at atten3 = 112 R/W (0b011100) + ADC1_CAL_VOL_ATTEN0 (BLOCK2) ADC1 calibration voltage at atten0 = 412 R/W (0x67) + ADC1_CAL_VOL_ATTEN1 (BLOCK2) ADC1 calibration voltage at atten1 = 392 R/W (0x62) + ADC1_CAL_VOL_ATTEN2 (BLOCK2) ADC1 calibration voltage at atten2 = 356 R/W (0x59) + ADC1_CAL_VOL_ATTEN3 (BLOCK2) ADC1 calibration voltage at atten3 = 412 R/W (0x67) + ADC2_CAL_VOL_ATTEN0 (BLOCK2) ADC2 calibration voltage at atten0 = -116 R/W (0x9d) + ADC2_CAL_VOL_ATTEN1 (BLOCK2) ADC2 calibration voltage at atten1 = -72 R/W (0b1010010) + ADC2_CAL_VOL_ATTEN2 (BLOCK2) ADC2 calibration voltage at atten2 = -64 R/W (0b1010000) + Config fuses: - DIS_ICACHE (BLOCK0) Disables ICache = False R/W (0b0) - DIS_DCACHE (BLOCK0) Disables DCache = False R/W (0b0) - DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0) - DIS_DOWNLOAD_DCACHE (BLOCK0) Disables Dcache when SoC is in Download mode = False R/W (0b0) - DIS_FORCE_DOWNLOAD (BLOCK0) Disables forcing chip into Download mode = False R/W (0b0) - DIS_CAN (BLOCK0) Disables the TWAI Controller hardware = False R/W (0b0) - DIS_APP_CPU (BLOCK0) Disables APP CPU = False R/W (0b0) - FLASH_TPUW (BLOCK0) Configures flash startup delay after SoC power-up, = 0 R/W (0x0) - unit is (ms/2). When the value is 15, delay is 7. - 5 ms - DIS_DIRECT_BOOT (BLOCK0) Disables direct boot mode = False R/W (0b0) - DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Selects the default UART for printing boot msg = UART0 R/W (0b0) - DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Disables download through USB-Serial-JTAG = False R/W (0b0) - UART_PRINT_CONTROL (BLOCK0) Sets the default UART boot message output mode = Enabled R/W (0b00) - FLASH_TYPE (BLOCK0) Selects SPI flash type = 4 data lines R/W (0b0) - FORCE_SEND_RESUME (BLOCK0) Forces ROM code to send an SPI flash resume comman = False R/W (0b0) - d during SPI boot - BLOCK_USR_DATA (BLOCK3) User data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - - Efuse fuses: - WR_DIS (BLOCK0) Disables programming of individual eFuses = 0 R/W (0x00000000) - RD_DIS (BLOCK0) Disables software reading from BLOCK4-10 = 0 R/W (0b0000000) - + WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000) + RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000) + DIS_ICACHE (BLOCK0) Set this bit to disable Icache = False R/W (0b0) + DIS_DCACHE (BLOCK0) Set this bit to disable Dcache = False R/W (0b0) + DIS_TWAI (BLOCK0) Set this bit to disable CAN function = False R/W (0b0) + DIS_APP_CPU (BLOCK0) Disable app cpu = False R/W (0b0) + DIS_DIRECT_BOOT (BLOCK0) Disable direct boot mode = False R/W (0b0) + UART_PRINT_CONTROL (BLOCK0) Set the default UART boot message output mode = Enable R/W (0b00) + PIN_POWER_SELECTION (BLOCK0) Set default power supply for GPIO33-GPIO37; set wh = VDD3P3_CPU R/W (0b0) + en SPI flash is initialized + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Flash fuses: + FLASH_TPUW (BLOCK0) Configures flash waiting time after power-up; in u = 0 R/W (0x0) + nit of ms. If the value is less than 15; the waiti + ng time is the configurable value. Otherwise; the + waiting time is twice the configurable value + FLASH_ECC_MODE (BLOCK0) Flash ECC mode in ROM = 16to18 byte R/W (0b0) + FLASH_TYPE (BLOCK0) SPI flash type = 4 data lines R/W (0b0) + FLASH_PAGE_SIZE (BLOCK0) Set Flash page size = 0 R/W (0b00) + FLASH_ECC_EN (BLOCK0) Set 1 to enable ECC for flash boot = False R/W (0b0) + FORCE_SEND_RESUME (BLOCK0) Set this bit to force ROM code to send a resume co = False R/W (0b0) + mmand during SPI boot + Identity fuses: - BLOCK0_VERSION (BLOCK0) BLOCK0 efuse version = 0 R/W (0b00) - SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) - ure) - MAC (BLOCK1) Factory MAC Address - = 7c:df:a1:00:3a:6e: (OK) R/W - WAFER_VERSION (BLOCK1) WAFER version = A R/W (0b000) - PKG_VERSION (BLOCK1) Package version - = ESP32-S3, QFN 7x7 56 pins R/W (0x0) - BLOCK1_VERSION (BLOCK1) BLOCK1 efuse version = 0 R/W (0b000) - OPTIONAL_UNIQUE_ID (BLOCK2)(0 errors): Optional unique 128-bit ID - = 7d 33 b8 bb 0b 13 b3 c8 71 37 0e e8 7c ab d5 92 R/W - BLOCK2_VERSION (BLOCK2) Version of BLOCK2 = With calibration R/W (0b001) - CUSTOM_MAC (BLOCK3) Custom MAC Address - = 00:00:00:00:00:00 (OK) R/W - + DISABLE_WAFER_VERSION_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0) + DISABLE_BLK_VERSION_MAJOR (BLOCK0) Disables check of blk version major = False R/W (0b0) + WAFER_VERSION_MINOR_LO (BLOCK1) WAFER_VERSION_MINOR least significant bits = 3 R/W (0b011) + PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000) + BLK_VERSION_MINOR (BLOCK1) BLK_VERSION_MINOR = 3 R/W (0b011) + WAFER_VERSION_MINOR_HI (BLOCK1) WAFER_VERSION_MINOR most significant bit = False R/W (0b0) + WAFER_VERSION_MAJOR (BLOCK1) WAFER_VERSION_MAJOR = 0 R/W (0b00) + OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID + = cb 3a c9 b8 88 2b c3 bc 5e f4 00 60 ac 25 be 4b R/W + BLK_VERSION_MAJOR (BLOCK2) BLK_VERSION_MAJOR of BLOCK2 = ADC calib V1 R/W (0b01) + WAFER_VERSION_MINOR (BLOCK0) calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI = 3 R/W (0x3) + << 3 + WAFER_VERSION_MINOR_LO (read only) + + Jtag fuses: + SOFT_DIS_JTAG (BLOCK0) Set these bits to disable JTAG in the soft way (od = 0 R/W (0b000) + d number 1 means disable ). JTAG can be enabled in + HMAC module + DIS_PAD_JTAG (BLOCK0) Set this bit to disable JTAG in the hard way. JTAG = False R/W (0b0) + is disabled permanently + STRAP_JTAG_SEL (BLOCK0) Set this bit to enable selection between usb_to_jt = False R/W (0b0) + ag and pad_to_jtag through strapping gpio10 when b + oth reg_dis_usb_jtag and reg_dis_pad_jtag are equa + l to 0 + + Mac fuses: + MAC (BLOCK1) MAC address + = ec:da:3b:41:f2:70 (OK) R/W + CUSTOM_MAC (BLOCK3) Custom MAC + = 00:00:00:00:00:00 (OK) R/W + Security fuses: - SOFT_DIS_JTAG (BLOCK0) Software disables JTAG. When software disabled, JT = False R/W (0b000) - AG can be activated temporarily by HMAC peripheral - HARD_DIS_JTAG (BLOCK0) Hardware disables JTAG permanently = False R/W (0b0) - DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Disables flash encryption when in download boot mo = False R/W (0b0) - des - SPI_BOOT_CRYPT_CNT (BLOCK0) Enables encryption and decryption, when an SPI boo = Disable R/W (0b000) - t mode is set. Enabled when 1 or 3 bits are set,di - sabled otherwise - SECURE_BOOT_KEY_REVOKE0 (BLOCK0) If set, revokes use of secure boot key digest 0 = False R/W (0b0) - SECURE_BOOT_KEY_REVOKE1 (BLOCK0) If set, revokes use of secure boot key digest 1 = False R/W (0b0) - SECURE_BOOT_KEY_REVOKE2 (BLOCK0) If set, revokes use of secure boot key digest 2 = False R/W (0b0) - KEY_PURPOSE_0 (BLOCK0) KEY0 purpose = USER R/W (0x0) - KEY_PURPOSE_1 (BLOCK0) KEY1 purpose = USER R/W (0x0) - KEY_PURPOSE_2 (BLOCK0) KEY2 purpose = USER R/W (0x0) - KEY_PURPOSE_3 (BLOCK0) KEY3 purpose = USER R/W (0x0) - KEY_PURPOSE_4 (BLOCK0) KEY4 purpose = USER R/W (0x0) - KEY_PURPOSE_5 (BLOCK0) KEY5 purpose = USER R/W (0x0) - SECURE_BOOT_EN (BLOCK0) Enables secure boot = False R/W (0b0) - SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Enables aggressive secure boot key revocation mode = False R/W (0b0) - DIS_DOWNLOAD_MODE (BLOCK0) Disables all Download boot modes = False R/W (0b0) - ENABLE_SECURITY_DOWNLOAD (BLOCK0) Enables secure UART download mode (read/write flas = False R/W (0b0) - h only) - BLOCK_KEY0 (BLOCK4)(0 errors): - Purpose: USER - Encryption key0 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY1 (BLOCK5)(0 errors): - Purpose: USER - Encryption key1 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY2 (BLOCK6)(0 errors): - Purpose: USER - Encryption key2 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY3 (BLOCK7)(0 errors): - Purpose: USER - Encryption key3 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY4 (BLOCK8)(0 errors): - Purpose: USER - Encryption key4 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY5 (BLOCK9)(0 errors): - Purpose: USER - Encryption key5 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_SYS_DATA2 (BLOCK10) System data (part 2) - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - - Spi_Pad_Config fuses: - SPI_PAD_CONFIG_CLK (BLOCK1) SPI CLK pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_Q (BLOCK1) SPI Q (D1) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D (BLOCK1) SPI D (D0) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_CS (BLOCK1) SPI CS pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_HD (BLOCK1) SPI HD (D3) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_WP (BLOCK1) SPI WP (D2) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_DQS (BLOCK1) SPI DQS pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D4 (BLOCK1) SPI D4 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D5 (BLOCK1) SPI D5 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D6 (BLOCK1) SPI D6 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D7 (BLOCK1) SPI D7 pad = 0 R/W (0b000000) - - Usb Config fuses: - DIS_USB (BLOCK0) Disables the USB OTG hardware = False R/W (0b0) - USB_EXCHG_PINS (BLOCK0) Exchanges USB D+ and D- pins = False R/W (0b0) - EXT_PHY_ENABLE (BLOCK0) Enables external USB PHY = False R/W (0b0) - USB_FORCE_NOPERSIST (BLOCK0) Forces to set USB BVALID to 1 = False R/W (0b0) - - Vdd_Spi Config fuses: - VDD_SPI_FORCE (BLOCK0) Force using VDD_SPI_XPD and VDD_SPI_TIEH to config = False R/W (0b0) - ure VDD_SPI LDO - VDD_SPI_XPD (BLOCK0) The VDD_SPI regulator is powered on = False R/W (0b0) - VDD_SPI_TIEH (BLOCK0) The VDD_SPI power supply voltage at reset = Connect to 1.8V LDO R/W (0b0) - PIN_POWER_SELECTION (BLOCK0) Sets default power supply for GPIO33..37, set when = VDD3P3_CPU R/W (0b0) - SPI flash is initialized - - Wdt Config fuses: - WDT_DELAY_SEL (BLOCK0) Selects RTC WDT timeout threshold at startup = 0 R/W (0b00) - + DIS_DOWNLOAD_ICACHE (BLOCK0) Set this bit to disable Icache in download mode (b = False R/W (0b0) + oot_mode[3:0] is 0; 1; 2; 3; 6; 7) + DIS_DOWNLOAD_DCACHE (BLOCK0) Set this bit to disable Dcache in download mode ( = False R/W (0b0) + boot_mode[3:0] is 0; 1; 2; 3; 6; 7) + DIS_FORCE_DOWNLOAD (BLOCK0) Set this bit to disable the function that forces c = False R/W (0b0) + hip into download mode + DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Set this bit to disable flash encryption when in d = False R/W (0b0) + ownload boot modes + SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) + and disabled otherwise + SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) + KEY_PURPOSE_0 (BLOCK0) Purpose of Key0 = USER R/W (0x0) + KEY_PURPOSE_1 (BLOCK0) Purpose of Key1 = USER R/W (0x0) + KEY_PURPOSE_2 (BLOCK0) Purpose of Key2 = USER R/W (0x0) + KEY_PURPOSE_3 (BLOCK0) Purpose of Key3 = USER R/W (0x0) + KEY_PURPOSE_4 (BLOCK0) Purpose of Key4 = USER R/W (0x0) + KEY_PURPOSE_5 (BLOCK0) Purpose of Key5 = USER R/W (0x0) + SECURE_BOOT_EN (BLOCK0) Set this bit to enable secure boot = False R/W (0b0) + SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Set this bit to enable revoking aggressive secure = False R/W (0b0) + boot + DIS_DOWNLOAD_MODE (BLOCK0) Set this bit to disable download mode (boot_mode[3 = False R/W (0b0) + :0] = 0; 1; 2; 3; 6; 7) + ENABLE_SECURITY_DOWNLOAD (BLOCK0) Set this bit to enable secure UART download mode = False R/W (0b0) + SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) + ure) + BLOCK_KEY0 (BLOCK4) + Purpose: USER + Key0 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY1 (BLOCK5) + Purpose: USER + Key1 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY2 (BLOCK6) + Purpose: USER + Key2 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY3 (BLOCK7) + Purpose: USER + Key3 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY4 (BLOCK8) + Purpose: USER + Key4 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY5 (BLOCK9) + Purpose: USER + Key5 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Spi Pad fuses: + SPI_PAD_CONFIG_CLK (BLOCK1) SPI_PAD_configure CLK = 0 R/W (0b000000) + SPI_PAD_CONFIG_Q (BLOCK1) SPI_PAD_configure Q(D1) = 0 R/W (0b000000) + SPI_PAD_CONFIG_D (BLOCK1) SPI_PAD_configure D(D0) = 0 R/W (0b000000) + SPI_PAD_CONFIG_CS (BLOCK1) SPI_PAD_configure CS = 0 R/W (0b000000) + SPI_PAD_CONFIG_HD (BLOCK1) SPI_PAD_configure HD(D3) = 0 R/W (0b000000) + SPI_PAD_CONFIG_WP (BLOCK1) SPI_PAD_configure WP(D2) = 0 R/W (0b000000) + SPI_PAD_CONFIG_DQS (BLOCK1) SPI_PAD_configure DQS = 0 R/W (0b000000) + SPI_PAD_CONFIG_D4 (BLOCK1) SPI_PAD_configure D4 = 0 R/W (0b000000) + SPI_PAD_CONFIG_D5 (BLOCK1) SPI_PAD_configure D5 = 0 R/W (0b000000) + SPI_PAD_CONFIG_D6 (BLOCK1) SPI_PAD_configure D6 = 0 R/W (0b000000) + SPI_PAD_CONFIG_D7 (BLOCK1) SPI_PAD_configure D7 = 0 R/W (0b000000) + + Usb fuses: + DIS_USB_OTG (BLOCK0) Set this bit to disable USB function = False R/W (0b0) + USB_EXCHG_PINS (BLOCK0) Set this bit to exchange USB D+ and D- pins = False R/W (0b0) + USB_EXT_PHY_ENABLE (BLOCK0) Set this bit to enable external PHY = False R/W (0b0) + DIS_USB_JTAG (BLOCK0) Set this bit to disable function of usb switch to = False R/W (0b0) + jtag in module of usb device + DIS_USB_SERIAL_JTAG (BLOCK0) Set this bit to disable usb device = False R/W (0b0) + USB_PHY_SEL (BLOCK0) This bit is used to switch internal PHY and extern + = internal PHY is assigned to USB Device while external PHY is assigned to USB OTG R/W (0b0) + al PHY for USB OTG and USB Device + DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) USB printing = Enable R/W (0b0) + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Set this bit to disable UART download mode through = False R/W (0b0) + USB + DIS_USB_OTG_DOWNLOAD_MODE (BLOCK0) Set this bit to disable download through USB-OTG = False R/W (0b0) + + Vdd fuses: + VDD_SPI_XPD (BLOCK0) SPI regulator power up signal = False R/W (0b0) + VDD_SPI_TIEH (BLOCK0) If VDD_SPI_FORCE is 1; determines VDD_SPI voltage + = VDD_SPI connects to 1.8 V LDO R/W (0b0) + VDD_SPI_FORCE (BLOCK0) Set this bit and force to use the configuration of = False R/W (0b0) + eFuse to configure VDD_SPI + + Wdt fuses: + WDT_DELAY_SEL (BLOCK0) RTC watchdog timeout threshold; in unit of slow cl = 40000 R/W (0b00) + ock cycle + Flash voltage (VDD_SPI) determined by GPIO45 on reset (GPIO45=High: VDD_SPI pin is powered from internal 1.8V LDO GPIO45=Low or NC: VDD_SPI pin is powered directly from VDD3P3_RTC_IO via resistor Rspi. Typically this voltage is 3.3 V). + To get a dump for all eFuse registers. .. code-block:: none espefuse.py -p PORT dump + espefuse.py v4.6-dev Connecting.... Detecting chip type... ESP32-S3 BLOCK0 ( ) [0 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 - MAC_SPI_8M_0 (BLOCK1 ) [1 ] read_regs: a1003a6e 00007cdf 00000000 00000000 00000000 00000000 - BLOCK_SYS_DATA (BLOCK2 ) [2 ] read_regs: bbb8337d c8b3130b e80e3771 92d5ab7c 8787ae10 02038687 38e50403 8628a386 + MAC_SPI_8M_0 (BLOCK1 ) [1 ] read_regs: 3b41f270 0000ecda 00000000 030c0000 2c707800 9800cc58 + BLOCK_SYS_DATA (BLOCK2 ) [2 ] read_regs: b8c93acb bcc32b88 6000f45e 4bbe25ac 8d8b16d1 924940b4 b2c4cee1 50a53ace BLOCK_USR_DATA (BLOCK3 ) [3 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 BLOCK_KEY0 (BLOCK4 ) [4 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 BLOCK_KEY1 (BLOCK5 ) [5 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 @@ -169,4 +209,9 @@ To get a dump for all eFuse registers. BLOCK_KEY4 (BLOCK8 ) [8 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 BLOCK_KEY5 (BLOCK9 ) [9 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 BLOCK_SYS_DATA2 (BLOCK10 ) [10] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 - espefuse.py v3.1-dev + + BLOCK0 ( ) [0 ] err__regs: 00000000 00000000 00000000 00000000 00000000 00000000 + EFUSE_RD_RS_ERR0_REG 0x00000000 + EFUSE_RD_RS_ERR1_REG 0x00000000 + + === Run "dump" command === diff --git a/docs/en/api-reference/system/inc/espefuse_summary_ESP32.rst b/docs/en/api-reference/system/inc/espefuse_summary_ESP32.rst index 98c17fbf32..2774f5d918 100644 --- a/docs/en/api-reference/system/inc/espefuse_summary_ESP32.rst +++ b/docs/en/api-reference/system/inc/espefuse_summary_ESP32.rst @@ -2,67 +2,96 @@ espefuse.py -p PORT summary - Connecting........__ + espefuse.py v4.6-dev + Connecting.... + Detecting chip type... Unsupported detection protocol, switching and trying again... + Connecting..... Detecting chip type... ESP32 - espefuse.py v3.1-dev - EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) + + === Run "summary" command === + EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) ---------------------------------------------------------------------------------------- Calibration fuses: - BLK3_PART_RESERVE (BLOCK0): BLOCK3 partially served for ADC calibration data = True R/W (0b1) - ADC_VREF (BLOCK0): Voltage reference calibration = 1114 R/W (0b00010) - ADC1_TP_LOW (BLOCK3): ADC1 150mV reading = 346 R/W (0b0010001) - ADC1_TP_HIGH (BLOCK3): ADC1 850mV reading = 3285 R/W (0b000000101) - ADC2_TP_LOW (BLOCK3): ADC2 150mV reading = 449 R/W (0b0000111) - ADC2_TP_HIGH (BLOCK3): ADC2 850mV reading = 3362 R/W (0b111110101) - + ADC_VREF (BLOCK0) True ADC reference voltage = 1121 R/W (0b00011) + Config fuses: - XPD_SDIO_FORCE (BLOCK0): Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = False R/W (0b0) - XPD_SDIO_REG (BLOCK0): If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = False R/W (0b0) - XPD_SDIO_TIEH (BLOCK0): If XPD_SDIO_FORCE & XPD_SDIO_REG = 1.8V R/W (0b0) - CLK8M_FREQ (BLOCK0): 8MHz clock freq override = 53 R/W (0x35) - SPI_PAD_CONFIG_CLK (BLOCK0): Override SD_CLK pad (GPIO6/SPICLK) = 0 R/W (0b00000) - SPI_PAD_CONFIG_Q (BLOCK0): Override SD_DATA_0 pad (GPIO7/SPIQ) = 0 R/W (0b00000) - SPI_PAD_CONFIG_D (BLOCK0): Override SD_DATA_1 pad (GPIO8/SPID) = 0 R/W (0b00000) - SPI_PAD_CONFIG_HD (BLOCK0): Override SD_DATA_2 pad (GPIO9/SPIHD) = 0 R/W (0b00000) - SPI_PAD_CONFIG_CS0 (BLOCK0): Override SD_CMD pad (GPIO11/SPICS0) = 0 R/W (0b00000) - DISABLE_SDIO_HOST (BLOCK0): Disable SDIO host = False R/W (0b0) - - Efuse fuses: - WR_DIS (BLOCK0): Efuse write disable mask = 0 R/W (0x0000) - RD_DIS (BLOCK0): Efuse read disable mask = 0 R/W (0x0) - CODING_SCHEME (BLOCK0): Efuse variable block length scheme - = 3/4 (BLK1-3 len=192 bits) R/W (0b01) - KEY_STATUS (BLOCK0): Usage of efuse block 3 (reserved) = False R/W (0b0) - + WR_DIS (BLOCK0) Efuse write disable mask = 0 R/W (0x0000) + RD_DIS (BLOCK0) Disable reading from BlOCK1-3 = 0 R/W (0x0) + DISABLE_APP_CPU (BLOCK0) Disables APP CPU = False R/W (0b0) + DISABLE_BT (BLOCK0) Disables Bluetooth = False R/W (0b0) + DIS_CACHE (BLOCK0) Disables cache = False R/W (0b0) + CHIP_CPU_FREQ_LOW (BLOCK0) If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the = False R/W (0b0) + ESP32's max CPU frequency is rated for 160MHz. 24 + 0MHz otherwise + CHIP_CPU_FREQ_RATED (BLOCK0) If set; the ESP32's maximum CPU frequency has been = True R/W (0b1) + rated + BLK3_PART_RESERVE (BLOCK0) BLOCK3 partially served for ADC calibration data = False R/W (0b0) + CLK8M_FREQ (BLOCK0) 8MHz clock freq override = 51 R/W (0x33) + VOL_LEVEL_HP_INV (BLOCK0) This field stores the voltage level for CPU to run = 0 R/W (0b00) + at 240 MHz; or for flash/PSRAM to run at 80 MHz.0 + x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: leve + l 4. (RO) + CODING_SCHEME (BLOCK0) Efuse variable block length scheme + = NONE (BLK1-3 len=256 bits) R/W (0b00) + CONSOLE_DEBUG_DISABLE (BLOCK0) Disable ROM BASIC interpreter fallback = True R/W (0b1) + DISABLE_SDIO_HOST (BLOCK0) = False R/W (0b0) + DISABLE_DL_CACHE (BLOCK0) Disable flash cache in UART bootloader = False R/W (0b0) + + Flash fuses: + FLASH_CRYPT_CNT (BLOCK0) Flash encryption is enabled if this field has an o = 0 R/W (0b0000000) + dd number of bits set + FLASH_CRYPT_CONFIG (BLOCK0) Flash encryption config (key tweak bits) = 0 R/W (0x0) + Identity fuses: - MAC (BLOCK0): Factory MAC Address - = 84:0d:8e:18:8e:44 (CRC 0xad OK) R/W - MAC_CRC (BLOCK0): CRC8 for factory MAC address = 173 R/W (0xad) - CHIP_VER_REV1 (BLOCK0): Silicon Revision 1 = True R/W (0b1) - CHIP_VER_REV2 (BLOCK0): Silicon Revision 2 = False R/W (0b0) - CHIP_VERSION (BLOCK0): Reserved for future chip versions = 2 R/W (0b10) - CHIP_PACKAGE (BLOCK0): Chip package identifier = 0 R/W (0b000) - MAC_VERSION (BLOCK3): Version of the MAC field = 0 R/W (0x00) - + CHIP_PACKAGE_4BIT (BLOCK0) Chip package identifier #4bit = False R/W (0b0) + CHIP_PACKAGE (BLOCK0) Chip package identifier = 1 R/W (0b001) + CHIP_VER_REV1 (BLOCK0) bit is set to 1 for rev1 silicon = True R/W (0b1) + CHIP_VER_REV2 (BLOCK0) = True R/W (0b1) + WAFER_VERSION_MINOR (BLOCK0) = 0 R/W (0b00) + WAFER_VERSION_MAJOR (BLOCK0) calc WAFER VERSION MAJOR from CHIP_VER_REV1 and CH = 3 R/W (0b011) + IP_VER_REV2 and apb_ctl_date (read only) + PKG_VERSION (BLOCK0) calc Chip package = CHIP_PACKAGE_4BIT << 3 + CHIP_ = 1 R/W (0x1) + PACKAGE (read only) + + Jtag fuses: + JTAG_DISABLE (BLOCK0) Disable JTAG = False R/W (0b0) + + Mac fuses: + MAC (BLOCK0) MAC address + = 94:b9:7e:5a:6e:58 (CRC 0xe2 OK) R/W + MAC_CRC (BLOCK0) CRC8 for MAC address = 226 R/W (0xe2) + MAC_VERSION (BLOCK3) Version of the MAC field = 0 R/W (0x00) + Security fuses: - FLASH_CRYPT_CNT (BLOCK0): Flash encryption mode counter = 0 R/W (0b0000000) - UART_DOWNLOAD_DIS (BLOCK0): Disable UART download mode (ESP32 rev3 only) = False R/W (0b0) - FLASH_CRYPT_CONFIG (BLOCK0): Flash encryption config (key tweak bits) = 0 R/W (0x0) - CONSOLE_DEBUG_DISABLE (BLOCK0): Disable ROM BASIC interpreter fallback = True R/W (0b1) - ABS_DONE_0 (BLOCK0): Secure boot V1 is enabled for bootloader image = False R/W (0b0) - ABS_DONE_1 (BLOCK0): Secure boot V2 is enabled for bootloader image = False R/W (0b0) - JTAG_DISABLE (BLOCK0): Disable JTAG = False R/W (0b0) - DISABLE_DL_ENCRYPT (BLOCK0): Disable flash encryption in UART bootloader = False R/W (0b0) - DISABLE_DL_DECRYPT (BLOCK0): Disable flash decryption in UART bootloader = False R/W (0b0) - DISABLE_DL_CACHE (BLOCK0): Disable flash cache in UART bootloader = False R/W (0b0) - BLOCK1 (BLOCK1): Flash encryption key - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK2 (BLOCK2): Secure boot key - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK3 (BLOCK3): Variable Block 3 - = 00 00 00 00 00 00 00 00 00 00 00 00 91 02 87 fa 00 00 00 00 00 00 00 00 R/W + UART_DOWNLOAD_DIS (BLOCK0) Disable UART download mode. Valid for ESP32 V3 and = False R/W (0b0) + newer; only + ABS_DONE_0 (BLOCK0) Secure boot V1 is enabled for bootloader image = False R/W (0b0) + ABS_DONE_1 (BLOCK0) Secure boot V2 is enabled for bootloader image = False R/W (0b0) + DISABLE_DL_ENCRYPT (BLOCK0) Disable flash encryption in UART bootloader = False R/W (0b0) + DISABLE_DL_DECRYPT (BLOCK0) Disable flash decryption in UART bootloader = False R/W (0b0) + KEY_STATUS (BLOCK0) Usage of efuse block 3 (reserved) = False R/W (0b0) + SECURE_VERSION (BLOCK3) Secure version for anti-rollback = 0 R/W (0x00000000) + BLOCK1 (BLOCK1) Flash encryption key + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK2 (BLOCK2) Security boot key + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK3 (BLOCK3) Variable Block 3 + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Spi Pad fuses: + SPI_PAD_CONFIG_HD (BLOCK0) read for SPI_pad_config_hd = 0 R/W (0b00000) + SPI_PAD_CONFIG_CLK (BLOCK0) Override SD_CLK pad (GPIO6/SPICLK) = 0 R/W (0b00000) + SPI_PAD_CONFIG_Q (BLOCK0) Override SD_DATA_0 pad (GPIO7/SPIQ) = 0 R/W (0b00000) + SPI_PAD_CONFIG_D (BLOCK0) Override SD_DATA_1 pad (GPIO8/SPID) = 0 R/W (0b00000) + SPI_PAD_CONFIG_CS0 (BLOCK0) Override SD_CMD pad (GPIO11/SPICS0) = 0 R/W (0b00000) + + Vdd fuses: + XPD_SDIO_REG (BLOCK0) read for XPD_SDIO_REG = False R/W (0b0) + XPD_SDIO_TIEH (BLOCK0) If XPD_SDIO_FORCE & XPD_SDIO_REG = 1.8V R/W (0b0) + XPD_SDIO_FORCE (BLOCK0) Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = False R/W (0b0) + + Flash voltage (VDD_SDIO) determined by GPIO12 on reset (High for 1.8V, Low/NC for 3.3V) - Flash voltage (VDD_SDIO) determined by GPIO12 on reset (High for 1.8V, Low/NC for 3.3V). To get a dump for all eFuse registers. @@ -70,10 +99,16 @@ To get a dump for all eFuse registers. espefuse.py -p PORT dump - Connecting........_ + espefuse.py v4.6-dev + Connecting.... + Detecting chip type... Unsupported detection protocol, switching and trying again... + Connecting....... Detecting chip type... ESP32 - BLOCK0 ( ) [0 ] read_regs: 00000000 8e188e44 00ad840d 0000e000 00000235 00000000 00000005 - BLOCK1 (flash_encryption) [1 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 - BLOCK2 (secure_boot_v1 s) [2 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 - BLOCK3 ( ) [3 ] read_regs: 00000000 00000000 00000000 fa870291 00000000 00000000 - espefuse.py v3.1-dev + BLOCK0 ( ) [0 ] read_regs: 00000000 7e5a6e58 00e294b9 0000a200 00000333 00100000 00000004 + BLOCK1 (flash_encryption) [1 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK2 (secure_boot_v1 s) [2 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK3 ( ) [3 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + + EFUSE_REG_DEC_STATUS 0x00000000 + + === Run "dump" command === diff --git a/docs/en/api-reference/system/inc/revisions_ESP32-C6.rst b/docs/en/api-reference/system/inc/revisions_ESP32-C6.rst index 21fca39fa4..4dfd7cd3b3 100644 --- a/docs/en/api-reference/system/inc/revisions_ESP32-C6.rst +++ b/docs/en/api-reference/system/inc/revisions_ESP32-C6.rst @@ -1,6 +1,8 @@ -+------------------------+ -| Revision (Major.Minor) | -+------------------------+ -| v0.0 | -+------------------------+ ++--------+------------------------+ +| ECO | Revision (Major.Minor) | ++--------+------------------------+ +| ECO0 | v0.0 | ++--------+------------------------+ +| ECO1 | v0.1 | ++--------+------------------------+ diff --git a/docs/en/api-reference/system/inc/revisions_ESP32-H2.rst b/docs/en/api-reference/system/inc/revisions_ESP32-H2.rst index 21fca39fa4..7bb4949df1 100644 --- a/docs/en/api-reference/system/inc/revisions_ESP32-H2.rst +++ b/docs/en/api-reference/system/inc/revisions_ESP32-H2.rst @@ -1,6 +1,10 @@ -+------------------------+ -| Revision (Major.Minor) | -+------------------------+ -| v0.0 | -+------------------------+ ++--------+------------------------+ +| ECO | Revision (Major.Minor) | ++--------+------------------------+ +| ECO0 | v0.0 | ++--------+------------------------+ +| ECO1 | v0.1 | ++--------+------------------------+ +| ECO2 | v0.2 | ++--------+------------------------+ diff --git a/docs/en/api-reference/system/inc/show-efuse-table_ESP32-C2.rst b/docs/en/api-reference/system/inc/show-efuse-table_ESP32-C2.rst index 759fffffc4..f8350d822f 100644 --- a/docs/en/api-reference/system/inc/show-efuse-table_ESP32-C2.rst +++ b/docs/en/api-reference/system/inc/show-efuse-table_ESP32-C2.rst @@ -7,70 +7,114 @@ Verifying efuse table... Max number of bits in BLK 256 Sorted efuse table: - # field_name efuse_block bit_start bit_count - 1 WR_DIS EFUSE_BLK0 0 8 - 2 WR_DIS.KEY0_RD_DIS EFUSE_BLK0 0 1 - 3 WR_DIS.GROUP_1 EFUSE_BLK0 1 1 - 4 WR_DIS.GROUP_2 EFUSE_BLK0 2 1 - 5 WR_DIS.SPI_BOOT_CRYPT_CNT EFUSE_BLK0 2 1 - 6 WR_DIS.GROUP_3 EFUSE_BLK0 3 1 - 7 WR_DIS.BLK0_RESERVED EFUSE_BLK0 4 1 - 8 WR_DIS.SYS_DATA_PART0 EFUSE_BLK0 5 1 - 9 WR_DIS.SYS_DATA_PART1 EFUSE_BLK0 6 1 - 10 WR_DIS.KEY0 EFUSE_BLK0 7 1 - 11 RD_DIS EFUSE_BLK0 32 2 - 12 RD_DIS.KEY0 EFUSE_BLK0 32 2 - 13 RD_DIS.KEY0.LOW EFUSE_BLK0 32 1 - 14 RD_DIS.KEY0.HI EFUSE_BLK0 33 1 - 15 WDT_DELAY_SEL EFUSE_BLK0 34 2 - 16 DIS_PAD_JTAG EFUSE_BLK0 36 1 - 17 DIS_DOWNLOAD_ICACHE EFUSE_BLK0 37 1 - 18 DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 38 1 - 19 SPI_BOOT_CRYPT_CNT EFUSE_BLK0 39 3 - 20 XTS_KEY_LENGTH_256 EFUSE_BLK0 42 1 - 21 UART_PRINT_CONTROL EFUSE_BLK0 43 2 - 22 FORCE_SEND_RESUME EFUSE_BLK0 45 1 - 23 DIS_DOWNLOAD_MODE EFUSE_BLK0 46 1 - 24 DIS_DIRECT_BOOT EFUSE_BLK0 47 1 - 25 ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 48 1 - 26 FLASH_TPUW EFUSE_BLK0 49 4 - 27 SECURE_BOOT_EN EFUSE_BLK0 53 1 - 28 SECURE_VERSION EFUSE_BLK0 54 4 - 29 USER_DATA EFUSE_BLK1 0 88 - 30 USER_DATA.MAC_CUSTOM EFUSE_BLK1 0 48 - 31 MAC_FACTORY EFUSE_BLK2 0 8 - 32 MAC_FACTORY EFUSE_BLK2 8 8 - 33 MAC_FACTORY EFUSE_BLK2 16 8 - 34 MAC_FACTORY EFUSE_BLK2 24 8 - 35 MAC_FACTORY EFUSE_BLK2 32 8 - 36 MAC_FACTORY EFUSE_BLK2 40 8 - 37 WAFER_VERSION EFUSE_BLK2 48 3 - 38 PKG_VERSION EFUSE_BLK2 51 3 - 39 BLOCK2_VERSION EFUSE_BLK2 54 3 - 40 RF_REF_I_BIAS_CONFIG EFUSE_BLK2 57 4 - 41 LDO_VOL_BIAS_CONFIG_LOW EFUSE_BLK2 61 3 - 42 LDO_VOL_BIAS_CONFIG_HIGH EFUSE_BLK2 64 27 - 43 PVT_LOW EFUSE_BLK2 91 5 - 44 PVT_HIGH EFUSE_BLK2 96 10 - 45 ADC_CALIBRATION_0 EFUSE_BLK2 106 22 - 46 ADC_CALIBRATION_1 EFUSE_BLK2 128 32 - 47 ADC_CALIBRATION_2 EFUSE_BLK2 160 32 - 48 KEY0 EFUSE_BLK3 0 256 - 49 KEY0.FE_256BIT EFUSE_BLK3 0 256 - 50 KEY0.FE_128BIT EFUSE_BLK3 0 128 - 51 KEY0.SB_128BIT EFUSE_BLK3 128 128 + # field_name efuse_block bit_start bit_count + 1 WR_DIS EFUSE_BLK0 0 8 + 2 WR_DIS.RD_DIS EFUSE_BLK0 0 1 + 3 WR_DIS.WDT_DELAY_SEL EFUSE_BLK0 1 1 + 4 WR_DIS.DIS_PAD_JTAG EFUSE_BLK0 1 1 + 5 WR_DIS.DIS_DOWNLOAD_ICACHE EFUSE_BLK0 1 1 + 6 WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 2 1 + 7 WR_DIS.SPI_BOOT_CRYPT_CNT EFUSE_BLK0 2 1 + 8 WR_DIS.XTS_KEY_LENGTH_256 EFUSE_BLK0 2 1 + 9 WR_DIS.SECURE_BOOT_EN EFUSE_BLK0 2 1 + 10 WR_DIS.UART_PRINT_CONTROL EFUSE_BLK0 3 1 + 11 WR_DIS.FORCE_SEND_RESUME EFUSE_BLK0 3 1 + 12 WR_DIS.DIS_DOWNLOAD_MODE EFUSE_BLK0 3 1 + 13 WR_DIS.DIS_DIRECT_BOOT EFUSE_BLK0 3 1 + 14 WR_DIS.ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 3 1 + 15 WR_DIS.FLASH_TPUW EFUSE_BLK0 3 1 + 16 WR_DIS.SECURE_VERSION EFUSE_BLK0 4 1 + 17 WR_DIS.CUSTOM_MAC_USED EFUSE_BLK0 4 1 + 18 WR_DIS.DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK0 4 1 + 19 WR_DIS.DISABLE_BLK_VERSION_MAJOR EFUSE_BLK0 4 1 + 20 WR_DIS.CUSTOM_MAC EFUSE_BLK0 5 1 + 21 WR_DIS.MAC EFUSE_BLK0 6 1 + 22 WR_DIS.WAFER_VERSION_MINOR EFUSE_BLK0 6 1 + 23 WR_DIS.WAFER_VERSION_MAJOR EFUSE_BLK0 6 1 + 24 WR_DIS.PKG_VERSION EFUSE_BLK0 6 1 + 25 WR_DIS.BLK_VERSION_MINOR EFUSE_BLK0 6 1 + 26 WR_DIS.BLK_VERSION_MAJOR EFUSE_BLK0 6 1 + 27 WR_DIS.OCODE EFUSE_BLK0 6 1 + 28 WR_DIS.TEMP_CALIB EFUSE_BLK0 6 1 + 29 WR_DIS.ADC1_INIT_CODE_ATTEN0 EFUSE_BLK0 6 1 + 30 WR_DIS.ADC1_INIT_CODE_ATTEN3 EFUSE_BLK0 6 1 + 31 WR_DIS.ADC1_CAL_VOL_ATTEN0 EFUSE_BLK0 6 1 + 32 WR_DIS.ADC1_CAL_VOL_ATTEN3 EFUSE_BLK0 6 1 + 33 WR_DIS.DIG_DBIAS_HVT EFUSE_BLK0 6 1 + 34 WR_DIS.DIG_LDO_SLP_DBIAS2 EFUSE_BLK0 6 1 + 35 WR_DIS.DIG_LDO_SLP_DBIAS26 EFUSE_BLK0 6 1 + 36 WR_DIS.DIG_LDO_ACT_DBIAS26 EFUSE_BLK0 6 1 + 37 WR_DIS.DIG_LDO_ACT_STEPD10 EFUSE_BLK0 6 1 + 38 WR_DIS.RTC_LDO_SLP_DBIAS13 EFUSE_BLK0 6 1 + 39 WR_DIS.RTC_LDO_SLP_DBIAS29 EFUSE_BLK0 6 1 + 40 WR_DIS.RTC_LDO_SLP_DBIAS31 EFUSE_BLK0 6 1 + 41 WR_DIS.RTC_LDO_ACT_DBIAS31 EFUSE_BLK0 6 1 + 42 WR_DIS.RTC_LDO_ACT_DBIAS13 EFUSE_BLK0 6 1 + 43 WR_DIS.ADC_CALIBRATION_3 EFUSE_BLK0 6 1 + 44 WR_DIS.BLOCK_KEY0 EFUSE_BLK0 7 1 + 45 RD_DIS EFUSE_BLK0 32 2 + 46 RD_DIS.KEY0 EFUSE_BLK0 32 2 + 47 RD_DIS.KEY0.LOW EFUSE_BLK0 32 1 + 48 RD_DIS.KEY0.HI EFUSE_BLK0 33 1 + 49 WDT_DELAY_SEL EFUSE_BLK0 34 2 + 50 DIS_PAD_JTAG EFUSE_BLK0 36 1 + 51 DIS_DOWNLOAD_ICACHE EFUSE_BLK0 37 1 + 52 DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 38 1 + 53 SPI_BOOT_CRYPT_CNT EFUSE_BLK0 39 3 + 54 XTS_KEY_LENGTH_256 EFUSE_BLK0 42 1 + 55 UART_PRINT_CONTROL EFUSE_BLK0 43 2 + 56 FORCE_SEND_RESUME EFUSE_BLK0 45 1 + 57 DIS_DOWNLOAD_MODE EFUSE_BLK0 46 1 + 58 DIS_DIRECT_BOOT EFUSE_BLK0 47 1 + 59 ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 48 1 + 60 FLASH_TPUW EFUSE_BLK0 49 4 + 61 SECURE_BOOT_EN EFUSE_BLK0 53 1 + 62 SECURE_VERSION EFUSE_BLK0 54 4 + 63 CUSTOM_MAC_USED EFUSE_BLK0 58 1 + 64 DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK0 59 1 + 65 DISABLE_BLK_VERSION_MAJOR EFUSE_BLK0 60 1 + 66 USER_DATA EFUSE_BLK1 0 88 + 67 USER_DATA.MAC_CUSTOM EFUSE_BLK1 0 48 + 68 MAC EFUSE_BLK2 0 8 + 69 MAC EFUSE_BLK2 8 8 + 70 MAC EFUSE_BLK2 16 8 + 71 MAC EFUSE_BLK2 24 8 + 72 MAC EFUSE_BLK2 32 8 + 73 MAC EFUSE_BLK2 40 8 + 74 WAFER_VERSION_MINOR EFUSE_BLK2 48 4 + 75 WAFER_VERSION_MAJOR EFUSE_BLK2 52 2 + 76 PKG_VERSION EFUSE_BLK2 54 3 + 77 BLK_VERSION_MINOR EFUSE_BLK2 57 3 + 78 BLK_VERSION_MAJOR EFUSE_BLK2 60 2 + 79 OCODE EFUSE_BLK2 62 7 + 80 TEMP_CALIB EFUSE_BLK2 69 9 + 81 ADC1_INIT_CODE_ATTEN0 EFUSE_BLK2 78 8 + 82 ADC1_INIT_CODE_ATTEN3 EFUSE_BLK2 86 5 + 83 ADC1_CAL_VOL_ATTEN0 EFUSE_BLK2 91 8 + 84 ADC1_CAL_VOL_ATTEN3 EFUSE_BLK2 99 6 + 85 DIG_DBIAS_HVT EFUSE_BLK2 105 5 + 86 DIG_LDO_SLP_DBIAS2 EFUSE_BLK2 110 7 + 87 DIG_LDO_SLP_DBIAS26 EFUSE_BLK2 117 8 + 88 DIG_LDO_ACT_DBIAS26 EFUSE_BLK2 125 6 + 89 DIG_LDO_ACT_STEPD10 EFUSE_BLK2 131 4 + 90 RTC_LDO_SLP_DBIAS13 EFUSE_BLK2 135 7 + 91 RTC_LDO_SLP_DBIAS29 EFUSE_BLK2 142 9 + 92 RTC_LDO_SLP_DBIAS31 EFUSE_BLK2 151 6 + 93 RTC_LDO_ACT_DBIAS31 EFUSE_BLK2 157 6 + 94 RTC_LDO_ACT_DBIAS13 EFUSE_BLK2 163 8 + 95 ADC_CALIBRATION_3 EFUSE_BLK2 192 11 + 96 KEY0 EFUSE_BLK3 0 256 + 97 KEY0.FE_256BIT EFUSE_BLK3 0 256 + 98 KEY0.FE_128BIT EFUSE_BLK3 0 128 + 99 KEY0.SB_128BIT EFUSE_BLK3 128 128 Used bits in efuse table: EFUSE_BLK0 - [0 7] [0 2] [2 7] [32 33] [32 33] [32 57] - + [0 7] [0 1] [1 1] [1 2] [2 2] ... [6 6] [6 6] [6 6] [6 6] [6 6] [6 6] [6 6] [6 6] [6 6] [6 7] [32 33] [32 33] [32 60] EFUSE_BLK1 [0 87] [0 47] - EFUSE_BLK2 - [0 191] - + [0 170] [192 202] EFUSE_BLK3 [0 255] [0 255] [0 255] - Note: Not printed ranges are free for using. (bits in EFUSE_BLK0 are reserved for Espressif) diff --git a/docs/en/api-reference/system/inc/show-efuse-table_ESP32-C3.rst b/docs/en/api-reference/system/inc/show-efuse-table_ESP32-C3.rst index 97a9cbb300..8cd7ae517d 100644 --- a/docs/en/api-reference/system/inc/show-efuse-table_ESP32-C3.rst +++ b/docs/en/api-reference/system/inc/show-efuse-table_ESP32-C3.rst @@ -5,164 +5,208 @@ Max number of bits in BLK 256 Sorted efuse table: - # field_name efuse_block bit_start bit_count - 1 WR_DIS EFUSE_BLK0 0 32 - 2 WR_DIS.RD_DIS EFUSE_BLK0 0 1 - 3 WR_DIS.GROUP_1 EFUSE_BLK0 2 1 - 4 WR_DIS.GROUP_2 EFUSE_BLK0 3 1 - 5 WR_DIS.SPI_BOOT_CRYPT_CNT EFUSE_BLK0 4 1 - 6 WR_DIS.SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 5 1 - 7 WR_DIS.SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 6 1 - 8 WR_DIS.SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 7 1 - 9 WR_DIS.KEY0_PURPOSE EFUSE_BLK0 8 1 - 10 WR_DIS.KEY1_PURPOSE EFUSE_BLK0 9 1 - 11 WR_DIS.KEY2_PURPOSE EFUSE_BLK0 10 1 - 12 WR_DIS.KEY3_PURPOSE EFUSE_BLK0 11 1 - 13 WR_DIS.KEY4_PURPOSE EFUSE_BLK0 12 1 - 14 WR_DIS.KEY5_PURPOSE EFUSE_BLK0 13 1 - 15 WR_DIS.SECURE_BOOT_EN EFUSE_BLK0 15 1 - 16 WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 16 1 - 17 WR_DIS.GROUP_3 EFUSE_BLK0 18 1 - 18 WR_DIS.BLK1 EFUSE_BLK0 20 1 - 19 WR_DIS.SYS_DATA_PART1 EFUSE_BLK0 21 1 - 20 WR_DIS.USER_DATA EFUSE_BLK0 22 1 - 21 WR_DIS.KEY0 EFUSE_BLK0 23 1 - 22 WR_DIS.KEY1 EFUSE_BLK0 24 1 - 23 WR_DIS.KEY2 EFUSE_BLK0 25 1 - 24 WR_DIS.KEY3 EFUSE_BLK0 26 1 - 25 WR_DIS.KEY4 EFUSE_BLK0 27 1 - 26 WR_DIS.KEY5 EFUSE_BLK0 28 1 - 27 WR_DIS.SYS_DATA_PART2 EFUSE_BLK0 29 1 - 28 RD_DIS EFUSE_BLK0 32 7 - 29 RD_DIS.KEY0 EFUSE_BLK0 32 1 - 30 RD_DIS.KEY1 EFUSE_BLK0 33 1 - 31 RD_DIS.KEY2 EFUSE_BLK0 34 1 - 32 RD_DIS.KEY3 EFUSE_BLK0 35 1 - 33 RD_DIS.KEY4 EFUSE_BLK0 36 1 - 34 RD_DIS.KEY5 EFUSE_BLK0 37 1 - 35 RD_DIS.SYS_DATA_PART2 EFUSE_BLK0 38 1 - 36 DIS_ICACHE EFUSE_BLK0 40 1 - 37 DIS_USB_JTAG EFUSE_BLK0 41 1 - 38 DIS_DOWNLOAD_ICACHE EFUSE_BLK0 42 1 - 39 DIS_USB_DEVICE EFUSE_BLK0 43 1 - 40 DIS_FORCE_DOWNLOAD EFUSE_BLK0 44 1 - 41 DIS_CAN EFUSE_BLK0 46 1 - 42 JTAG_SEL_ENABLE EFUSE_BLK0 47 1 - 43 SOFT_DIS_JTAG EFUSE_BLK0 48 3 - 44 DIS_PAD_JTAG EFUSE_BLK0 51 1 - 45 DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 52 1 - 46 USB_DREFH EFUSE_BLK0 53 2 - 47 USB_DREFL EFUSE_BLK0 55 2 - 48 USB_EXCHG_PINS EFUSE_BLK0 57 1 - 49 VDD_SPI_AS_GPIO EFUSE_BLK0 58 1 - 50 BTLC_GPIO_ENABLE EFUSE_BLK0 59 2 - 51 POWERGLITCH_EN EFUSE_BLK0 61 1 - 52 POWER_GLITCH_DSENSE EFUSE_BLK0 62 2 - 53 WDT_DELAY_SEL EFUSE_BLK0 80 2 - 54 SPI_BOOT_CRYPT_CNT EFUSE_BLK0 82 3 - 55 SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 85 1 - 56 SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 86 1 - 57 SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 87 1 - 58 KEY_PURPOSE_0 EFUSE_BLK0 88 4 - 59 KEY_PURPOSE_1 EFUSE_BLK0 92 4 - 60 KEY_PURPOSE_2 EFUSE_BLK0 96 4 - 61 KEY_PURPOSE_3 EFUSE_BLK0 100 4 - 62 KEY_PURPOSE_4 EFUSE_BLK0 104 4 - 63 KEY_PURPOSE_5 EFUSE_BLK0 108 4 - 64 SECURE_BOOT_EN EFUSE_BLK0 116 1 - 65 SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 117 1 - 66 FLASH_TPUW EFUSE_BLK0 124 4 - 67 DIS_DOWNLOAD_MODE EFUSE_BLK0 128 1 - 68 DIS_DIRECT_BOOT EFUSE_BLK0 129 1 - 69 DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 130 1 - 70 DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 132 1 - 71 ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 133 1 - 72 UART_PRINT_CONTROL EFUSE_BLK0 134 2 - 73 FORCE_SEND_RESUME EFUSE_BLK0 141 1 - 74 SECURE_VERSION EFUSE_BLK0 142 16 - 75 ERR_RST_ENABLE EFUSE_BLK0 159 1 - 76 MAC_FACTORY EFUSE_BLK1 0 8 - 77 MAC_FACTORY EFUSE_BLK1 8 8 - 78 MAC_FACTORY EFUSE_BLK1 16 8 - 79 MAC_FACTORY EFUSE_BLK1 24 8 - 80 MAC_FACTORY EFUSE_BLK1 32 8 - 81 MAC_FACTORY EFUSE_BLK1 40 8 - 82 SPI_PAD_CONFIG_CLK EFUSE_BLK1 48 6 - 83 SPI_PAD_CONFIG_Q_D1 EFUSE_BLK1 54 6 - 84 SPI_PAD_CONFIG_D_D0 EFUSE_BLK1 60 6 - 85 SPI_PAD_CONFIG_CS EFUSE_BLK1 66 6 - 86 SPI_PAD_CONFIG_HD_D3 EFUSE_BLK1 72 6 - 87 SPI_PAD_CONFIG_WP_D2 EFUSE_BLK1 78 6 - 88 SPI_PAD_CONFIG_DQS EFUSE_BLK1 84 6 - 89 SPI_PAD_CONFIG_D4 EFUSE_BLK1 90 6 - 90 SPI_PAD_CONFIG_D5 EFUSE_BLK1 96 6 - 91 SPI_PAD_CONFIG_D6 EFUSE_BLK1 102 6 - 92 SPI_PAD_CONFIG_D7 EFUSE_BLK1 108 6 - 93 WAFER_VERSION EFUSE_BLK1 114 3 - 94 PKG_VERSION EFUSE_BLK1 117 3 - 95 BLOCK1_VERSION EFUSE_BLK1 120 3 - 96 K_RTC_LDO EFUSE_BLK1 135 7 - 97 K_DIG_LDO EFUSE_BLK1 142 7 - 98 V_RTC_DBIAS20 EFUSE_BLK1 149 8 - 99 V_DIG_DBIAS20 EFUSE_BLK1 157 8 - 100 DIG_DBIAS_HVT EFUSE_BLK1 165 5 - 101 THRES_HVT EFUSE_BLK1 170 10 - 102 SYS_DATA_PART2 EFUSE_BLK10 0 256 - 103 OPTIONAL_UNIQUE_ID EFUSE_BLK2 0 128 - 104 BLOCK2_VERSION EFUSE_BLK2 128 3 - 105 TEMP_CALIB EFUSE_BLK2 131 9 - 106 OCODE EFUSE_BLK2 140 8 - 107 ADC1_INIT_CODE_ATTEN0 EFUSE_BLK2 148 10 - 108 ADC1_INIT_CODE_ATTEN1 EFUSE_BLK2 158 10 - 109 ADC1_INIT_CODE_ATTEN2 EFUSE_BLK2 168 10 - 110 ADC1_INIT_CODE_ATTEN3 EFUSE_BLK2 178 10 - 111 ADC1_CAL_VOL_ATTEN0 EFUSE_BLK2 188 10 - 112 ADC1_CAL_VOL_ATTEN1 EFUSE_BLK2 198 10 - 113 ADC1_CAL_VOL_ATTEN2 EFUSE_BLK2 208 10 - 114 ADC1_CAL_VOL_ATTEN3 EFUSE_BLK2 218 10 - 115 USER_DATA EFUSE_BLK3 0 256 - 116 USER_DATA.MAC_CUSTOM EFUSE_BLK3 200 48 - 117 KEY0 EFUSE_BLK4 0 256 - 118 KEY1 EFUSE_BLK5 0 256 - 119 KEY2 EFUSE_BLK6 0 256 - 120 KEY3 EFUSE_BLK7 0 256 - 121 KEY4 EFUSE_BLK8 0 256 - 122 KEY5 EFUSE_BLK9 0 256 + # field_name efuse_block bit_start bit_count + 1 WR_DIS EFUSE_BLK0 0 32 + 2 WR_DIS.RD_DIS EFUSE_BLK0 0 1 + 3 WR_DIS.DIS_ICACHE EFUSE_BLK0 2 1 + 4 WR_DIS.DIS_USB_JTAG EFUSE_BLK0 2 1 + 5 WR_DIS.DIS_DOWNLOAD_ICACHE EFUSE_BLK0 2 1 + 6 WR_DIS.DIS_USB_SERIAL_JTAG EFUSE_BLK0 2 1 + 7 WR_DIS.DIS_FORCE_DOWNLOAD EFUSE_BLK0 2 1 + 8 WR_DIS.DIS_TWAI EFUSE_BLK0 2 1 + 9 WR_DIS.JTAG_SEL_ENABLE EFUSE_BLK0 2 1 + 10 WR_DIS.DIS_PAD_JTAG EFUSE_BLK0 2 1 + 11 WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 2 1 + 12 WR_DIS.WDT_DELAY_SEL EFUSE_BLK0 3 1 + 13 WR_DIS.SPI_BOOT_CRYPT_CNT EFUSE_BLK0 4 1 + 14 WR_DIS.SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 5 1 + 15 WR_DIS.SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 6 1 + 16 WR_DIS.SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 7 1 + 17 WR_DIS.KEY_PURPOSE_0 EFUSE_BLK0 8 1 + 18 WR_DIS.KEY_PURPOSE_1 EFUSE_BLK0 9 1 + 19 WR_DIS.KEY_PURPOSE_2 EFUSE_BLK0 10 1 + 20 WR_DIS.KEY_PURPOSE_3 EFUSE_BLK0 11 1 + 21 WR_DIS.KEY_PURPOSE_4 EFUSE_BLK0 12 1 + 22 WR_DIS.KEY_PURPOSE_5 EFUSE_BLK0 13 1 + 23 WR_DIS.SECURE_BOOT_EN EFUSE_BLK0 15 1 + 24 WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 16 1 + 25 WR_DIS.FLASH_TPUW EFUSE_BLK0 18 1 + 26 WR_DIS.DIS_DOWNLOAD_MODE EFUSE_BLK0 18 1 + 27 WR_DIS.DIS_DIRECT_BOOT EFUSE_BLK0 18 1 + 28 WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 18 1 + 29 WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 18 1 + 30 WR_DIS.ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 18 1 + 31 WR_DIS.UART_PRINT_CONTROL EFUSE_BLK0 18 1 + 32 WR_DIS.FORCE_SEND_RESUME EFUSE_BLK0 18 1 + 33 WR_DIS.SECURE_VERSION EFUSE_BLK0 18 1 + 34 WR_DIS.ERR_RST_ENABLE EFUSE_BLK0 19 1 + 35 WR_DIS.DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK0 19 1 + 36 WR_DIS.DISABLE_BLK_VERSION_MAJOR EFUSE_BLK0 19 1 + 37 WR_DIS.BLK1 EFUSE_BLK0 20 1 + 38 WR_DIS.MAC EFUSE_BLK0 20 1 + 39 WR_DIS.SPI_PAD_CONFIG_CLK EFUSE_BLK0 20 1 + 40 WR_DIS.SPI_PAD_CONFIG_Q EFUSE_BLK0 20 1 + 41 WR_DIS.SPI_PAD_CONFIG_D EFUSE_BLK0 20 1 + 42 WR_DIS.SPI_PAD_CONFIG_CS EFUSE_BLK0 20 1 + 43 WR_DIS.SPI_PAD_CONFIG_HD EFUSE_BLK0 20 1 + 44 WR_DIS.SPI_PAD_CONFIG_WP EFUSE_BLK0 20 1 + 45 WR_DIS.SPI_PAD_CONFIG_DQS EFUSE_BLK0 20 1 + 46 WR_DIS.SPI_PAD_CONFIG_D4 EFUSE_BLK0 20 1 + 47 WR_DIS.SPI_PAD_CONFIG_D5 EFUSE_BLK0 20 1 + 48 WR_DIS.SPI_PAD_CONFIG_D6 EFUSE_BLK0 20 1 + 49 WR_DIS.SPI_PAD_CONFIG_D7 EFUSE_BLK0 20 1 + 50 WR_DIS.WAFER_VERSION_MINOR_LO EFUSE_BLK0 20 1 + 51 WR_DIS.PKG_VERSION EFUSE_BLK0 20 1 + 52 WR_DIS.BLK_VERSION_MINOR EFUSE_BLK0 20 1 + 53 WR_DIS.K_RTC_LDO EFUSE_BLK0 20 1 + 54 WR_DIS.K_DIG_LDO EFUSE_BLK0 20 1 + 55 WR_DIS.V_RTC_DBIAS20 EFUSE_BLK0 20 1 + 56 WR_DIS.V_DIG_DBIAS20 EFUSE_BLK0 20 1 + 57 WR_DIS.DIG_DBIAS_HVT EFUSE_BLK0 20 1 + 58 WR_DIS.THRES_HVT EFUSE_BLK0 20 1 + 59 WR_DIS.WAFER_VERSION_MINOR_HI EFUSE_BLK0 20 1 + 60 WR_DIS.WAFER_VERSION_MAJOR EFUSE_BLK0 20 1 + 61 WR_DIS.SYS_DATA_PART1 EFUSE_BLK0 21 1 + 62 WR_DIS.OPTIONAL_UNIQUE_ID EFUSE_BLK0 21 1 + 63 WR_DIS.BLK_VERSION_MAJOR EFUSE_BLK0 21 1 + 64 WR_DIS.TEMP_CALIB EFUSE_BLK0 21 1 + 65 WR_DIS.OCODE EFUSE_BLK0 21 1 + 66 WR_DIS.ADC1_INIT_CODE_ATTEN0 EFUSE_BLK0 21 1 + 67 WR_DIS.ADC1_INIT_CODE_ATTEN1 EFUSE_BLK0 21 1 + 68 WR_DIS.ADC1_INIT_CODE_ATTEN2 EFUSE_BLK0 21 1 + 69 WR_DIS.ADC1_INIT_CODE_ATTEN3 EFUSE_BLK0 21 1 + 70 WR_DIS.ADC1_CAL_VOL_ATTEN0 EFUSE_BLK0 21 1 + 71 WR_DIS.ADC1_CAL_VOL_ATTEN1 EFUSE_BLK0 21 1 + 72 WR_DIS.ADC1_CAL_VOL_ATTEN2 EFUSE_BLK0 21 1 + 73 WR_DIS.ADC1_CAL_VOL_ATTEN3 EFUSE_BLK0 21 1 + 74 WR_DIS.BLOCK_USR_DATA EFUSE_BLK0 22 1 + 75 WR_DIS.CUSTOM_MAC EFUSE_BLK0 22 1 + 76 WR_DIS.BLOCK_KEY0 EFUSE_BLK0 23 1 + 77 WR_DIS.BLOCK_KEY1 EFUSE_BLK0 24 1 + 78 WR_DIS.BLOCK_KEY2 EFUSE_BLK0 25 1 + 79 WR_DIS.BLOCK_KEY3 EFUSE_BLK0 26 1 + 80 WR_DIS.BLOCK_KEY4 EFUSE_BLK0 27 1 + 81 WR_DIS.BLOCK_KEY5 EFUSE_BLK0 28 1 + 82 WR_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 29 1 + 83 WR_DIS.USB_EXCHG_PINS EFUSE_BLK0 30 1 + 84 WR_DIS.VDD_SPI_AS_GPIO EFUSE_BLK0 30 1 + 85 WR_DIS.SOFT_DIS_JTAG EFUSE_BLK0 31 1 + 86 RD_DIS EFUSE_BLK0 32 7 + 87 RD_DIS.BLOCK_KEY0 EFUSE_BLK0 32 1 + 88 RD_DIS.BLOCK_KEY1 EFUSE_BLK0 33 1 + 89 RD_DIS.BLOCK_KEY2 EFUSE_BLK0 34 1 + 90 RD_DIS.BLOCK_KEY3 EFUSE_BLK0 35 1 + 91 RD_DIS.BLOCK_KEY4 EFUSE_BLK0 36 1 + 92 RD_DIS.BLOCK_KEY5 EFUSE_BLK0 37 1 + 93 RD_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 38 1 + 94 DIS_ICACHE EFUSE_BLK0 40 1 + 95 DIS_USB_JTAG EFUSE_BLK0 41 1 + 96 DIS_DOWNLOAD_ICACHE EFUSE_BLK0 42 1 + 97 DIS_USB_SERIAL_JTAG EFUSE_BLK0 43 1 + 98 DIS_FORCE_DOWNLOAD EFUSE_BLK0 44 1 + 99 DIS_TWAI EFUSE_BLK0 46 1 + 100 JTAG_SEL_ENABLE EFUSE_BLK0 47 1 + 101 SOFT_DIS_JTAG EFUSE_BLK0 48 3 + 102 DIS_PAD_JTAG EFUSE_BLK0 51 1 + 103 DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 52 1 + 104 USB_EXCHG_PINS EFUSE_BLK0 57 1 + 105 VDD_SPI_AS_GPIO EFUSE_BLK0 58 1 + 106 WDT_DELAY_SEL EFUSE_BLK0 80 2 + 107 SPI_BOOT_CRYPT_CNT EFUSE_BLK0 82 3 + 108 SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 85 1 + 109 SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 86 1 + 110 SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 87 1 + 111 KEY_PURPOSE_0 EFUSE_BLK0 88 4 + 112 KEY_PURPOSE_1 EFUSE_BLK0 92 4 + 113 KEY_PURPOSE_2 EFUSE_BLK0 96 4 + 114 KEY_PURPOSE_3 EFUSE_BLK0 100 4 + 115 KEY_PURPOSE_4 EFUSE_BLK0 104 4 + 116 KEY_PURPOSE_5 EFUSE_BLK0 108 4 + 117 SECURE_BOOT_EN EFUSE_BLK0 116 1 + 118 SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 117 1 + 119 FLASH_TPUW EFUSE_BLK0 124 4 + 120 DIS_DOWNLOAD_MODE EFUSE_BLK0 128 1 + 121 DIS_DIRECT_BOOT EFUSE_BLK0 129 1 + 122 DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 130 1 + 123 DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 132 1 + 124 ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 133 1 + 125 UART_PRINT_CONTROL EFUSE_BLK0 134 2 + 126 FORCE_SEND_RESUME EFUSE_BLK0 141 1 + 127 SECURE_VERSION EFUSE_BLK0 142 16 + 128 ERR_RST_ENABLE EFUSE_BLK0 159 1 + 129 DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK0 160 1 + 130 DISABLE_BLK_VERSION_MAJOR EFUSE_BLK0 161 1 + 131 MAC EFUSE_BLK1 0 8 + 132 MAC EFUSE_BLK1 8 8 + 133 MAC EFUSE_BLK1 16 8 + 134 MAC EFUSE_BLK1 24 8 + 135 MAC EFUSE_BLK1 32 8 + 136 MAC EFUSE_BLK1 40 8 + 137 SPI_PAD_CONFIG_CLK EFUSE_BLK1 48 6 + 138 SPI_PAD_CONFIG_Q EFUSE_BLK1 54 6 + 139 SPI_PAD_CONFIG_D EFUSE_BLK1 60 6 + 140 SPI_PAD_CONFIG_CS EFUSE_BLK1 66 6 + 141 SPI_PAD_CONFIG_HD EFUSE_BLK1 72 6 + 142 SPI_PAD_CONFIG_WP EFUSE_BLK1 78 6 + 143 SPI_PAD_CONFIG_DQS EFUSE_BLK1 84 6 + 144 SPI_PAD_CONFIG_D4 EFUSE_BLK1 90 6 + 145 SPI_PAD_CONFIG_D5 EFUSE_BLK1 96 6 + 146 SPI_PAD_CONFIG_D6 EFUSE_BLK1 102 6 + 147 SPI_PAD_CONFIG_D7 EFUSE_BLK1 108 6 + 148 WAFER_VERSION_MINOR_LO EFUSE_BLK1 114 3 + 149 PKG_VERSION EFUSE_BLK1 117 3 + 150 BLK_VERSION_MINOR EFUSE_BLK1 120 3 + 151 K_RTC_LDO EFUSE_BLK1 135 7 + 152 K_DIG_LDO EFUSE_BLK1 142 7 + 153 V_RTC_DBIAS20 EFUSE_BLK1 149 8 + 154 V_DIG_DBIAS20 EFUSE_BLK1 157 8 + 155 DIG_DBIAS_HVT EFUSE_BLK1 165 5 + 156 THRES_HVT EFUSE_BLK1 170 10 + 157 WAFER_VERSION_MINOR_HI EFUSE_BLK1 183 1 + 158 WAFER_VERSION_MAJOR EFUSE_BLK1 184 2 + 159 SYS_DATA_PART2 EFUSE_BLK10 0 256 + 160 OPTIONAL_UNIQUE_ID EFUSE_BLK2 0 128 + 161 BLK_VERSION_MAJOR EFUSE_BLK2 128 2 + 162 TEMP_CALIB EFUSE_BLK2 131 9 + 163 OCODE EFUSE_BLK2 140 8 + 164 ADC1_INIT_CODE_ATTEN0 EFUSE_BLK2 148 10 + 165 ADC1_INIT_CODE_ATTEN1 EFUSE_BLK2 158 10 + 166 ADC1_INIT_CODE_ATTEN2 EFUSE_BLK2 168 10 + 167 ADC1_INIT_CODE_ATTEN3 EFUSE_BLK2 178 10 + 168 ADC1_CAL_VOL_ATTEN0 EFUSE_BLK2 188 10 + 169 ADC1_CAL_VOL_ATTEN1 EFUSE_BLK2 198 10 + 170 ADC1_CAL_VOL_ATTEN2 EFUSE_BLK2 208 10 + 171 ADC1_CAL_VOL_ATTEN3 EFUSE_BLK2 218 10 + 172 USER_DATA EFUSE_BLK3 0 256 + 173 USER_DATA.MAC_CUSTOM EFUSE_BLK3 200 48 + 174 KEY0 EFUSE_BLK4 0 256 + 175 KEY1 EFUSE_BLK5 0 256 + 176 KEY2 EFUSE_BLK6 0 256 + 177 KEY3 EFUSE_BLK7 0 256 + 178 KEY4 EFUSE_BLK8 0 256 + 179 KEY5 EFUSE_BLK9 0 256 Used bits in efuse table: EFUSE_BLK0 - [0 31] [0 0] [2 13] [15 16] [18 18] [20 29] [32 38] [32 38] [40 44] [46 63] [80 111] [116 117] [124 130] [132 135] [141 157] [159 159] - + [0 31] [0 0] [2 2] ... [40 44] [46 52] [57 58] [80 111] [116 117] [124 130] [132 135] [141 157] [159 161] EFUSE_BLK1 - [0 122] [135 179] - + [0 122] [135 179] [183 185] EFUSE_BLK10 [0 255] - EFUSE_BLK2 - [0 227] - + [0 129] [131 227] EFUSE_BLK3 [0 255] [200 247] - EFUSE_BLK4 [0 255] - EFUSE_BLK5 [0 255] - EFUSE_BLK6 [0 255] - EFUSE_BLK7 [0 255] - EFUSE_BLK8 [0 255] - EFUSE_BLK9 [0 255] - Note: Not printed ranges are free for using. (bits in EFUSE_BLK0 are reserved for Espressif) - Parsing efuse CSV input file $IDF_PATH/components/efuse/esp32c3/esp_efuse_table.csv ... - Verifying efuse table... \ No newline at end of file diff --git a/docs/en/api-reference/system/inc/show-efuse-table_ESP32-C6.rst b/docs/en/api-reference/system/inc/show-efuse-table_ESP32-C6.rst index 55f67a6321..b9af8bd062 100644 --- a/docs/en/api-reference/system/inc/show-efuse-table_ESP32-C6.rst +++ b/docs/en/api-reference/system/inc/show-efuse-table_ESP32-C6.rst @@ -7,168 +7,168 @@ Parsing efuse CSV input file esp32c6/esp_efuse_table.csv ... Verifying efuse table... Sorted efuse table: - # field_name efuse_block bit_start bit_count - 1 WR_DIS EFUSE_BLK0 0 32 - 2 WR_DIS.RD_DIS EFUSE_BLK0 0 1 - 3 WR_DIS.SWAP_UART_SDIO_EN EFUSE_BLK0 1 1 - 4 WR_DIS.GROUP_1 EFUSE_BLK0 2 1 - 5 WR_DIS.GROUP_2 EFUSE_BLK0 3 1 - 6 WR_DIS.SPI_BOOT_CRYPT_CNT EFUSE_BLK0 4 1 - 7 WR_DIS.SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 5 1 - 8 WR_DIS.SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 6 1 - 9 WR_DIS.SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 7 1 - 10 WR_DIS.KEY0_PURPOSE EFUSE_BLK0 8 1 - 11 WR_DIS.KEY1_PURPOSE EFUSE_BLK0 9 1 - 12 WR_DIS.KEY2_PURPOSE EFUSE_BLK0 10 1 - 13 WR_DIS.KEY3_PURPOSE EFUSE_BLK0 11 1 - 14 WR_DIS.KEY4_PURPOSE EFUSE_BLK0 12 1 - 15 WR_DIS.KEY5_PURPOSE EFUSE_BLK0 13 1 - 16 WR_DIS.SEC_DPA_LEVEL EFUSE_BLK0 14 1 - 17 WR_DIS.SECURE_BOOT_EN EFUSE_BLK0 15 1 - 18 WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 16 1 - 19 WR_DIS.GROUP_3 EFUSE_BLK0 18 1 - 20 WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE EFUSE_BLK0 19 1 - 21 WR_DIS.BLK1 EFUSE_BLK0 20 1 - 22 WR_DIS.SYS_DATA_PART1 EFUSE_BLK0 21 1 - 23 WR_DIS.USER_DATA EFUSE_BLK0 22 1 - 24 WR_DIS.KEY0 EFUSE_BLK0 23 1 - 25 WR_DIS.KEY1 EFUSE_BLK0 24 1 - 26 WR_DIS.KEY2 EFUSE_BLK0 25 1 - 27 WR_DIS.KEY3 EFUSE_BLK0 26 1 - 28 WR_DIS.KEY4 EFUSE_BLK0 27 1 - 29 WR_DIS.KEY5 EFUSE_BLK0 28 1 - 30 WR_DIS.SYS_DATA_PART2 EFUSE_BLK0 29 1 - 31 RD_DIS EFUSE_BLK0 32 7 - 32 RD_DIS.KEY0 EFUSE_BLK0 32 1 - 33 RD_DIS.KEY1 EFUSE_BLK0 33 1 - 34 RD_DIS.KEY2 EFUSE_BLK0 34 1 - 35 RD_DIS.KEY3 EFUSE_BLK0 35 1 - 36 RD_DIS.KEY4 EFUSE_BLK0 36 1 - 37 RD_DIS.KEY5 EFUSE_BLK0 37 1 - 38 RD_DIS.SYS_DATA_PART2 EFUSE_BLK0 38 1 - 39 SWAP_UART_SDIO_EN EFUSE_BLK0 39 1 - 40 DIS_ICACHE EFUSE_BLK0 40 1 - 41 DIS_USB_JTAG EFUSE_BLK0 41 1 - 42 DIS_DOWNLOAD_ICACHE EFUSE_BLK0 42 1 - 43 DIS_USB_SERIAL_JTAG EFUSE_BLK0 43 1 - 44 DIS_FORCE_DOWNLOAD EFUSE_BLK0 44 1 - 45 DIS_SPI_DOWNLOAD_MSPI EFUSE_BLK0 45 1 - 46 DIS_TWAI EFUSE_BLK0 46 1 - 47 JTAG_SEL_ENABLE EFUSE_BLK0 47 1 - 48 SOFT_DIS_JTAG EFUSE_BLK0 48 3 - 49 DIS_PAD_JTAG EFUSE_BLK0 51 1 - 50 DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 52 1 - 51 USB_EXCHG_PINS EFUSE_BLK0 57 1 - 52 VDD_SPI_AS_GPIO EFUSE_BLK0 58 1 - 53 WDT_DELAY_SEL EFUSE_BLK0 80 2 - 54 SPI_BOOT_CRYPT_CNT EFUSE_BLK0 82 3 - 55 SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 85 1 - 56 SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 86 1 - 57 SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 87 1 - 58 KEY_PURPOSE_0 EFUSE_BLK0 88 4 - 59 KEY_PURPOSE_1 EFUSE_BLK0 92 4 - 60 KEY_PURPOSE_2 EFUSE_BLK0 96 4 - 61 KEY_PURPOSE_3 EFUSE_BLK0 100 4 - 62 KEY_PURPOSE_4 EFUSE_BLK0 104 4 - 63 KEY_PURPOSE_5 EFUSE_BLK0 108 4 - 64 SEC_DPA_LEVEL EFUSE_BLK0 112 2 - 65 CRYPT_DPA_ENABLE EFUSE_BLK0 115 1 - 66 SECURE_BOOT_EN EFUSE_BLK0 116 1 - 67 SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 117 1 - 68 FLASH_TPUW EFUSE_BLK0 124 4 - 69 DIS_DOWNLOAD_MODE EFUSE_BLK0 128 1 - 70 DIS_DIRECT_BOOT EFUSE_BLK0 129 1 - 71 DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 130 1 - 72 DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 132 1 - 73 ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 133 1 - 74 UART_PRINT_CONTROL EFUSE_BLK0 134 2 - 75 FORCE_SEND_RESUME EFUSE_BLK0 141 1 - 76 SECURE_VERSION EFUSE_BLK0 142 16 - 77 SECURE_BOOT_DISABLE_FAST_WAKE EFUSE_BLK0 158 1 - 78 DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK0 160 1 - 79 DISABLE_BLK_VERSION_MAJOR EFUSE_BLK0 161 1 - 80 MAC_FACTORY EFUSE_BLK1 0 8 - 81 MAC_FACTORY EFUSE_BLK1 8 8 - 82 MAC_FACTORY EFUSE_BLK1 16 8 - 83 MAC_FACTORY EFUSE_BLK1 24 8 - 84 MAC_FACTORY EFUSE_BLK1 32 8 - 85 MAC_FACTORY EFUSE_BLK1 40 8 - 86 SPI_PAD_CONFIG_CLK EFUSE_BLK1 48 6 - 87 SPI_PAD_CONFIG_Q_D1 EFUSE_BLK1 54 6 - 88 SPI_PAD_CONFIG_D_D0 EFUSE_BLK1 60 6 - 89 SPI_PAD_CONFIG_CS EFUSE_BLK1 66 6 - 90 SPI_PAD_CONFIG_HD_D3 EFUSE_BLK1 72 6 - 91 SPI_PAD_CONFIG_WP_D2 EFUSE_BLK1 78 6 - 92 SPI_PAD_CONFIG_DQS EFUSE_BLK1 84 6 - 93 SPI_PAD_CONFIG_D4 EFUSE_BLK1 90 6 - 94 SPI_PAD_CONFIG_D5 EFUSE_BLK1 96 6 - 95 SPI_PAD_CONFIG_D6 EFUSE_BLK1 102 6 - 96 SPI_PAD_CONFIG_D7 EFUSE_BLK1 108 6 - 97 WAFER_VERSION_MINOR EFUSE_BLK1 114 3 - 98 PKG_VERSION EFUSE_BLK1 117 3 - 99 BLK_VERSION_MINOR EFUSE_BLK1 120 3 - 100 K_RTC_LDO EFUSE_BLK1 135 7 - 101 K_DIG_LDO EFUSE_BLK1 142 7 - 102 V_RTC_DBIAS20 EFUSE_BLK1 149 8 - 103 V_DIG_DBIAS20 EFUSE_BLK1 157 8 - 104 DIG_DBIAS_HVT EFUSE_BLK1 165 5 - 105 THRES_HVT EFUSE_BLK1 170 10 - 106 WAFER_VERSION_MINOR EFUSE_BLK1 183 1 - 107 WAFER_VERSION_MAJOR EFUSE_BLK1 184 2 - 108 SYS_DATA_PART2 EFUSE_BLK10 0 256 - 109 OPTIONAL_UNIQUE_ID EFUSE_BLK2 0 128 - 110 BLK_VERSION_MAJOR EFUSE_BLK2 128 2 - 111 TEMP_CALIB EFUSE_BLK2 131 9 - 112 OCODE EFUSE_BLK2 140 8 - 113 ADC1_INIT_CODE_ATTEN0 EFUSE_BLK2 148 10 - 114 ADC1_INIT_CODE_ATTEN1 EFUSE_BLK2 158 10 - 115 ADC1_INIT_CODE_ATTEN2 EFUSE_BLK2 168 10 - 116 ADC1_INIT_CODE_ATTEN3 EFUSE_BLK2 178 10 - 117 ADC1_CAL_VOL_ATTEN0 EFUSE_BLK2 188 10 - 118 ADC1_CAL_VOL_ATTEN1 EFUSE_BLK2 198 10 - 119 ADC1_CAL_VOL_ATTEN2 EFUSE_BLK2 208 10 - 120 ADC1_CAL_VOL_ATTEN3 EFUSE_BLK2 218 10 - 121 USER_DATA EFUSE_BLK3 0 256 - 122 USER_DATA.MAC_CUSTOM EFUSE_BLK3 200 48 - 123 KEY0 EFUSE_BLK4 0 256 - 124 KEY1 EFUSE_BLK5 0 256 - 125 KEY2 EFUSE_BLK6 0 256 - 126 KEY3 EFUSE_BLK7 0 256 - 127 KEY4 EFUSE_BLK8 0 256 - 128 KEY5 EFUSE_BLK9 0 256 + # field_name efuse_block bit_start bit_count + 1 WR_DIS EFUSE_BLK0 0 32 + 2 WR_DIS.RD_DIS EFUSE_BLK0 0 1 + 3 WR_DIS.CRYPT_DPA_ENABLE EFUSE_BLK0 1 1 + 4 WR_DIS.SWAP_UART_SDIO_EN EFUSE_BLK0 2 1 + 5 WR_DIS.DIS_ICACHE EFUSE_BLK0 2 1 + 6 WR_DIS.DIS_USB_JTAG EFUSE_BLK0 2 1 + 7 WR_DIS.DIS_DOWNLOAD_ICACHE EFUSE_BLK0 2 1 + 8 WR_DIS.DIS_USB_SERIAL_JTAG EFUSE_BLK0 2 1 + 9 WR_DIS.DIS_FORCE_DOWNLOAD EFUSE_BLK0 2 1 + 10 WR_DIS.DIS_TWAI EFUSE_BLK0 2 1 + 11 WR_DIS.JTAG_SEL_ENABLE EFUSE_BLK0 2 1 + 12 WR_DIS.DIS_PAD_JTAG EFUSE_BLK0 2 1 + 13 WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 2 1 + 14 WR_DIS.WDT_DELAY_SEL EFUSE_BLK0 3 1 + 15 WR_DIS.SPI_BOOT_CRYPT_CNT EFUSE_BLK0 4 1 + 16 WR_DIS.SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 5 1 + 17 WR_DIS.SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 6 1 + 18 WR_DIS.SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 7 1 + 19 WR_DIS.KEY_PURPOSE_0 EFUSE_BLK0 8 1 + 20 WR_DIS.KEY_PURPOSE_1 EFUSE_BLK0 9 1 + 21 WR_DIS.KEY_PURPOSE_2 EFUSE_BLK0 10 1 + 22 WR_DIS.KEY_PURPOSE_3 EFUSE_BLK0 11 1 + 23 WR_DIS.KEY_PURPOSE_4 EFUSE_BLK0 12 1 + 24 WR_DIS.KEY_PURPOSE_5 EFUSE_BLK0 13 1 + 25 WR_DIS.SEC_DPA_LEVEL EFUSE_BLK0 14 1 + 26 WR_DIS.SECURE_BOOT_EN EFUSE_BLK0 15 1 + 27 WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 16 1 + 28 WR_DIS.SPI_DOWNLOAD_MSPI_DIS EFUSE_BLK0 17 1 + 29 WR_DIS.FLASH_TPUW EFUSE_BLK0 18 1 + 30 WR_DIS.DIS_DOWNLOAD_MODE EFUSE_BLK0 18 1 + 31 WR_DIS.DIS_DIRECT_BOOT EFUSE_BLK0 18 1 + 32 WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 18 1 + 33 WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 18 1 + 34 WR_DIS.ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 18 1 + 35 WR_DIS.UART_PRINT_CONTROL EFUSE_BLK0 18 1 + 36 WR_DIS.FORCE_SEND_RESUME EFUSE_BLK0 18 1 + 37 WR_DIS.SECURE_VERSION EFUSE_BLK0 18 1 + 38 WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE EFUSE_BLK0 19 1 + 39 WR_DIS.DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK0 19 1 + 40 WR_DIS.DISABLE_BLK_VERSION_MAJOR EFUSE_BLK0 19 1 + 41 WR_DIS.BLK1 EFUSE_BLK0 20 1 + 42 WR_DIS.MAC EFUSE_BLK0 20 1 + 43 WR_DIS.MAC_EXT EFUSE_BLK0 20 1 + 44 WR_DIS.WAFER_VERSION_MINOR EFUSE_BLK0 20 1 + 45 WR_DIS.WAFER_VERSION_MAJOR EFUSE_BLK0 20 1 + 46 WR_DIS.PKG_VERSION EFUSE_BLK0 20 1 + 47 WR_DIS.BLK_VERSION_MINOR EFUSE_BLK0 20 1 + 48 WR_DIS.BLK_VERSION_MAJOR EFUSE_BLK0 20 1 + 49 WR_DIS.FLASH_CAP EFUSE_BLK0 20 1 + 50 WR_DIS.FLASH_TEMP EFUSE_BLK0 20 1 + 51 WR_DIS.FLASH_VENDOR EFUSE_BLK0 20 1 + 52 WR_DIS.SYS_DATA_PART1 EFUSE_BLK0 21 1 + 53 WR_DIS.OPTIONAL_UNIQUE_ID EFUSE_BLK0 21 1 + 54 WR_DIS.BLOCK_USR_DATA EFUSE_BLK0 22 1 + 55 WR_DIS.CUSTOM_MAC EFUSE_BLK0 22 1 + 56 WR_DIS.BLOCK_KEY0 EFUSE_BLK0 23 1 + 57 WR_DIS.BLOCK_KEY1 EFUSE_BLK0 24 1 + 58 WR_DIS.BLOCK_KEY2 EFUSE_BLK0 25 1 + 59 WR_DIS.BLOCK_KEY3 EFUSE_BLK0 26 1 + 60 WR_DIS.BLOCK_KEY4 EFUSE_BLK0 27 1 + 61 WR_DIS.BLOCK_KEY5 EFUSE_BLK0 28 1 + 62 WR_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 29 1 + 63 WR_DIS.USB_EXCHG_PINS EFUSE_BLK0 30 1 + 64 WR_DIS.VDD_SPI_AS_GPIO EFUSE_BLK0 30 1 + 65 WR_DIS.SOFT_DIS_JTAG EFUSE_BLK0 31 1 + 66 RD_DIS EFUSE_BLK0 32 7 + 67 RD_DIS.BLOCK_KEY0 EFUSE_BLK0 32 1 + 68 RD_DIS.BLOCK_KEY1 EFUSE_BLK0 33 1 + 69 RD_DIS.BLOCK_KEY2 EFUSE_BLK0 34 1 + 70 RD_DIS.BLOCK_KEY3 EFUSE_BLK0 35 1 + 71 RD_DIS.BLOCK_KEY4 EFUSE_BLK0 36 1 + 72 RD_DIS.BLOCK_KEY5 EFUSE_BLK0 37 1 + 73 RD_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 38 1 + 74 SWAP_UART_SDIO_EN EFUSE_BLK0 39 1 + 75 DIS_ICACHE EFUSE_BLK0 40 1 + 76 DIS_USB_JTAG EFUSE_BLK0 41 1 + 77 DIS_DOWNLOAD_ICACHE EFUSE_BLK0 42 1 + 78 DIS_USB_SERIAL_JTAG EFUSE_BLK0 43 1 + 79 DIS_FORCE_DOWNLOAD EFUSE_BLK0 44 1 + 80 SPI_DOWNLOAD_MSPI_DIS EFUSE_BLK0 45 1 + 81 DIS_TWAI EFUSE_BLK0 46 1 + 82 JTAG_SEL_ENABLE EFUSE_BLK0 47 1 + 83 SOFT_DIS_JTAG EFUSE_BLK0 48 3 + 84 DIS_PAD_JTAG EFUSE_BLK0 51 1 + 85 DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 52 1 + 86 USB_EXCHG_PINS EFUSE_BLK0 57 1 + 87 VDD_SPI_AS_GPIO EFUSE_BLK0 58 1 + 88 WDT_DELAY_SEL EFUSE_BLK0 80 2 + 89 SPI_BOOT_CRYPT_CNT EFUSE_BLK0 82 3 + 90 SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 85 1 + 91 SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 86 1 + 92 SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 87 1 + 93 KEY_PURPOSE_0 EFUSE_BLK0 88 4 + 94 KEY_PURPOSE_1 EFUSE_BLK0 92 4 + 95 KEY_PURPOSE_2 EFUSE_BLK0 96 4 + 96 KEY_PURPOSE_3 EFUSE_BLK0 100 4 + 97 KEY_PURPOSE_4 EFUSE_BLK0 104 4 + 98 KEY_PURPOSE_5 EFUSE_BLK0 108 4 + 99 SEC_DPA_LEVEL EFUSE_BLK0 112 2 + 100 CRYPT_DPA_ENABLE EFUSE_BLK0 114 1 + 101 SECURE_BOOT_EN EFUSE_BLK0 116 1 + 102 SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 117 1 + 103 FLASH_TPUW EFUSE_BLK0 124 4 + 104 DIS_DOWNLOAD_MODE EFUSE_BLK0 128 1 + 105 DIS_DIRECT_BOOT EFUSE_BLK0 129 1 + 106 DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 130 1 + 107 DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 132 1 + 108 ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 133 1 + 109 UART_PRINT_CONTROL EFUSE_BLK0 134 2 + 110 FORCE_SEND_RESUME EFUSE_BLK0 141 1 + 111 SECURE_VERSION EFUSE_BLK0 142 16 + 112 SECURE_BOOT_DISABLE_FAST_WAKE EFUSE_BLK0 158 1 + 113 DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK0 160 1 + 114 DISABLE_BLK_VERSION_MAJOR EFUSE_BLK0 161 1 + 115 MAC EFUSE_BLK1 0 8 + 116 MAC EFUSE_BLK1 8 8 + 117 MAC EFUSE_BLK1 16 8 + 118 MAC EFUSE_BLK1 24 8 + 119 MAC EFUSE_BLK1 32 8 + 120 MAC EFUSE_BLK1 40 8 + 121 MAC_EXT EFUSE_BLK1 48 16 + 122 WAFER_VERSION_MINOR EFUSE_BLK1 114 4 + 123 WAFER_VERSION_MAJOR EFUSE_BLK1 118 2 + 124 PKG_VERSION EFUSE_BLK1 120 3 + 125 BLK_VERSION_MINOR EFUSE_BLK1 123 3 + 126 BLK_VERSION_MAJOR EFUSE_BLK1 126 2 + 127 FLASH_CAP EFUSE_BLK1 128 3 + 128 FLASH_TEMP EFUSE_BLK1 131 2 + 129 FLASH_VENDOR EFUSE_BLK1 133 3 + 130 SYS_DATA_PART2 EFUSE_BLK10 0 256 + 131 OPTIONAL_UNIQUE_ID EFUSE_BLK2 0 128 + 132 USER_DATA EFUSE_BLK3 0 256 + 133 USER_DATA.MAC_CUSTOM EFUSE_BLK3 200 48 + 134 KEY0 EFUSE_BLK4 0 256 + 135 KEY1 EFUSE_BLK5 0 256 + 136 KEY2 EFUSE_BLK6 0 256 + 137 KEY3 EFUSE_BLK7 0 256 + 138 KEY4 EFUSE_BLK8 0 256 + 139 KEY5 EFUSE_BLK9 0 256 Used bits in efuse table: EFUSE_BLK0 - [0 31] [0 16] [18 29] [32 38] [32 52] [57 58] [80 113] [115 117] [124 130] [132 135] [141 158] [160 161] - + [0 31] [0 2] [2 2] ... [30 38] [32 52] [57 58] [80 114] [116 117] [124 130] [132 135] [141 158] [160 161] EFUSE_BLK1 - [0 122] [135 179] [183 185] - + [0 63] [114 135] EFUSE_BLK10 [0 255] - EFUSE_BLK2 - [0 129] [131 227] - + [0 127] EFUSE_BLK3 [0 255] [200 247] - EFUSE_BLK4 [0 255] - EFUSE_BLK5 [0 255] - EFUSE_BLK6 [0 255] - EFUSE_BLK7 [0 255] - EFUSE_BLK8 [0 255] - EFUSE_BLK9 [0 255] - Note: Not printed ranges are free for using. (bits in EFUSE_BLK0 are reserved for Espressif) diff --git a/docs/en/api-reference/system/inc/show-efuse-table_ESP32-H2.rst b/docs/en/api-reference/system/inc/show-efuse-table_ESP32-H2.rst index 5eb6007d56..67c5d0b13d 100644 --- a/docs/en/api-reference/system/inc/show-efuse-table_ESP32-H2.rst +++ b/docs/en/api-reference/system/inc/show-efuse-table_ESP32-H2.rst @@ -1,4 +1,177 @@ .. code-block:: none - TO BE UPDATED + $ ./efuse_table_gen.py -t IDF_TARGET_PATH_NAME {IDF_TARGET_PATH_NAME}/esp_efuse_table.csv --info + + Max number of bits in BLK 256 + Parsing efuse CSV input file esp32c6/esp_efuse_table.csv ... + Verifying efuse table... + Sorted efuse table: + # field_name efuse_block bit_start bit_count + 1 WR_DIS EFUSE_BLK0 0 32 + 2 WR_DIS.RD_DIS EFUSE_BLK0 0 1 + 3 WR_DIS.DIS_ICACHE EFUSE_BLK0 2 1 + 4 WR_DIS.DIS_USB_JTAG EFUSE_BLK0 2 1 + 5 WR_DIS.POWERGLITCH_EN EFUSE_BLK0 2 1 + 6 WR_DIS.DIS_FORCE_DOWNLOAD EFUSE_BLK0 2 1 + 7 WR_DIS.SPI_DOWNLOAD_MSPI_DIS EFUSE_BLK0 2 1 + 8 WR_DIS.DIS_TWAI EFUSE_BLK0 2 1 + 9 WR_DIS.JTAG_SEL_ENABLE EFUSE_BLK0 2 1 + 10 WR_DIS.DIS_PAD_JTAG EFUSE_BLK0 2 1 + 11 WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 2 1 + 12 WR_DIS.WDT_DELAY_SEL EFUSE_BLK0 3 1 + 13 WR_DIS.SPI_BOOT_CRYPT_CNT EFUSE_BLK0 4 1 + 14 WR_DIS.SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 5 1 + 15 WR_DIS.SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 6 1 + 16 WR_DIS.SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 7 1 + 17 WR_DIS.KEY_PURPOSE_0 EFUSE_BLK0 8 1 + 18 WR_DIS.KEY_PURPOSE_1 EFUSE_BLK0 9 1 + 19 WR_DIS.KEY_PURPOSE_2 EFUSE_BLK0 10 1 + 20 WR_DIS.KEY_PURPOSE_3 EFUSE_BLK0 11 1 + 21 WR_DIS.KEY_PURPOSE_4 EFUSE_BLK0 12 1 + 22 WR_DIS.KEY_PURPOSE_5 EFUSE_BLK0 13 1 + 23 WR_DIS.SEC_DPA_LEVEL EFUSE_BLK0 14 1 + 24 WR_DIS.CRYPT_DPA_ENABLE EFUSE_BLK0 14 1 + 25 WR_DIS.SECURE_BOOT_EN EFUSE_BLK0 15 1 + 26 WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 16 1 + 27 WR_DIS.ECDSA_FORCE_USE_HARDWARE_K EFUSE_BLK0 17 1 + 28 WR_DIS.FLASH_TPUW EFUSE_BLK0 18 1 + 29 WR_DIS.DIS_DOWNLOAD_MODE EFUSE_BLK0 18 1 + 30 WR_DIS.DIS_DIRECT_BOOT EFUSE_BLK0 18 1 + 31 WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 18 1 + 32 WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 18 1 + 33 WR_DIS.ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 18 1 + 34 WR_DIS.UART_PRINT_CONTROL EFUSE_BLK0 18 1 + 35 WR_DIS.FORCE_SEND_RESUME EFUSE_BLK0 18 1 + 36 WR_DIS.SECURE_VERSION EFUSE_BLK0 18 1 + 37 WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE EFUSE_BLK0 18 1 + 38 WR_DIS.HYS_EN_PAD0 EFUSE_BLK0 19 1 + 39 WR_DIS.HYS_EN_PAD1 EFUSE_BLK0 19 1 + 40 WR_DIS.BLK1 EFUSE_BLK0 20 1 + 41 WR_DIS.MAC EFUSE_BLK0 20 1 + 42 WR_DIS.MAC_EXT EFUSE_BLK0 20 1 + 43 WR_DIS.WAFER_VERSION_MINOR EFUSE_BLK0 20 1 + 44 WR_DIS.WAFER_VERSION_MAJOR EFUSE_BLK0 20 1 + 45 WR_DIS.DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK0 20 1 + 46 WR_DIS.FLASH_CAP EFUSE_BLK0 20 1 + 47 WR_DIS.FLASH_TEMP EFUSE_BLK0 20 1 + 48 WR_DIS.FLASH_VENDOR EFUSE_BLK0 20 1 + 49 WR_DIS.PKG_VERSION EFUSE_BLK0 20 1 + 50 WR_DIS.SYS_DATA_PART1 EFUSE_BLK0 21 1 + 51 WR_DIS.OPTIONAL_UNIQUE_ID EFUSE_BLK0 21 1 + 52 WR_DIS.BLK_VERSION_MINOR EFUSE_BLK0 21 1 + 53 WR_DIS.BLK_VERSION_MAJOR EFUSE_BLK0 21 1 + 54 WR_DIS.DISABLE_BLK_VERSION_MAJOR EFUSE_BLK0 21 1 + 55 WR_DIS.BLOCK_USR_DATA EFUSE_BLK0 22 1 + 56 WR_DIS.CUSTOM_MAC EFUSE_BLK0 22 1 + 57 WR_DIS.BLOCK_KEY0 EFUSE_BLK0 23 1 + 58 WR_DIS.BLOCK_KEY1 EFUSE_BLK0 24 1 + 59 WR_DIS.BLOCK_KEY2 EFUSE_BLK0 25 1 + 60 WR_DIS.BLOCK_KEY3 EFUSE_BLK0 26 1 + 61 WR_DIS.BLOCK_KEY4 EFUSE_BLK0 27 1 + 62 WR_DIS.BLOCK_KEY5 EFUSE_BLK0 28 1 + 63 WR_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 29 1 + 64 WR_DIS.USB_EXCHG_PINS EFUSE_BLK0 30 1 + 65 WR_DIS.VDD_SPI_AS_GPIO EFUSE_BLK0 30 1 + 66 WR_DIS.SOFT_DIS_JTAG EFUSE_BLK0 31 1 + 67 RD_DIS EFUSE_BLK0 32 7 + 68 RD_DIS.BLOCK_KEY0 EFUSE_BLK0 32 1 + 69 RD_DIS.BLOCK_KEY1 EFUSE_BLK0 33 1 + 70 RD_DIS.BLOCK_KEY2 EFUSE_BLK0 34 1 + 71 RD_DIS.BLOCK_KEY3 EFUSE_BLK0 35 1 + 72 RD_DIS.BLOCK_KEY4 EFUSE_BLK0 36 1 + 73 RD_DIS.BLOCK_KEY5 EFUSE_BLK0 37 1 + 74 RD_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 38 1 + 75 DIS_ICACHE EFUSE_BLK0 40 1 + 76 DIS_USB_JTAG EFUSE_BLK0 41 1 + 77 POWERGLITCH_EN EFUSE_BLK0 42 1 + 78 DIS_FORCE_DOWNLOAD EFUSE_BLK0 44 1 + 79 SPI_DOWNLOAD_MSPI_DIS EFUSE_BLK0 45 1 + 80 DIS_TWAI EFUSE_BLK0 46 1 + 81 JTAG_SEL_ENABLE EFUSE_BLK0 47 1 + 82 SOFT_DIS_JTAG EFUSE_BLK0 48 3 + 83 DIS_PAD_JTAG EFUSE_BLK0 51 1 + 84 DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 52 1 + 85 USB_EXCHG_PINS EFUSE_BLK0 57 1 + 86 VDD_SPI_AS_GPIO EFUSE_BLK0 58 1 + 87 WDT_DELAY_SEL EFUSE_BLK0 80 2 + 88 SPI_BOOT_CRYPT_CNT EFUSE_BLK0 82 3 + 89 SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 85 1 + 90 SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 86 1 + 91 SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 87 1 + 92 KEY_PURPOSE_0 EFUSE_BLK0 88 4 + 93 KEY_PURPOSE_1 EFUSE_BLK0 92 4 + 94 KEY_PURPOSE_2 EFUSE_BLK0 96 4 + 95 KEY_PURPOSE_3 EFUSE_BLK0 100 4 + 96 KEY_PURPOSE_4 EFUSE_BLK0 104 4 + 97 KEY_PURPOSE_5 EFUSE_BLK0 108 4 + 98 SEC_DPA_LEVEL EFUSE_BLK0 112 2 + 99 ECDSA_FORCE_USE_HARDWARE_K EFUSE_BLK0 114 1 + 100 CRYPT_DPA_ENABLE EFUSE_BLK0 115 1 + 101 SECURE_BOOT_EN EFUSE_BLK0 116 1 + 102 SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 117 1 + 103 FLASH_TPUW EFUSE_BLK0 124 4 + 104 DIS_DOWNLOAD_MODE EFUSE_BLK0 128 1 + 105 DIS_DIRECT_BOOT EFUSE_BLK0 129 1 + 106 DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 130 1 + 107 DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 132 1 + 108 ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 133 1 + 109 UART_PRINT_CONTROL EFUSE_BLK0 134 2 + 110 FORCE_SEND_RESUME EFUSE_BLK0 136 1 + 111 SECURE_VERSION EFUSE_BLK0 137 16 + 112 SECURE_BOOT_DISABLE_FAST_WAKE EFUSE_BLK0 153 1 + 113 HYS_EN_PAD0 EFUSE_BLK0 154 6 + 114 HYS_EN_PAD1 EFUSE_BLK0 160 22 + 115 MAC EFUSE_BLK1 0 8 + 116 MAC EFUSE_BLK1 8 8 + 117 MAC EFUSE_BLK1 16 8 + 118 MAC EFUSE_BLK1 24 8 + 119 MAC EFUSE_BLK1 32 8 + 120 MAC EFUSE_BLK1 40 8 + 121 MAC_EXT EFUSE_BLK1 48 16 + 122 WAFER_VERSION_MINOR EFUSE_BLK1 114 3 + 123 WAFER_VERSION_MAJOR EFUSE_BLK1 117 2 + 124 DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK1 119 1 + 125 FLASH_CAP EFUSE_BLK1 120 3 + 126 FLASH_TEMP EFUSE_BLK1 123 2 + 127 FLASH_VENDOR EFUSE_BLK1 125 3 + 128 PKG_VERSION EFUSE_BLK1 128 3 + 129 SYS_DATA_PART2 EFUSE_BLK10 0 256 + 130 OPTIONAL_UNIQUE_ID EFUSE_BLK2 0 128 + 131 BLK_VERSION_MINOR EFUSE_BLK2 130 3 + 132 BLK_VERSION_MAJOR EFUSE_BLK2 133 2 + 133 DISABLE_BLK_VERSION_MAJOR EFUSE_BLK2 135 1 + 134 USER_DATA EFUSE_BLK3 0 256 + 135 USER_DATA.MAC_CUSTOM EFUSE_BLK3 200 48 + 136 KEY0 EFUSE_BLK4 0 256 + 137 KEY1 EFUSE_BLK5 0 256 + 138 KEY2 EFUSE_BLK6 0 256 + 139 KEY3 EFUSE_BLK7 0 256 + 140 KEY4 EFUSE_BLK8 0 256 + 141 KEY5 EFUSE_BLK9 0 256 + + Used bits in efuse table: + EFUSE_BLK0 + [0 31] [0 0] [2 2] ... [21 22] [22 30] [30 38] [32 38] [40 42] [44 52] [57 58] [80 117] [124 130] [132 181] + EFUSE_BLK1 + [0 63] [114 130] + EFUSE_BLK10 + [0 255] + EFUSE_BLK2 + [0 127] [130 135] + EFUSE_BLK3 + [0 255] [200 247] + EFUSE_BLK4 + [0 255] + EFUSE_BLK5 + [0 255] + EFUSE_BLK6 + [0 255] + EFUSE_BLK7 + [0 255] + EFUSE_BLK8 + [0 255] + EFUSE_BLK9 + [0 255] + Note: Not printed ranges are free for using. (bits in EFUSE_BLK0 are reserved for Espressif) + diff --git a/docs/en/api-reference/system/inc/show-efuse-table_ESP32-S2.rst b/docs/en/api-reference/system/inc/show-efuse-table_ESP32-S2.rst index 53d4632639..dbd7d53958 100644 --- a/docs/en/api-reference/system/inc/show-efuse-table_ESP32-S2.rst +++ b/docs/en/api-reference/system/inc/show-efuse-table_ESP32-S2.rst @@ -10,149 +10,225 @@ # field_name efuse_block bit_start bit_count 1 WR_DIS EFUSE_BLK0 0 32 2 WR_DIS.RD_DIS EFUSE_BLK0 0 1 - 3 WR_DIS.DIS_RTC_RAM_BOOT EFUSE_BLK0 1 1 - 4 WR_DIS.GROUP_1 EFUSE_BLK0 2 1 - 5 WR_DIS.GROUP_2 EFUSE_BLK0 3 1 - 6 WR_DIS.SPI_BOOT_CRYPT_CNT EFUSE_BLK0 4 1 - 7 WR_DIS.SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 5 1 - 8 WR_DIS.SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 6 1 - 9 WR_DIS.SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 7 1 - 10 WR_DIS.KEY0_PURPOSE EFUSE_BLK0 8 1 - 11 WR_DIS.KEY1_PURPOSE EFUSE_BLK0 9 1 - 12 WR_DIS.KEY2_PURPOSE EFUSE_BLK0 10 1 - 13 WR_DIS.KEY3_PURPOSE EFUSE_BLK0 11 1 - 14 WR_DIS.KEY4_PURPOSE EFUSE_BLK0 12 1 - 15 WR_DIS.KEY5_PURPOSE EFUSE_BLK0 13 1 - 16 WR_DIS.SECURE_BOOT_EN EFUSE_BLK0 15 1 - 17 WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 16 1 - 18 WR_DIS.GROUP_3 EFUSE_BLK0 18 1 - 19 WR_DIS.BLK1 EFUSE_BLK0 20 1 - 20 WR_DIS.SYS_DATA_PART1 EFUSE_BLK0 21 1 - 21 WR_DIS.USER_DATA EFUSE_BLK0 22 1 - 22 WR_DIS.KEY0 EFUSE_BLK0 23 1 - 23 WR_DIS.KEY1 EFUSE_BLK0 24 1 - 24 WR_DIS.KEY2 EFUSE_BLK0 25 1 - 25 WR_DIS.KEY3 EFUSE_BLK0 26 1 - 26 WR_DIS.KEY4 EFUSE_BLK0 27 1 - 27 WR_DIS.KEY5 EFUSE_BLK0 28 1 - 28 WR_DIS.SYS_DATA_PART2 EFUSE_BLK0 29 1 - 29 WR_DIS.USB_EXCHG_PINS EFUSE_BLK0 30 1 - 30 RD_DIS EFUSE_BLK0 32 7 - 31 RD_DIS.KEY0 EFUSE_BLK0 32 1 - 32 RD_DIS.KEY1 EFUSE_BLK0 33 1 - 33 RD_DIS.KEY2 EFUSE_BLK0 34 1 - 34 RD_DIS.KEY3 EFUSE_BLK0 35 1 - 35 RD_DIS.KEY4 EFUSE_BLK0 36 1 - 36 RD_DIS.KEY5 EFUSE_BLK0 37 1 - 37 RD_DIS.SYS_DATA_PART2 EFUSE_BLK0 38 1 - 38 DIS_RTC_RAM_BOOT EFUSE_BLK0 39 1 - 39 DIS_ICACHE EFUSE_BLK0 40 1 - 40 DIS_DCACHE EFUSE_BLK0 41 1 - 41 DIS_DOWNLOAD_ICACHE EFUSE_BLK0 42 1 - 42 DIS_DOWNLOAD_DCACHE EFUSE_BLK0 43 1 - 43 DIS_FORCE_DOWNLOAD EFUSE_BLK0 44 1 - 44 DIS_USB EFUSE_BLK0 45 1 - 45 DIS_CAN EFUSE_BLK0 46 1 - 46 DIS_BOOT_REMAP EFUSE_BLK0 47 1 - 47 SOFT_DIS_JTAG EFUSE_BLK0 49 1 - 48 HARD_DIS_JTAG EFUSE_BLK0 50 1 - 49 DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 51 1 - 50 USB_EXCHG_PINS EFUSE_BLK0 56 1 - 51 USB_EXT_PHY_ENABLE EFUSE_BLK0 57 1 - 52 BLOCK0_VERSION EFUSE_BLK0 59 2 - 53 VDD_SPI_XPD EFUSE_BLK0 68 1 - 54 VDD_SPI_TIEH EFUSE_BLK0 69 1 - 55 VDD_SPI_FORCE EFUSE_BLK0 70 1 - 56 WDT_DELAY_SEL EFUSE_BLK0 80 2 - 57 SPI_BOOT_CRYPT_CNT EFUSE_BLK0 82 3 - 58 SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 85 1 - 59 SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 86 1 - 60 SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 87 1 - 61 KEY_PURPOSE_0 EFUSE_BLK0 88 4 - 62 KEY_PURPOSE_1 EFUSE_BLK0 92 4 - 63 KEY_PURPOSE_2 EFUSE_BLK0 96 4 - 64 KEY_PURPOSE_3 EFUSE_BLK0 100 4 - 65 KEY_PURPOSE_4 EFUSE_BLK0 104 4 - 66 KEY_PURPOSE_5 EFUSE_BLK0 108 4 - 67 SECURE_BOOT_EN EFUSE_BLK0 116 1 - 68 SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 117 1 - 69 FLASH_TPUW EFUSE_BLK0 124 4 - 70 DIS_DOWNLOAD_MODE EFUSE_BLK0 128 1 - 71 DIS_LEGACY_SPI_BOOT EFUSE_BLK0 129 1 - 72 UART_PRINT_CHANNEL EFUSE_BLK0 130 1 - 73 DIS_USB_DOWNLOAD_MODE EFUSE_BLK0 132 1 - 74 ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 133 1 - 75 UART_PRINT_CONTROL EFUSE_BLK0 134 2 - 76 PIN_POWER_SELECTION EFUSE_BLK0 136 1 - 77 FLASH_TYPE EFUSE_BLK0 137 1 - 78 FORCE_SEND_RESUME EFUSE_BLK0 138 1 - 79 SECURE_VERSION EFUSE_BLK0 139 16 - 80 MAC_FACTORY EFUSE_BLK1 0 8 - 81 MAC_FACTORY EFUSE_BLK1 8 8 - 82 MAC_FACTORY EFUSE_BLK1 16 8 - 83 MAC_FACTORY EFUSE_BLK1 24 8 - 84 MAC_FACTORY EFUSE_BLK1 32 8 - 85 MAC_FACTORY EFUSE_BLK1 40 8 - 86 SPI_PAD_CONFIG_CLK EFUSE_BLK1 48 6 - 87 SPI_PAD_CONFIG_Q_D1 EFUSE_BLK1 54 6 - 88 SPI_PAD_CONFIG_D_D0 EFUSE_BLK1 60 6 - 89 SPI_PAD_CONFIG_CS EFUSE_BLK1 66 6 - 90 SPI_PAD_CONFIG_HD_D3 EFUSE_BLK1 72 6 - 91 SPI_PAD_CONFIG_WP_D2 EFUSE_BLK1 78 6 - 92 SPI_PAD_CONFIG_DQS EFUSE_BLK1 84 6 - 93 SPI_PAD_CONFIG_D4 EFUSE_BLK1 90 6 - 94 SPI_PAD_CONFIG_D5 EFUSE_BLK1 96 6 - 95 SPI_PAD_CONFIG_D6 EFUSE_BLK1 102 6 - 96 SPI_PAD_CONFIG_D7 EFUSE_BLK1 108 6 - 97 WAFER_VERSION EFUSE_BLK1 114 3 - 98 FLASH_VERSION EFUSE_BLK1 117 4 - 99 BLOCK1_VERSION EFUSE_BLK1 121 3 - 100 PSRAM_VERSION EFUSE_BLK1 124 4 - 101 PKG_VERSION EFUSE_BLK1 128 4 - 102 SYS_DATA_PART2 EFUSE_BLK10 0 256 - 103 OPTIONAL_UNIQUE_ID EFUSE_BLK2 0 128 - 104 BLOCK2_VERSION EFUSE_BLK2 132 3 - 105 USER_DATA EFUSE_BLK3 0 256 - 106 USER_DATA.MAC_CUSTOM EFUSE_BLK3 200 48 - 107 KEY0 EFUSE_BLK4 0 256 - 108 KEY1 EFUSE_BLK5 0 256 - 109 KEY2 EFUSE_BLK6 0 256 - 110 KEY3 EFUSE_BLK7 0 256 - 111 KEY4 EFUSE_BLK8 0 256 - 112 KEY5 EFUSE_BLK9 0 256 + 3 WR_DIS.DIS_ICACHE EFUSE_BLK0 2 1 + 4 WR_DIS.DIS_DCACHE EFUSE_BLK0 2 1 + 5 WR_DIS.DIS_DOWNLOAD_ICACHE EFUSE_BLK0 2 1 + 6 WR_DIS.DIS_DOWNLOAD_DCACHE EFUSE_BLK0 2 1 + 7 WR_DIS.DIS_FORCE_DOWNLOAD EFUSE_BLK0 2 1 + 8 WR_DIS.DIS_USB EFUSE_BLK0 2 1 + 9 WR_DIS.DIS_TWAI EFUSE_BLK0 2 1 + 10 WR_DIS.DIS_BOOT_REMAP EFUSE_BLK0 2 1 + 11 WR_DIS.SOFT_DIS_JTAG EFUSE_BLK0 2 1 + 12 WR_DIS.HARD_DIS_JTAG EFUSE_BLK0 2 1 + 13 WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 2 1 + 14 WR_DIS.VDD_SPI_XPD EFUSE_BLK0 3 1 + 15 WR_DIS.VDD_SPI_TIEH EFUSE_BLK0 3 1 + 16 WR_DIS.VDD_SPI_FORCE EFUSE_BLK0 3 1 + 17 WR_DIS.WDT_DELAY_SEL EFUSE_BLK0 3 1 + 18 WR_DIS.SPI_BOOT_CRYPT_CNT EFUSE_BLK0 4 1 + 19 WR_DIS.SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 5 1 + 20 WR_DIS.SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 6 1 + 21 WR_DIS.SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 7 1 + 22 WR_DIS.KEY_PURPOSE_0 EFUSE_BLK0 8 1 + 23 WR_DIS.KEY_PURPOSE_1 EFUSE_BLK0 9 1 + 24 WR_DIS.KEY_PURPOSE_2 EFUSE_BLK0 10 1 + 25 WR_DIS.KEY_PURPOSE_3 EFUSE_BLK0 11 1 + 26 WR_DIS.KEY_PURPOSE_4 EFUSE_BLK0 12 1 + 27 WR_DIS.KEY_PURPOSE_5 EFUSE_BLK0 13 1 + 28 WR_DIS.SECURE_BOOT_EN EFUSE_BLK0 15 1 + 29 WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 16 1 + 30 WR_DIS.FLASH_TPUW EFUSE_BLK0 18 1 + 31 WR_DIS.DIS_DOWNLOAD_MODE EFUSE_BLK0 18 1 + 32 WR_DIS.DIS_LEGACY_SPI_BOOT EFUSE_BLK0 18 1 + 33 WR_DIS.UART_PRINT_CHANNEL EFUSE_BLK0 18 1 + 34 WR_DIS.DIS_USB_DOWNLOAD_MODE EFUSE_BLK0 18 1 + 35 WR_DIS.ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 18 1 + 36 WR_DIS.UART_PRINT_CONTROL EFUSE_BLK0 18 1 + 37 WR_DIS.PIN_POWER_SELECTION EFUSE_BLK0 18 1 + 38 WR_DIS.FLASH_TYPE EFUSE_BLK0 18 1 + 39 WR_DIS.FORCE_SEND_RESUME EFUSE_BLK0 18 1 + 40 WR_DIS.SECURE_VERSION EFUSE_BLK0 18 1 + 41 WR_DIS.BLK1 EFUSE_BLK0 20 1 + 42 WR_DIS.MAC EFUSE_BLK0 20 1 + 43 WR_DIS.SPI_PAD_CONFIG_CLK EFUSE_BLK0 20 1 + 44 WR_DIS.SPI_PAD_CONFIG_Q EFUSE_BLK0 20 1 + 45 WR_DIS.SPI_PAD_CONFIG_D EFUSE_BLK0 20 1 + 46 WR_DIS.SPI_PAD_CONFIG_CS EFUSE_BLK0 20 1 + 47 WR_DIS.SPI_PAD_CONFIG_HD EFUSE_BLK0 20 1 + 48 WR_DIS.SPI_PAD_CONFIG_WP EFUSE_BLK0 20 1 + 49 WR_DIS.SPI_PAD_CONFIG_DQS EFUSE_BLK0 20 1 + 50 WR_DIS.SPI_PAD_CONFIG_D4 EFUSE_BLK0 20 1 + 51 WR_DIS.SPI_PAD_CONFIG_D5 EFUSE_BLK0 20 1 + 52 WR_DIS.SPI_PAD_CONFIG_D6 EFUSE_BLK0 20 1 + 53 WR_DIS.SPI_PAD_CONFIG_D7 EFUSE_BLK0 20 1 + 54 WR_DIS.WAFER_VERSION_MAJOR EFUSE_BLK0 20 1 + 55 WR_DIS.WAFER_VERSION_MINOR_HI EFUSE_BLK0 20 1 + 56 WR_DIS.FLASH_VERSION EFUSE_BLK0 20 1 + 57 WR_DIS.BLK_VERSION_MAJOR EFUSE_BLK0 20 1 + 58 WR_DIS.PSRAM_VERSION EFUSE_BLK0 20 1 + 59 WR_DIS.PKG_VERSION EFUSE_BLK0 20 1 + 60 WR_DIS.WAFER_VERSION_MINOR_LO EFUSE_BLK0 20 1 + 61 WR_DIS.SYS_DATA_PART1 EFUSE_BLK0 21 1 + 62 WR_DIS.OPTIONAL_UNIQUE_ID EFUSE_BLK0 21 1 + 63 WR_DIS.ADC_CALIB EFUSE_BLK0 21 1 + 64 WR_DIS.BLK_VERSION_MINOR EFUSE_BLK0 21 1 + 65 WR_DIS.TEMP_CALIB EFUSE_BLK0 21 1 + 66 WR_DIS.RTCCALIB_V1IDX_A10H EFUSE_BLK0 21 1 + 67 WR_DIS.RTCCALIB_V1IDX_A11H EFUSE_BLK0 21 1 + 68 WR_DIS.RTCCALIB_V1IDX_A12H EFUSE_BLK0 21 1 + 69 WR_DIS.RTCCALIB_V1IDX_A13H EFUSE_BLK0 21 1 + 70 WR_DIS.RTCCALIB_V1IDX_A20H EFUSE_BLK0 21 1 + 71 WR_DIS.RTCCALIB_V1IDX_A21H EFUSE_BLK0 21 1 + 72 WR_DIS.RTCCALIB_V1IDX_A22H EFUSE_BLK0 21 1 + 73 WR_DIS.RTCCALIB_V1IDX_A23H EFUSE_BLK0 21 1 + 74 WR_DIS.RTCCALIB_V1IDX_A10L EFUSE_BLK0 21 1 + 75 WR_DIS.RTCCALIB_V1IDX_A11L EFUSE_BLK0 21 1 + 76 WR_DIS.RTCCALIB_V1IDX_A12L EFUSE_BLK0 21 1 + 77 WR_DIS.RTCCALIB_V1IDX_A13L EFUSE_BLK0 21 1 + 78 WR_DIS.RTCCALIB_V1IDX_A20L EFUSE_BLK0 21 1 + 79 WR_DIS.RTCCALIB_V1IDX_A21L EFUSE_BLK0 21 1 + 80 WR_DIS.RTCCALIB_V1IDX_A22L EFUSE_BLK0 21 1 + 81 WR_DIS.RTCCALIB_V1IDX_A23L EFUSE_BLK0 21 1 + 82 WR_DIS.BLOCK_USR_DATA EFUSE_BLK0 22 1 + 83 WR_DIS.CUSTOM_MAC EFUSE_BLK0 22 1 + 84 WR_DIS.BLOCK_KEY0 EFUSE_BLK0 23 1 + 85 WR_DIS.BLOCK_KEY1 EFUSE_BLK0 24 1 + 86 WR_DIS.BLOCK_KEY2 EFUSE_BLK0 25 1 + 87 WR_DIS.BLOCK_KEY3 EFUSE_BLK0 26 1 + 88 WR_DIS.BLOCK_KEY4 EFUSE_BLK0 27 1 + 89 WR_DIS.BLOCK_KEY5 EFUSE_BLK0 28 1 + 90 WR_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 29 1 + 91 WR_DIS.USB_EXCHG_PINS EFUSE_BLK0 30 1 + 92 WR_DIS.USB_EXT_PHY_ENABLE EFUSE_BLK0 30 1 + 93 WR_DIS.USB_FORCE_NOPERSIST EFUSE_BLK0 30 1 + 94 WR_DIS.BLOCK0_VERSION EFUSE_BLK0 30 1 + 95 RD_DIS EFUSE_BLK0 32 7 + 96 RD_DIS.BLOCK_KEY0 EFUSE_BLK0 32 1 + 97 RD_DIS.BLOCK_KEY1 EFUSE_BLK0 33 1 + 98 RD_DIS.BLOCK_KEY2 EFUSE_BLK0 34 1 + 99 RD_DIS.BLOCK_KEY3 EFUSE_BLK0 35 1 + 100 RD_DIS.BLOCK_KEY4 EFUSE_BLK0 36 1 + 101 RD_DIS.BLOCK_KEY5 EFUSE_BLK0 37 1 + 102 RD_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 38 1 + 103 DIS_ICACHE EFUSE_BLK0 40 1 + 104 DIS_DCACHE EFUSE_BLK0 41 1 + 105 DIS_DOWNLOAD_ICACHE EFUSE_BLK0 42 1 + 106 DIS_DOWNLOAD_DCACHE EFUSE_BLK0 43 1 + 107 DIS_FORCE_DOWNLOAD EFUSE_BLK0 44 1 + 108 DIS_USB EFUSE_BLK0 45 1 + 109 DIS_TWAI EFUSE_BLK0 46 1 + 110 DIS_BOOT_REMAP EFUSE_BLK0 47 1 + 111 SOFT_DIS_JTAG EFUSE_BLK0 49 1 + 112 HARD_DIS_JTAG EFUSE_BLK0 50 1 + 113 DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 51 1 + 114 USB_EXCHG_PINS EFUSE_BLK0 56 1 + 115 USB_EXT_PHY_ENABLE EFUSE_BLK0 57 1 + 116 USB_FORCE_NOPERSIST EFUSE_BLK0 58 1 + 117 BLOCK0_VERSION EFUSE_BLK0 59 2 + 118 VDD_SPI_XPD EFUSE_BLK0 68 1 + 119 VDD_SPI_TIEH EFUSE_BLK0 69 1 + 120 VDD_SPI_FORCE EFUSE_BLK0 70 1 + 121 WDT_DELAY_SEL EFUSE_BLK0 80 2 + 122 SPI_BOOT_CRYPT_CNT EFUSE_BLK0 82 3 + 123 SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 85 1 + 124 SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 86 1 + 125 SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 87 1 + 126 KEY_PURPOSE_0 EFUSE_BLK0 88 4 + 127 KEY_PURPOSE_1 EFUSE_BLK0 92 4 + 128 KEY_PURPOSE_2 EFUSE_BLK0 96 4 + 129 KEY_PURPOSE_3 EFUSE_BLK0 100 4 + 130 KEY_PURPOSE_4 EFUSE_BLK0 104 4 + 131 KEY_PURPOSE_5 EFUSE_BLK0 108 4 + 132 SECURE_BOOT_EN EFUSE_BLK0 116 1 + 133 SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 117 1 + 134 FLASH_TPUW EFUSE_BLK0 124 4 + 135 DIS_DOWNLOAD_MODE EFUSE_BLK0 128 1 + 136 DIS_LEGACY_SPI_BOOT EFUSE_BLK0 129 1 + 137 UART_PRINT_CHANNEL EFUSE_BLK0 130 1 + 138 DIS_USB_DOWNLOAD_MODE EFUSE_BLK0 132 1 + 139 ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 133 1 + 140 UART_PRINT_CONTROL EFUSE_BLK0 134 2 + 141 PIN_POWER_SELECTION EFUSE_BLK0 136 1 + 142 FLASH_TYPE EFUSE_BLK0 137 1 + 143 FORCE_SEND_RESUME EFUSE_BLK0 138 1 + 144 SECURE_VERSION EFUSE_BLK0 139 16 + 145 DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK0 160 1 + 146 DISABLE_BLK_VERSION_MAJOR EFUSE_BLK0 161 1 + 147 MAC EFUSE_BLK1 0 8 + 148 MAC EFUSE_BLK1 8 8 + 149 MAC EFUSE_BLK1 16 8 + 150 MAC EFUSE_BLK1 24 8 + 151 MAC EFUSE_BLK1 32 8 + 152 MAC EFUSE_BLK1 40 8 + 153 SPI_PAD_CONFIG_CLK EFUSE_BLK1 48 6 + 154 SPI_PAD_CONFIG_Q EFUSE_BLK1 54 6 + 155 SPI_PAD_CONFIG_D EFUSE_BLK1 60 6 + 156 SPI_PAD_CONFIG_CS EFUSE_BLK1 66 6 + 157 SPI_PAD_CONFIG_HD EFUSE_BLK1 72 6 + 158 SPI_PAD_CONFIG_WP EFUSE_BLK1 78 6 + 159 SPI_PAD_CONFIG_DQS EFUSE_BLK1 84 6 + 160 SPI_PAD_CONFIG_D4 EFUSE_BLK1 90 6 + 161 SPI_PAD_CONFIG_D5 EFUSE_BLK1 96 6 + 162 SPI_PAD_CONFIG_D6 EFUSE_BLK1 102 6 + 163 SPI_PAD_CONFIG_D7 EFUSE_BLK1 108 6 + 164 WAFER_VERSION_MAJOR EFUSE_BLK1 114 2 + 165 WAFER_VERSION_MINOR_HI EFUSE_BLK1 116 1 + 166 FLASH_VERSION EFUSE_BLK1 117 4 + 167 BLK_VERSION_MAJOR EFUSE_BLK1 121 2 + 168 PSRAM_VERSION EFUSE_BLK1 124 4 + 169 PKG_VERSION EFUSE_BLK1 128 4 + 170 WAFER_VERSION_MINOR_LO EFUSE_BLK1 132 3 + 171 SYS_DATA_PART2 EFUSE_BLK10 0 256 + 172 OPTIONAL_UNIQUE_ID EFUSE_BLK2 0 128 + 173 ADC_CALIB EFUSE_BLK2 128 4 + 174 BLK_VERSION_MINOR EFUSE_BLK2 132 3 + 175 TEMP_CALIB EFUSE_BLK2 135 9 + 176 RTCCALIB_V1IDX_A10H EFUSE_BLK2 144 8 + 177 RTCCALIB_V1IDX_A11H EFUSE_BLK2 152 8 + 178 RTCCALIB_V1IDX_A12H EFUSE_BLK2 160 8 + 179 RTCCALIB_V1IDX_A13H EFUSE_BLK2 168 8 + 180 RTCCALIB_V1IDX_A20H EFUSE_BLK2 176 8 + 181 RTCCALIB_V1IDX_A21H EFUSE_BLK2 184 8 + 182 RTCCALIB_V1IDX_A22H EFUSE_BLK2 192 8 + 183 RTCCALIB_V1IDX_A23H EFUSE_BLK2 200 8 + 184 RTCCALIB_V1IDX_A10L EFUSE_BLK2 208 6 + 185 RTCCALIB_V1IDX_A11L EFUSE_BLK2 214 6 + 186 RTCCALIB_V1IDX_A12L EFUSE_BLK2 220 6 + 187 RTCCALIB_V1IDX_A13L EFUSE_BLK2 226 6 + 188 RTCCALIB_V1IDX_A20L EFUSE_BLK2 232 6 + 189 RTCCALIB_V1IDX_A21L EFUSE_BLK2 238 6 + 190 RTCCALIB_V1IDX_A22L EFUSE_BLK2 244 6 + 191 RTCCALIB_V1IDX_A23L EFUSE_BLK2 250 6 + 192 USER_DATA EFUSE_BLK3 0 256 + 193 USER_DATA.MAC_CUSTOM EFUSE_BLK3 200 48 + 194 KEY0 EFUSE_BLK4 0 256 + 195 KEY1 EFUSE_BLK5 0 256 + 196 KEY2 EFUSE_BLK6 0 256 + 197 KEY3 EFUSE_BLK7 0 256 + 198 KEY4 EFUSE_BLK8 0 256 + 199 KEY5 EFUSE_BLK9 0 256 Used bits in efuse table: EFUSE_BLK0 - [0 31] [0 13] [15 16] [18 18] [20 30] [32 38] [32 47] [49 51] [56 57] [59 60] [68 70] [80 111] [116 117] [124 130] [132 154] - + [0 31] [0 0] [2 2] ... [32 38] [40 47] [49 51] [56 60] [68 70] [80 111] [116 117] [124 130] [132 154] [160 161] EFUSE_BLK1 - [0 131] - + [0 122] [124 134] EFUSE_BLK10 [0 255] - EFUSE_BLK2 - [0 127] [132 134] - + [0 255] EFUSE_BLK3 [0 255] [200 247] - EFUSE_BLK4 [0 255] - EFUSE_BLK5 [0 255] - EFUSE_BLK6 [0 255] - EFUSE_BLK7 [0 255] - EFUSE_BLK8 [0 255] - EFUSE_BLK9 [0 255] - - Note: Not printed ranges are free for using. (bits in EFUSE_BLK0 are reserved for Espressif) + Note: Not printed ranges are free for using. (bits in EFUSE_BLK0 are reserved for Espressif) \ No newline at end of file diff --git a/docs/en/api-reference/system/inc/show-efuse-table_ESP32-S3.rst b/docs/en/api-reference/system/inc/show-efuse-table_ESP32-S3.rst index b6ca519150..60a6cf09e8 100644 --- a/docs/en/api-reference/system/inc/show-efuse-table_ESP32-S3.rst +++ b/docs/en/api-reference/system/inc/show-efuse-table_ESP32-S3.rst @@ -5,176 +5,248 @@ Max number of bits in BLK 256 Sorted efuse table: - # field_name efuse_block bit_start bit_count - 1 WR_DIS EFUSE_BLK0 0 32 - 2 WR_DIS.RD_DIS EFUSE_BLK0 0 1 - 3 WR_DIS.GROUP_1 EFUSE_BLK0 2 1 - 4 WR_DIS.GROUP_2 EFUSE_BLK0 3 1 - 5 WR_DIS.SPI_BOOT_CRYPT_CNT EFUSE_BLK0 4 1 - 6 WR_DIS.SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 5 1 - 7 WR_DIS.SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 6 1 - 8 WR_DIS.SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 7 1 - 9 WR_DIS.KEY0_PURPOSE EFUSE_BLK0 8 1 - 10 WR_DIS.KEY1_PURPOSE EFUSE_BLK0 9 1 - 11 WR_DIS.KEY2_PURPOSE EFUSE_BLK0 10 1 - 12 WR_DIS.KEY3_PURPOSE EFUSE_BLK0 11 1 - 13 WR_DIS.KEY4_PURPOSE EFUSE_BLK0 12 1 - 14 WR_DIS.KEY5_PURPOSE EFUSE_BLK0 13 1 - 15 WR_DIS.SECURE_BOOT_EN EFUSE_BLK0 15 1 - 16 WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 16 1 - 17 WR_DIS.GROUP_3 EFUSE_BLK0 18 1 - 18 WR_DIS.BLK1 EFUSE_BLK0 20 1 - 19 WR_DIS.SYS_DATA_PART1 EFUSE_BLK0 21 1 - 20 WR_DIS.USER_DATA EFUSE_BLK0 22 1 - 21 WR_DIS.KEY0 EFUSE_BLK0 23 1 - 22 WR_DIS.KEY1 EFUSE_BLK0 24 1 - 23 WR_DIS.KEY2 EFUSE_BLK0 25 1 - 24 WR_DIS.KEY3 EFUSE_BLK0 26 1 - 25 WR_DIS.KEY4 EFUSE_BLK0 27 1 - 26 WR_DIS.KEY5 EFUSE_BLK0 28 1 - 27 WR_DIS.SYS_DATA_PART2 EFUSE_BLK0 29 1 - 28 WR_DIS.USB_EXCHG_PINS EFUSE_BLK0 30 1 - 29 RD_DIS EFUSE_BLK0 32 7 - 30 RD_DIS.KEY0 EFUSE_BLK0 32 1 - 31 RD_DIS.KEY1 EFUSE_BLK0 33 1 - 32 RD_DIS.KEY2 EFUSE_BLK0 34 1 - 33 RD_DIS.KEY3 EFUSE_BLK0 35 1 - 34 RD_DIS.KEY4 EFUSE_BLK0 36 1 - 35 RD_DIS.KEY5 EFUSE_BLK0 37 1 - 36 RD_DIS.SYS_DATA_PART2 EFUSE_BLK0 38 1 - 37 DIS_ICACHE EFUSE_BLK0 40 1 - 38 DIS_DCACHE EFUSE_BLK0 41 1 - 39 DIS_DOWNLOAD_ICACHE EFUSE_BLK0 42 1 - 40 DIS_DOWNLOAD_DCACHE EFUSE_BLK0 43 1 - 41 DIS_FORCE_DOWNLOAD EFUSE_BLK0 44 1 - 42 DIS_USB EFUSE_BLK0 45 1 - 43 DIS_CAN EFUSE_BLK0 46 1 - 44 DIS_APP_CPU EFUSE_BLK0 47 1 - 45 SOFT_DIS_JTAG EFUSE_BLK0 48 3 - 46 HARD_DIS_JTAG EFUSE_BLK0 51 1 - 47 DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 52 1 - 48 USB_EXCHG_PINS EFUSE_BLK0 57 1 - 49 USB_EXT_PHY_ENABLE EFUSE_BLK0 58 1 - 50 BTLC_GPIO_ENABLE EFUSE_BLK0 59 2 - 51 VDD_SPI_XPD EFUSE_BLK0 68 1 - 52 VDD_SPI_TIEH EFUSE_BLK0 69 1 - 53 VDD_SPI_FORCE EFUSE_BLK0 70 1 - 54 WDT_DELAY_SEL EFUSE_BLK0 80 2 - 55 SPI_BOOT_CRYPT_CNT EFUSE_BLK0 82 3 - 56 SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 85 1 - 57 SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 86 1 - 58 SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 87 1 - 59 KEY_PURPOSE_0 EFUSE_BLK0 88 4 - 60 KEY_PURPOSE_1 EFUSE_BLK0 92 4 - 61 KEY_PURPOSE_2 EFUSE_BLK0 96 4 - 62 KEY_PURPOSE_3 EFUSE_BLK0 100 4 - 63 KEY_PURPOSE_4 EFUSE_BLK0 104 4 - 64 KEY_PURPOSE_5 EFUSE_BLK0 108 4 - 65 SECURE_BOOT_EN EFUSE_BLK0 116 1 - 66 SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 117 1 - 67 DIS_USB_JTAG EFUSE_BLK0 118 1 - 68 DIS_USB_SERIAL_JTAG EFUSE_BLK0 119 1 - 69 STRAP_JTAG_SEL EFUSE_BLK0 120 1 - 70 USB_PHY_SEL EFUSE_BLK0 121 1 - 71 FLASH_TPUW EFUSE_BLK0 124 4 - 72 DIS_DOWNLOAD_MODE EFUSE_BLK0 128 1 - 73 DIS_DIRECT_BOOT EFUSE_BLK0 129 1 - 74 DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 130 1 - 75 FLASH_ECC_MODE EFUSE_BLK0 131 1 - 76 DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 132 1 - 77 ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 133 1 - 78 UART_PRINT_CONTROL EFUSE_BLK0 134 2 - 79 PIN_POWER_SELECTION EFUSE_BLK0 136 1 - 80 FLASH_TYPE EFUSE_BLK0 137 1 - 81 FLASH_PAGE_SIZE EFUSE_BLK0 138 2 - 82 FLASH_ECC_EN EFUSE_BLK0 140 1 - 83 FORCE_SEND_RESUME EFUSE_BLK0 141 1 - 84 SECURE_VERSION EFUSE_BLK0 142 16 - 85 DIS_USB_OTG_DOWNLOAD_MODE EFUSE_BLK0 159 1 - 86 MAC_FACTORY EFUSE_BLK1 0 8 - 87 MAC_FACTORY EFUSE_BLK1 8 8 - 88 MAC_FACTORY EFUSE_BLK1 16 8 - 89 MAC_FACTORY EFUSE_BLK1 24 8 - 90 MAC_FACTORY EFUSE_BLK1 32 8 - 91 MAC_FACTORY EFUSE_BLK1 40 8 - 92 SPI_PAD_CONFIG_CLK EFUSE_BLK1 48 6 - 93 SPI_PAD_CONFIG_Q_D1 EFUSE_BLK1 54 6 - 94 SPI_PAD_CONFIG_D_D0 EFUSE_BLK1 60 6 - 95 SPI_PAD_CONFIG_CS EFUSE_BLK1 66 6 - 96 SPI_PAD_CONFIG_HD_D3 EFUSE_BLK1 72 6 - 97 SPI_PAD_CONFIG_WP_D2 EFUSE_BLK1 78 6 - 98 SPI_PAD_CONFIG_DQS EFUSE_BLK1 84 6 - 99 SPI_PAD_CONFIG_D4 EFUSE_BLK1 90 6 - 100 SPI_PAD_CONFIG_D5 EFUSE_BLK1 96 6 - 101 SPI_PAD_CONFIG_D6 EFUSE_BLK1 102 6 - 102 SPI_PAD_CONFIG_D7 EFUSE_BLK1 108 6 - 103 WAFER_VERSION EFUSE_BLK1 114 3 - 104 PKG_VERSION EFUSE_BLK1 117 3 - 105 BLK_VER_MINOR EFUSE_BLK1 120 3 - 106 ADC2_CAL_VOL_ATTEN3 EFUSE_BLK1 186 6 - 107 SYS_DATA_PART2 EFUSE_BLK10 0 256 - 108 OPTIONAL_UNIQUE_ID EFUSE_BLK2 0 128 - 109 BLK_VER_MAJOR EFUSE_BLK2 128 2 - 110 TEMP_CALIB EFUSE_BLK2 132 9 - 111 OCODE EFUSE_BLK2 141 8 - 112 ADC1_INIT_CODE_ATTEN0 EFUSE_BLK2 149 8 - 113 ADC1_INIT_CODE_ATTEN1 EFUSE_BLK2 157 6 - 114 ADC1_INIT_CODE_ATTEN2 EFUSE_BLK2 163 6 - 115 ADC1_INIT_CODE_ATTEN3 EFUSE_BLK2 169 6 - 116 ADC2_INIT_CODE_ATTEN0 EFUSE_BLK2 175 8 - 117 ADC2_INIT_CODE_ATTEN1 EFUSE_BLK2 183 6 - 118 ADC2_INIT_CODE_ATTEN2 EFUSE_BLK2 189 6 - 119 ADC2_INIT_CODE_ATTEN3 EFUSE_BLK2 195 6 - 120 ADC1_CAL_VOL_ATTEN0 EFUSE_BLK2 201 8 - 121 ADC1_CAL_VOL_ATTEN1 EFUSE_BLK2 209 8 - 122 ADC1_CAL_VOL_ATTEN2 EFUSE_BLK2 217 8 - 123 ADC1_CAL_VOL_ATTEN3 EFUSE_BLK2 225 8 - 124 ADC2_CAL_VOL_ATTEN0 EFUSE_BLK2 233 8 - 125 ADC2_CAL_VOL_ATTEN1 EFUSE_BLK2 241 7 - 126 ADC2_CAL_VOL_ATTEN2 EFUSE_BLK2 248 7 - 127 USER_DATA EFUSE_BLK3 0 256 - 128 USER_DATA.MAC_CUSTOM EFUSE_BLK3 200 48 - 129 KEY0 EFUSE_BLK4 0 256 - 130 KEY1 EFUSE_BLK5 0 256 - 131 KEY2 EFUSE_BLK6 0 256 - 132 KEY3 EFUSE_BLK7 0 256 - 133 KEY4 EFUSE_BLK8 0 256 - 134 KEY5 EFUSE_BLK9 0 256 + # field_name efuse_block bit_start bit_count + 1 WR_DIS EFUSE_BLK0 0 32 + 2 WR_DIS.RD_DIS EFUSE_BLK0 0 1 + 3 WR_DIS.DIS_ICACHE EFUSE_BLK0 2 1 + 4 WR_DIS.DIS_DCACHE EFUSE_BLK0 2 1 + 5 WR_DIS.DIS_DOWNLOAD_ICACHE EFUSE_BLK0 2 1 + 6 WR_DIS.DIS_DOWNLOAD_DCACHE EFUSE_BLK0 2 1 + 7 WR_DIS.DIS_FORCE_DOWNLOAD EFUSE_BLK0 2 1 + 8 WR_DIS.DIS_USB_OTG EFUSE_BLK0 2 1 + 9 WR_DIS.DIS_TWAI EFUSE_BLK0 2 1 + 10 WR_DIS.DIS_APP_CPU EFUSE_BLK0 2 1 + 11 WR_DIS.DIS_PAD_JTAG EFUSE_BLK0 2 1 + 12 WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 2 1 + 13 WR_DIS.DIS_USB_JTAG EFUSE_BLK0 2 1 + 14 WR_DIS.DIS_USB_SERIAL_JTAG EFUSE_BLK0 2 1 + 15 WR_DIS.STRAP_JTAG_SEL EFUSE_BLK0 2 1 + 16 WR_DIS.USB_PHY_SEL EFUSE_BLK0 2 1 + 17 WR_DIS.VDD_SPI_XPD EFUSE_BLK0 3 1 + 18 WR_DIS.VDD_SPI_TIEH EFUSE_BLK0 3 1 + 19 WR_DIS.VDD_SPI_FORCE EFUSE_BLK0 3 1 + 20 WR_DIS.WDT_DELAY_SEL EFUSE_BLK0 3 1 + 21 WR_DIS.SPI_BOOT_CRYPT_CNT EFUSE_BLK0 4 1 + 22 WR_DIS.SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 5 1 + 23 WR_DIS.SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 6 1 + 24 WR_DIS.SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 7 1 + 25 WR_DIS.KEY_PURPOSE_0 EFUSE_BLK0 8 1 + 26 WR_DIS.KEY_PURPOSE_1 EFUSE_BLK0 9 1 + 27 WR_DIS.KEY_PURPOSE_2 EFUSE_BLK0 10 1 + 28 WR_DIS.KEY_PURPOSE_3 EFUSE_BLK0 11 1 + 29 WR_DIS.KEY_PURPOSE_4 EFUSE_BLK0 12 1 + 30 WR_DIS.KEY_PURPOSE_5 EFUSE_BLK0 13 1 + 31 WR_DIS.SECURE_BOOT_EN EFUSE_BLK0 15 1 + 32 WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 16 1 + 33 WR_DIS.FLASH_TPUW EFUSE_BLK0 18 1 + 34 WR_DIS.DIS_DOWNLOAD_MODE EFUSE_BLK0 18 1 + 35 WR_DIS.DIS_DIRECT_BOOT EFUSE_BLK0 18 1 + 36 WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 18 1 + 37 WR_DIS.FLASH_ECC_MODE EFUSE_BLK0 18 1 + 38 WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 18 1 + 39 WR_DIS.ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 18 1 + 40 WR_DIS.UART_PRINT_CONTROL EFUSE_BLK0 18 1 + 41 WR_DIS.PIN_POWER_SELECTION EFUSE_BLK0 18 1 + 42 WR_DIS.FLASH_TYPE EFUSE_BLK0 18 1 + 43 WR_DIS.FLASH_PAGE_SIZE EFUSE_BLK0 18 1 + 44 WR_DIS.FLASH_ECC_EN EFUSE_BLK0 18 1 + 45 WR_DIS.FORCE_SEND_RESUME EFUSE_BLK0 18 1 + 46 WR_DIS.SECURE_VERSION EFUSE_BLK0 18 1 + 47 WR_DIS.DIS_USB_OTG_DOWNLOAD_MODE EFUSE_BLK0 19 1 + 48 WR_DIS.DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK0 19 1 + 49 WR_DIS.DISABLE_BLK_VERSION_MAJOR EFUSE_BLK0 19 1 + 50 WR_DIS.BLK1 EFUSE_BLK0 20 1 + 51 WR_DIS.MAC EFUSE_BLK0 20 1 + 52 WR_DIS.SPI_PAD_CONFIG_CLK EFUSE_BLK0 20 1 + 53 WR_DIS.SPI_PAD_CONFIG_Q EFUSE_BLK0 20 1 + 54 WR_DIS.SPI_PAD_CONFIG_D EFUSE_BLK0 20 1 + 55 WR_DIS.SPI_PAD_CONFIG_CS EFUSE_BLK0 20 1 + 56 WR_DIS.SPI_PAD_CONFIG_HD EFUSE_BLK0 20 1 + 57 WR_DIS.SPI_PAD_CONFIG_WP EFUSE_BLK0 20 1 + 58 WR_DIS.SPI_PAD_CONFIG_DQS EFUSE_BLK0 20 1 + 59 WR_DIS.SPI_PAD_CONFIG_D4 EFUSE_BLK0 20 1 + 60 WR_DIS.SPI_PAD_CONFIG_D5 EFUSE_BLK0 20 1 + 61 WR_DIS.SPI_PAD_CONFIG_D6 EFUSE_BLK0 20 1 + 62 WR_DIS.SPI_PAD_CONFIG_D7 EFUSE_BLK0 20 1 + 63 WR_DIS.WAFER_VERSION_MINOR_LO EFUSE_BLK0 20 1 + 64 WR_DIS.PKG_VERSION EFUSE_BLK0 20 1 + 65 WR_DIS.BLK_VERSION_MINOR EFUSE_BLK0 20 1 + 66 WR_DIS.K_RTC_LDO EFUSE_BLK0 20 1 + 67 WR_DIS.K_DIG_LDO EFUSE_BLK0 20 1 + 68 WR_DIS.V_RTC_DBIAS20 EFUSE_BLK0 20 1 + 69 WR_DIS.V_DIG_DBIAS20 EFUSE_BLK0 20 1 + 70 WR_DIS.DIG_DBIAS_HVT EFUSE_BLK0 20 1 + 71 WR_DIS.WAFER_VERSION_MINOR_HI EFUSE_BLK0 20 1 + 72 WR_DIS.WAFER_VERSION_MAJOR EFUSE_BLK0 20 1 + 73 WR_DIS.ADC2_CAL_VOL_ATTEN3 EFUSE_BLK0 20 1 + 74 WR_DIS.SYS_DATA_PART1 EFUSE_BLK0 21 1 + 75 WR_DIS.OPTIONAL_UNIQUE_ID EFUSE_BLK0 21 1 + 76 WR_DIS.BLK_VERSION_MAJOR EFUSE_BLK0 21 1 + 77 WR_DIS.TEMP_CALIB EFUSE_BLK0 21 1 + 78 WR_DIS.OCODE EFUSE_BLK0 21 1 + 79 WR_DIS.ADC1_INIT_CODE_ATTEN0 EFUSE_BLK0 21 1 + 80 WR_DIS.ADC1_INIT_CODE_ATTEN1 EFUSE_BLK0 21 1 + 81 WR_DIS.ADC1_INIT_CODE_ATTEN2 EFUSE_BLK0 21 1 + 82 WR_DIS.ADC1_INIT_CODE_ATTEN3 EFUSE_BLK0 21 1 + 83 WR_DIS.ADC2_INIT_CODE_ATTEN0 EFUSE_BLK0 21 1 + 84 WR_DIS.ADC2_INIT_CODE_ATTEN1 EFUSE_BLK0 21 1 + 85 WR_DIS.ADC2_INIT_CODE_ATTEN2 EFUSE_BLK0 21 1 + 86 WR_DIS.ADC2_INIT_CODE_ATTEN3 EFUSE_BLK0 21 1 + 87 WR_DIS.ADC1_CAL_VOL_ATTEN0 EFUSE_BLK0 21 1 + 88 WR_DIS.ADC1_CAL_VOL_ATTEN1 EFUSE_BLK0 21 1 + 89 WR_DIS.ADC1_CAL_VOL_ATTEN2 EFUSE_BLK0 21 1 + 90 WR_DIS.ADC1_CAL_VOL_ATTEN3 EFUSE_BLK0 21 1 + 91 WR_DIS.ADC2_CAL_VOL_ATTEN0 EFUSE_BLK0 21 1 + 92 WR_DIS.ADC2_CAL_VOL_ATTEN1 EFUSE_BLK0 21 1 + 93 WR_DIS.ADC2_CAL_VOL_ATTEN2 EFUSE_BLK0 21 1 + 94 WR_DIS.BLOCK_USR_DATA EFUSE_BLK0 22 1 + 95 WR_DIS.CUSTOM_MAC EFUSE_BLK0 22 1 + 96 WR_DIS.BLOCK_KEY0 EFUSE_BLK0 23 1 + 97 WR_DIS.BLOCK_KEY1 EFUSE_BLK0 24 1 + 98 WR_DIS.BLOCK_KEY2 EFUSE_BLK0 25 1 + 99 WR_DIS.BLOCK_KEY3 EFUSE_BLK0 26 1 + 100 WR_DIS.BLOCK_KEY4 EFUSE_BLK0 27 1 + 101 WR_DIS.BLOCK_KEY5 EFUSE_BLK0 28 1 + 102 WR_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 29 1 + 103 WR_DIS.USB_EXCHG_PINS EFUSE_BLK0 30 1 + 104 WR_DIS.USB_EXT_PHY_ENABLE EFUSE_BLK0 30 1 + 105 WR_DIS.SOFT_DIS_JTAG EFUSE_BLK0 31 1 + 106 RD_DIS EFUSE_BLK0 32 7 + 107 RD_DIS.BLOCK_KEY0 EFUSE_BLK0 32 1 + 108 RD_DIS.BLOCK_KEY1 EFUSE_BLK0 33 1 + 109 RD_DIS.BLOCK_KEY2 EFUSE_BLK0 34 1 + 110 RD_DIS.BLOCK_KEY3 EFUSE_BLK0 35 1 + 111 RD_DIS.BLOCK_KEY4 EFUSE_BLK0 36 1 + 112 RD_DIS.BLOCK_KEY5 EFUSE_BLK0 37 1 + 113 RD_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 38 1 + 114 DIS_ICACHE EFUSE_BLK0 40 1 + 115 DIS_DCACHE EFUSE_BLK0 41 1 + 116 DIS_DOWNLOAD_ICACHE EFUSE_BLK0 42 1 + 117 DIS_DOWNLOAD_DCACHE EFUSE_BLK0 43 1 + 118 DIS_FORCE_DOWNLOAD EFUSE_BLK0 44 1 + 119 DIS_USB_OTG EFUSE_BLK0 45 1 + 120 DIS_TWAI EFUSE_BLK0 46 1 + 121 DIS_APP_CPU EFUSE_BLK0 47 1 + 122 SOFT_DIS_JTAG EFUSE_BLK0 48 3 + 123 DIS_PAD_JTAG EFUSE_BLK0 51 1 + 124 DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 52 1 + 125 USB_EXCHG_PINS EFUSE_BLK0 57 1 + 126 USB_EXT_PHY_ENABLE EFUSE_BLK0 58 1 + 127 VDD_SPI_XPD EFUSE_BLK0 68 1 + 128 VDD_SPI_TIEH EFUSE_BLK0 69 1 + 129 VDD_SPI_FORCE EFUSE_BLK0 70 1 + 130 WDT_DELAY_SEL EFUSE_BLK0 80 2 + 131 SPI_BOOT_CRYPT_CNT EFUSE_BLK0 82 3 + 132 SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 85 1 + 133 SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 86 1 + 134 SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 87 1 + 135 KEY_PURPOSE_0 EFUSE_BLK0 88 4 + 136 KEY_PURPOSE_1 EFUSE_BLK0 92 4 + 137 KEY_PURPOSE_2 EFUSE_BLK0 96 4 + 138 KEY_PURPOSE_3 EFUSE_BLK0 100 4 + 139 KEY_PURPOSE_4 EFUSE_BLK0 104 4 + 140 KEY_PURPOSE_5 EFUSE_BLK0 108 4 + 141 SECURE_BOOT_EN EFUSE_BLK0 116 1 + 142 SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 117 1 + 143 DIS_USB_JTAG EFUSE_BLK0 118 1 + 144 DIS_USB_SERIAL_JTAG EFUSE_BLK0 119 1 + 145 STRAP_JTAG_SEL EFUSE_BLK0 120 1 + 146 USB_PHY_SEL EFUSE_BLK0 121 1 + 147 FLASH_TPUW EFUSE_BLK0 124 4 + 148 DIS_DOWNLOAD_MODE EFUSE_BLK0 128 1 + 149 DIS_DIRECT_BOOT EFUSE_BLK0 129 1 + 150 DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 130 1 + 151 FLASH_ECC_MODE EFUSE_BLK0 131 1 + 152 DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 132 1 + 153 ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 133 1 + 154 UART_PRINT_CONTROL EFUSE_BLK0 134 2 + 155 PIN_POWER_SELECTION EFUSE_BLK0 136 1 + 156 FLASH_TYPE EFUSE_BLK0 137 1 + 157 FLASH_PAGE_SIZE EFUSE_BLK0 138 2 + 158 FLASH_ECC_EN EFUSE_BLK0 140 1 + 159 FORCE_SEND_RESUME EFUSE_BLK0 141 1 + 160 SECURE_VERSION EFUSE_BLK0 142 16 + 161 DIS_USB_OTG_DOWNLOAD_MODE EFUSE_BLK0 159 1 + 162 DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK0 160 1 + 163 DISABLE_BLK_VERSION_MAJOR EFUSE_BLK0 161 1 + 164 MAC EFUSE_BLK1 0 8 + 165 MAC EFUSE_BLK1 8 8 + 166 MAC EFUSE_BLK1 16 8 + 167 MAC EFUSE_BLK1 24 8 + 168 MAC EFUSE_BLK1 32 8 + 169 MAC EFUSE_BLK1 40 8 + 170 SPI_PAD_CONFIG_CLK EFUSE_BLK1 48 6 + 171 SPI_PAD_CONFIG_Q EFUSE_BLK1 54 6 + 172 SPI_PAD_CONFIG_D EFUSE_BLK1 60 6 + 173 SPI_PAD_CONFIG_CS EFUSE_BLK1 66 6 + 174 SPI_PAD_CONFIG_HD EFUSE_BLK1 72 6 + 175 SPI_PAD_CONFIG_WP EFUSE_BLK1 78 6 + 176 SPI_PAD_CONFIG_DQS EFUSE_BLK1 84 6 + 177 SPI_PAD_CONFIG_D4 EFUSE_BLK1 90 6 + 178 SPI_PAD_CONFIG_D5 EFUSE_BLK1 96 6 + 179 SPI_PAD_CONFIG_D6 EFUSE_BLK1 102 6 + 180 SPI_PAD_CONFIG_D7 EFUSE_BLK1 108 6 + 181 WAFER_VERSION_MINOR_LO EFUSE_BLK1 114 3 + 182 PKG_VERSION EFUSE_BLK1 117 3 + 183 BLK_VERSION_MINOR EFUSE_BLK1 120 3 + 184 K_RTC_LDO EFUSE_BLK1 141 7 + 185 K_DIG_LDO EFUSE_BLK1 148 7 + 186 V_RTC_DBIAS20 EFUSE_BLK1 155 8 + 187 V_DIG_DBIAS20 EFUSE_BLK1 163 8 + 188 DIG_DBIAS_HVT EFUSE_BLK1 171 5 + 189 WAFER_VERSION_MINOR_HI EFUSE_BLK1 183 1 + 190 WAFER_VERSION_MAJOR EFUSE_BLK1 184 2 + 191 ADC2_CAL_VOL_ATTEN3 EFUSE_BLK1 186 6 + 192 SYS_DATA_PART2 EFUSE_BLK10 0 256 + 193 OPTIONAL_UNIQUE_ID EFUSE_BLK2 0 128 + 194 BLK_VERSION_MAJOR EFUSE_BLK2 128 2 + 195 TEMP_CALIB EFUSE_BLK2 132 9 + 196 OCODE EFUSE_BLK2 141 8 + 197 ADC1_INIT_CODE_ATTEN0 EFUSE_BLK2 149 8 + 198 ADC1_INIT_CODE_ATTEN1 EFUSE_BLK2 157 6 + 199 ADC1_INIT_CODE_ATTEN2 EFUSE_BLK2 163 6 + 200 ADC1_INIT_CODE_ATTEN3 EFUSE_BLK2 169 6 + 201 ADC2_INIT_CODE_ATTEN0 EFUSE_BLK2 175 8 + 202 ADC2_INIT_CODE_ATTEN1 EFUSE_BLK2 183 6 + 203 ADC2_INIT_CODE_ATTEN2 EFUSE_BLK2 189 6 + 204 ADC2_INIT_CODE_ATTEN3 EFUSE_BLK2 195 6 + 205 ADC1_CAL_VOL_ATTEN0 EFUSE_BLK2 201 8 + 206 ADC1_CAL_VOL_ATTEN1 EFUSE_BLK2 209 8 + 207 ADC1_CAL_VOL_ATTEN2 EFUSE_BLK2 217 8 + 208 ADC1_CAL_VOL_ATTEN3 EFUSE_BLK2 225 8 + 209 ADC2_CAL_VOL_ATTEN0 EFUSE_BLK2 233 8 + 210 ADC2_CAL_VOL_ATTEN1 EFUSE_BLK2 241 7 + 211 ADC2_CAL_VOL_ATTEN2 EFUSE_BLK2 248 7 + 212 USER_DATA EFUSE_BLK3 0 256 + 213 USER_DATA.MAC_CUSTOM EFUSE_BLK3 200 48 + 214 KEY0 EFUSE_BLK4 0 256 + 215 KEY1 EFUSE_BLK5 0 256 + 216 KEY2 EFUSE_BLK6 0 256 + 217 KEY3 EFUSE_BLK7 0 256 + 218 KEY4 EFUSE_BLK8 0 256 + 219 KEY5 EFUSE_BLK9 0 256 Used bits in efuse table: EFUSE_BLK0 - [0 31] [0 0] [2 13] [15 16] [18 18] [20 30] [32 38] [32 38] [40 52] [57 60] [68 70] [80 111] [116 121] [124 157] [159 159] - + [0 31] [0 0] [2 2] ... [22 30] [30 38] [32 38] [40 52] [57 58] [68 70] [80 111] [116 121] [124 157] [159 161] EFUSE_BLK1 - [0 122] [186 191] - + [0 122] [141 175] [183 191] EFUSE_BLK10 [0 255] - EFUSE_BLK2 [0 129] [132 254] - EFUSE_BLK3 [0 255] [200 247] - EFUSE_BLK4 [0 255] - EFUSE_BLK5 [0 255] - EFUSE_BLK6 [0 255] - EFUSE_BLK7 [0 255] - EFUSE_BLK8 [0 255] - EFUSE_BLK9 [0 255] - Note: Not printed ranges are free for using. (bits in EFUSE_BLK0 are reserved for Espressif) - Parsing efuse CSV input file $IDF_PATH/components/efuse/esp32s3/esp_efuse_table.csv ... - Verifying efuse table... diff --git a/docs/en/api-reference/system/inc/show-efuse-table_ESP32.rst b/docs/en/api-reference/system/inc/show-efuse-table_ESP32.rst index 98f728ffaf..3ee3de8026 100644 --- a/docs/en/api-reference/system/inc/show-efuse-table_ESP32.rst +++ b/docs/en/api-reference/system/inc/show-efuse-table_ESP32.rst @@ -8,65 +8,124 @@ Max number of bits in BLK 192 Sorted efuse table: # field_name efuse_block bit_start bit_count - 1 WR_DIS_EFUSE_RD_DISABLE EFUSE_BLK0 0 1 - 2 WR_DIS_FLASH_CRYPT_CNT EFUSE_BLK0 2 1 - 3 WR_DIS_BLK1 EFUSE_BLK0 7 1 - 4 WR_DIS_BLK2 EFUSE_BLK0 8 1 - 5 WR_DIS_BLK3 EFUSE_BLK0 9 1 - 6 RD_DIS_BLK1 EFUSE_BLK0 16 1 - 7 RD_DIS_BLK2 EFUSE_BLK0 17 1 - 8 RD_DIS_BLK3 EFUSE_BLK0 18 1 - 9 FLASH_CRYPT_CNT EFUSE_BLK0 20 7 - 10 UART_DOWNLOAD_DIS EFUSE_BLK0 27 1 - 11 MAC_FACTORY EFUSE_BLK0 32 8 - 12 MAC_FACTORY EFUSE_BLK0 40 8 - 13 MAC_FACTORY EFUSE_BLK0 48 8 - 14 MAC_FACTORY EFUSE_BLK0 56 8 - 15 MAC_FACTORY EFUSE_BLK0 64 8 - 16 MAC_FACTORY EFUSE_BLK0 72 8 - 17 MAC_FACTORY_CRC EFUSE_BLK0 80 8 - 18 CHIP_VER_DIS_APP_CPU EFUSE_BLK0 96 1 - 19 CHIP_VER_DIS_BT EFUSE_BLK0 97 1 - 20 CHIP_VER_PKG EFUSE_BLK0 98 1 - 21 CHIP_VER_PKG EFUSE_BLK0 105 3 - 22 CHIP_CPU_FREQ_LOW EFUSE_BLK0 108 1 - 23 CHIP_CPU_FREQ_RATED EFUSE_BLK0 109 1 - 24 CHIP_VER_REV1 EFUSE_BLK0 111 1 - 25 ADC_VREF_AND_SDIO_DREF EFUSE_BLK0 136 6 - 26 XPD_SDIO_REG EFUSE_BLK0 142 1 - 27 SDIO_TIEH EFUSE_BLK0 143 1 - 28 SDIO_FORCE EFUSE_BLK0 144 1 - 29 CHIP_VER_REV2 EFUSE_BLK0 180 1 - 30 ENCRYPT_CONFIG EFUSE_BLK0 188 4 - 31 CONSOLE_DEBUG_DISABLE EFUSE_BLK0 194 1 - 32 ABS_DONE_0 EFUSE_BLK0 196 1 - 33 ABS_DONE_1 EFUSE_BLK0 197 1 - 34 DISABLE_JTAG EFUSE_BLK0 198 1 - 35 DISABLE_DL_ENCRYPT EFUSE_BLK0 199 1 - 36 DISABLE_DL_DECRYPT EFUSE_BLK0 200 1 - 37 DISABLE_DL_CACHE EFUSE_BLK0 201 1 - 38 ENCRYPT_FLASH_KEY EFUSE_BLK1 0 192 - 39 SECURE_BOOT_KEY EFUSE_BLK2 0 192 - 40 MAC_CUSTOM_CRC EFUSE_BLK3 0 8 - 41 MAC_CUSTOM EFUSE_BLK3 8 48 - 42 ADC1_TP_LOW EFUSE_BLK3 96 7 - 43 ADC1_TP_HIGH EFUSE_BLK3 103 9 - 44 ADC2_TP_LOW EFUSE_BLK3 112 7 - 45 ADC2_TP_HIGH EFUSE_BLK3 119 9 - 46 SECURE_VERSION EFUSE_BLK3 128 32 - 47 MAC_CUSTOM_VER EFUSE_BLK3 184 8 + 1 WR_DIS EFUSE_BLK0 0 16 + 2 WR_DIS.RD_DIS EFUSE_BLK0 0 1 + 3 WR_DIS.WR_DIS EFUSE_BLK0 1 1 + 4 WR_DIS.FLASH_CRYPT_CNT EFUSE_BLK0 2 1 + 5 WR_DIS.UART_DOWNLOAD_DIS EFUSE_BLK0 2 1 + 6 WR_DIS.MAC EFUSE_BLK0 3 1 + 7 WR_DIS.MAC_CRC EFUSE_BLK0 3 1 + 8 WR_DIS.DISABLE_APP_CPU EFUSE_BLK0 3 1 + 9 WR_DIS.DISABLE_BT EFUSE_BLK0 3 1 + 10 WR_DIS.DIS_CACHE EFUSE_BLK0 3 1 + 11 WR_DIS.VOL_LEVEL_HP_INV EFUSE_BLK0 3 1 + 12 WR_DIS.CLK8M_FREQ EFUSE_BLK0 4 1 + 13 WR_DIS.ADC_VREF EFUSE_BLK0 4 1 + 14 WR_DIS.XPD_SDIO_REG EFUSE_BLK0 5 1 + 15 WR_DIS.XPD_SDIO_TIEH EFUSE_BLK0 5 1 + 16 WR_DIS.XPD_SDIO_FORCE EFUSE_BLK0 5 1 + 17 WR_DIS.SPI_PAD_CONFIG_CLK EFUSE_BLK0 6 1 + 18 WR_DIS.SPI_PAD_CONFIG_Q EFUSE_BLK0 6 1 + 19 WR_DIS.SPI_PAD_CONFIG_D EFUSE_BLK0 6 1 + 20 WR_DIS.SPI_PAD_CONFIG_CS0 EFUSE_BLK0 6 1 + 21 WR_DIS.BLOCK1 EFUSE_BLK0 7 1 + 22 WR_DIS.BLOCK2 EFUSE_BLK0 8 1 + 23 WR_DIS.BLOCK3 EFUSE_BLK0 9 1 + 24 WR_DIS.CUSTOM_MAC_CRC EFUSE_BLK0 9 1 + 25 WR_DIS.CUSTOM_MAC EFUSE_BLK0 9 1 + 26 WR_DIS.ADC1_TP_LOW EFUSE_BLK0 9 1 + 27 WR_DIS.ADC1_TP_HIGH EFUSE_BLK0 9 1 + 28 WR_DIS.ADC2_TP_LOW EFUSE_BLK0 9 1 + 29 WR_DIS.ADC2_TP_HIGH EFUSE_BLK0 9 1 + 30 WR_DIS.SECURE_VERSION EFUSE_BLK0 9 1 + 31 WR_DIS.MAC_VERSION EFUSE_BLK0 9 1 + 32 WR_DIS.BLK3_PART_RESERVE EFUSE_BLK0 10 1 + 33 WR_DIS.FLASH_CRYPT_CONFIG EFUSE_BLK0 10 1 + 34 WR_DIS.CODING_SCHEME EFUSE_BLK0 10 1 + 35 WR_DIS.KEY_STATUS EFUSE_BLK0 10 1 + 36 WR_DIS.ABS_DONE_0 EFUSE_BLK0 12 1 + 37 WR_DIS.ABS_DONE_1 EFUSE_BLK0 13 1 + 38 WR_DIS.JTAG_DISABLE EFUSE_BLK0 14 1 + 39 WR_DIS.CONSOLE_DEBUG_DISABLE EFUSE_BLK0 15 1 + 40 WR_DIS.DISABLE_DL_ENCRYPT EFUSE_BLK0 15 1 + 41 WR_DIS.DISABLE_DL_DECRYPT EFUSE_BLK0 15 1 + 42 WR_DIS.DISABLE_DL_CACHE EFUSE_BLK0 15 1 + 43 RD_DIS EFUSE_BLK0 16 4 + 44 RD_DIS.BLOCK1 EFUSE_BLK0 16 1 + 45 RD_DIS.BLOCK2 EFUSE_BLK0 17 1 + 46 RD_DIS.BLOCK3 EFUSE_BLK0 18 1 + 47 RD_DIS.CUSTOM_MAC_CRC EFUSE_BLK0 18 1 + 48 RD_DIS.CUSTOM_MAC EFUSE_BLK0 18 1 + 49 RD_DIS.ADC1_TP_LOW EFUSE_BLK0 18 1 + 50 RD_DIS.ADC1_TP_HIGH EFUSE_BLK0 18 1 + 51 RD_DIS.ADC2_TP_LOW EFUSE_BLK0 18 1 + 52 RD_DIS.ADC2_TP_HIGH EFUSE_BLK0 18 1 + 53 RD_DIS.SECURE_VERSION EFUSE_BLK0 18 1 + 54 RD_DIS.MAC_VERSION EFUSE_BLK0 18 1 + 55 RD_DIS.BLK3_PART_RESERVE EFUSE_BLK0 19 1 + 56 RD_DIS.FLASH_CRYPT_CONFIG EFUSE_BLK0 19 1 + 57 RD_DIS.CODING_SCHEME EFUSE_BLK0 19 1 + 58 RD_DIS.KEY_STATUS EFUSE_BLK0 19 1 + 59 FLASH_CRYPT_CNT EFUSE_BLK0 20 7 + 60 UART_DOWNLOAD_DIS EFUSE_BLK0 27 1 + 61 MAC EFUSE_BLK0 32 8 + 62 MAC EFUSE_BLK0 40 8 + 63 MAC EFUSE_BLK0 48 8 + 64 MAC EFUSE_BLK0 56 8 + 65 MAC EFUSE_BLK0 64 8 + 66 MAC EFUSE_BLK0 72 8 + 67 MAC_CRC EFUSE_BLK0 80 8 + 68 DISABLE_APP_CPU EFUSE_BLK0 96 1 + 69 DISABLE_BT EFUSE_BLK0 97 1 + 70 CHIP_PACKAGE_4BIT EFUSE_BLK0 98 1 + 71 DIS_CACHE EFUSE_BLK0 99 1 + 72 SPI_PAD_CONFIG_HD EFUSE_BLK0 100 5 + 73 CHIP_PACKAGE EFUSE_BLK0 105 3 + 74 CHIP_CPU_FREQ_LOW EFUSE_BLK0 108 1 + 75 CHIP_CPU_FREQ_RATED EFUSE_BLK0 109 1 + 76 BLK3_PART_RESERVE EFUSE_BLK0 110 1 + 77 CHIP_VER_REV1 EFUSE_BLK0 111 1 + 78 CLK8M_FREQ EFUSE_BLK0 128 8 + 79 ADC_VREF EFUSE_BLK0 136 5 + 80 XPD_SDIO_REG EFUSE_BLK0 142 1 + 81 XPD_SDIO_TIEH EFUSE_BLK0 143 1 + 82 XPD_SDIO_FORCE EFUSE_BLK0 144 1 + 83 SPI_PAD_CONFIG_CLK EFUSE_BLK0 160 5 + 84 SPI_PAD_CONFIG_Q EFUSE_BLK0 165 5 + 85 SPI_PAD_CONFIG_D EFUSE_BLK0 170 5 + 86 SPI_PAD_CONFIG_CS0 EFUSE_BLK0 175 5 + 87 CHIP_VER_REV2 EFUSE_BLK0 180 1 + 88 VOL_LEVEL_HP_INV EFUSE_BLK0 182 2 + 89 WAFER_VERSION_MINOR EFUSE_BLK0 184 2 + 90 FLASH_CRYPT_CONFIG EFUSE_BLK0 188 4 + 91 CODING_SCHEME EFUSE_BLK0 192 2 + 92 CONSOLE_DEBUG_DISABLE EFUSE_BLK0 194 1 + 93 DISABLE_SDIO_HOST EFUSE_BLK0 195 1 + 94 ABS_DONE_0 EFUSE_BLK0 196 1 + 95 ABS_DONE_1 EFUSE_BLK0 197 1 + 96 JTAG_DISABLE EFUSE_BLK0 198 1 + 97 DISABLE_DL_ENCRYPT EFUSE_BLK0 199 1 + 98 DISABLE_DL_DECRYPT EFUSE_BLK0 200 1 + 99 DISABLE_DL_CACHE EFUSE_BLK0 201 1 + 100 KEY_STATUS EFUSE_BLK0 202 1 + 101 BLOCK1 EFUSE_BLK1 0 192 + 102 BLOCK2 EFUSE_BLK2 0 192 + 103 CUSTOM_MAC_CRC EFUSE_BLK3 0 8 + 104 MAC_CUSTOM EFUSE_BLK3 8 48 + 105 ADC1_TP_LOW EFUSE_BLK3 96 7 + 106 ADC1_TP_HIGH EFUSE_BLK3 103 9 + 107 ADC2_TP_LOW EFUSE_BLK3 112 7 + 108 ADC2_TP_HIGH EFUSE_BLK3 119 9 + 109 SECURE_VERSION EFUSE_BLK3 128 32 + 110 MAC_VERSION EFUSE_BLK3 184 8 Used bits in efuse table: EFUSE_BLK0 - [0 0] [2 2] [7 9] [16 18] [20 27] [32 87] [96 98] [105 109] [111 111] [136 144] [180 180] [188 191] [194 194] [196 201] - + [0 15] [0 2] [2 3] ... [19 19] [19 27] [32 87] [96 111] [128 140] [142 144] [160 180] [182 185] [188 202] EFUSE_BLK1 [0 191] - EFUSE_BLK2 [0 191] - EFUSE_BLK3 [0 55] [96 159] [184 191] - Note: Not printed ranges are free for using. (bits in EFUSE_BLK0 are reserved for Espressif) diff --git a/docs/zh_CN/api-reference/system/inc/espefuse_summary_ESP32-H2.rst b/docs/zh_CN/api-reference/system/inc/espefuse_summary_ESP32-H2.rst index e5a43ee310..cd1534e12f 100644 --- a/docs/zh_CN/api-reference/system/inc/espefuse_summary_ESP32-H2.rst +++ b/docs/zh_CN/api-reference/system/inc/espefuse_summary_ESP32-H2.rst @@ -1,3 +1 @@ -.. code-block:: none - - TO BE UPDATED +.. include:: ../../../en/api-reference/system/inc/espefuse_summary_ESP32-H2.rst \ No newline at end of file diff --git a/docs/zh_CN/api-reference/system/inc/revisions_ESP32-H2.rst b/docs/zh_CN/api-reference/system/inc/revisions_ESP32-H2.rst index 21fca39fa4..6f59d9e940 100644 --- a/docs/zh_CN/api-reference/system/inc/revisions_ESP32-H2.rst +++ b/docs/zh_CN/api-reference/system/inc/revisions_ESP32-H2.rst @@ -1,6 +1 @@ - -+------------------------+ -| Revision (Major.Minor) | -+------------------------+ -| v0.0 | -+------------------------+ +.. include:: ../../../en/api-reference/system/inc/revisions_ESP32-H2.rst diff --git a/docs/zh_CN/api-reference/system/inc/show-efuse-table_ESP32-H2.rst b/docs/zh_CN/api-reference/system/inc/show-efuse-table_ESP32-H2.rst index 5eb6007d56..479b56ee63 100644 --- a/docs/zh_CN/api-reference/system/inc/show-efuse-table_ESP32-H2.rst +++ b/docs/zh_CN/api-reference/system/inc/show-efuse-table_ESP32-H2.rst @@ -1,4 +1 @@ - -.. code-block:: none - - TO BE UPDATED +.. include:: ../../../en/api-reference/system/inc/show-efuse-table_ESP32-H2.rst