From 78a2e2cb2f561c2896242ba40086949102649734 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Fri, 23 May 2025 14:28:28 +0800 Subject: [PATCH] change(apm): update apm soc headers of c5 --- .../soc/esp32c5/register/soc/cpu_apm_reg.h | 320 ++-- .../soc/esp32c5/register/soc/cpu_apm_struct.h | 140 +- .../soc/esp32c5/register/soc/hp_apm_reg.h | 650 ++++--- .../soc/esp32c5/register/soc/hp_apm_struct.h | 254 ++- .../soc/esp32c5/register/soc/lp_apm0_reg.h | 288 +-- .../soc/esp32c5/register/soc/lp_apm0_struct.h | 100 +- .../soc/esp32c5/register/soc/lp_apm_reg.h | 314 ++-- .../soc/esp32c5/register/soc/lp_apm_struct.h | 134 +- .../soc/esp32c5/register/soc/lp_tee_reg.h | 143 +- .../soc/esp32c5/register/soc/lp_tee_struct.h | 138 +- components/soc/esp32c5/register/soc/tee_reg.h | 1619 +++++------------ .../soc/esp32c5/register/soc/tee_struct.h | 820 ++------- 12 files changed, 1791 insertions(+), 3129 deletions(-) diff --git a/components/soc/esp32c5/register/soc/cpu_apm_reg.h b/components/soc/esp32c5/register/soc/cpu_apm_reg.h index 9c6a7cbe52..daf755e202 100644 --- a/components/soc/esp32c5/register/soc/cpu_apm_reg.h +++ b/components/soc/esp32c5/register/soc/cpu_apm_reg.h @@ -12,13 +12,13 @@ extern "C" { #endif /** CPU_APM_REGION_FILTER_EN_REG register - * Region filter enable register + * Region enable register */ #define CPU_APM_REGION_FILTER_EN_REG (DR_REG_CPU_APM_BASE + 0x0) /** CPU_APM_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1; - * Configure bit $n (0-7) to enable region $n. - * 0: disable - * 1: enable + * Configures bit $n (0-7) to enable region $n (0-7). + * 0: Disable + * 1: Enable */ #define CPU_APM_REGION_FILTER_EN 0x000000FFU #define CPU_APM_REGION_FILTER_EN_M (CPU_APM_REGION_FILTER_EN_V << CPU_APM_REGION_FILTER_EN_S) @@ -37,7 +37,7 @@ extern "C" { #define CPU_APM_REGION0_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION0_ADDR_START_L_S 0 /** CPU_APM_REGION0_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 0. + * Configures the start address of region 0. */ #define CPU_APM_REGION0_ADDR_START 0x0000007FU #define CPU_APM_REGION0_ADDR_START_M (CPU_APM_REGION0_ADDR_START_V << CPU_APM_REGION0_ADDR_START_S) @@ -63,7 +63,7 @@ extern "C" { #define CPU_APM_REGION0_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION0_ADDR_END_L_S 0 /** CPU_APM_REGION0_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 0. + * Configures the end address of region 0. */ #define CPU_APM_REGION0_ADDR_END 0x0000007FU #define CPU_APM_REGION0_ADDR_END_M (CPU_APM_REGION0_ADDR_END_V << CPU_APM_REGION0_ADDR_END_S) @@ -78,74 +78,78 @@ extern "C" { #define CPU_APM_REGION0_ADDR_END_H_S 19 /** CPU_APM_REGION0_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION0_ATTR_REG (DR_REG_CPU_APM_BASE + 0xc) /** CPU_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 0. + * Configures the execution permission in region 0 in REE0 mode. */ #define CPU_APM_REGION0_R0_X (BIT(0)) #define CPU_APM_REGION0_R0_X_M (CPU_APM_REGION0_R0_X_V << CPU_APM_REGION0_R0_X_S) #define CPU_APM_REGION0_R0_X_V 0x00000001U #define CPU_APM_REGION0_R0_X_S 0 /** CPU_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 0. + * Configures the write permission in region 0 in REE0 mode. */ #define CPU_APM_REGION0_R0_W (BIT(1)) #define CPU_APM_REGION0_R0_W_M (CPU_APM_REGION0_R0_W_V << CPU_APM_REGION0_R0_W_S) #define CPU_APM_REGION0_R0_W_V 0x00000001U #define CPU_APM_REGION0_R0_W_S 1 /** CPU_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 0. + * Configures the read permission in region 0 in REE0 mode. */ #define CPU_APM_REGION0_R0_R (BIT(2)) #define CPU_APM_REGION0_R0_R_M (CPU_APM_REGION0_R0_R_V << CPU_APM_REGION0_R0_R_S) #define CPU_APM_REGION0_R0_R_V 0x00000001U #define CPU_APM_REGION0_R0_R_S 2 /** CPU_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 0. + * Configures the execution permission in region 0 in REE1 mode. */ #define CPU_APM_REGION0_R1_X (BIT(4)) #define CPU_APM_REGION0_R1_X_M (CPU_APM_REGION0_R1_X_V << CPU_APM_REGION0_R1_X_S) #define CPU_APM_REGION0_R1_X_V 0x00000001U #define CPU_APM_REGION0_R1_X_S 4 /** CPU_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 0. + * Configures the write permission in region 0 in REE1 mode. */ #define CPU_APM_REGION0_R1_W (BIT(5)) #define CPU_APM_REGION0_R1_W_M (CPU_APM_REGION0_R1_W_V << CPU_APM_REGION0_R1_W_S) #define CPU_APM_REGION0_R1_W_V 0x00000001U #define CPU_APM_REGION0_R1_W_S 5 /** CPU_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 0. + * Configures the read permission in region 0 in REE1 mode. */ #define CPU_APM_REGION0_R1_R (BIT(6)) #define CPU_APM_REGION0_R1_R_M (CPU_APM_REGION0_R1_R_V << CPU_APM_REGION0_R1_R_S) #define CPU_APM_REGION0_R1_R_V 0x00000001U #define CPU_APM_REGION0_R1_R_S 6 /** CPU_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 0. + * Configures the execution permission in region 0 in REE2 mode. */ #define CPU_APM_REGION0_R2_X (BIT(8)) #define CPU_APM_REGION0_R2_X_M (CPU_APM_REGION0_R2_X_V << CPU_APM_REGION0_R2_X_S) #define CPU_APM_REGION0_R2_X_V 0x00000001U #define CPU_APM_REGION0_R2_X_S 8 /** CPU_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 0. + * Configures the write permission in region 0 in REE2 mode. */ #define CPU_APM_REGION0_R2_W (BIT(9)) #define CPU_APM_REGION0_R2_W_M (CPU_APM_REGION0_R2_W_V << CPU_APM_REGION0_R2_W_S) #define CPU_APM_REGION0_R2_W_V 0x00000001U #define CPU_APM_REGION0_R2_W_S 9 /** CPU_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 0. + * Configures the read permission in region 0 in REE2 mode. */ #define CPU_APM_REGION0_R2_R (BIT(10)) #define CPU_APM_REGION0_R2_R_M (CPU_APM_REGION0_R2_R_V << CPU_APM_REGION0_R2_R_S) #define CPU_APM_REGION0_R2_R_V 0x00000001U #define CPU_APM_REGION0_R2_R_S 10 /** CPU_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 0's configuration registers + * (CPU_APM_REGION0_ADDR_START_REG, CPU_APM_REGION0_ADDR_END_REG, and + * CPU_APM_REGION0_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION0_LOCK (BIT(11)) #define CPU_APM_REGION0_LOCK_M (CPU_APM_REGION0_LOCK_V << CPU_APM_REGION0_LOCK_S) @@ -164,7 +168,7 @@ extern "C" { #define CPU_APM_REGION1_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION1_ADDR_START_L_S 0 /** CPU_APM_REGION1_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 1. + * Configures the start address of region 1. */ #define CPU_APM_REGION1_ADDR_START 0x0000007FU #define CPU_APM_REGION1_ADDR_START_M (CPU_APM_REGION1_ADDR_START_V << CPU_APM_REGION1_ADDR_START_S) @@ -190,7 +194,7 @@ extern "C" { #define CPU_APM_REGION1_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION1_ADDR_END_L_S 0 /** CPU_APM_REGION1_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 1. + * Configures the end address of region 1. */ #define CPU_APM_REGION1_ADDR_END 0x0000007FU #define CPU_APM_REGION1_ADDR_END_M (CPU_APM_REGION1_ADDR_END_V << CPU_APM_REGION1_ADDR_END_S) @@ -205,74 +209,78 @@ extern "C" { #define CPU_APM_REGION1_ADDR_END_H_S 19 /** CPU_APM_REGION1_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION1_ATTR_REG (DR_REG_CPU_APM_BASE + 0x18) /** CPU_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 1. + * Configures the execution permission in region 1 in REE0 mode. */ #define CPU_APM_REGION1_R0_X (BIT(0)) #define CPU_APM_REGION1_R0_X_M (CPU_APM_REGION1_R0_X_V << CPU_APM_REGION1_R0_X_S) #define CPU_APM_REGION1_R0_X_V 0x00000001U #define CPU_APM_REGION1_R0_X_S 0 /** CPU_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 1. + * Configures the write permission in region 1 in REE0 mode. */ #define CPU_APM_REGION1_R0_W (BIT(1)) #define CPU_APM_REGION1_R0_W_M (CPU_APM_REGION1_R0_W_V << CPU_APM_REGION1_R0_W_S) #define CPU_APM_REGION1_R0_W_V 0x00000001U #define CPU_APM_REGION1_R0_W_S 1 /** CPU_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 1. + * Configures the read permission in region 1 in REE0 mode. */ #define CPU_APM_REGION1_R0_R (BIT(2)) #define CPU_APM_REGION1_R0_R_M (CPU_APM_REGION1_R0_R_V << CPU_APM_REGION1_R0_R_S) #define CPU_APM_REGION1_R0_R_V 0x00000001U #define CPU_APM_REGION1_R0_R_S 2 /** CPU_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 1. + * Configures the execution permission in region 1 in REE1 mode. */ #define CPU_APM_REGION1_R1_X (BIT(4)) #define CPU_APM_REGION1_R1_X_M (CPU_APM_REGION1_R1_X_V << CPU_APM_REGION1_R1_X_S) #define CPU_APM_REGION1_R1_X_V 0x00000001U #define CPU_APM_REGION1_R1_X_S 4 /** CPU_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 1. + * Configures the write permission in region 1 in REE1 mode. */ #define CPU_APM_REGION1_R1_W (BIT(5)) #define CPU_APM_REGION1_R1_W_M (CPU_APM_REGION1_R1_W_V << CPU_APM_REGION1_R1_W_S) #define CPU_APM_REGION1_R1_W_V 0x00000001U #define CPU_APM_REGION1_R1_W_S 5 /** CPU_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 1. + * Configures the read permission in region 1 in REE1 mode. */ #define CPU_APM_REGION1_R1_R (BIT(6)) #define CPU_APM_REGION1_R1_R_M (CPU_APM_REGION1_R1_R_V << CPU_APM_REGION1_R1_R_S) #define CPU_APM_REGION1_R1_R_V 0x00000001U #define CPU_APM_REGION1_R1_R_S 6 /** CPU_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 1. + * Configures the execution permission in region 1 in REE2 mode. */ #define CPU_APM_REGION1_R2_X (BIT(8)) #define CPU_APM_REGION1_R2_X_M (CPU_APM_REGION1_R2_X_V << CPU_APM_REGION1_R2_X_S) #define CPU_APM_REGION1_R2_X_V 0x00000001U #define CPU_APM_REGION1_R2_X_S 8 /** CPU_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 1. + * Configures the write permission in region 1 in REE2 mode. */ #define CPU_APM_REGION1_R2_W (BIT(9)) #define CPU_APM_REGION1_R2_W_M (CPU_APM_REGION1_R2_W_V << CPU_APM_REGION1_R2_W_S) #define CPU_APM_REGION1_R2_W_V 0x00000001U #define CPU_APM_REGION1_R2_W_S 9 /** CPU_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 1. + * Configures the read permission in region 1 in REE2 mode. */ #define CPU_APM_REGION1_R2_R (BIT(10)) #define CPU_APM_REGION1_R2_R_M (CPU_APM_REGION1_R2_R_V << CPU_APM_REGION1_R2_R_S) #define CPU_APM_REGION1_R2_R_V 0x00000001U #define CPU_APM_REGION1_R2_R_S 10 /** CPU_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 1's configuration registers + * (CPU_APM_REGION1_ADDR_START_REG, CPU_APM_REGION1_ADDR_END_REG, and + * CPU_APM_REGION1_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION1_LOCK (BIT(11)) #define CPU_APM_REGION1_LOCK_M (CPU_APM_REGION1_LOCK_V << CPU_APM_REGION1_LOCK_S) @@ -291,7 +299,7 @@ extern "C" { #define CPU_APM_REGION2_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION2_ADDR_START_L_S 0 /** CPU_APM_REGION2_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 2. + * Configures the start address of region 2. */ #define CPU_APM_REGION2_ADDR_START 0x0000007FU #define CPU_APM_REGION2_ADDR_START_M (CPU_APM_REGION2_ADDR_START_V << CPU_APM_REGION2_ADDR_START_S) @@ -317,7 +325,7 @@ extern "C" { #define CPU_APM_REGION2_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION2_ADDR_END_L_S 0 /** CPU_APM_REGION2_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 2. + * Configures the end address of region 2. */ #define CPU_APM_REGION2_ADDR_END 0x0000007FU #define CPU_APM_REGION2_ADDR_END_M (CPU_APM_REGION2_ADDR_END_V << CPU_APM_REGION2_ADDR_END_S) @@ -332,74 +340,78 @@ extern "C" { #define CPU_APM_REGION2_ADDR_END_H_S 19 /** CPU_APM_REGION2_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION2_ATTR_REG (DR_REG_CPU_APM_BASE + 0x24) /** CPU_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 2. + * Configures the execution permission in region 2 in REE0 mode. */ #define CPU_APM_REGION2_R0_X (BIT(0)) #define CPU_APM_REGION2_R0_X_M (CPU_APM_REGION2_R0_X_V << CPU_APM_REGION2_R0_X_S) #define CPU_APM_REGION2_R0_X_V 0x00000001U #define CPU_APM_REGION2_R0_X_S 0 /** CPU_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 2. + * Configures the write permission in region 2 in REE0 mode. */ #define CPU_APM_REGION2_R0_W (BIT(1)) #define CPU_APM_REGION2_R0_W_M (CPU_APM_REGION2_R0_W_V << CPU_APM_REGION2_R0_W_S) #define CPU_APM_REGION2_R0_W_V 0x00000001U #define CPU_APM_REGION2_R0_W_S 1 /** CPU_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 2. + * Configures the read permission in region 2 in REE0 mode. */ #define CPU_APM_REGION2_R0_R (BIT(2)) #define CPU_APM_REGION2_R0_R_M (CPU_APM_REGION2_R0_R_V << CPU_APM_REGION2_R0_R_S) #define CPU_APM_REGION2_R0_R_V 0x00000001U #define CPU_APM_REGION2_R0_R_S 2 /** CPU_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 2. + * Configures the execution permission in region 2 in REE1 mode. */ #define CPU_APM_REGION2_R1_X (BIT(4)) #define CPU_APM_REGION2_R1_X_M (CPU_APM_REGION2_R1_X_V << CPU_APM_REGION2_R1_X_S) #define CPU_APM_REGION2_R1_X_V 0x00000001U #define CPU_APM_REGION2_R1_X_S 4 /** CPU_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 2. + * Configures the write permission in region 2 in REE1 mode. */ #define CPU_APM_REGION2_R1_W (BIT(5)) #define CPU_APM_REGION2_R1_W_M (CPU_APM_REGION2_R1_W_V << CPU_APM_REGION2_R1_W_S) #define CPU_APM_REGION2_R1_W_V 0x00000001U #define CPU_APM_REGION2_R1_W_S 5 /** CPU_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 2. + * Configures the read permission in region 2 in REE1 mode. */ #define CPU_APM_REGION2_R1_R (BIT(6)) #define CPU_APM_REGION2_R1_R_M (CPU_APM_REGION2_R1_R_V << CPU_APM_REGION2_R1_R_S) #define CPU_APM_REGION2_R1_R_V 0x00000001U #define CPU_APM_REGION2_R1_R_S 6 /** CPU_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 2. + * Configures the execution permission in region 2 in REE2 mode. */ #define CPU_APM_REGION2_R2_X (BIT(8)) #define CPU_APM_REGION2_R2_X_M (CPU_APM_REGION2_R2_X_V << CPU_APM_REGION2_R2_X_S) #define CPU_APM_REGION2_R2_X_V 0x00000001U #define CPU_APM_REGION2_R2_X_S 8 /** CPU_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 2. + * Configures the write permission in region 2 in REE2 mode. */ #define CPU_APM_REGION2_R2_W (BIT(9)) #define CPU_APM_REGION2_R2_W_M (CPU_APM_REGION2_R2_W_V << CPU_APM_REGION2_R2_W_S) #define CPU_APM_REGION2_R2_W_V 0x00000001U #define CPU_APM_REGION2_R2_W_S 9 /** CPU_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 2. + * Configures the read permission in region 2 in REE2 mode. */ #define CPU_APM_REGION2_R2_R (BIT(10)) #define CPU_APM_REGION2_R2_R_M (CPU_APM_REGION2_R2_R_V << CPU_APM_REGION2_R2_R_S) #define CPU_APM_REGION2_R2_R_V 0x00000001U #define CPU_APM_REGION2_R2_R_S 10 /** CPU_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 2's configuration registers + * (CPU_APM_REGION2_ADDR_START_REG, CPU_APM_REGION2_ADDR_END_REG, and + * CPU_APM_REGION2_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION2_LOCK (BIT(11)) #define CPU_APM_REGION2_LOCK_M (CPU_APM_REGION2_LOCK_V << CPU_APM_REGION2_LOCK_S) @@ -418,7 +430,7 @@ extern "C" { #define CPU_APM_REGION3_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION3_ADDR_START_L_S 0 /** CPU_APM_REGION3_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 3. + * Configures the start address of region 3. */ #define CPU_APM_REGION3_ADDR_START 0x0000007FU #define CPU_APM_REGION3_ADDR_START_M (CPU_APM_REGION3_ADDR_START_V << CPU_APM_REGION3_ADDR_START_S) @@ -444,7 +456,7 @@ extern "C" { #define CPU_APM_REGION3_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION3_ADDR_END_L_S 0 /** CPU_APM_REGION3_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 3. + * Configures the end address of region 3. */ #define CPU_APM_REGION3_ADDR_END 0x0000007FU #define CPU_APM_REGION3_ADDR_END_M (CPU_APM_REGION3_ADDR_END_V << CPU_APM_REGION3_ADDR_END_S) @@ -459,74 +471,78 @@ extern "C" { #define CPU_APM_REGION3_ADDR_END_H_S 19 /** CPU_APM_REGION3_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION3_ATTR_REG (DR_REG_CPU_APM_BASE + 0x30) /** CPU_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 3. + * Configures the execution permission in region 3 in REE0 mode. */ #define CPU_APM_REGION3_R0_X (BIT(0)) #define CPU_APM_REGION3_R0_X_M (CPU_APM_REGION3_R0_X_V << CPU_APM_REGION3_R0_X_S) #define CPU_APM_REGION3_R0_X_V 0x00000001U #define CPU_APM_REGION3_R0_X_S 0 /** CPU_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 3. + * Configures the write permission in region 3 in REE0 mode. */ #define CPU_APM_REGION3_R0_W (BIT(1)) #define CPU_APM_REGION3_R0_W_M (CPU_APM_REGION3_R0_W_V << CPU_APM_REGION3_R0_W_S) #define CPU_APM_REGION3_R0_W_V 0x00000001U #define CPU_APM_REGION3_R0_W_S 1 /** CPU_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 3. + * Configures the read permission in region 3 in REE0 mode. */ #define CPU_APM_REGION3_R0_R (BIT(2)) #define CPU_APM_REGION3_R0_R_M (CPU_APM_REGION3_R0_R_V << CPU_APM_REGION3_R0_R_S) #define CPU_APM_REGION3_R0_R_V 0x00000001U #define CPU_APM_REGION3_R0_R_S 2 /** CPU_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 3. + * Configures the execution permission in region 3 in REE1 mode. */ #define CPU_APM_REGION3_R1_X (BIT(4)) #define CPU_APM_REGION3_R1_X_M (CPU_APM_REGION3_R1_X_V << CPU_APM_REGION3_R1_X_S) #define CPU_APM_REGION3_R1_X_V 0x00000001U #define CPU_APM_REGION3_R1_X_S 4 /** CPU_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 3. + * Configures the write permission in region 3 in REE1 mode. */ #define CPU_APM_REGION3_R1_W (BIT(5)) #define CPU_APM_REGION3_R1_W_M (CPU_APM_REGION3_R1_W_V << CPU_APM_REGION3_R1_W_S) #define CPU_APM_REGION3_R1_W_V 0x00000001U #define CPU_APM_REGION3_R1_W_S 5 /** CPU_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 3. + * Configures the read permission in region 3 in REE1 mode. */ #define CPU_APM_REGION3_R1_R (BIT(6)) #define CPU_APM_REGION3_R1_R_M (CPU_APM_REGION3_R1_R_V << CPU_APM_REGION3_R1_R_S) #define CPU_APM_REGION3_R1_R_V 0x00000001U #define CPU_APM_REGION3_R1_R_S 6 /** CPU_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 3. + * Configures the execution permission in region 3 in REE2 mode. */ #define CPU_APM_REGION3_R2_X (BIT(8)) #define CPU_APM_REGION3_R2_X_M (CPU_APM_REGION3_R2_X_V << CPU_APM_REGION3_R2_X_S) #define CPU_APM_REGION3_R2_X_V 0x00000001U #define CPU_APM_REGION3_R2_X_S 8 /** CPU_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 3. + * Configures the write permission in region 3 in REE2 mode. */ #define CPU_APM_REGION3_R2_W (BIT(9)) #define CPU_APM_REGION3_R2_W_M (CPU_APM_REGION3_R2_W_V << CPU_APM_REGION3_R2_W_S) #define CPU_APM_REGION3_R2_W_V 0x00000001U #define CPU_APM_REGION3_R2_W_S 9 /** CPU_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 3. + * Configures the read permission in region 3 in REE2 mode. */ #define CPU_APM_REGION3_R2_R (BIT(10)) #define CPU_APM_REGION3_R2_R_M (CPU_APM_REGION3_R2_R_V << CPU_APM_REGION3_R2_R_S) #define CPU_APM_REGION3_R2_R_V 0x00000001U #define CPU_APM_REGION3_R2_R_S 10 /** CPU_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 3's configuration registers + * (CPU_APM_REGION3_ADDR_START_REG, CPU_APM_REGION3_ADDR_END_REG, and + * CPU_APM_REGION3_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION3_LOCK (BIT(11)) #define CPU_APM_REGION3_LOCK_M (CPU_APM_REGION3_LOCK_V << CPU_APM_REGION3_LOCK_S) @@ -545,7 +561,7 @@ extern "C" { #define CPU_APM_REGION4_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION4_ADDR_START_L_S 0 /** CPU_APM_REGION4_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 4. + * Configures the start address of region 4. */ #define CPU_APM_REGION4_ADDR_START 0x0000007FU #define CPU_APM_REGION4_ADDR_START_M (CPU_APM_REGION4_ADDR_START_V << CPU_APM_REGION4_ADDR_START_S) @@ -571,7 +587,7 @@ extern "C" { #define CPU_APM_REGION4_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION4_ADDR_END_L_S 0 /** CPU_APM_REGION4_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 4. + * Configures the end address of region 4. */ #define CPU_APM_REGION4_ADDR_END 0x0000007FU #define CPU_APM_REGION4_ADDR_END_M (CPU_APM_REGION4_ADDR_END_V << CPU_APM_REGION4_ADDR_END_S) @@ -586,74 +602,78 @@ extern "C" { #define CPU_APM_REGION4_ADDR_END_H_S 19 /** CPU_APM_REGION4_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION4_ATTR_REG (DR_REG_CPU_APM_BASE + 0x3c) /** CPU_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 4. + * Configures the execution permission in region 4 in REE0 mode. */ #define CPU_APM_REGION4_R0_X (BIT(0)) #define CPU_APM_REGION4_R0_X_M (CPU_APM_REGION4_R0_X_V << CPU_APM_REGION4_R0_X_S) #define CPU_APM_REGION4_R0_X_V 0x00000001U #define CPU_APM_REGION4_R0_X_S 0 /** CPU_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 4. + * Configures the write permission in region 4 in REE0 mode. */ #define CPU_APM_REGION4_R0_W (BIT(1)) #define CPU_APM_REGION4_R0_W_M (CPU_APM_REGION4_R0_W_V << CPU_APM_REGION4_R0_W_S) #define CPU_APM_REGION4_R0_W_V 0x00000001U #define CPU_APM_REGION4_R0_W_S 1 /** CPU_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 4. + * Configures the read permission in region 4 in REE0 mode. */ #define CPU_APM_REGION4_R0_R (BIT(2)) #define CPU_APM_REGION4_R0_R_M (CPU_APM_REGION4_R0_R_V << CPU_APM_REGION4_R0_R_S) #define CPU_APM_REGION4_R0_R_V 0x00000001U #define CPU_APM_REGION4_R0_R_S 2 /** CPU_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 4. + * Configures the execution permission in region 4 in REE1 mode. */ #define CPU_APM_REGION4_R1_X (BIT(4)) #define CPU_APM_REGION4_R1_X_M (CPU_APM_REGION4_R1_X_V << CPU_APM_REGION4_R1_X_S) #define CPU_APM_REGION4_R1_X_V 0x00000001U #define CPU_APM_REGION4_R1_X_S 4 /** CPU_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 4. + * Configures the write permission in region 4 in REE1 mode. */ #define CPU_APM_REGION4_R1_W (BIT(5)) #define CPU_APM_REGION4_R1_W_M (CPU_APM_REGION4_R1_W_V << CPU_APM_REGION4_R1_W_S) #define CPU_APM_REGION4_R1_W_V 0x00000001U #define CPU_APM_REGION4_R1_W_S 5 /** CPU_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 4. + * Configures the read permission in region 4 in REE1 mode. */ #define CPU_APM_REGION4_R1_R (BIT(6)) #define CPU_APM_REGION4_R1_R_M (CPU_APM_REGION4_R1_R_V << CPU_APM_REGION4_R1_R_S) #define CPU_APM_REGION4_R1_R_V 0x00000001U #define CPU_APM_REGION4_R1_R_S 6 /** CPU_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 4. + * Configures the execution permission in region 4 in REE2 mode. */ #define CPU_APM_REGION4_R2_X (BIT(8)) #define CPU_APM_REGION4_R2_X_M (CPU_APM_REGION4_R2_X_V << CPU_APM_REGION4_R2_X_S) #define CPU_APM_REGION4_R2_X_V 0x00000001U #define CPU_APM_REGION4_R2_X_S 8 /** CPU_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 4. + * Configures the write permission in region 4 in REE2 mode. */ #define CPU_APM_REGION4_R2_W (BIT(9)) #define CPU_APM_REGION4_R2_W_M (CPU_APM_REGION4_R2_W_V << CPU_APM_REGION4_R2_W_S) #define CPU_APM_REGION4_R2_W_V 0x00000001U #define CPU_APM_REGION4_R2_W_S 9 /** CPU_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 4. + * Configures the read permission in region 4 in REE2 mode. */ #define CPU_APM_REGION4_R2_R (BIT(10)) #define CPU_APM_REGION4_R2_R_M (CPU_APM_REGION4_R2_R_V << CPU_APM_REGION4_R2_R_S) #define CPU_APM_REGION4_R2_R_V 0x00000001U #define CPU_APM_REGION4_R2_R_S 10 /** CPU_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 4's configuration registers + * (CPU_APM_REGION4_ADDR_START_REG, CPU_APM_REGION4_ADDR_END_REG, and + * CPU_APM_REGION4_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION4_LOCK (BIT(11)) #define CPU_APM_REGION4_LOCK_M (CPU_APM_REGION4_LOCK_V << CPU_APM_REGION4_LOCK_S) @@ -672,7 +692,7 @@ extern "C" { #define CPU_APM_REGION5_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION5_ADDR_START_L_S 0 /** CPU_APM_REGION5_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 5. + * Configures the start address of region 5. */ #define CPU_APM_REGION5_ADDR_START 0x0000007FU #define CPU_APM_REGION5_ADDR_START_M (CPU_APM_REGION5_ADDR_START_V << CPU_APM_REGION5_ADDR_START_S) @@ -698,7 +718,7 @@ extern "C" { #define CPU_APM_REGION5_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION5_ADDR_END_L_S 0 /** CPU_APM_REGION5_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 5. + * Configures the end address of region 5. */ #define CPU_APM_REGION5_ADDR_END 0x0000007FU #define CPU_APM_REGION5_ADDR_END_M (CPU_APM_REGION5_ADDR_END_V << CPU_APM_REGION5_ADDR_END_S) @@ -713,74 +733,78 @@ extern "C" { #define CPU_APM_REGION5_ADDR_END_H_S 19 /** CPU_APM_REGION5_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION5_ATTR_REG (DR_REG_CPU_APM_BASE + 0x48) /** CPU_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 5. + * Configures the execution permission in region 5 in REE0 mode. */ #define CPU_APM_REGION5_R0_X (BIT(0)) #define CPU_APM_REGION5_R0_X_M (CPU_APM_REGION5_R0_X_V << CPU_APM_REGION5_R0_X_S) #define CPU_APM_REGION5_R0_X_V 0x00000001U #define CPU_APM_REGION5_R0_X_S 0 /** CPU_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 5. + * Configures the write permission in region 5 in REE0 mode. */ #define CPU_APM_REGION5_R0_W (BIT(1)) #define CPU_APM_REGION5_R0_W_M (CPU_APM_REGION5_R0_W_V << CPU_APM_REGION5_R0_W_S) #define CPU_APM_REGION5_R0_W_V 0x00000001U #define CPU_APM_REGION5_R0_W_S 1 /** CPU_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 5. + * Configures the read permission in region 5 in REE0 mode. */ #define CPU_APM_REGION5_R0_R (BIT(2)) #define CPU_APM_REGION5_R0_R_M (CPU_APM_REGION5_R0_R_V << CPU_APM_REGION5_R0_R_S) #define CPU_APM_REGION5_R0_R_V 0x00000001U #define CPU_APM_REGION5_R0_R_S 2 /** CPU_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 5. + * Configures the execution permission in region 5 in REE1 mode. */ #define CPU_APM_REGION5_R1_X (BIT(4)) #define CPU_APM_REGION5_R1_X_M (CPU_APM_REGION5_R1_X_V << CPU_APM_REGION5_R1_X_S) #define CPU_APM_REGION5_R1_X_V 0x00000001U #define CPU_APM_REGION5_R1_X_S 4 /** CPU_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 5. + * Configures the write permission in region 5 in REE1 mode. */ #define CPU_APM_REGION5_R1_W (BIT(5)) #define CPU_APM_REGION5_R1_W_M (CPU_APM_REGION5_R1_W_V << CPU_APM_REGION5_R1_W_S) #define CPU_APM_REGION5_R1_W_V 0x00000001U #define CPU_APM_REGION5_R1_W_S 5 /** CPU_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 5. + * Configures the read permission in region 5 in REE1 mode. */ #define CPU_APM_REGION5_R1_R (BIT(6)) #define CPU_APM_REGION5_R1_R_M (CPU_APM_REGION5_R1_R_V << CPU_APM_REGION5_R1_R_S) #define CPU_APM_REGION5_R1_R_V 0x00000001U #define CPU_APM_REGION5_R1_R_S 6 /** CPU_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 5. + * Configures the execution permission in region 5 in REE2 mode. */ #define CPU_APM_REGION5_R2_X (BIT(8)) #define CPU_APM_REGION5_R2_X_M (CPU_APM_REGION5_R2_X_V << CPU_APM_REGION5_R2_X_S) #define CPU_APM_REGION5_R2_X_V 0x00000001U #define CPU_APM_REGION5_R2_X_S 8 /** CPU_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 5. + * Configures the write permission in region 5 in REE2 mode. */ #define CPU_APM_REGION5_R2_W (BIT(9)) #define CPU_APM_REGION5_R2_W_M (CPU_APM_REGION5_R2_W_V << CPU_APM_REGION5_R2_W_S) #define CPU_APM_REGION5_R2_W_V 0x00000001U #define CPU_APM_REGION5_R2_W_S 9 /** CPU_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 5. + * Configures the read permission in region 5 in REE2 mode. */ #define CPU_APM_REGION5_R2_R (BIT(10)) #define CPU_APM_REGION5_R2_R_M (CPU_APM_REGION5_R2_R_V << CPU_APM_REGION5_R2_R_S) #define CPU_APM_REGION5_R2_R_V 0x00000001U #define CPU_APM_REGION5_R2_R_S 10 /** CPU_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 5's configuration registers + * (CPU_APM_REGION5_ADDR_START_REG, CPU_APM_REGION5_ADDR_END_REG, and + * CPU_APM_REGION5_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION5_LOCK (BIT(11)) #define CPU_APM_REGION5_LOCK_M (CPU_APM_REGION5_LOCK_V << CPU_APM_REGION5_LOCK_S) @@ -799,7 +823,7 @@ extern "C" { #define CPU_APM_REGION6_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION6_ADDR_START_L_S 0 /** CPU_APM_REGION6_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 6. + * Configures the start address of region 6. */ #define CPU_APM_REGION6_ADDR_START 0x0000007FU #define CPU_APM_REGION6_ADDR_START_M (CPU_APM_REGION6_ADDR_START_V << CPU_APM_REGION6_ADDR_START_S) @@ -825,7 +849,7 @@ extern "C" { #define CPU_APM_REGION6_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION6_ADDR_END_L_S 0 /** CPU_APM_REGION6_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 6. + * Configures the end address of region 6. */ #define CPU_APM_REGION6_ADDR_END 0x0000007FU #define CPU_APM_REGION6_ADDR_END_M (CPU_APM_REGION6_ADDR_END_V << CPU_APM_REGION6_ADDR_END_S) @@ -840,74 +864,78 @@ extern "C" { #define CPU_APM_REGION6_ADDR_END_H_S 19 /** CPU_APM_REGION6_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION6_ATTR_REG (DR_REG_CPU_APM_BASE + 0x54) /** CPU_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 6. + * Configures the execution permission in region 6 in REE0 mode. */ #define CPU_APM_REGION6_R0_X (BIT(0)) #define CPU_APM_REGION6_R0_X_M (CPU_APM_REGION6_R0_X_V << CPU_APM_REGION6_R0_X_S) #define CPU_APM_REGION6_R0_X_V 0x00000001U #define CPU_APM_REGION6_R0_X_S 0 /** CPU_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 6. + * Configures the write permission in region 6 in REE0 mode. */ #define CPU_APM_REGION6_R0_W (BIT(1)) #define CPU_APM_REGION6_R0_W_M (CPU_APM_REGION6_R0_W_V << CPU_APM_REGION6_R0_W_S) #define CPU_APM_REGION6_R0_W_V 0x00000001U #define CPU_APM_REGION6_R0_W_S 1 /** CPU_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 6. + * Configures the read permission in region 6 in REE0 mode. */ #define CPU_APM_REGION6_R0_R (BIT(2)) #define CPU_APM_REGION6_R0_R_M (CPU_APM_REGION6_R0_R_V << CPU_APM_REGION6_R0_R_S) #define CPU_APM_REGION6_R0_R_V 0x00000001U #define CPU_APM_REGION6_R0_R_S 2 /** CPU_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 6. + * Configures the execution permission in region 6 in REE1 mode. */ #define CPU_APM_REGION6_R1_X (BIT(4)) #define CPU_APM_REGION6_R1_X_M (CPU_APM_REGION6_R1_X_V << CPU_APM_REGION6_R1_X_S) #define CPU_APM_REGION6_R1_X_V 0x00000001U #define CPU_APM_REGION6_R1_X_S 4 /** CPU_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 6. + * Configures the write permission in region 6 in REE1 mode. */ #define CPU_APM_REGION6_R1_W (BIT(5)) #define CPU_APM_REGION6_R1_W_M (CPU_APM_REGION6_R1_W_V << CPU_APM_REGION6_R1_W_S) #define CPU_APM_REGION6_R1_W_V 0x00000001U #define CPU_APM_REGION6_R1_W_S 5 /** CPU_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 6. + * Configures the read permission in region 6 in REE1 mode. */ #define CPU_APM_REGION6_R1_R (BIT(6)) #define CPU_APM_REGION6_R1_R_M (CPU_APM_REGION6_R1_R_V << CPU_APM_REGION6_R1_R_S) #define CPU_APM_REGION6_R1_R_V 0x00000001U #define CPU_APM_REGION6_R1_R_S 6 /** CPU_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 6. + * Configures the execution permission in region 6 in REE2 mode. */ #define CPU_APM_REGION6_R2_X (BIT(8)) #define CPU_APM_REGION6_R2_X_M (CPU_APM_REGION6_R2_X_V << CPU_APM_REGION6_R2_X_S) #define CPU_APM_REGION6_R2_X_V 0x00000001U #define CPU_APM_REGION6_R2_X_S 8 /** CPU_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 6. + * Configures the write permission in region 6 in REE2 mode. */ #define CPU_APM_REGION6_R2_W (BIT(9)) #define CPU_APM_REGION6_R2_W_M (CPU_APM_REGION6_R2_W_V << CPU_APM_REGION6_R2_W_S) #define CPU_APM_REGION6_R2_W_V 0x00000001U #define CPU_APM_REGION6_R2_W_S 9 /** CPU_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 6. + * Configures the read permission in region 6 in REE2 mode. */ #define CPU_APM_REGION6_R2_R (BIT(10)) #define CPU_APM_REGION6_R2_R_M (CPU_APM_REGION6_R2_R_V << CPU_APM_REGION6_R2_R_S) #define CPU_APM_REGION6_R2_R_V 0x00000001U #define CPU_APM_REGION6_R2_R_S 10 /** CPU_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 6's configuration registers + * (CPU_APM_REGION6_ADDR_START_REG, CPU_APM_REGION6_ADDR_END_REG, and + * CPU_APM_REGION6_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION6_LOCK (BIT(11)) #define CPU_APM_REGION6_LOCK_M (CPU_APM_REGION6_LOCK_V << CPU_APM_REGION6_LOCK_S) @@ -926,7 +954,7 @@ extern "C" { #define CPU_APM_REGION7_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION7_ADDR_START_L_S 0 /** CPU_APM_REGION7_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 7. + * Configures the start address of region 7. */ #define CPU_APM_REGION7_ADDR_START 0x0000007FU #define CPU_APM_REGION7_ADDR_START_M (CPU_APM_REGION7_ADDR_START_V << CPU_APM_REGION7_ADDR_START_S) @@ -952,7 +980,7 @@ extern "C" { #define CPU_APM_REGION7_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION7_ADDR_END_L_S 0 /** CPU_APM_REGION7_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 7. + * Configures the end address of region 7. */ #define CPU_APM_REGION7_ADDR_END 0x0000007FU #define CPU_APM_REGION7_ADDR_END_M (CPU_APM_REGION7_ADDR_END_V << CPU_APM_REGION7_ADDR_END_S) @@ -967,74 +995,78 @@ extern "C" { #define CPU_APM_REGION7_ADDR_END_H_S 19 /** CPU_APM_REGION7_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION7_ATTR_REG (DR_REG_CPU_APM_BASE + 0x60) /** CPU_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 7. + * Configures the execution permission in region 7 in REE0 mode. */ #define CPU_APM_REGION7_R0_X (BIT(0)) #define CPU_APM_REGION7_R0_X_M (CPU_APM_REGION7_R0_X_V << CPU_APM_REGION7_R0_X_S) #define CPU_APM_REGION7_R0_X_V 0x00000001U #define CPU_APM_REGION7_R0_X_S 0 /** CPU_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 7. + * Configures the write permission in region 7 in REE0 mode. */ #define CPU_APM_REGION7_R0_W (BIT(1)) #define CPU_APM_REGION7_R0_W_M (CPU_APM_REGION7_R0_W_V << CPU_APM_REGION7_R0_W_S) #define CPU_APM_REGION7_R0_W_V 0x00000001U #define CPU_APM_REGION7_R0_W_S 1 /** CPU_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 7. + * Configures the read permission in region 7 in REE0 mode. */ #define CPU_APM_REGION7_R0_R (BIT(2)) #define CPU_APM_REGION7_R0_R_M (CPU_APM_REGION7_R0_R_V << CPU_APM_REGION7_R0_R_S) #define CPU_APM_REGION7_R0_R_V 0x00000001U #define CPU_APM_REGION7_R0_R_S 2 /** CPU_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 7. + * Configures the execution permission in region 7 in REE1 mode. */ #define CPU_APM_REGION7_R1_X (BIT(4)) #define CPU_APM_REGION7_R1_X_M (CPU_APM_REGION7_R1_X_V << CPU_APM_REGION7_R1_X_S) #define CPU_APM_REGION7_R1_X_V 0x00000001U #define CPU_APM_REGION7_R1_X_S 4 /** CPU_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 7. + * Configures the write permission in region 7 in REE1 mode. */ #define CPU_APM_REGION7_R1_W (BIT(5)) #define CPU_APM_REGION7_R1_W_M (CPU_APM_REGION7_R1_W_V << CPU_APM_REGION7_R1_W_S) #define CPU_APM_REGION7_R1_W_V 0x00000001U #define CPU_APM_REGION7_R1_W_S 5 /** CPU_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 7. + * Configures the read permission in region 7 in REE1 mode. */ #define CPU_APM_REGION7_R1_R (BIT(6)) #define CPU_APM_REGION7_R1_R_M (CPU_APM_REGION7_R1_R_V << CPU_APM_REGION7_R1_R_S) #define CPU_APM_REGION7_R1_R_V 0x00000001U #define CPU_APM_REGION7_R1_R_S 6 /** CPU_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 7. + * Configures the execution permission in region 7 in REE2 mode. */ #define CPU_APM_REGION7_R2_X (BIT(8)) #define CPU_APM_REGION7_R2_X_M (CPU_APM_REGION7_R2_X_V << CPU_APM_REGION7_R2_X_S) #define CPU_APM_REGION7_R2_X_V 0x00000001U #define CPU_APM_REGION7_R2_X_S 8 /** CPU_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 7. + * Configures the write permission in region 7 in REE2 mode. */ #define CPU_APM_REGION7_R2_W (BIT(9)) #define CPU_APM_REGION7_R2_W_M (CPU_APM_REGION7_R2_W_V << CPU_APM_REGION7_R2_W_S) #define CPU_APM_REGION7_R2_W_V 0x00000001U #define CPU_APM_REGION7_R2_W_S 9 /** CPU_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 7. + * Configures the read permission in region 7 in REE2 mode. */ #define CPU_APM_REGION7_R2_R (BIT(10)) #define CPU_APM_REGION7_R2_R_M (CPU_APM_REGION7_R2_R_V << CPU_APM_REGION7_R2_R_S) #define CPU_APM_REGION7_R2_R_V 0x00000001U #define CPU_APM_REGION7_R2_R_S 10 /** CPU_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 7's configuration registers + * (CPU_APM_REGION7_ADDR_START_REG, CPU_APM_REGION7_ADDR_END_REG, and + * CPU_APM_REGION7_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION7_LOCK (BIT(11)) #define CPU_APM_REGION7_LOCK_M (CPU_APM_REGION7_LOCK_V << CPU_APM_REGION7_LOCK_S) @@ -1042,18 +1074,22 @@ extern "C" { #define CPU_APM_REGION7_LOCK_S 11 /** CPU_APM_FUNC_CTRL_REG register - * APM function control register + * APM access path permission management register */ #define CPU_APM_FUNC_CTRL_REG (DR_REG_CPU_APM_BASE + 0xc4) /** CPU_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures whether to enable permission management for CPU_APM_CTRL M0. + * 0: Disable + * 1: Enable */ #define CPU_APM_M0_FUNC_EN (BIT(0)) #define CPU_APM_M0_FUNC_EN_M (CPU_APM_M0_FUNC_EN_V << CPU_APM_M0_FUNC_EN_S) #define CPU_APM_M0_FUNC_EN_V 0x00000001U #define CPU_APM_M0_FUNC_EN_S 0 /** CPU_APM_M1_FUNC_EN : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable + * Configures whether to enable permission management for CPU_APM_CTRL M1. + * 0: Disable + * 1: Enable */ #define CPU_APM_M1_FUNC_EN (BIT(1)) #define CPU_APM_M1_FUNC_EN_M (CPU_APM_M1_FUNC_EN_V << CPU_APM_M1_FUNC_EN_S) @@ -1061,13 +1097,13 @@ extern "C" { #define CPU_APM_M1_FUNC_EN_S 1 /** CPU_APM_M0_STATUS_REG register - * M0 status register + * CPU_APM_CTRL M0 status register */ #define CPU_APM_M0_STATUS_REG (DR_REG_CPU_APM_BASE + 0xc8) /** CPU_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define CPU_APM_M0_EXCEPTION_STATUS 0x00000003U #define CPU_APM_M0_EXCEPTION_STATUS_M (CPU_APM_M0_EXCEPTION_STATUS_V << CPU_APM_M0_EXCEPTION_STATUS_S) @@ -1075,11 +1111,11 @@ extern "C" { #define CPU_APM_M0_EXCEPTION_STATUS_S 0 /** CPU_APM_M0_STATUS_CLR_REG register - * M0 status clear register + * CPU_APM_CTRL M0 status clear register */ #define CPU_APM_M0_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xcc) /** CPU_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; - * Configures to clear exception status. + * Write 1 to clear exception status. */ #define CPU_APM_M0_EXCEPTION_STATUS_CLR (BIT(0)) #define CPU_APM_M0_EXCEPTION_STATUS_CLR_M (CPU_APM_M0_EXCEPTION_STATUS_CLR_V << CPU_APM_M0_EXCEPTION_STATUS_CLR_S) @@ -1087,25 +1123,25 @@ extern "C" { #define CPU_APM_M0_EXCEPTION_STATUS_CLR_S 0 /** CPU_APM_M0_EXCEPTION_INFO0_REG register - * M0 exception_info0 register + * CPU_APM_CTRL M0 exception information register */ #define CPU_APM_M0_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xd0) /** CPU_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define CPU_APM_M0_EXCEPTION_REGION 0x0000FFFFU #define CPU_APM_M0_EXCEPTION_REGION_M (CPU_APM_M0_EXCEPTION_REGION_V << CPU_APM_M0_EXCEPTION_REGION_S) #define CPU_APM_M0_EXCEPTION_REGION_V 0x0000FFFFU #define CPU_APM_M0_EXCEPTION_REGION_S 0 /** CPU_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define CPU_APM_M0_EXCEPTION_MODE 0x00000003U #define CPU_APM_M0_EXCEPTION_MODE_M (CPU_APM_M0_EXCEPTION_MODE_V << CPU_APM_M0_EXCEPTION_MODE_S) #define CPU_APM_M0_EXCEPTION_MODE_V 0x00000003U #define CPU_APM_M0_EXCEPTION_MODE_S 16 /** CPU_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define CPU_APM_M0_EXCEPTION_ID 0x0000001FU #define CPU_APM_M0_EXCEPTION_ID_M (CPU_APM_M0_EXCEPTION_ID_V << CPU_APM_M0_EXCEPTION_ID_S) @@ -1113,11 +1149,11 @@ extern "C" { #define CPU_APM_M0_EXCEPTION_ID_S 18 /** CPU_APM_M0_EXCEPTION_INFO1_REG register - * M0 exception_info1 register + * CPU_APM_CTRL M0 exception information register */ #define CPU_APM_M0_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xd4) /** CPU_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define CPU_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU #define CPU_APM_M0_EXCEPTION_ADDR_M (CPU_APM_M0_EXCEPTION_ADDR_V << CPU_APM_M0_EXCEPTION_ADDR_S) @@ -1125,13 +1161,13 @@ extern "C" { #define CPU_APM_M0_EXCEPTION_ADDR_S 0 /** CPU_APM_M1_STATUS_REG register - * M1 status register + * CPU_APM_CTRL M1 status register */ #define CPU_APM_M1_STATUS_REG (DR_REG_CPU_APM_BASE + 0xd8) /** CPU_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define CPU_APM_M1_EXCEPTION_STATUS 0x00000003U #define CPU_APM_M1_EXCEPTION_STATUS_M (CPU_APM_M1_EXCEPTION_STATUS_V << CPU_APM_M1_EXCEPTION_STATUS_S) @@ -1139,11 +1175,11 @@ extern "C" { #define CPU_APM_M1_EXCEPTION_STATUS_S 0 /** CPU_APM_M1_STATUS_CLR_REG register - * M1 status clear register + * CPU_APM_CTRL M1 status clear register */ #define CPU_APM_M1_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xdc) /** CPU_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; - * Configures to clear exception status. + * Write 1 to clear exception status. */ #define CPU_APM_M1_EXCEPTION_STATUS_CLR (BIT(0)) #define CPU_APM_M1_EXCEPTION_STATUS_CLR_M (CPU_APM_M1_EXCEPTION_STATUS_CLR_V << CPU_APM_M1_EXCEPTION_STATUS_CLR_S) @@ -1151,25 +1187,25 @@ extern "C" { #define CPU_APM_M1_EXCEPTION_STATUS_CLR_S 0 /** CPU_APM_M1_EXCEPTION_INFO0_REG register - * M1 exception_info0 register + * CPU_APM_CTRL M1 exception information register */ #define CPU_APM_M1_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xe0) /** CPU_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define CPU_APM_M1_EXCEPTION_REGION 0x0000FFFFU #define CPU_APM_M1_EXCEPTION_REGION_M (CPU_APM_M1_EXCEPTION_REGION_V << CPU_APM_M1_EXCEPTION_REGION_S) #define CPU_APM_M1_EXCEPTION_REGION_V 0x0000FFFFU #define CPU_APM_M1_EXCEPTION_REGION_S 0 /** CPU_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define CPU_APM_M1_EXCEPTION_MODE 0x00000003U #define CPU_APM_M1_EXCEPTION_MODE_M (CPU_APM_M1_EXCEPTION_MODE_V << CPU_APM_M1_EXCEPTION_MODE_S) #define CPU_APM_M1_EXCEPTION_MODE_V 0x00000003U #define CPU_APM_M1_EXCEPTION_MODE_S 16 /** CPU_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define CPU_APM_M1_EXCEPTION_ID 0x0000001FU #define CPU_APM_M1_EXCEPTION_ID_M (CPU_APM_M1_EXCEPTION_ID_V << CPU_APM_M1_EXCEPTION_ID_S) @@ -1177,11 +1213,11 @@ extern "C" { #define CPU_APM_M1_EXCEPTION_ID_S 18 /** CPU_APM_M1_EXCEPTION_INFO1_REG register - * M1 exception_info1 register + * CPU_APM_CTRL M1 exception information register */ #define CPU_APM_M1_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xe4) /** CPU_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define CPU_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU #define CPU_APM_M1_EXCEPTION_ADDR_M (CPU_APM_M1_EXCEPTION_ADDR_V << CPU_APM_M1_EXCEPTION_ADDR_S) @@ -1189,22 +1225,22 @@ extern "C" { #define CPU_APM_M1_EXCEPTION_ADDR_S 0 /** CPU_APM_INT_EN_REG register - * APM interrupt enable register + * CPU_APM_CTRL M0/1 interrupt enable register */ #define CPU_APM_INT_EN_REG (DR_REG_CPU_APM_BASE + 0x118) /** CPU_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; - * Configures to enable APM M0 interrupt. - * 0: disable - * 1: enable + * Configures whether to enable CPU_APM_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ #define CPU_APM_M0_APM_INT_EN (BIT(0)) #define CPU_APM_M0_APM_INT_EN_M (CPU_APM_M0_APM_INT_EN_V << CPU_APM_M0_APM_INT_EN_S) #define CPU_APM_M0_APM_INT_EN_V 0x00000001U #define CPU_APM_M0_APM_INT_EN_S 0 /** CPU_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; - * Configures to enable APM M1 interrupt. - * 0: disable - * 1: enable + * Configures whether to enable CPU_APM_CTRL M1 interrupt. + * 0: Disable + * 1: Enable */ #define CPU_APM_M1_APM_INT_EN (BIT(1)) #define CPU_APM_M1_APM_INT_EN_M (CPU_APM_M1_APM_INT_EN_V << CPU_APM_M1_APM_INT_EN_S) @@ -1217,8 +1253,8 @@ extern "C" { #define CPU_APM_CLOCK_GATE_REG (DR_REG_CPU_APM_BASE + 0x7f8) /** CPU_APM_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ #define CPU_APM_CLK_EN (BIT(0)) #define CPU_APM_CLK_EN_M (CPU_APM_CLK_EN_V << CPU_APM_CLK_EN_S) diff --git a/components/soc/esp32c5/register/soc/cpu_apm_struct.h b/components/soc/esp32c5/register/soc/cpu_apm_struct.h index c8198eeecb..49d283b39c 100644 --- a/components/soc/esp32c5/register/soc/cpu_apm_struct.h +++ b/components/soc/esp32c5/register/soc/cpu_apm_struct.h @@ -10,16 +10,16 @@ extern "C" { #endif -/** Group: Region filter enable register */ +/** Group: Configuration Registers */ /** Type of region_filter_en register - * Region filter enable register + * Region enable register */ typedef union { struct { /** region_filter_en : R/W; bitpos: [7:0]; default: 1; - * Configure bit $n (0-7) to enable region $n. - * 0: disable - * 1: enable + * Configures bit $n (0-7) to enable region $n (0-7). + * 0: Disable + * 1: Enable */ uint32_t region_filter_en:8; uint32_t reserved_8:24; @@ -28,7 +28,7 @@ typedef union { } cpu_apm_region_filter_en_reg_t; -/** Group: Region address register */ +/** Group: Region Address Registers */ /** Type of regionn_addr_start register * Region address register */ @@ -39,7 +39,7 @@ typedef union { */ uint32_t regionn_addr_start_l:12; /** regionn_addr_start : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region n. + * Configures the start address of region n. */ uint32_t regionn_addr_start:7; /** regionn_addr_start_h : HRO; bitpos: [31:19]; default: 2064; @@ -60,7 +60,7 @@ typedef union { */ uint32_t regionn_addr_end_l:12; /** regionn_addr_end : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region n. + * Configures the end address of region n. */ uint32_t regionn_addr_end:7; /** regionn_addr_end_h : HRO; bitpos: [31:19]; default: 2064; @@ -71,53 +71,55 @@ typedef union { uint32_t val; } cpu_apm_regionn_addr_end_reg_t; - -/** Group: Region access authority attribute register */ /** Type of regionn_attr register - * Region access authority attribute register + * Region access permissions configuration register */ typedef union { struct { /** regionn_r0_x : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region n. + * Configures the execution permission in region n in REE0 mode. */ uint32_t regionn_r0_x:1; /** regionn_r0_w : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region n. + * Configures the write permission in region n in REE0 mode. */ uint32_t regionn_r0_w:1; /** regionn_r0_r : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region n. + * Configures the read permission in region n in REE0 mode. */ uint32_t regionn_r0_r:1; uint32_t reserved_3:1; /** regionn_r1_x : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region n. + * Configures the execution permission in region n in REE1 mode. */ uint32_t regionn_r1_x:1; /** regionn_r1_w : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region n. + * Configures the write permission in region n in REE1 mode. */ uint32_t regionn_r1_w:1; /** regionn_r1_r : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region n. + * Configures the read permission in region n in REE1 mode. */ uint32_t regionn_r1_r:1; uint32_t reserved_7:1; /** regionn_r2_x : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region n. + * Configures the execution permission in region n in REE2 mode. */ uint32_t regionn_r2_x:1; /** regionn_r2_w : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region n. + * Configures the write permission in region n in REE2 mode. */ uint32_t regionn_r2_w:1; /** regionn_r2_r : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region n. + * Configures the read permission in region n in REE2 mode. */ uint32_t regionn_r2_r:1; /** regionn_lock : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region n's configuration registers + * (CPU_APM_REGIONn_ADDR_START_REG, CPU_APM_REGIONn_ADDR_END_REG, and + * CPU_APM_REGIONn_ATTR_REG). + * 0: Do not lock + * 1: Lock */ uint32_t regionn_lock:1; uint32_t reserved_12:20; @@ -125,19 +127,21 @@ typedef union { uint32_t val; } cpu_apm_regionn_attr_reg_t; - -/** Group: function control register */ /** Type of func_ctrl register - * APM function control register + * APM access path permission management register */ typedef union { struct { /** m0_func_en : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures whether to enable permission management for CPU_APM_CTRL M0. + * 0: Disable + * 1: Enable */ uint32_t m0_func_en:1; /** m1_func_en : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable + * Configures whether to enable permission management for CPU_APM_CTRL M1. + * 0: Disable + * 1: Enable */ uint32_t m1_func_en:1; uint32_t reserved_2:30; @@ -146,16 +150,16 @@ typedef union { } cpu_apm_func_ctrl_reg_t; -/** Group: M0 status register */ +/** Group: Status Registers */ /** Type of m0_status register - * M0 status register + * CPU_APM_CTRL M0 status register */ typedef union { struct { /** m0_exception_status : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m0_exception_status:2; uint32_t reserved_2:30; @@ -163,15 +167,13 @@ typedef union { uint32_t val; } cpu_apm_m0_status_reg_t; - -/** Group: M0 status clear register */ /** Type of m0_status_clr register - * M0 status clear register + * CPU_APM_CTRL M0 status clear register */ typedef union { struct { /** m0_exception_status_clr : WT; bitpos: [0]; default: 0; - * Configures to clear exception status. + * Write 1 to clear exception status. */ uint32_t m0_exception_status_clr:1; uint32_t reserved_1:31; @@ -179,23 +181,21 @@ typedef union { uint32_t val; } cpu_apm_m0_status_clr_reg_t; - -/** Group: M0 exception_info0 register */ /** Type of m0_exception_info0 register - * M0 exception_info0 register + * CPU_APM_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m0_exception_region:16; /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m0_exception_mode:2; /** m0_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m0_exception_id:5; uint32_t reserved_23:9; @@ -203,32 +203,28 @@ typedef union { uint32_t val; } cpu_apm_m0_exception_info0_reg_t; - -/** Group: M0 exception_info1 register */ /** Type of m0_exception_info1 register - * M0 exception_info1 register + * CPU_APM_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m0_exception_addr:32; }; uint32_t val; } cpu_apm_m0_exception_info1_reg_t; - -/** Group: M1 status register */ /** Type of m1_status register - * M1 status register + * CPU_APM_CTRL M1 status register */ typedef union { struct { /** m1_exception_status : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m1_exception_status:2; uint32_t reserved_2:30; @@ -236,15 +232,13 @@ typedef union { uint32_t val; } cpu_apm_m1_status_reg_t; - -/** Group: M1 status clear register */ /** Type of m1_status_clr register - * M1 status clear register + * CPU_APM_CTRL M1 status clear register */ typedef union { struct { /** m1_exception_status_clr : WT; bitpos: [0]; default: 0; - * Configures to clear exception status. + * Write 1 to clear exception status. */ uint32_t m1_exception_status_clr:1; uint32_t reserved_1:31; @@ -252,23 +246,21 @@ typedef union { uint32_t val; } cpu_apm_m1_status_clr_reg_t; - -/** Group: M1 exception_info0 register */ /** Type of m1_exception_info0 register - * M1 exception_info0 register + * CPU_APM_CTRL M1 exception information register */ typedef union { struct { /** m1_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m1_exception_region:16; /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m1_exception_mode:2; /** m1_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m1_exception_id:5; uint32_t reserved_23:9; @@ -276,15 +268,13 @@ typedef union { uint32_t val; } cpu_apm_m1_exception_info0_reg_t; - -/** Group: M1 exception_info1 register */ /** Type of m1_exception_info1 register - * M1 exception_info1 register + * CPU_APM_CTRL M1 exception information register */ typedef union { struct { /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m1_exception_addr:32; }; @@ -292,22 +282,22 @@ typedef union { } cpu_apm_m1_exception_info1_reg_t; -/** Group: APM interrupt enable register */ +/** Group: Interrupt Registers */ /** Type of int_en register - * APM interrupt enable register + * CPU_APM_CTRL M0/1 interrupt enable register */ typedef union { struct { /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; - * Configures to enable APM M0 interrupt. - * 0: disable - * 1: enable + * Configures whether to enable CPU_APM_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m0_apm_int_en:1; /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; - * Configures to enable APM M1 interrupt. - * 0: disable - * 1: enable + * Configures whether to enable CPU_APM_CTRL M1 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m1_apm_int_en:1; uint32_t reserved_2:30; @@ -316,7 +306,7 @@ typedef union { } cpu_apm_int_en_reg_t; -/** Group: Clock gating register */ +/** Group: Clock Gating Registers */ /** Type of clock_gate register * Clock gating register */ @@ -324,8 +314,8 @@ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -334,7 +324,7 @@ typedef union { } cpu_apm_clock_gate_reg_t; -/** Group: Version control register */ +/** Group: Version Control Registers */ /** Type of date register * Version control register */ diff --git a/components/soc/esp32c5/register/soc/hp_apm_reg.h b/components/soc/esp32c5/register/soc/hp_apm_reg.h index ae587c5944..4179bf0815 100644 --- a/components/soc/esp32c5/register/soc/hp_apm_reg.h +++ b/components/soc/esp32c5/register/soc/hp_apm_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,13 +12,13 @@ extern "C" { #endif /** HP_APM_REGION_FILTER_EN_REG register - * Region filter enable register + * Region enable register */ #define HP_APM_REGION_FILTER_EN_REG (DR_REG_HP_APM_BASE + 0x0) /** HP_APM_REGION_FILTER_EN : R/W; bitpos: [15:0]; default: 1; - * Configure bit $n (0-15) to enable region $n.\\ - * 0: disable \\ - * 1: enable \\ + * Configure bit $n (0-15) to enable region $n (0-15). + * 0: Disable + * 1: Enable */ #define HP_APM_REGION_FILTER_EN 0x0000FFFFU #define HP_APM_REGION_FILTER_EN_M (HP_APM_REGION_FILTER_EN_V << HP_APM_REGION_FILTER_EN_S) @@ -30,7 +30,7 @@ extern "C" { */ #define HP_APM_REGION0_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4) /** HP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 0. + * Configures the start address of region 0. */ #define HP_APM_REGION0_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION0_ADDR_START_M (HP_APM_REGION0_ADDR_START_V << HP_APM_REGION0_ADDR_START_S) @@ -42,7 +42,7 @@ extern "C" { */ #define HP_APM_REGION0_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8) /** HP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 0. + * Configures the end address of region 0. */ #define HP_APM_REGION0_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION0_ADDR_END_M (HP_APM_REGION0_ADDR_END_V << HP_APM_REGION0_ADDR_END_S) @@ -50,74 +50,78 @@ extern "C" { #define HP_APM_REGION0_ADDR_END_S 0 /** HP_APM_REGION0_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION0_ATTR_REG (DR_REG_HP_APM_BASE + 0xc) /** HP_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 0. + * Configures the execution permission in region 0 in REE0 mode. */ #define HP_APM_REGION0_R0_X (BIT(0)) #define HP_APM_REGION0_R0_X_M (HP_APM_REGION0_R0_X_V << HP_APM_REGION0_R0_X_S) #define HP_APM_REGION0_R0_X_V 0x00000001U #define HP_APM_REGION0_R0_X_S 0 /** HP_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 0. + * Configures the write permission in region 0 in REE0 mode. */ #define HP_APM_REGION0_R0_W (BIT(1)) #define HP_APM_REGION0_R0_W_M (HP_APM_REGION0_R0_W_V << HP_APM_REGION0_R0_W_S) #define HP_APM_REGION0_R0_W_V 0x00000001U #define HP_APM_REGION0_R0_W_S 1 /** HP_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 0. + * Configures the read permission in region 0 in REE0 mode. */ #define HP_APM_REGION0_R0_R (BIT(2)) #define HP_APM_REGION0_R0_R_M (HP_APM_REGION0_R0_R_V << HP_APM_REGION0_R0_R_S) #define HP_APM_REGION0_R0_R_V 0x00000001U #define HP_APM_REGION0_R0_R_S 2 /** HP_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 0. + * Configures the execution permission in region 0 in REE1 mode. */ #define HP_APM_REGION0_R1_X (BIT(4)) #define HP_APM_REGION0_R1_X_M (HP_APM_REGION0_R1_X_V << HP_APM_REGION0_R1_X_S) #define HP_APM_REGION0_R1_X_V 0x00000001U #define HP_APM_REGION0_R1_X_S 4 /** HP_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 0. + * Configures the write permission in region 0 in REE1 mode. */ #define HP_APM_REGION0_R1_W (BIT(5)) #define HP_APM_REGION0_R1_W_M (HP_APM_REGION0_R1_W_V << HP_APM_REGION0_R1_W_S) #define HP_APM_REGION0_R1_W_V 0x00000001U #define HP_APM_REGION0_R1_W_S 5 /** HP_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 0. + * Configures the read permission in region 0 in REE1 mode. */ #define HP_APM_REGION0_R1_R (BIT(6)) #define HP_APM_REGION0_R1_R_M (HP_APM_REGION0_R1_R_V << HP_APM_REGION0_R1_R_S) #define HP_APM_REGION0_R1_R_V 0x00000001U #define HP_APM_REGION0_R1_R_S 6 /** HP_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 0. + * Configures the execution permission in region 0 in REE2 mode. */ #define HP_APM_REGION0_R2_X (BIT(8)) #define HP_APM_REGION0_R2_X_M (HP_APM_REGION0_R2_X_V << HP_APM_REGION0_R2_X_S) #define HP_APM_REGION0_R2_X_V 0x00000001U #define HP_APM_REGION0_R2_X_S 8 /** HP_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 0. + * Configures the write permission in region 0 in REE2 mode. */ #define HP_APM_REGION0_R2_W (BIT(9)) #define HP_APM_REGION0_R2_W_M (HP_APM_REGION0_R2_W_V << HP_APM_REGION0_R2_W_S) #define HP_APM_REGION0_R2_W_V 0x00000001U #define HP_APM_REGION0_R2_W_S 9 /** HP_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 0. + * Configures the read permission in region 0 in REE2 mode. */ #define HP_APM_REGION0_R2_R (BIT(10)) #define HP_APM_REGION0_R2_R_M (HP_APM_REGION0_R2_R_V << HP_APM_REGION0_R2_R_S) #define HP_APM_REGION0_R2_R_V 0x00000001U #define HP_APM_REGION0_R2_R_S 10 /** HP_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 0 configuration registers + * (HP_APM_REGION0_ADDR_START_REG, HP_APM_REGION0_ADDR_END_REG and + * HP_APM_REGION0_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION0_LOCK (BIT(11)) #define HP_APM_REGION0_LOCK_M (HP_APM_REGION0_LOCK_V << HP_APM_REGION0_LOCK_S) @@ -129,7 +133,7 @@ extern "C" { */ #define HP_APM_REGION1_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x10) /** HP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 1. + * Configures the start address of region 1. */ #define HP_APM_REGION1_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION1_ADDR_START_M (HP_APM_REGION1_ADDR_START_V << HP_APM_REGION1_ADDR_START_S) @@ -141,7 +145,7 @@ extern "C" { */ #define HP_APM_REGION1_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x14) /** HP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 1. + * Configures the end address of region 1. */ #define HP_APM_REGION1_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION1_ADDR_END_M (HP_APM_REGION1_ADDR_END_V << HP_APM_REGION1_ADDR_END_S) @@ -149,74 +153,78 @@ extern "C" { #define HP_APM_REGION1_ADDR_END_S 0 /** HP_APM_REGION1_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION1_ATTR_REG (DR_REG_HP_APM_BASE + 0x18) /** HP_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 1. + * Configures the execution permission in region 1 in REE0 mode. */ #define HP_APM_REGION1_R0_X (BIT(0)) #define HP_APM_REGION1_R0_X_M (HP_APM_REGION1_R0_X_V << HP_APM_REGION1_R0_X_S) #define HP_APM_REGION1_R0_X_V 0x00000001U #define HP_APM_REGION1_R0_X_S 0 /** HP_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 1. + * Configures the write permission in region 1 in REE0 mode. */ #define HP_APM_REGION1_R0_W (BIT(1)) #define HP_APM_REGION1_R0_W_M (HP_APM_REGION1_R0_W_V << HP_APM_REGION1_R0_W_S) #define HP_APM_REGION1_R0_W_V 0x00000001U #define HP_APM_REGION1_R0_W_S 1 /** HP_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 1. + * Configures the read permission in region 1 in REE0 mode. */ #define HP_APM_REGION1_R0_R (BIT(2)) #define HP_APM_REGION1_R0_R_M (HP_APM_REGION1_R0_R_V << HP_APM_REGION1_R0_R_S) #define HP_APM_REGION1_R0_R_V 0x00000001U #define HP_APM_REGION1_R0_R_S 2 /** HP_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 1. + * Configures the execution permission in region 1 in REE1 mode. */ #define HP_APM_REGION1_R1_X (BIT(4)) #define HP_APM_REGION1_R1_X_M (HP_APM_REGION1_R1_X_V << HP_APM_REGION1_R1_X_S) #define HP_APM_REGION1_R1_X_V 0x00000001U #define HP_APM_REGION1_R1_X_S 4 /** HP_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 1. + * Configures the write permission in region 1 in REE1 mode. */ #define HP_APM_REGION1_R1_W (BIT(5)) #define HP_APM_REGION1_R1_W_M (HP_APM_REGION1_R1_W_V << HP_APM_REGION1_R1_W_S) #define HP_APM_REGION1_R1_W_V 0x00000001U #define HP_APM_REGION1_R1_W_S 5 /** HP_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 1. + * Configures the read permission in region 1 in REE1 mode. */ #define HP_APM_REGION1_R1_R (BIT(6)) #define HP_APM_REGION1_R1_R_M (HP_APM_REGION1_R1_R_V << HP_APM_REGION1_R1_R_S) #define HP_APM_REGION1_R1_R_V 0x00000001U #define HP_APM_REGION1_R1_R_S 6 /** HP_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 1. + * Configures the execution permission in region 1 in REE2 mode. */ #define HP_APM_REGION1_R2_X (BIT(8)) #define HP_APM_REGION1_R2_X_M (HP_APM_REGION1_R2_X_V << HP_APM_REGION1_R2_X_S) #define HP_APM_REGION1_R2_X_V 0x00000001U #define HP_APM_REGION1_R2_X_S 8 /** HP_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 1. + * Configures the write permission in region 1 in REE2 mode. */ #define HP_APM_REGION1_R2_W (BIT(9)) #define HP_APM_REGION1_R2_W_M (HP_APM_REGION1_R2_W_V << HP_APM_REGION1_R2_W_S) #define HP_APM_REGION1_R2_W_V 0x00000001U #define HP_APM_REGION1_R2_W_S 9 /** HP_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 1. + * Configures the read permission in region 1 in REE2 mode. */ #define HP_APM_REGION1_R2_R (BIT(10)) #define HP_APM_REGION1_R2_R_M (HP_APM_REGION1_R2_R_V << HP_APM_REGION1_R2_R_S) #define HP_APM_REGION1_R2_R_V 0x00000001U #define HP_APM_REGION1_R2_R_S 10 /** HP_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 1 configuration registers + * (HP_APM_REGION1_ADDR_START_REG, HP_APM_REGION1_ADDR_END_REG and + * HP_APM_REGION1_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION1_LOCK (BIT(11)) #define HP_APM_REGION1_LOCK_M (HP_APM_REGION1_LOCK_V << HP_APM_REGION1_LOCK_S) @@ -228,7 +236,7 @@ extern "C" { */ #define HP_APM_REGION2_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x1c) /** HP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 2. + * Configures the start address of region 2. */ #define HP_APM_REGION2_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION2_ADDR_START_M (HP_APM_REGION2_ADDR_START_V << HP_APM_REGION2_ADDR_START_S) @@ -240,7 +248,7 @@ extern "C" { */ #define HP_APM_REGION2_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x20) /** HP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 2. + * Configures the end address of region 2. */ #define HP_APM_REGION2_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION2_ADDR_END_M (HP_APM_REGION2_ADDR_END_V << HP_APM_REGION2_ADDR_END_S) @@ -248,74 +256,78 @@ extern "C" { #define HP_APM_REGION2_ADDR_END_S 0 /** HP_APM_REGION2_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION2_ATTR_REG (DR_REG_HP_APM_BASE + 0x24) /** HP_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 2. + * Configures the execution permission in region 2 in REE0 mode. */ #define HP_APM_REGION2_R0_X (BIT(0)) #define HP_APM_REGION2_R0_X_M (HP_APM_REGION2_R0_X_V << HP_APM_REGION2_R0_X_S) #define HP_APM_REGION2_R0_X_V 0x00000001U #define HP_APM_REGION2_R0_X_S 0 /** HP_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 2. + * Configures the write permission in region 2 in REE0 mode. */ #define HP_APM_REGION2_R0_W (BIT(1)) #define HP_APM_REGION2_R0_W_M (HP_APM_REGION2_R0_W_V << HP_APM_REGION2_R0_W_S) #define HP_APM_REGION2_R0_W_V 0x00000001U #define HP_APM_REGION2_R0_W_S 1 /** HP_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 2. + * Configures the read permission in region 2 in REE0 mode. */ #define HP_APM_REGION2_R0_R (BIT(2)) #define HP_APM_REGION2_R0_R_M (HP_APM_REGION2_R0_R_V << HP_APM_REGION2_R0_R_S) #define HP_APM_REGION2_R0_R_V 0x00000001U #define HP_APM_REGION2_R0_R_S 2 /** HP_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 2. + * Configures the execution permission in region 2 in REE1 mode. */ #define HP_APM_REGION2_R1_X (BIT(4)) #define HP_APM_REGION2_R1_X_M (HP_APM_REGION2_R1_X_V << HP_APM_REGION2_R1_X_S) #define HP_APM_REGION2_R1_X_V 0x00000001U #define HP_APM_REGION2_R1_X_S 4 /** HP_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 2. + * Configures the write permission in region 2 in REE1 mode. */ #define HP_APM_REGION2_R1_W (BIT(5)) #define HP_APM_REGION2_R1_W_M (HP_APM_REGION2_R1_W_V << HP_APM_REGION2_R1_W_S) #define HP_APM_REGION2_R1_W_V 0x00000001U #define HP_APM_REGION2_R1_W_S 5 /** HP_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 2. + * Configures the read permission in region 2 in REE1 mode. */ #define HP_APM_REGION2_R1_R (BIT(6)) #define HP_APM_REGION2_R1_R_M (HP_APM_REGION2_R1_R_V << HP_APM_REGION2_R1_R_S) #define HP_APM_REGION2_R1_R_V 0x00000001U #define HP_APM_REGION2_R1_R_S 6 /** HP_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 2. + * Configures the execution permission in region 2 in REE2 mode. */ #define HP_APM_REGION2_R2_X (BIT(8)) #define HP_APM_REGION2_R2_X_M (HP_APM_REGION2_R2_X_V << HP_APM_REGION2_R2_X_S) #define HP_APM_REGION2_R2_X_V 0x00000001U #define HP_APM_REGION2_R2_X_S 8 /** HP_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 2. + * Configures the write permission in region 2 in REE2 mode. */ #define HP_APM_REGION2_R2_W (BIT(9)) #define HP_APM_REGION2_R2_W_M (HP_APM_REGION2_R2_W_V << HP_APM_REGION2_R2_W_S) #define HP_APM_REGION2_R2_W_V 0x00000001U #define HP_APM_REGION2_R2_W_S 9 /** HP_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 2. + * Configures the read permission in region 2 in REE2 mode. */ #define HP_APM_REGION2_R2_R (BIT(10)) #define HP_APM_REGION2_R2_R_M (HP_APM_REGION2_R2_R_V << HP_APM_REGION2_R2_R_S) #define HP_APM_REGION2_R2_R_V 0x00000001U #define HP_APM_REGION2_R2_R_S 10 /** HP_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 2 configuration registers + * (HP_APM_REGION2_ADDR_START_REG, HP_APM_REGION2_ADDR_END_REG and + * HP_APM_REGION2_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION2_LOCK (BIT(11)) #define HP_APM_REGION2_LOCK_M (HP_APM_REGION2_LOCK_V << HP_APM_REGION2_LOCK_S) @@ -327,7 +339,7 @@ extern "C" { */ #define HP_APM_REGION3_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x28) /** HP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 3. + * Configures the start address of region 3. */ #define HP_APM_REGION3_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION3_ADDR_START_M (HP_APM_REGION3_ADDR_START_V << HP_APM_REGION3_ADDR_START_S) @@ -339,7 +351,7 @@ extern "C" { */ #define HP_APM_REGION3_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x2c) /** HP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 3. + * Configures the end address of region 3. */ #define HP_APM_REGION3_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION3_ADDR_END_M (HP_APM_REGION3_ADDR_END_V << HP_APM_REGION3_ADDR_END_S) @@ -347,74 +359,78 @@ extern "C" { #define HP_APM_REGION3_ADDR_END_S 0 /** HP_APM_REGION3_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION3_ATTR_REG (DR_REG_HP_APM_BASE + 0x30) /** HP_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 3. + * Configures the execution permission in region 3 in REE0 mode. */ #define HP_APM_REGION3_R0_X (BIT(0)) #define HP_APM_REGION3_R0_X_M (HP_APM_REGION3_R0_X_V << HP_APM_REGION3_R0_X_S) #define HP_APM_REGION3_R0_X_V 0x00000001U #define HP_APM_REGION3_R0_X_S 0 /** HP_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 3. + * Configures the write permission in region 3 in REE0 mode. */ #define HP_APM_REGION3_R0_W (BIT(1)) #define HP_APM_REGION3_R0_W_M (HP_APM_REGION3_R0_W_V << HP_APM_REGION3_R0_W_S) #define HP_APM_REGION3_R0_W_V 0x00000001U #define HP_APM_REGION3_R0_W_S 1 /** HP_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 3. + * Configures the read permission in region 3 in REE0 mode. */ #define HP_APM_REGION3_R0_R (BIT(2)) #define HP_APM_REGION3_R0_R_M (HP_APM_REGION3_R0_R_V << HP_APM_REGION3_R0_R_S) #define HP_APM_REGION3_R0_R_V 0x00000001U #define HP_APM_REGION3_R0_R_S 2 /** HP_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 3. + * Configures the execution permission in region 3 in REE1 mode. */ #define HP_APM_REGION3_R1_X (BIT(4)) #define HP_APM_REGION3_R1_X_M (HP_APM_REGION3_R1_X_V << HP_APM_REGION3_R1_X_S) #define HP_APM_REGION3_R1_X_V 0x00000001U #define HP_APM_REGION3_R1_X_S 4 /** HP_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 3. + * Configures the write permission in region 3 in REE1 mode. */ #define HP_APM_REGION3_R1_W (BIT(5)) #define HP_APM_REGION3_R1_W_M (HP_APM_REGION3_R1_W_V << HP_APM_REGION3_R1_W_S) #define HP_APM_REGION3_R1_W_V 0x00000001U #define HP_APM_REGION3_R1_W_S 5 /** HP_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 3. + * Configures the read permission in region 3 in REE1 mode. */ #define HP_APM_REGION3_R1_R (BIT(6)) #define HP_APM_REGION3_R1_R_M (HP_APM_REGION3_R1_R_V << HP_APM_REGION3_R1_R_S) #define HP_APM_REGION3_R1_R_V 0x00000001U #define HP_APM_REGION3_R1_R_S 6 /** HP_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 3. + * Configures the execution permission in region 3 in REE2 mode. */ #define HP_APM_REGION3_R2_X (BIT(8)) #define HP_APM_REGION3_R2_X_M (HP_APM_REGION3_R2_X_V << HP_APM_REGION3_R2_X_S) #define HP_APM_REGION3_R2_X_V 0x00000001U #define HP_APM_REGION3_R2_X_S 8 /** HP_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 3. + * Configures the write permission in region 3 in REE2 mode. */ #define HP_APM_REGION3_R2_W (BIT(9)) #define HP_APM_REGION3_R2_W_M (HP_APM_REGION3_R2_W_V << HP_APM_REGION3_R2_W_S) #define HP_APM_REGION3_R2_W_V 0x00000001U #define HP_APM_REGION3_R2_W_S 9 /** HP_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 3. + * Configures the read permission in region 3 in REE2 mode. */ #define HP_APM_REGION3_R2_R (BIT(10)) #define HP_APM_REGION3_R2_R_M (HP_APM_REGION3_R2_R_V << HP_APM_REGION3_R2_R_S) #define HP_APM_REGION3_R2_R_V 0x00000001U #define HP_APM_REGION3_R2_R_S 10 /** HP_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 3 configuration registers + * (HP_APM_REGION3_ADDR_START_REG, HP_APM_REGION3_ADDR_END_REG and + * HP_APM_REGION3_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION3_LOCK (BIT(11)) #define HP_APM_REGION3_LOCK_M (HP_APM_REGION3_LOCK_V << HP_APM_REGION3_LOCK_S) @@ -426,7 +442,7 @@ extern "C" { */ #define HP_APM_REGION4_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x34) /** HP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 4. + * Configures the start address of region 4. */ #define HP_APM_REGION4_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION4_ADDR_START_M (HP_APM_REGION4_ADDR_START_V << HP_APM_REGION4_ADDR_START_S) @@ -438,7 +454,7 @@ extern "C" { */ #define HP_APM_REGION4_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x38) /** HP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 4. + * Configures the end address of region 4. */ #define HP_APM_REGION4_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION4_ADDR_END_M (HP_APM_REGION4_ADDR_END_V << HP_APM_REGION4_ADDR_END_S) @@ -446,74 +462,78 @@ extern "C" { #define HP_APM_REGION4_ADDR_END_S 0 /** HP_APM_REGION4_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION4_ATTR_REG (DR_REG_HP_APM_BASE + 0x3c) /** HP_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 4. + * Configures the execution permission in region 4 in REE0 mode. */ #define HP_APM_REGION4_R0_X (BIT(0)) #define HP_APM_REGION4_R0_X_M (HP_APM_REGION4_R0_X_V << HP_APM_REGION4_R0_X_S) #define HP_APM_REGION4_R0_X_V 0x00000001U #define HP_APM_REGION4_R0_X_S 0 /** HP_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 4. + * Configures the write permission in region 4 in REE0 mode. */ #define HP_APM_REGION4_R0_W (BIT(1)) #define HP_APM_REGION4_R0_W_M (HP_APM_REGION4_R0_W_V << HP_APM_REGION4_R0_W_S) #define HP_APM_REGION4_R0_W_V 0x00000001U #define HP_APM_REGION4_R0_W_S 1 /** HP_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 4. + * Configures the read permission in region 4 in REE0 mode. */ #define HP_APM_REGION4_R0_R (BIT(2)) #define HP_APM_REGION4_R0_R_M (HP_APM_REGION4_R0_R_V << HP_APM_REGION4_R0_R_S) #define HP_APM_REGION4_R0_R_V 0x00000001U #define HP_APM_REGION4_R0_R_S 2 /** HP_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 4. + * Configures the execution permission in region 4 in REE1 mode. */ #define HP_APM_REGION4_R1_X (BIT(4)) #define HP_APM_REGION4_R1_X_M (HP_APM_REGION4_R1_X_V << HP_APM_REGION4_R1_X_S) #define HP_APM_REGION4_R1_X_V 0x00000001U #define HP_APM_REGION4_R1_X_S 4 /** HP_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 4. + * Configures the write permission in region 4 in REE1 mode. */ #define HP_APM_REGION4_R1_W (BIT(5)) #define HP_APM_REGION4_R1_W_M (HP_APM_REGION4_R1_W_V << HP_APM_REGION4_R1_W_S) #define HP_APM_REGION4_R1_W_V 0x00000001U #define HP_APM_REGION4_R1_W_S 5 /** HP_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 4. + * Configures the read permission in region 4 in REE1 mode. */ #define HP_APM_REGION4_R1_R (BIT(6)) #define HP_APM_REGION4_R1_R_M (HP_APM_REGION4_R1_R_V << HP_APM_REGION4_R1_R_S) #define HP_APM_REGION4_R1_R_V 0x00000001U #define HP_APM_REGION4_R1_R_S 6 /** HP_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 4. + * Configures the execution permission in region 4 in REE2 mode. */ #define HP_APM_REGION4_R2_X (BIT(8)) #define HP_APM_REGION4_R2_X_M (HP_APM_REGION4_R2_X_V << HP_APM_REGION4_R2_X_S) #define HP_APM_REGION4_R2_X_V 0x00000001U #define HP_APM_REGION4_R2_X_S 8 /** HP_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 4. + * Configures the write permission in region 4 in REE2 mode. */ #define HP_APM_REGION4_R2_W (BIT(9)) #define HP_APM_REGION4_R2_W_M (HP_APM_REGION4_R2_W_V << HP_APM_REGION4_R2_W_S) #define HP_APM_REGION4_R2_W_V 0x00000001U #define HP_APM_REGION4_R2_W_S 9 /** HP_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 4. + * Configures the read permission in region 4 in REE2 mode. */ #define HP_APM_REGION4_R2_R (BIT(10)) #define HP_APM_REGION4_R2_R_M (HP_APM_REGION4_R2_R_V << HP_APM_REGION4_R2_R_S) #define HP_APM_REGION4_R2_R_V 0x00000001U #define HP_APM_REGION4_R2_R_S 10 /** HP_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 4 configuration registers + * (HP_APM_REGION4_ADDR_START_REG, HP_APM_REGION4_ADDR_END_REG and + * HP_APM_REGION4_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION4_LOCK (BIT(11)) #define HP_APM_REGION4_LOCK_M (HP_APM_REGION4_LOCK_V << HP_APM_REGION4_LOCK_S) @@ -525,7 +545,7 @@ extern "C" { */ #define HP_APM_REGION5_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x40) /** HP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 5. + * Configures the start address of region 5. */ #define HP_APM_REGION5_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION5_ADDR_START_M (HP_APM_REGION5_ADDR_START_V << HP_APM_REGION5_ADDR_START_S) @@ -537,7 +557,7 @@ extern "C" { */ #define HP_APM_REGION5_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x44) /** HP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 5. + * Configures the end address of region 5. */ #define HP_APM_REGION5_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION5_ADDR_END_M (HP_APM_REGION5_ADDR_END_V << HP_APM_REGION5_ADDR_END_S) @@ -545,74 +565,78 @@ extern "C" { #define HP_APM_REGION5_ADDR_END_S 0 /** HP_APM_REGION5_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION5_ATTR_REG (DR_REG_HP_APM_BASE + 0x48) /** HP_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 5. + * Configures the execution permission in region 5 in REE0 mode. */ #define HP_APM_REGION5_R0_X (BIT(0)) #define HP_APM_REGION5_R0_X_M (HP_APM_REGION5_R0_X_V << HP_APM_REGION5_R0_X_S) #define HP_APM_REGION5_R0_X_V 0x00000001U #define HP_APM_REGION5_R0_X_S 0 /** HP_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 5. + * Configures the write permission in region 5 in REE0 mode. */ #define HP_APM_REGION5_R0_W (BIT(1)) #define HP_APM_REGION5_R0_W_M (HP_APM_REGION5_R0_W_V << HP_APM_REGION5_R0_W_S) #define HP_APM_REGION5_R0_W_V 0x00000001U #define HP_APM_REGION5_R0_W_S 1 /** HP_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 5. + * Configures the read permission in region 5 in REE0 mode. */ #define HP_APM_REGION5_R0_R (BIT(2)) #define HP_APM_REGION5_R0_R_M (HP_APM_REGION5_R0_R_V << HP_APM_REGION5_R0_R_S) #define HP_APM_REGION5_R0_R_V 0x00000001U #define HP_APM_REGION5_R0_R_S 2 /** HP_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 5. + * Configures the execution permission in region 5 in REE1 mode. */ #define HP_APM_REGION5_R1_X (BIT(4)) #define HP_APM_REGION5_R1_X_M (HP_APM_REGION5_R1_X_V << HP_APM_REGION5_R1_X_S) #define HP_APM_REGION5_R1_X_V 0x00000001U #define HP_APM_REGION5_R1_X_S 4 /** HP_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 5. + * Configures the write permission in region 5 in REE1 mode. */ #define HP_APM_REGION5_R1_W (BIT(5)) #define HP_APM_REGION5_R1_W_M (HP_APM_REGION5_R1_W_V << HP_APM_REGION5_R1_W_S) #define HP_APM_REGION5_R1_W_V 0x00000001U #define HP_APM_REGION5_R1_W_S 5 /** HP_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 5. + * Configures the read permission in region 5 in REE1 mode. */ #define HP_APM_REGION5_R1_R (BIT(6)) #define HP_APM_REGION5_R1_R_M (HP_APM_REGION5_R1_R_V << HP_APM_REGION5_R1_R_S) #define HP_APM_REGION5_R1_R_V 0x00000001U #define HP_APM_REGION5_R1_R_S 6 /** HP_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 5. + * Configures the execution permission in region 5 in REE2 mode. */ #define HP_APM_REGION5_R2_X (BIT(8)) #define HP_APM_REGION5_R2_X_M (HP_APM_REGION5_R2_X_V << HP_APM_REGION5_R2_X_S) #define HP_APM_REGION5_R2_X_V 0x00000001U #define HP_APM_REGION5_R2_X_S 8 /** HP_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 5. + * Configures the write permission in region 5 in REE2 mode. */ #define HP_APM_REGION5_R2_W (BIT(9)) #define HP_APM_REGION5_R2_W_M (HP_APM_REGION5_R2_W_V << HP_APM_REGION5_R2_W_S) #define HP_APM_REGION5_R2_W_V 0x00000001U #define HP_APM_REGION5_R2_W_S 9 /** HP_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 5. + * Configures the read permission in region 5 in REE2 mode. */ #define HP_APM_REGION5_R2_R (BIT(10)) #define HP_APM_REGION5_R2_R_M (HP_APM_REGION5_R2_R_V << HP_APM_REGION5_R2_R_S) #define HP_APM_REGION5_R2_R_V 0x00000001U #define HP_APM_REGION5_R2_R_S 10 /** HP_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 5 configuration registers + * (HP_APM_REGION5_ADDR_START_REG, HP_APM_REGION5_ADDR_END_REG and + * HP_APM_REGION5_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION5_LOCK (BIT(11)) #define HP_APM_REGION5_LOCK_M (HP_APM_REGION5_LOCK_V << HP_APM_REGION5_LOCK_S) @@ -624,7 +648,7 @@ extern "C" { */ #define HP_APM_REGION6_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4c) /** HP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 6. + * Configures the start address of region 6. */ #define HP_APM_REGION6_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION6_ADDR_START_M (HP_APM_REGION6_ADDR_START_V << HP_APM_REGION6_ADDR_START_S) @@ -636,7 +660,7 @@ extern "C" { */ #define HP_APM_REGION6_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x50) /** HP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 6. + * Configures the end address of region 6. */ #define HP_APM_REGION6_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION6_ADDR_END_M (HP_APM_REGION6_ADDR_END_V << HP_APM_REGION6_ADDR_END_S) @@ -644,74 +668,78 @@ extern "C" { #define HP_APM_REGION6_ADDR_END_S 0 /** HP_APM_REGION6_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION6_ATTR_REG (DR_REG_HP_APM_BASE + 0x54) /** HP_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 6. + * Configures the execution permission in region 6 in REE0 mode. */ #define HP_APM_REGION6_R0_X (BIT(0)) #define HP_APM_REGION6_R0_X_M (HP_APM_REGION6_R0_X_V << HP_APM_REGION6_R0_X_S) #define HP_APM_REGION6_R0_X_V 0x00000001U #define HP_APM_REGION6_R0_X_S 0 /** HP_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 6. + * Configures the write permission in region 6 in REE0 mode. */ #define HP_APM_REGION6_R0_W (BIT(1)) #define HP_APM_REGION6_R0_W_M (HP_APM_REGION6_R0_W_V << HP_APM_REGION6_R0_W_S) #define HP_APM_REGION6_R0_W_V 0x00000001U #define HP_APM_REGION6_R0_W_S 1 /** HP_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 6. + * Configures the read permission in region 6 in REE0 mode. */ #define HP_APM_REGION6_R0_R (BIT(2)) #define HP_APM_REGION6_R0_R_M (HP_APM_REGION6_R0_R_V << HP_APM_REGION6_R0_R_S) #define HP_APM_REGION6_R0_R_V 0x00000001U #define HP_APM_REGION6_R0_R_S 2 /** HP_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 6. + * Configures the execution permission in region 6 in REE1 mode. */ #define HP_APM_REGION6_R1_X (BIT(4)) #define HP_APM_REGION6_R1_X_M (HP_APM_REGION6_R1_X_V << HP_APM_REGION6_R1_X_S) #define HP_APM_REGION6_R1_X_V 0x00000001U #define HP_APM_REGION6_R1_X_S 4 /** HP_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 6. + * Configures the write permission in region 6 in REE1 mode. */ #define HP_APM_REGION6_R1_W (BIT(5)) #define HP_APM_REGION6_R1_W_M (HP_APM_REGION6_R1_W_V << HP_APM_REGION6_R1_W_S) #define HP_APM_REGION6_R1_W_V 0x00000001U #define HP_APM_REGION6_R1_W_S 5 /** HP_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 6. + * Configures the read permission in region 6 in REE1 mode. */ #define HP_APM_REGION6_R1_R (BIT(6)) #define HP_APM_REGION6_R1_R_M (HP_APM_REGION6_R1_R_V << HP_APM_REGION6_R1_R_S) #define HP_APM_REGION6_R1_R_V 0x00000001U #define HP_APM_REGION6_R1_R_S 6 /** HP_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 6. + * Configures the execution permission in region 6 in REE2 mode. */ #define HP_APM_REGION6_R2_X (BIT(8)) #define HP_APM_REGION6_R2_X_M (HP_APM_REGION6_R2_X_V << HP_APM_REGION6_R2_X_S) #define HP_APM_REGION6_R2_X_V 0x00000001U #define HP_APM_REGION6_R2_X_S 8 /** HP_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 6. + * Configures the write permission in region 6 in REE2 mode. */ #define HP_APM_REGION6_R2_W (BIT(9)) #define HP_APM_REGION6_R2_W_M (HP_APM_REGION6_R2_W_V << HP_APM_REGION6_R2_W_S) #define HP_APM_REGION6_R2_W_V 0x00000001U #define HP_APM_REGION6_R2_W_S 9 /** HP_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 6. + * Configures the read permission in region 6 in REE2 mode. */ #define HP_APM_REGION6_R2_R (BIT(10)) #define HP_APM_REGION6_R2_R_M (HP_APM_REGION6_R2_R_V << HP_APM_REGION6_R2_R_S) #define HP_APM_REGION6_R2_R_V 0x00000001U #define HP_APM_REGION6_R2_R_S 10 /** HP_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 6 configuration registers + * (HP_APM_REGION6_ADDR_START_REG, HP_APM_REGION6_ADDR_END_REG and + * HP_APM_REGION6_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION6_LOCK (BIT(11)) #define HP_APM_REGION6_LOCK_M (HP_APM_REGION6_LOCK_V << HP_APM_REGION6_LOCK_S) @@ -723,7 +751,7 @@ extern "C" { */ #define HP_APM_REGION7_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x58) /** HP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 7. + * Configures the start address of region 7. */ #define HP_APM_REGION7_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION7_ADDR_START_M (HP_APM_REGION7_ADDR_START_V << HP_APM_REGION7_ADDR_START_S) @@ -735,7 +763,7 @@ extern "C" { */ #define HP_APM_REGION7_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x5c) /** HP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 7. + * Configures the end address of region 7. */ #define HP_APM_REGION7_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION7_ADDR_END_M (HP_APM_REGION7_ADDR_END_V << HP_APM_REGION7_ADDR_END_S) @@ -743,74 +771,78 @@ extern "C" { #define HP_APM_REGION7_ADDR_END_S 0 /** HP_APM_REGION7_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION7_ATTR_REG (DR_REG_HP_APM_BASE + 0x60) /** HP_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 7. + * Configures the execution permission in region 7 in REE0 mode. */ #define HP_APM_REGION7_R0_X (BIT(0)) #define HP_APM_REGION7_R0_X_M (HP_APM_REGION7_R0_X_V << HP_APM_REGION7_R0_X_S) #define HP_APM_REGION7_R0_X_V 0x00000001U #define HP_APM_REGION7_R0_X_S 0 /** HP_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 7. + * Configures the write permission in region 7 in REE0 mode. */ #define HP_APM_REGION7_R0_W (BIT(1)) #define HP_APM_REGION7_R0_W_M (HP_APM_REGION7_R0_W_V << HP_APM_REGION7_R0_W_S) #define HP_APM_REGION7_R0_W_V 0x00000001U #define HP_APM_REGION7_R0_W_S 1 /** HP_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 7. + * Configures the read permission in region 7 in REE0 mode. */ #define HP_APM_REGION7_R0_R (BIT(2)) #define HP_APM_REGION7_R0_R_M (HP_APM_REGION7_R0_R_V << HP_APM_REGION7_R0_R_S) #define HP_APM_REGION7_R0_R_V 0x00000001U #define HP_APM_REGION7_R0_R_S 2 /** HP_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 7. + * Configures the execution permission in region 7 in REE1 mode. */ #define HP_APM_REGION7_R1_X (BIT(4)) #define HP_APM_REGION7_R1_X_M (HP_APM_REGION7_R1_X_V << HP_APM_REGION7_R1_X_S) #define HP_APM_REGION7_R1_X_V 0x00000001U #define HP_APM_REGION7_R1_X_S 4 /** HP_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 7. + * Configures the write permission in region 7 in REE1 mode. */ #define HP_APM_REGION7_R1_W (BIT(5)) #define HP_APM_REGION7_R1_W_M (HP_APM_REGION7_R1_W_V << HP_APM_REGION7_R1_W_S) #define HP_APM_REGION7_R1_W_V 0x00000001U #define HP_APM_REGION7_R1_W_S 5 /** HP_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 7. + * Configures the read permission in region 7 in REE1 mode. */ #define HP_APM_REGION7_R1_R (BIT(6)) #define HP_APM_REGION7_R1_R_M (HP_APM_REGION7_R1_R_V << HP_APM_REGION7_R1_R_S) #define HP_APM_REGION7_R1_R_V 0x00000001U #define HP_APM_REGION7_R1_R_S 6 /** HP_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 7. + * Configures the execution permission in region 7 in REE2 mode. */ #define HP_APM_REGION7_R2_X (BIT(8)) #define HP_APM_REGION7_R2_X_M (HP_APM_REGION7_R2_X_V << HP_APM_REGION7_R2_X_S) #define HP_APM_REGION7_R2_X_V 0x00000001U #define HP_APM_REGION7_R2_X_S 8 /** HP_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 7. + * Configures the write permission in region 7 in REE2 mode. */ #define HP_APM_REGION7_R2_W (BIT(9)) #define HP_APM_REGION7_R2_W_M (HP_APM_REGION7_R2_W_V << HP_APM_REGION7_R2_W_S) #define HP_APM_REGION7_R2_W_V 0x00000001U #define HP_APM_REGION7_R2_W_S 9 /** HP_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 7. + * Configures the read permission in region 7 in REE2 mode. */ #define HP_APM_REGION7_R2_R (BIT(10)) #define HP_APM_REGION7_R2_R_M (HP_APM_REGION7_R2_R_V << HP_APM_REGION7_R2_R_S) #define HP_APM_REGION7_R2_R_V 0x00000001U #define HP_APM_REGION7_R2_R_S 10 /** HP_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 7 configuration registers + * (HP_APM_REGION7_ADDR_START_REG, HP_APM_REGION7_ADDR_END_REG and + * HP_APM_REGION7_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION7_LOCK (BIT(11)) #define HP_APM_REGION7_LOCK_M (HP_APM_REGION7_LOCK_V << HP_APM_REGION7_LOCK_S) @@ -822,7 +854,7 @@ extern "C" { */ #define HP_APM_REGION8_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x64) /** HP_APM_REGION8_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 8. + * Configures the start address of region 8. */ #define HP_APM_REGION8_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION8_ADDR_START_M (HP_APM_REGION8_ADDR_START_V << HP_APM_REGION8_ADDR_START_S) @@ -834,7 +866,7 @@ extern "C" { */ #define HP_APM_REGION8_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x68) /** HP_APM_REGION8_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 8. + * Configures the end address of region 8. */ #define HP_APM_REGION8_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION8_ADDR_END_M (HP_APM_REGION8_ADDR_END_V << HP_APM_REGION8_ADDR_END_S) @@ -842,74 +874,78 @@ extern "C" { #define HP_APM_REGION8_ADDR_END_S 0 /** HP_APM_REGION8_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION8_ATTR_REG (DR_REG_HP_APM_BASE + 0x6c) /** HP_APM_REGION8_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 8. + * Configures the execution permission in region 8 in REE0 mode. */ #define HP_APM_REGION8_R0_X (BIT(0)) #define HP_APM_REGION8_R0_X_M (HP_APM_REGION8_R0_X_V << HP_APM_REGION8_R0_X_S) #define HP_APM_REGION8_R0_X_V 0x00000001U #define HP_APM_REGION8_R0_X_S 0 /** HP_APM_REGION8_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 8. + * Configures the write permission in region 8 in REE0 mode. */ #define HP_APM_REGION8_R0_W (BIT(1)) #define HP_APM_REGION8_R0_W_M (HP_APM_REGION8_R0_W_V << HP_APM_REGION8_R0_W_S) #define HP_APM_REGION8_R0_W_V 0x00000001U #define HP_APM_REGION8_R0_W_S 1 /** HP_APM_REGION8_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 8. + * Configures the read permission in region 8 in REE0 mode. */ #define HP_APM_REGION8_R0_R (BIT(2)) #define HP_APM_REGION8_R0_R_M (HP_APM_REGION8_R0_R_V << HP_APM_REGION8_R0_R_S) #define HP_APM_REGION8_R0_R_V 0x00000001U #define HP_APM_REGION8_R0_R_S 2 /** HP_APM_REGION8_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 8. + * Configures the execution permission in region 8 in REE1 mode. */ #define HP_APM_REGION8_R1_X (BIT(4)) #define HP_APM_REGION8_R1_X_M (HP_APM_REGION8_R1_X_V << HP_APM_REGION8_R1_X_S) #define HP_APM_REGION8_R1_X_V 0x00000001U #define HP_APM_REGION8_R1_X_S 4 /** HP_APM_REGION8_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 8. + * Configures the write permission in region 8 in REE1 mode. */ #define HP_APM_REGION8_R1_W (BIT(5)) #define HP_APM_REGION8_R1_W_M (HP_APM_REGION8_R1_W_V << HP_APM_REGION8_R1_W_S) #define HP_APM_REGION8_R1_W_V 0x00000001U #define HP_APM_REGION8_R1_W_S 5 /** HP_APM_REGION8_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 8. + * Configures the read permission in region 8 in REE1 mode. */ #define HP_APM_REGION8_R1_R (BIT(6)) #define HP_APM_REGION8_R1_R_M (HP_APM_REGION8_R1_R_V << HP_APM_REGION8_R1_R_S) #define HP_APM_REGION8_R1_R_V 0x00000001U #define HP_APM_REGION8_R1_R_S 6 /** HP_APM_REGION8_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 8. + * Configures the execution permission in region 8 in REE2 mode. */ #define HP_APM_REGION8_R2_X (BIT(8)) #define HP_APM_REGION8_R2_X_M (HP_APM_REGION8_R2_X_V << HP_APM_REGION8_R2_X_S) #define HP_APM_REGION8_R2_X_V 0x00000001U #define HP_APM_REGION8_R2_X_S 8 /** HP_APM_REGION8_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 8. + * Configures the write permission in region 8 in REE2 mode. */ #define HP_APM_REGION8_R2_W (BIT(9)) #define HP_APM_REGION8_R2_W_M (HP_APM_REGION8_R2_W_V << HP_APM_REGION8_R2_W_S) #define HP_APM_REGION8_R2_W_V 0x00000001U #define HP_APM_REGION8_R2_W_S 9 /** HP_APM_REGION8_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 8. + * Configures the read permission in region 8 in REE2 mode. */ #define HP_APM_REGION8_R2_R (BIT(10)) #define HP_APM_REGION8_R2_R_M (HP_APM_REGION8_R2_R_V << HP_APM_REGION8_R2_R_S) #define HP_APM_REGION8_R2_R_V 0x00000001U #define HP_APM_REGION8_R2_R_S 10 /** HP_APM_REGION8_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 8 configuration registers + * (HP_APM_REGION8_ADDR_START_REG, HP_APM_REGION8_ADDR_END_REG and + * HP_APM_REGION8_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION8_LOCK (BIT(11)) #define HP_APM_REGION8_LOCK_M (HP_APM_REGION8_LOCK_V << HP_APM_REGION8_LOCK_S) @@ -921,7 +957,7 @@ extern "C" { */ #define HP_APM_REGION9_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x70) /** HP_APM_REGION9_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 9. + * Configures the start address of region 9. */ #define HP_APM_REGION9_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION9_ADDR_START_M (HP_APM_REGION9_ADDR_START_V << HP_APM_REGION9_ADDR_START_S) @@ -933,7 +969,7 @@ extern "C" { */ #define HP_APM_REGION9_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x74) /** HP_APM_REGION9_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 9. + * Configures the end address of region 9. */ #define HP_APM_REGION9_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION9_ADDR_END_M (HP_APM_REGION9_ADDR_END_V << HP_APM_REGION9_ADDR_END_S) @@ -941,74 +977,78 @@ extern "C" { #define HP_APM_REGION9_ADDR_END_S 0 /** HP_APM_REGION9_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION9_ATTR_REG (DR_REG_HP_APM_BASE + 0x78) /** HP_APM_REGION9_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 9. + * Configures the execution permission in region 9 in REE0 mode. */ #define HP_APM_REGION9_R0_X (BIT(0)) #define HP_APM_REGION9_R0_X_M (HP_APM_REGION9_R0_X_V << HP_APM_REGION9_R0_X_S) #define HP_APM_REGION9_R0_X_V 0x00000001U #define HP_APM_REGION9_R0_X_S 0 /** HP_APM_REGION9_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 9. + * Configures the write permission in region 9 in REE0 mode. */ #define HP_APM_REGION9_R0_W (BIT(1)) #define HP_APM_REGION9_R0_W_M (HP_APM_REGION9_R0_W_V << HP_APM_REGION9_R0_W_S) #define HP_APM_REGION9_R0_W_V 0x00000001U #define HP_APM_REGION9_R0_W_S 1 /** HP_APM_REGION9_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 9. + * Configures the read permission in region 9 in REE0 mode. */ #define HP_APM_REGION9_R0_R (BIT(2)) #define HP_APM_REGION9_R0_R_M (HP_APM_REGION9_R0_R_V << HP_APM_REGION9_R0_R_S) #define HP_APM_REGION9_R0_R_V 0x00000001U #define HP_APM_REGION9_R0_R_S 2 /** HP_APM_REGION9_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 9. + * Configures the execution permission in region 9 in REE1 mode. */ #define HP_APM_REGION9_R1_X (BIT(4)) #define HP_APM_REGION9_R1_X_M (HP_APM_REGION9_R1_X_V << HP_APM_REGION9_R1_X_S) #define HP_APM_REGION9_R1_X_V 0x00000001U #define HP_APM_REGION9_R1_X_S 4 /** HP_APM_REGION9_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 9. + * Configures the write permission in region 9 in REE1 mode. */ #define HP_APM_REGION9_R1_W (BIT(5)) #define HP_APM_REGION9_R1_W_M (HP_APM_REGION9_R1_W_V << HP_APM_REGION9_R1_W_S) #define HP_APM_REGION9_R1_W_V 0x00000001U #define HP_APM_REGION9_R1_W_S 5 /** HP_APM_REGION9_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 9. + * Configures the read permission in region 9 in REE1 mode. */ #define HP_APM_REGION9_R1_R (BIT(6)) #define HP_APM_REGION9_R1_R_M (HP_APM_REGION9_R1_R_V << HP_APM_REGION9_R1_R_S) #define HP_APM_REGION9_R1_R_V 0x00000001U #define HP_APM_REGION9_R1_R_S 6 /** HP_APM_REGION9_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 9. + * Configures the execution permission in region 9 in REE2 mode. */ #define HP_APM_REGION9_R2_X (BIT(8)) #define HP_APM_REGION9_R2_X_M (HP_APM_REGION9_R2_X_V << HP_APM_REGION9_R2_X_S) #define HP_APM_REGION9_R2_X_V 0x00000001U #define HP_APM_REGION9_R2_X_S 8 /** HP_APM_REGION9_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 9. + * Configures the write permission in region 9 in REE2 mode. */ #define HP_APM_REGION9_R2_W (BIT(9)) #define HP_APM_REGION9_R2_W_M (HP_APM_REGION9_R2_W_V << HP_APM_REGION9_R2_W_S) #define HP_APM_REGION9_R2_W_V 0x00000001U #define HP_APM_REGION9_R2_W_S 9 /** HP_APM_REGION9_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 9. + * Configures the read permission in region 9 in REE2 mode. */ #define HP_APM_REGION9_R2_R (BIT(10)) #define HP_APM_REGION9_R2_R_M (HP_APM_REGION9_R2_R_V << HP_APM_REGION9_R2_R_S) #define HP_APM_REGION9_R2_R_V 0x00000001U #define HP_APM_REGION9_R2_R_S 10 /** HP_APM_REGION9_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 9 configuration registers + * (HP_APM_REGION9_ADDR_START_REG, HP_APM_REGION9_ADDR_END_REG and + * HP_APM_REGION9_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION9_LOCK (BIT(11)) #define HP_APM_REGION9_LOCK_M (HP_APM_REGION9_LOCK_V << HP_APM_REGION9_LOCK_S) @@ -1020,7 +1060,7 @@ extern "C" { */ #define HP_APM_REGION10_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x7c) /** HP_APM_REGION10_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 10. + * Configures the start address of region 10. */ #define HP_APM_REGION10_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION10_ADDR_START_M (HP_APM_REGION10_ADDR_START_V << HP_APM_REGION10_ADDR_START_S) @@ -1032,7 +1072,7 @@ extern "C" { */ #define HP_APM_REGION10_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x80) /** HP_APM_REGION10_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 10. + * Configures the end address of region 10. */ #define HP_APM_REGION10_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION10_ADDR_END_M (HP_APM_REGION10_ADDR_END_V << HP_APM_REGION10_ADDR_END_S) @@ -1040,74 +1080,78 @@ extern "C" { #define HP_APM_REGION10_ADDR_END_S 0 /** HP_APM_REGION10_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION10_ATTR_REG (DR_REG_HP_APM_BASE + 0x84) /** HP_APM_REGION10_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 10. + * Configures the execution permission in region 10 in REE0 mode. */ #define HP_APM_REGION10_R0_X (BIT(0)) #define HP_APM_REGION10_R0_X_M (HP_APM_REGION10_R0_X_V << HP_APM_REGION10_R0_X_S) #define HP_APM_REGION10_R0_X_V 0x00000001U #define HP_APM_REGION10_R0_X_S 0 /** HP_APM_REGION10_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 10. + * Configures the write permission in region 10 in REE0 mode. */ #define HP_APM_REGION10_R0_W (BIT(1)) #define HP_APM_REGION10_R0_W_M (HP_APM_REGION10_R0_W_V << HP_APM_REGION10_R0_W_S) #define HP_APM_REGION10_R0_W_V 0x00000001U #define HP_APM_REGION10_R0_W_S 1 /** HP_APM_REGION10_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 10. + * Configures the read permission in region 10 in REE0 mode. */ #define HP_APM_REGION10_R0_R (BIT(2)) #define HP_APM_REGION10_R0_R_M (HP_APM_REGION10_R0_R_V << HP_APM_REGION10_R0_R_S) #define HP_APM_REGION10_R0_R_V 0x00000001U #define HP_APM_REGION10_R0_R_S 2 /** HP_APM_REGION10_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 10. + * Configures the execution permission in region 10 in REE1 mode. */ #define HP_APM_REGION10_R1_X (BIT(4)) #define HP_APM_REGION10_R1_X_M (HP_APM_REGION10_R1_X_V << HP_APM_REGION10_R1_X_S) #define HP_APM_REGION10_R1_X_V 0x00000001U #define HP_APM_REGION10_R1_X_S 4 /** HP_APM_REGION10_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 10. + * Configures the write permission in region 10 in REE1 mode. */ #define HP_APM_REGION10_R1_W (BIT(5)) #define HP_APM_REGION10_R1_W_M (HP_APM_REGION10_R1_W_V << HP_APM_REGION10_R1_W_S) #define HP_APM_REGION10_R1_W_V 0x00000001U #define HP_APM_REGION10_R1_W_S 5 /** HP_APM_REGION10_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 10. + * Configures the read permission in region 10 in REE1 mode. */ #define HP_APM_REGION10_R1_R (BIT(6)) #define HP_APM_REGION10_R1_R_M (HP_APM_REGION10_R1_R_V << HP_APM_REGION10_R1_R_S) #define HP_APM_REGION10_R1_R_V 0x00000001U #define HP_APM_REGION10_R1_R_S 6 /** HP_APM_REGION10_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 10. + * Configures the execution permission in region 10 in REE2 mode. */ #define HP_APM_REGION10_R2_X (BIT(8)) #define HP_APM_REGION10_R2_X_M (HP_APM_REGION10_R2_X_V << HP_APM_REGION10_R2_X_S) #define HP_APM_REGION10_R2_X_V 0x00000001U #define HP_APM_REGION10_R2_X_S 8 /** HP_APM_REGION10_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 10. + * Configures the write permission in region 10 in REE2 mode. */ #define HP_APM_REGION10_R2_W (BIT(9)) #define HP_APM_REGION10_R2_W_M (HP_APM_REGION10_R2_W_V << HP_APM_REGION10_R2_W_S) #define HP_APM_REGION10_R2_W_V 0x00000001U #define HP_APM_REGION10_R2_W_S 9 /** HP_APM_REGION10_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 10. + * Configures the read permission in region 10 in REE2 mode. */ #define HP_APM_REGION10_R2_R (BIT(10)) #define HP_APM_REGION10_R2_R_M (HP_APM_REGION10_R2_R_V << HP_APM_REGION10_R2_R_S) #define HP_APM_REGION10_R2_R_V 0x00000001U #define HP_APM_REGION10_R2_R_S 10 /** HP_APM_REGION10_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 10 configuration registers + * (HP_APM_REGION10_ADDR_START_REG, HP_APM_REGION10_ADDR_END_REG and + * HP_APM_REGION10_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION10_LOCK (BIT(11)) #define HP_APM_REGION10_LOCK_M (HP_APM_REGION10_LOCK_V << HP_APM_REGION10_LOCK_S) @@ -1119,7 +1163,7 @@ extern "C" { */ #define HP_APM_REGION11_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x88) /** HP_APM_REGION11_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 11. + * Configures the start address of region 11. */ #define HP_APM_REGION11_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION11_ADDR_START_M (HP_APM_REGION11_ADDR_START_V << HP_APM_REGION11_ADDR_START_S) @@ -1131,7 +1175,7 @@ extern "C" { */ #define HP_APM_REGION11_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8c) /** HP_APM_REGION11_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 11. + * Configures the end address of region 11. */ #define HP_APM_REGION11_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION11_ADDR_END_M (HP_APM_REGION11_ADDR_END_V << HP_APM_REGION11_ADDR_END_S) @@ -1139,74 +1183,78 @@ extern "C" { #define HP_APM_REGION11_ADDR_END_S 0 /** HP_APM_REGION11_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION11_ATTR_REG (DR_REG_HP_APM_BASE + 0x90) /** HP_APM_REGION11_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 11. + * Configures the execution permission in region 11 in REE0 mode. */ #define HP_APM_REGION11_R0_X (BIT(0)) #define HP_APM_REGION11_R0_X_M (HP_APM_REGION11_R0_X_V << HP_APM_REGION11_R0_X_S) #define HP_APM_REGION11_R0_X_V 0x00000001U #define HP_APM_REGION11_R0_X_S 0 /** HP_APM_REGION11_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 11. + * Configures the write permission in region 11 in REE0 mode. */ #define HP_APM_REGION11_R0_W (BIT(1)) #define HP_APM_REGION11_R0_W_M (HP_APM_REGION11_R0_W_V << HP_APM_REGION11_R0_W_S) #define HP_APM_REGION11_R0_W_V 0x00000001U #define HP_APM_REGION11_R0_W_S 1 /** HP_APM_REGION11_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 11. + * Configures the read permission in region 11 in REE0 mode. */ #define HP_APM_REGION11_R0_R (BIT(2)) #define HP_APM_REGION11_R0_R_M (HP_APM_REGION11_R0_R_V << HP_APM_REGION11_R0_R_S) #define HP_APM_REGION11_R0_R_V 0x00000001U #define HP_APM_REGION11_R0_R_S 2 /** HP_APM_REGION11_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 11. + * Configures the execution permission in region 11 in REE1 mode. */ #define HP_APM_REGION11_R1_X (BIT(4)) #define HP_APM_REGION11_R1_X_M (HP_APM_REGION11_R1_X_V << HP_APM_REGION11_R1_X_S) #define HP_APM_REGION11_R1_X_V 0x00000001U #define HP_APM_REGION11_R1_X_S 4 /** HP_APM_REGION11_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 11. + * Configures the write permission in region 11 in REE1 mode. */ #define HP_APM_REGION11_R1_W (BIT(5)) #define HP_APM_REGION11_R1_W_M (HP_APM_REGION11_R1_W_V << HP_APM_REGION11_R1_W_S) #define HP_APM_REGION11_R1_W_V 0x00000001U #define HP_APM_REGION11_R1_W_S 5 /** HP_APM_REGION11_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 11. + * Configures the read permission in region 11 in REE1 mode. */ #define HP_APM_REGION11_R1_R (BIT(6)) #define HP_APM_REGION11_R1_R_M (HP_APM_REGION11_R1_R_V << HP_APM_REGION11_R1_R_S) #define HP_APM_REGION11_R1_R_V 0x00000001U #define HP_APM_REGION11_R1_R_S 6 /** HP_APM_REGION11_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 11. + * Configures the execution permission in region 11 in REE2 mode. */ #define HP_APM_REGION11_R2_X (BIT(8)) #define HP_APM_REGION11_R2_X_M (HP_APM_REGION11_R2_X_V << HP_APM_REGION11_R2_X_S) #define HP_APM_REGION11_R2_X_V 0x00000001U #define HP_APM_REGION11_R2_X_S 8 /** HP_APM_REGION11_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 11. + * Configures the write permission in region 11 in REE2 mode. */ #define HP_APM_REGION11_R2_W (BIT(9)) #define HP_APM_REGION11_R2_W_M (HP_APM_REGION11_R2_W_V << HP_APM_REGION11_R2_W_S) #define HP_APM_REGION11_R2_W_V 0x00000001U #define HP_APM_REGION11_R2_W_S 9 /** HP_APM_REGION11_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 11. + * Configures the read permission in region 11 in REE2 mode. */ #define HP_APM_REGION11_R2_R (BIT(10)) #define HP_APM_REGION11_R2_R_M (HP_APM_REGION11_R2_R_V << HP_APM_REGION11_R2_R_S) #define HP_APM_REGION11_R2_R_V 0x00000001U #define HP_APM_REGION11_R2_R_S 10 /** HP_APM_REGION11_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 11 configuration registers + * (HP_APM_REGION11_ADDR_START_REG, HP_APM_REGION11_ADDR_END_REG and + * HP_APM_REGION11_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION11_LOCK (BIT(11)) #define HP_APM_REGION11_LOCK_M (HP_APM_REGION11_LOCK_V << HP_APM_REGION11_LOCK_S) @@ -1218,7 +1266,7 @@ extern "C" { */ #define HP_APM_REGION12_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x94) /** HP_APM_REGION12_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 12. + * Configures the start address of region 12. */ #define HP_APM_REGION12_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION12_ADDR_START_M (HP_APM_REGION12_ADDR_START_V << HP_APM_REGION12_ADDR_START_S) @@ -1230,7 +1278,7 @@ extern "C" { */ #define HP_APM_REGION12_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x98) /** HP_APM_REGION12_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 12. + * Configures the end address of region 12. */ #define HP_APM_REGION12_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION12_ADDR_END_M (HP_APM_REGION12_ADDR_END_V << HP_APM_REGION12_ADDR_END_S) @@ -1238,74 +1286,78 @@ extern "C" { #define HP_APM_REGION12_ADDR_END_S 0 /** HP_APM_REGION12_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION12_ATTR_REG (DR_REG_HP_APM_BASE + 0x9c) /** HP_APM_REGION12_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 12. + * Configures the execution permission in region 12 in REE0 mode. */ #define HP_APM_REGION12_R0_X (BIT(0)) #define HP_APM_REGION12_R0_X_M (HP_APM_REGION12_R0_X_V << HP_APM_REGION12_R0_X_S) #define HP_APM_REGION12_R0_X_V 0x00000001U #define HP_APM_REGION12_R0_X_S 0 /** HP_APM_REGION12_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 12. + * Configures the write permission in region 12 in REE0 mode. */ #define HP_APM_REGION12_R0_W (BIT(1)) #define HP_APM_REGION12_R0_W_M (HP_APM_REGION12_R0_W_V << HP_APM_REGION12_R0_W_S) #define HP_APM_REGION12_R0_W_V 0x00000001U #define HP_APM_REGION12_R0_W_S 1 /** HP_APM_REGION12_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 12. + * Configures the read permission in region 12 in REE0 mode. */ #define HP_APM_REGION12_R0_R (BIT(2)) #define HP_APM_REGION12_R0_R_M (HP_APM_REGION12_R0_R_V << HP_APM_REGION12_R0_R_S) #define HP_APM_REGION12_R0_R_V 0x00000001U #define HP_APM_REGION12_R0_R_S 2 /** HP_APM_REGION12_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 12. + * Configures the execution permission in region 12 in REE1 mode. */ #define HP_APM_REGION12_R1_X (BIT(4)) #define HP_APM_REGION12_R1_X_M (HP_APM_REGION12_R1_X_V << HP_APM_REGION12_R1_X_S) #define HP_APM_REGION12_R1_X_V 0x00000001U #define HP_APM_REGION12_R1_X_S 4 /** HP_APM_REGION12_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 12. + * Configures the write permission in region 12 in REE1 mode. */ #define HP_APM_REGION12_R1_W (BIT(5)) #define HP_APM_REGION12_R1_W_M (HP_APM_REGION12_R1_W_V << HP_APM_REGION12_R1_W_S) #define HP_APM_REGION12_R1_W_V 0x00000001U #define HP_APM_REGION12_R1_W_S 5 /** HP_APM_REGION12_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 12. + * Configures the read permission in region 12 in REE1 mode. */ #define HP_APM_REGION12_R1_R (BIT(6)) #define HP_APM_REGION12_R1_R_M (HP_APM_REGION12_R1_R_V << HP_APM_REGION12_R1_R_S) #define HP_APM_REGION12_R1_R_V 0x00000001U #define HP_APM_REGION12_R1_R_S 6 /** HP_APM_REGION12_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 12. + * Configures the execution permission in region 12 in REE2 mode. */ #define HP_APM_REGION12_R2_X (BIT(8)) #define HP_APM_REGION12_R2_X_M (HP_APM_REGION12_R2_X_V << HP_APM_REGION12_R2_X_S) #define HP_APM_REGION12_R2_X_V 0x00000001U #define HP_APM_REGION12_R2_X_S 8 /** HP_APM_REGION12_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 12. + * Configures the write permission in region 12 in REE2 mode. */ #define HP_APM_REGION12_R2_W (BIT(9)) #define HP_APM_REGION12_R2_W_M (HP_APM_REGION12_R2_W_V << HP_APM_REGION12_R2_W_S) #define HP_APM_REGION12_R2_W_V 0x00000001U #define HP_APM_REGION12_R2_W_S 9 /** HP_APM_REGION12_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 12. + * Configures the read permission in region 12 in REE2 mode. */ #define HP_APM_REGION12_R2_R (BIT(10)) #define HP_APM_REGION12_R2_R_M (HP_APM_REGION12_R2_R_V << HP_APM_REGION12_R2_R_S) #define HP_APM_REGION12_R2_R_V 0x00000001U #define HP_APM_REGION12_R2_R_S 10 /** HP_APM_REGION12_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 12 configuration registers + * (HP_APM_REGION12_ADDR_START_REG, HP_APM_REGION12_ADDR_END_REG and + * HP_APM_REGION12_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION12_LOCK (BIT(11)) #define HP_APM_REGION12_LOCK_M (HP_APM_REGION12_LOCK_V << HP_APM_REGION12_LOCK_S) @@ -1317,7 +1369,7 @@ extern "C" { */ #define HP_APM_REGION13_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xa0) /** HP_APM_REGION13_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 13. + * Configures the start address of region 13. */ #define HP_APM_REGION13_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION13_ADDR_START_M (HP_APM_REGION13_ADDR_START_V << HP_APM_REGION13_ADDR_START_S) @@ -1329,7 +1381,7 @@ extern "C" { */ #define HP_APM_REGION13_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xa4) /** HP_APM_REGION13_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 13. + * Configures the end address of region 13. */ #define HP_APM_REGION13_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION13_ADDR_END_M (HP_APM_REGION13_ADDR_END_V << HP_APM_REGION13_ADDR_END_S) @@ -1337,74 +1389,78 @@ extern "C" { #define HP_APM_REGION13_ADDR_END_S 0 /** HP_APM_REGION13_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION13_ATTR_REG (DR_REG_HP_APM_BASE + 0xa8) /** HP_APM_REGION13_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 13. + * Configures the execution permission in region 13 in REE0 mode. */ #define HP_APM_REGION13_R0_X (BIT(0)) #define HP_APM_REGION13_R0_X_M (HP_APM_REGION13_R0_X_V << HP_APM_REGION13_R0_X_S) #define HP_APM_REGION13_R0_X_V 0x00000001U #define HP_APM_REGION13_R0_X_S 0 /** HP_APM_REGION13_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 13. + * Configures the write permission in region 13 in REE0 mode. */ #define HP_APM_REGION13_R0_W (BIT(1)) #define HP_APM_REGION13_R0_W_M (HP_APM_REGION13_R0_W_V << HP_APM_REGION13_R0_W_S) #define HP_APM_REGION13_R0_W_V 0x00000001U #define HP_APM_REGION13_R0_W_S 1 /** HP_APM_REGION13_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 13. + * Configures the read permission in region 13 in REE0 mode. */ #define HP_APM_REGION13_R0_R (BIT(2)) #define HP_APM_REGION13_R0_R_M (HP_APM_REGION13_R0_R_V << HP_APM_REGION13_R0_R_S) #define HP_APM_REGION13_R0_R_V 0x00000001U #define HP_APM_REGION13_R0_R_S 2 /** HP_APM_REGION13_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 13. + * Configures the execution permission in region 13 in REE1 mode. */ #define HP_APM_REGION13_R1_X (BIT(4)) #define HP_APM_REGION13_R1_X_M (HP_APM_REGION13_R1_X_V << HP_APM_REGION13_R1_X_S) #define HP_APM_REGION13_R1_X_V 0x00000001U #define HP_APM_REGION13_R1_X_S 4 /** HP_APM_REGION13_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 13. + * Configures the write permission in region 13 in REE1 mode. */ #define HP_APM_REGION13_R1_W (BIT(5)) #define HP_APM_REGION13_R1_W_M (HP_APM_REGION13_R1_W_V << HP_APM_REGION13_R1_W_S) #define HP_APM_REGION13_R1_W_V 0x00000001U #define HP_APM_REGION13_R1_W_S 5 /** HP_APM_REGION13_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 13. + * Configures the read permission in region 13 in REE1 mode. */ #define HP_APM_REGION13_R1_R (BIT(6)) #define HP_APM_REGION13_R1_R_M (HP_APM_REGION13_R1_R_V << HP_APM_REGION13_R1_R_S) #define HP_APM_REGION13_R1_R_V 0x00000001U #define HP_APM_REGION13_R1_R_S 6 /** HP_APM_REGION13_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 13. + * Configures the execution permission in region 13 in REE2 mode. */ #define HP_APM_REGION13_R2_X (BIT(8)) #define HP_APM_REGION13_R2_X_M (HP_APM_REGION13_R2_X_V << HP_APM_REGION13_R2_X_S) #define HP_APM_REGION13_R2_X_V 0x00000001U #define HP_APM_REGION13_R2_X_S 8 /** HP_APM_REGION13_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 13. + * Configures the write permission in region 13 in REE2 mode. */ #define HP_APM_REGION13_R2_W (BIT(9)) #define HP_APM_REGION13_R2_W_M (HP_APM_REGION13_R2_W_V << HP_APM_REGION13_R2_W_S) #define HP_APM_REGION13_R2_W_V 0x00000001U #define HP_APM_REGION13_R2_W_S 9 /** HP_APM_REGION13_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 13. + * Configures the read permission in region 13 in REE2 mode. */ #define HP_APM_REGION13_R2_R (BIT(10)) #define HP_APM_REGION13_R2_R_M (HP_APM_REGION13_R2_R_V << HP_APM_REGION13_R2_R_S) #define HP_APM_REGION13_R2_R_V 0x00000001U #define HP_APM_REGION13_R2_R_S 10 /** HP_APM_REGION13_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 13 configuration registers + * (HP_APM_REGION13_ADDR_START_REG, HP_APM_REGION13_ADDR_END_REG and + * HP_APM_REGION13_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION13_LOCK (BIT(11)) #define HP_APM_REGION13_LOCK_M (HP_APM_REGION13_LOCK_V << HP_APM_REGION13_LOCK_S) @@ -1416,7 +1472,7 @@ extern "C" { */ #define HP_APM_REGION14_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xac) /** HP_APM_REGION14_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 14. + * Configures the start address of region 14. */ #define HP_APM_REGION14_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION14_ADDR_START_M (HP_APM_REGION14_ADDR_START_V << HP_APM_REGION14_ADDR_START_S) @@ -1428,7 +1484,7 @@ extern "C" { */ #define HP_APM_REGION14_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xb0) /** HP_APM_REGION14_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 14. + * Configures the end address of region 14. */ #define HP_APM_REGION14_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION14_ADDR_END_M (HP_APM_REGION14_ADDR_END_V << HP_APM_REGION14_ADDR_END_S) @@ -1436,74 +1492,78 @@ extern "C" { #define HP_APM_REGION14_ADDR_END_S 0 /** HP_APM_REGION14_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION14_ATTR_REG (DR_REG_HP_APM_BASE + 0xb4) /** HP_APM_REGION14_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 14. + * Configures the execution permission in region 14 in REE0 mode. */ #define HP_APM_REGION14_R0_X (BIT(0)) #define HP_APM_REGION14_R0_X_M (HP_APM_REGION14_R0_X_V << HP_APM_REGION14_R0_X_S) #define HP_APM_REGION14_R0_X_V 0x00000001U #define HP_APM_REGION14_R0_X_S 0 /** HP_APM_REGION14_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 14. + * Configures the write permission in region 14 in REE0 mode. */ #define HP_APM_REGION14_R0_W (BIT(1)) #define HP_APM_REGION14_R0_W_M (HP_APM_REGION14_R0_W_V << HP_APM_REGION14_R0_W_S) #define HP_APM_REGION14_R0_W_V 0x00000001U #define HP_APM_REGION14_R0_W_S 1 /** HP_APM_REGION14_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 14. + * Configures the read permission in region 14 in REE0 mode. */ #define HP_APM_REGION14_R0_R (BIT(2)) #define HP_APM_REGION14_R0_R_M (HP_APM_REGION14_R0_R_V << HP_APM_REGION14_R0_R_S) #define HP_APM_REGION14_R0_R_V 0x00000001U #define HP_APM_REGION14_R0_R_S 2 /** HP_APM_REGION14_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 14. + * Configures the execution permission in region 14 in REE1 mode. */ #define HP_APM_REGION14_R1_X (BIT(4)) #define HP_APM_REGION14_R1_X_M (HP_APM_REGION14_R1_X_V << HP_APM_REGION14_R1_X_S) #define HP_APM_REGION14_R1_X_V 0x00000001U #define HP_APM_REGION14_R1_X_S 4 /** HP_APM_REGION14_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 14. + * Configures the write permission in region 14 in REE1 mode. */ #define HP_APM_REGION14_R1_W (BIT(5)) #define HP_APM_REGION14_R1_W_M (HP_APM_REGION14_R1_W_V << HP_APM_REGION14_R1_W_S) #define HP_APM_REGION14_R1_W_V 0x00000001U #define HP_APM_REGION14_R1_W_S 5 /** HP_APM_REGION14_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 14. + * Configures the read permission in region 14 in REE1 mode. */ #define HP_APM_REGION14_R1_R (BIT(6)) #define HP_APM_REGION14_R1_R_M (HP_APM_REGION14_R1_R_V << HP_APM_REGION14_R1_R_S) #define HP_APM_REGION14_R1_R_V 0x00000001U #define HP_APM_REGION14_R1_R_S 6 /** HP_APM_REGION14_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 14. + * Configures the execution permission in region 14 in REE2 mode. */ #define HP_APM_REGION14_R2_X (BIT(8)) #define HP_APM_REGION14_R2_X_M (HP_APM_REGION14_R2_X_V << HP_APM_REGION14_R2_X_S) #define HP_APM_REGION14_R2_X_V 0x00000001U #define HP_APM_REGION14_R2_X_S 8 /** HP_APM_REGION14_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 14. + * Configures the write permission in region 14 in REE2 mode. */ #define HP_APM_REGION14_R2_W (BIT(9)) #define HP_APM_REGION14_R2_W_M (HP_APM_REGION14_R2_W_V << HP_APM_REGION14_R2_W_S) #define HP_APM_REGION14_R2_W_V 0x00000001U #define HP_APM_REGION14_R2_W_S 9 /** HP_APM_REGION14_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 14. + * Configures the read permission in region 14 in REE2 mode. */ #define HP_APM_REGION14_R2_R (BIT(10)) #define HP_APM_REGION14_R2_R_M (HP_APM_REGION14_R2_R_V << HP_APM_REGION14_R2_R_S) #define HP_APM_REGION14_R2_R_V 0x00000001U #define HP_APM_REGION14_R2_R_S 10 /** HP_APM_REGION14_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 14 configuration registers + * (HP_APM_REGION14_ADDR_START_REG, HP_APM_REGION14_ADDR_END_REG and + * HP_APM_REGION14_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION14_LOCK (BIT(11)) #define HP_APM_REGION14_LOCK_M (HP_APM_REGION14_LOCK_V << HP_APM_REGION14_LOCK_S) @@ -1515,7 +1575,7 @@ extern "C" { */ #define HP_APM_REGION15_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xb8) /** HP_APM_REGION15_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 15. + * Configures the start address of region 15. */ #define HP_APM_REGION15_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION15_ADDR_START_M (HP_APM_REGION15_ADDR_START_V << HP_APM_REGION15_ADDR_START_S) @@ -1527,7 +1587,7 @@ extern "C" { */ #define HP_APM_REGION15_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xbc) /** HP_APM_REGION15_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 15. + * Configures the end address of region 15. */ #define HP_APM_REGION15_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION15_ADDR_END_M (HP_APM_REGION15_ADDR_END_V << HP_APM_REGION15_ADDR_END_S) @@ -1535,74 +1595,78 @@ extern "C" { #define HP_APM_REGION15_ADDR_END_S 0 /** HP_APM_REGION15_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION15_ATTR_REG (DR_REG_HP_APM_BASE + 0xc0) /** HP_APM_REGION15_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 15. + * Configures the execution permission in region 15 in REE0 mode. */ #define HP_APM_REGION15_R0_X (BIT(0)) #define HP_APM_REGION15_R0_X_M (HP_APM_REGION15_R0_X_V << HP_APM_REGION15_R0_X_S) #define HP_APM_REGION15_R0_X_V 0x00000001U #define HP_APM_REGION15_R0_X_S 0 /** HP_APM_REGION15_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 15. + * Configures the write permission in region 15 in REE0 mode. */ #define HP_APM_REGION15_R0_W (BIT(1)) #define HP_APM_REGION15_R0_W_M (HP_APM_REGION15_R0_W_V << HP_APM_REGION15_R0_W_S) #define HP_APM_REGION15_R0_W_V 0x00000001U #define HP_APM_REGION15_R0_W_S 1 /** HP_APM_REGION15_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 15. + * Configures the read permission in region 15 in REE0 mode. */ #define HP_APM_REGION15_R0_R (BIT(2)) #define HP_APM_REGION15_R0_R_M (HP_APM_REGION15_R0_R_V << HP_APM_REGION15_R0_R_S) #define HP_APM_REGION15_R0_R_V 0x00000001U #define HP_APM_REGION15_R0_R_S 2 /** HP_APM_REGION15_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 15. + * Configures the execution permission in region 15 in REE1 mode. */ #define HP_APM_REGION15_R1_X (BIT(4)) #define HP_APM_REGION15_R1_X_M (HP_APM_REGION15_R1_X_V << HP_APM_REGION15_R1_X_S) #define HP_APM_REGION15_R1_X_V 0x00000001U #define HP_APM_REGION15_R1_X_S 4 /** HP_APM_REGION15_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 15. + * Configures the write permission in region 15 in REE1 mode. */ #define HP_APM_REGION15_R1_W (BIT(5)) #define HP_APM_REGION15_R1_W_M (HP_APM_REGION15_R1_W_V << HP_APM_REGION15_R1_W_S) #define HP_APM_REGION15_R1_W_V 0x00000001U #define HP_APM_REGION15_R1_W_S 5 /** HP_APM_REGION15_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 15. + * Configures the read permission in region 15 in REE1 mode. */ #define HP_APM_REGION15_R1_R (BIT(6)) #define HP_APM_REGION15_R1_R_M (HP_APM_REGION15_R1_R_V << HP_APM_REGION15_R1_R_S) #define HP_APM_REGION15_R1_R_V 0x00000001U #define HP_APM_REGION15_R1_R_S 6 /** HP_APM_REGION15_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 15. + * Configures the execution permission in region 15 in REE2 mode. */ #define HP_APM_REGION15_R2_X (BIT(8)) #define HP_APM_REGION15_R2_X_M (HP_APM_REGION15_R2_X_V << HP_APM_REGION15_R2_X_S) #define HP_APM_REGION15_R2_X_V 0x00000001U #define HP_APM_REGION15_R2_X_S 8 /** HP_APM_REGION15_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 15. + * Configures the write permission in region 15 in REE2 mode. */ #define HP_APM_REGION15_R2_W (BIT(9)) #define HP_APM_REGION15_R2_W_M (HP_APM_REGION15_R2_W_V << HP_APM_REGION15_R2_W_S) #define HP_APM_REGION15_R2_W_V 0x00000001U #define HP_APM_REGION15_R2_W_S 9 /** HP_APM_REGION15_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 15. + * Configures the read permission in region 15 in REE2 mode. */ #define HP_APM_REGION15_R2_R (BIT(10)) #define HP_APM_REGION15_R2_R_M (HP_APM_REGION15_R2_R_V << HP_APM_REGION15_R2_R_S) #define HP_APM_REGION15_R2_R_V 0x00000001U #define HP_APM_REGION15_R2_R_S 10 /** HP_APM_REGION15_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 15 configuration registers + * (HP_APM_REGION15_ADDR_START_REG, HP_APM_REGION15_ADDR_END_REG and + * HP_APM_REGION15_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION15_LOCK (BIT(11)) #define HP_APM_REGION15_LOCK_M (HP_APM_REGION15_LOCK_V << HP_APM_REGION15_LOCK_S) @@ -1610,39 +1674,39 @@ extern "C" { #define HP_APM_REGION15_LOCK_S 11 /** HP_APM_FUNC_CTRL_REG register - * APM function control register + * APM access path permission management register */ #define HP_APM_FUNC_CTRL_REG (DR_REG_HP_APM_BASE + 0xc4) /** HP_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures to enable permission management for HP_APM_CTRL M0. */ #define HP_APM_M0_FUNC_EN (BIT(0)) #define HP_APM_M0_FUNC_EN_M (HP_APM_M0_FUNC_EN_V << HP_APM_M0_FUNC_EN_S) #define HP_APM_M0_FUNC_EN_V 0x00000001U #define HP_APM_M0_FUNC_EN_S 0 /** HP_APM_M1_FUNC_EN : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable + * Configures to enable permission management for HP_APM_CTRL M1. */ #define HP_APM_M1_FUNC_EN (BIT(1)) #define HP_APM_M1_FUNC_EN_M (HP_APM_M1_FUNC_EN_V << HP_APM_M1_FUNC_EN_S) #define HP_APM_M1_FUNC_EN_V 0x00000001U #define HP_APM_M1_FUNC_EN_S 1 /** HP_APM_M2_FUNC_EN : R/W; bitpos: [2]; default: 1; - * PMS M2 function enable + * Configures to enable permission management for HP_APM_CTRL M2. */ #define HP_APM_M2_FUNC_EN (BIT(2)) #define HP_APM_M2_FUNC_EN_M (HP_APM_M2_FUNC_EN_V << HP_APM_M2_FUNC_EN_S) #define HP_APM_M2_FUNC_EN_V 0x00000001U #define HP_APM_M2_FUNC_EN_S 2 /** HP_APM_M3_FUNC_EN : R/W; bitpos: [3]; default: 1; - * PMS M3 function enable + * Configures to enable permission management for HP_APM_CTRL M3. */ #define HP_APM_M3_FUNC_EN (BIT(3)) #define HP_APM_M3_FUNC_EN_M (HP_APM_M3_FUNC_EN_V << HP_APM_M3_FUNC_EN_S) #define HP_APM_M3_FUNC_EN_V 0x00000001U #define HP_APM_M3_FUNC_EN_S 3 /** HP_APM_M4_FUNC_EN : R/W; bitpos: [4]; default: 1; - * PMS M4 function enable + * Configures to enable permission management for HP_APM_CTRL M4. */ #define HP_APM_M4_FUNC_EN (BIT(4)) #define HP_APM_M4_FUNC_EN_M (HP_APM_M4_FUNC_EN_V << HP_APM_M4_FUNC_EN_S) @@ -1650,13 +1714,13 @@ extern "C" { #define HP_APM_M4_FUNC_EN_S 4 /** HP_APM_M0_STATUS_REG register - * M0 status register + * HP_APM_CTRL M0 status register */ #define HP_APM_M0_STATUS_REG (DR_REG_HP_APM_BASE + 0xc8) /** HP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define HP_APM_M0_EXCEPTION_STATUS 0x00000003U #define HP_APM_M0_EXCEPTION_STATUS_M (HP_APM_M0_EXCEPTION_STATUS_V << HP_APM_M0_EXCEPTION_STATUS_S) @@ -1664,7 +1728,7 @@ extern "C" { #define HP_APM_M0_EXCEPTION_STATUS_S 0 /** HP_APM_M0_STATUS_CLR_REG register - * M0 status clear register + * HP_APM_CTRL M0 status clear register */ #define HP_APM_M0_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xcc) /** HP_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -1676,25 +1740,25 @@ extern "C" { #define HP_APM_M0_EXCEPTION_STATUS_CLR_S 0 /** HP_APM_M0_EXCEPTION_INFO0_REG register - * M0 exception_info0 register + * HP_APM_CTRL M0 exception information register */ #define HP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xd0) /** HP_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define HP_APM_M0_EXCEPTION_REGION 0x0000FFFFU #define HP_APM_M0_EXCEPTION_REGION_M (HP_APM_M0_EXCEPTION_REGION_V << HP_APM_M0_EXCEPTION_REGION_S) #define HP_APM_M0_EXCEPTION_REGION_V 0x0000FFFFU #define HP_APM_M0_EXCEPTION_REGION_S 0 /** HP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define HP_APM_M0_EXCEPTION_MODE 0x00000003U #define HP_APM_M0_EXCEPTION_MODE_M (HP_APM_M0_EXCEPTION_MODE_V << HP_APM_M0_EXCEPTION_MODE_S) #define HP_APM_M0_EXCEPTION_MODE_V 0x00000003U #define HP_APM_M0_EXCEPTION_MODE_S 16 /** HP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define HP_APM_M0_EXCEPTION_ID 0x0000001FU #define HP_APM_M0_EXCEPTION_ID_M (HP_APM_M0_EXCEPTION_ID_V << HP_APM_M0_EXCEPTION_ID_S) @@ -1702,11 +1766,11 @@ extern "C" { #define HP_APM_M0_EXCEPTION_ID_S 18 /** HP_APM_M0_EXCEPTION_INFO1_REG register - * M0 exception_info1 register + * HP_APM_CTRL M0 exception information register */ #define HP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xd4) /** HP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define HP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU #define HP_APM_M0_EXCEPTION_ADDR_M (HP_APM_M0_EXCEPTION_ADDR_V << HP_APM_M0_EXCEPTION_ADDR_S) @@ -1714,13 +1778,13 @@ extern "C" { #define HP_APM_M0_EXCEPTION_ADDR_S 0 /** HP_APM_M1_STATUS_REG register - * M1 status register + * HP_APM_CTRL M1 status register */ #define HP_APM_M1_STATUS_REG (DR_REG_HP_APM_BASE + 0xd8) /** HP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define HP_APM_M1_EXCEPTION_STATUS 0x00000003U #define HP_APM_M1_EXCEPTION_STATUS_M (HP_APM_M1_EXCEPTION_STATUS_V << HP_APM_M1_EXCEPTION_STATUS_S) @@ -1728,7 +1792,7 @@ extern "C" { #define HP_APM_M1_EXCEPTION_STATUS_S 0 /** HP_APM_M1_STATUS_CLR_REG register - * M1 status clear register + * HP_APM_CTRL M1 status clear register */ #define HP_APM_M1_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xdc) /** HP_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -1740,25 +1804,25 @@ extern "C" { #define HP_APM_M1_EXCEPTION_STATUS_CLR_S 0 /** HP_APM_M1_EXCEPTION_INFO0_REG register - * M1 exception_info0 register + * HP_APM_CTRL M1 exception information register */ #define HP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xe0) /** HP_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define HP_APM_M1_EXCEPTION_REGION 0x0000FFFFU #define HP_APM_M1_EXCEPTION_REGION_M (HP_APM_M1_EXCEPTION_REGION_V << HP_APM_M1_EXCEPTION_REGION_S) #define HP_APM_M1_EXCEPTION_REGION_V 0x0000FFFFU #define HP_APM_M1_EXCEPTION_REGION_S 0 /** HP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define HP_APM_M1_EXCEPTION_MODE 0x00000003U #define HP_APM_M1_EXCEPTION_MODE_M (HP_APM_M1_EXCEPTION_MODE_V << HP_APM_M1_EXCEPTION_MODE_S) #define HP_APM_M1_EXCEPTION_MODE_V 0x00000003U #define HP_APM_M1_EXCEPTION_MODE_S 16 /** HP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define HP_APM_M1_EXCEPTION_ID 0x0000001FU #define HP_APM_M1_EXCEPTION_ID_M (HP_APM_M1_EXCEPTION_ID_V << HP_APM_M1_EXCEPTION_ID_S) @@ -1766,11 +1830,11 @@ extern "C" { #define HP_APM_M1_EXCEPTION_ID_S 18 /** HP_APM_M1_EXCEPTION_INFO1_REG register - * M1 exception_info1 register + * HP_APM_CTRL M1 exception information register */ #define HP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xe4) /** HP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define HP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU #define HP_APM_M1_EXCEPTION_ADDR_M (HP_APM_M1_EXCEPTION_ADDR_V << HP_APM_M1_EXCEPTION_ADDR_S) @@ -1778,13 +1842,13 @@ extern "C" { #define HP_APM_M1_EXCEPTION_ADDR_S 0 /** HP_APM_M2_STATUS_REG register - * M2 status register + * HP_APM_CTRL M2 status register */ #define HP_APM_M2_STATUS_REG (DR_REG_HP_APM_BASE + 0xe8) /** HP_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define HP_APM_M2_EXCEPTION_STATUS 0x00000003U #define HP_APM_M2_EXCEPTION_STATUS_M (HP_APM_M2_EXCEPTION_STATUS_V << HP_APM_M2_EXCEPTION_STATUS_S) @@ -1792,7 +1856,7 @@ extern "C" { #define HP_APM_M2_EXCEPTION_STATUS_S 0 /** HP_APM_M2_STATUS_CLR_REG register - * M2 status clear register + * HP_APM_CTRL M2 status clear register */ #define HP_APM_M2_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xec) /** HP_APM_M2_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -1804,25 +1868,25 @@ extern "C" { #define HP_APM_M2_EXCEPTION_STATUS_CLR_S 0 /** HP_APM_M2_EXCEPTION_INFO0_REG register - * M2 exception_info0 register + * HP_APM_CTRL M2 exception information register */ #define HP_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xf0) /** HP_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define HP_APM_M2_EXCEPTION_REGION 0x0000FFFFU #define HP_APM_M2_EXCEPTION_REGION_M (HP_APM_M2_EXCEPTION_REGION_V << HP_APM_M2_EXCEPTION_REGION_S) #define HP_APM_M2_EXCEPTION_REGION_V 0x0000FFFFU #define HP_APM_M2_EXCEPTION_REGION_S 0 /** HP_APM_M2_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define HP_APM_M2_EXCEPTION_MODE 0x00000003U #define HP_APM_M2_EXCEPTION_MODE_M (HP_APM_M2_EXCEPTION_MODE_V << HP_APM_M2_EXCEPTION_MODE_S) #define HP_APM_M2_EXCEPTION_MODE_V 0x00000003U #define HP_APM_M2_EXCEPTION_MODE_S 16 /** HP_APM_M2_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define HP_APM_M2_EXCEPTION_ID 0x0000001FU #define HP_APM_M2_EXCEPTION_ID_M (HP_APM_M2_EXCEPTION_ID_V << HP_APM_M2_EXCEPTION_ID_S) @@ -1830,11 +1894,11 @@ extern "C" { #define HP_APM_M2_EXCEPTION_ID_S 18 /** HP_APM_M2_EXCEPTION_INFO1_REG register - * M2 exception_info1 register + * HP_APM_CTRL M2 exception information register */ #define HP_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xf4) /** HP_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define HP_APM_M2_EXCEPTION_ADDR 0xFFFFFFFFU #define HP_APM_M2_EXCEPTION_ADDR_M (HP_APM_M2_EXCEPTION_ADDR_V << HP_APM_M2_EXCEPTION_ADDR_S) @@ -1842,13 +1906,13 @@ extern "C" { #define HP_APM_M2_EXCEPTION_ADDR_S 0 /** HP_APM_M3_STATUS_REG register - * M3 status register + * HP_APM_CTRL M3 status register */ #define HP_APM_M3_STATUS_REG (DR_REG_HP_APM_BASE + 0xf8) /** HP_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define HP_APM_M3_EXCEPTION_STATUS 0x00000003U #define HP_APM_M3_EXCEPTION_STATUS_M (HP_APM_M3_EXCEPTION_STATUS_V << HP_APM_M3_EXCEPTION_STATUS_S) @@ -1856,7 +1920,7 @@ extern "C" { #define HP_APM_M3_EXCEPTION_STATUS_S 0 /** HP_APM_M3_STATUS_CLR_REG register - * M3 status clear register + * HP_APM_CTRL M3 status clear register */ #define HP_APM_M3_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xfc) /** HP_APM_M3_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -1868,25 +1932,25 @@ extern "C" { #define HP_APM_M3_EXCEPTION_STATUS_CLR_S 0 /** HP_APM_M3_EXCEPTION_INFO0_REG register - * M3 exception_info0 register + * HP_APM_CTRL M3 exception information register */ #define HP_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x100) /** HP_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define HP_APM_M3_EXCEPTION_REGION 0x0000FFFFU #define HP_APM_M3_EXCEPTION_REGION_M (HP_APM_M3_EXCEPTION_REGION_V << HP_APM_M3_EXCEPTION_REGION_S) #define HP_APM_M3_EXCEPTION_REGION_V 0x0000FFFFU #define HP_APM_M3_EXCEPTION_REGION_S 0 /** HP_APM_M3_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define HP_APM_M3_EXCEPTION_MODE 0x00000003U #define HP_APM_M3_EXCEPTION_MODE_M (HP_APM_M3_EXCEPTION_MODE_V << HP_APM_M3_EXCEPTION_MODE_S) #define HP_APM_M3_EXCEPTION_MODE_V 0x00000003U #define HP_APM_M3_EXCEPTION_MODE_S 16 /** HP_APM_M3_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define HP_APM_M3_EXCEPTION_ID 0x0000001FU #define HP_APM_M3_EXCEPTION_ID_M (HP_APM_M3_EXCEPTION_ID_V << HP_APM_M3_EXCEPTION_ID_S) @@ -1894,11 +1958,11 @@ extern "C" { #define HP_APM_M3_EXCEPTION_ID_S 18 /** HP_APM_M3_EXCEPTION_INFO1_REG register - * M3 exception_info1 register + * HP_APM_CTRL M3 exception information register */ #define HP_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x104) /** HP_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define HP_APM_M3_EXCEPTION_ADDR 0xFFFFFFFFU #define HP_APM_M3_EXCEPTION_ADDR_M (HP_APM_M3_EXCEPTION_ADDR_V << HP_APM_M3_EXCEPTION_ADDR_S) @@ -1906,13 +1970,13 @@ extern "C" { #define HP_APM_M3_EXCEPTION_ADDR_S 0 /** HP_APM_M4_STATUS_REG register - * M4 status register + * HP_APM_CTRL M4 status register */ #define HP_APM_M4_STATUS_REG (DR_REG_HP_APM_BASE + 0x108) /** HP_APM_M4_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define HP_APM_M4_EXCEPTION_STATUS 0x00000003U #define HP_APM_M4_EXCEPTION_STATUS_M (HP_APM_M4_EXCEPTION_STATUS_V << HP_APM_M4_EXCEPTION_STATUS_S) @@ -1920,7 +1984,7 @@ extern "C" { #define HP_APM_M4_EXCEPTION_STATUS_S 0 /** HP_APM_M4_STATUS_CLR_REG register - * M4 status clear register + * HP_APM_CTRL M4 status clear register */ #define HP_APM_M4_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0x10c) /** HP_APM_M4_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -1932,25 +1996,25 @@ extern "C" { #define HP_APM_M4_EXCEPTION_STATUS_CLR_S 0 /** HP_APM_M4_EXCEPTION_INFO0_REG register - * M4 exception_info0 register + * HP_APM_CTRL M4 exception information register */ #define HP_APM_M4_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x110) /** HP_APM_M4_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define HP_APM_M4_EXCEPTION_REGION 0x0000FFFFU #define HP_APM_M4_EXCEPTION_REGION_M (HP_APM_M4_EXCEPTION_REGION_V << HP_APM_M4_EXCEPTION_REGION_S) #define HP_APM_M4_EXCEPTION_REGION_V 0x0000FFFFU #define HP_APM_M4_EXCEPTION_REGION_S 0 /** HP_APM_M4_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define HP_APM_M4_EXCEPTION_MODE 0x00000003U #define HP_APM_M4_EXCEPTION_MODE_M (HP_APM_M4_EXCEPTION_MODE_V << HP_APM_M4_EXCEPTION_MODE_S) #define HP_APM_M4_EXCEPTION_MODE_V 0x00000003U #define HP_APM_M4_EXCEPTION_MODE_S 16 /** HP_APM_M4_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define HP_APM_M4_EXCEPTION_ID 0x0000001FU #define HP_APM_M4_EXCEPTION_ID_M (HP_APM_M4_EXCEPTION_ID_V << HP_APM_M4_EXCEPTION_ID_S) @@ -1958,11 +2022,11 @@ extern "C" { #define HP_APM_M4_EXCEPTION_ID_S 18 /** HP_APM_M4_EXCEPTION_INFO1_REG register - * M4 exception_info1 register + * HP_APM_CTRL M4 exception information register */ #define HP_APM_M4_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x114) /** HP_APM_M4_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define HP_APM_M4_EXCEPTION_ADDR 0xFFFFFFFFU #define HP_APM_M4_EXCEPTION_ADDR_M (HP_APM_M4_EXCEPTION_ADDR_V << HP_APM_M4_EXCEPTION_ADDR_S) @@ -1970,49 +2034,49 @@ extern "C" { #define HP_APM_M4_EXCEPTION_ADDR_S 0 /** HP_APM_INT_EN_REG register - * APM interrupt enable register + * HP_APM_CTRL M0/1/2/3/4 interrupt enable register */ #define HP_APM_INT_EN_REG (DR_REG_HP_APM_BASE + 0x118) /** HP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; - * Configures to enable APM M0 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ #define HP_APM_M0_APM_INT_EN (BIT(0)) #define HP_APM_M0_APM_INT_EN_M (HP_APM_M0_APM_INT_EN_V << HP_APM_M0_APM_INT_EN_S) #define HP_APM_M0_APM_INT_EN_V 0x00000001U #define HP_APM_M0_APM_INT_EN_S 0 /** HP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; - * Configures to enable APM M1 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M1 interrupt. + * 0: Disable + * 1: Enable */ #define HP_APM_M1_APM_INT_EN (BIT(1)) #define HP_APM_M1_APM_INT_EN_M (HP_APM_M1_APM_INT_EN_V << HP_APM_M1_APM_INT_EN_S) #define HP_APM_M1_APM_INT_EN_V 0x00000001U #define HP_APM_M1_APM_INT_EN_S 1 /** HP_APM_M2_APM_INT_EN : R/W; bitpos: [2]; default: 0; - * Configures to enable APM M2 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M2 interrupt. + * 0: Disable + * 1: Enable */ #define HP_APM_M2_APM_INT_EN (BIT(2)) #define HP_APM_M2_APM_INT_EN_M (HP_APM_M2_APM_INT_EN_V << HP_APM_M2_APM_INT_EN_S) #define HP_APM_M2_APM_INT_EN_V 0x00000001U #define HP_APM_M2_APM_INT_EN_S 2 /** HP_APM_M3_APM_INT_EN : R/W; bitpos: [3]; default: 0; - * Configures to enable APM M3 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M3 interrupt. + * 0: Disable + * 1: Enable */ #define HP_APM_M3_APM_INT_EN (BIT(3)) #define HP_APM_M3_APM_INT_EN_M (HP_APM_M3_APM_INT_EN_V << HP_APM_M3_APM_INT_EN_S) #define HP_APM_M3_APM_INT_EN_V 0x00000001U #define HP_APM_M3_APM_INT_EN_S 3 /** HP_APM_M4_APM_INT_EN : R/W; bitpos: [4]; default: 0; - * Configures to enable APM M4 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M4 interrupt. + * 0: Disable + * 1: Enable */ #define HP_APM_M4_APM_INT_EN (BIT(4)) #define HP_APM_M4_APM_INT_EN_M (HP_APM_M4_APM_INT_EN_V << HP_APM_M4_APM_INT_EN_S) @@ -2024,9 +2088,9 @@ extern "C" { */ #define HP_APM_CLOCK_GATE_REG (DR_REG_HP_APM_BASE + 0x7f8) /** HP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; - * Configures whether to keep the clock always on.\\ - * 0: enable automatic clock gating \\ - * 1: keep the clock always on \\ + * Configures whether to keep the clock always on. + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ #define HP_APM_CLK_EN (BIT(0)) #define HP_APM_CLK_EN_M (HP_APM_CLK_EN_V << HP_APM_CLK_EN_S) diff --git a/components/soc/esp32c5/register/soc/hp_apm_struct.h b/components/soc/esp32c5/register/soc/hp_apm_struct.h index 87648ad8c3..0f3335eb0c 100644 --- a/components/soc/esp32c5/register/soc/hp_apm_struct.h +++ b/components/soc/esp32c5/register/soc/hp_apm_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,16 +10,16 @@ extern "C" { #endif -/** Group: Region filter enable register */ +/** Group: Configuration Registers */ /** Type of region_filter_en register - * Region filter enable register + * Region enable register */ typedef union { struct { /** region_filter_en : R/W; bitpos: [15:0]; default: 1; - * Configure bit $n (0-15) to enable region $n.\\ - * 0: disable \\ - * 1: enable \\ + * Configure bit $n (0-15) to enable region $n (0-15). + * 0: Disable + * 1: Enable */ uint32_t region_filter_en:16; uint32_t reserved_16:16; @@ -27,15 +27,13 @@ typedef union { uint32_t val; } hp_apm_region_filter_en_reg_t; - -/** Group: Region address register */ /** Type of regionn_addr_start register * Region address register */ typedef union { struct { /** regionn_addr_start : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region n. + * Configures the start address of region n. */ uint32_t regionn_addr_start:32; }; @@ -48,60 +46,62 @@ typedef union { typedef union { struct { /** regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region n. + * Configures the end address of region n. */ uint32_t regionn_addr_end:32; }; uint32_t val; } hp_apm_regionn_addr_end_reg_t; - -/** Group: Region access authority attribute register */ /** Type of regionn_attr register - * Region access authority attribute register + * Region access permissions configuration register */ typedef union { struct { /** regionn_r0_x : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region n. + * Configures the execution permission in region n in REE0 mode. */ uint32_t regionn_r0_x:1; /** regionn_r0_w : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region n. + * Configures the write permission in region n in REE0 mode. */ uint32_t regionn_r0_w:1; /** regionn_r0_r : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region n. + * Configures the read permission in region n in REE0 mode. */ uint32_t regionn_r0_r:1; uint32_t reserved_3:1; /** regionn_r1_x : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region n. + * Configures the execution permission in region n in REE1 mode. */ uint32_t regionn_r1_x:1; /** regionn_r1_w : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region n. + * Configures the write permission in region n in REE1 mode. */ uint32_t regionn_r1_w:1; /** regionn_r1_r : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region n. + * Configures the read permission in region n in REE1 mode. */ uint32_t regionn_r1_r:1; uint32_t reserved_7:1; /** regionn_r2_x : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region n. + * Configures the execution permission in region n in REE2 mode. */ uint32_t regionn_r2_x:1; /** regionn_r2_w : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region n. + * Configures the write permission in region n in REE2 mode. */ uint32_t regionn_r2_w:1; /** regionn_r2_r : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region n. + * Configures the read permission in region n in REE2 mode. */ uint32_t regionn_r2_r:1; /** regionn_lock : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region n configuration registers + * (HP_APM_REGIONn_ADDR_START_REG, HP_APM_REGIONn_ADDR_END_REG and + * HP_APM_REGIONn_ATTR_REG). + * 0: Do not lock + * 1: Lock */ uint32_t regionn_lock:1; uint32_t reserved_12:20; @@ -109,31 +109,29 @@ typedef union { uint32_t val; } hp_apm_regionn_attr_reg_t; - -/** Group: function control register */ /** Type of func_ctrl register - * APM function control register + * APM access path permission management register */ typedef union { struct { /** m0_func_en : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures to enable permission management for HP_APM_CTRL M0. */ uint32_t m0_func_en:1; /** m1_func_en : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable + * Configures to enable permission management for HP_APM_CTRL M1. */ uint32_t m1_func_en:1; /** m2_func_en : R/W; bitpos: [2]; default: 1; - * PMS M2 function enable + * Configures to enable permission management for HP_APM_CTRL M2. */ uint32_t m2_func_en:1; /** m3_func_en : R/W; bitpos: [3]; default: 1; - * PMS M3 function enable + * Configures to enable permission management for HP_APM_CTRL M3. */ uint32_t m3_func_en:1; /** m4_func_en : R/W; bitpos: [4]; default: 1; - * PMS M4 function enable + * Configures to enable permission management for HP_APM_CTRL M4. */ uint32_t m4_func_en:1; uint32_t reserved_5:27; @@ -142,16 +140,16 @@ typedef union { } hp_apm_func_ctrl_reg_t; -/** Group: M0 status register */ +/** Group: Status Registers */ /** Type of m0_status register - * M0 status register + * HP_APM_CTRL M0 status register */ typedef union { struct { /** m0_exception_status : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m0_exception_status:2; uint32_t reserved_2:30; @@ -159,10 +157,8 @@ typedef union { uint32_t val; } hp_apm_m0_status_reg_t; - -/** Group: M0 status clear register */ /** Type of m0_status_clr register - * M0 status clear register + * HP_APM_CTRL M0 status clear register */ typedef union { struct { @@ -175,23 +171,21 @@ typedef union { uint32_t val; } hp_apm_m0_status_clr_reg_t; - -/** Group: M0 exception_info0 register */ /** Type of m0_exception_info0 register - * M0 exception_info0 register + * HP_APM_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m0_exception_region:16; /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m0_exception_mode:2; /** m0_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m0_exception_id:5; uint32_t reserved_23:9; @@ -199,32 +193,28 @@ typedef union { uint32_t val; } hp_apm_m0_exception_info0_reg_t; - -/** Group: M0 exception_info1 register */ /** Type of m0_exception_info1 register - * M0 exception_info1 register + * HP_APM_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m0_exception_addr:32; }; uint32_t val; } hp_apm_m0_exception_info1_reg_t; - -/** Group: M1 status register */ /** Type of m1_status register - * M1 status register + * HP_APM_CTRL M1 status register */ typedef union { struct { /** m1_exception_status : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m1_exception_status:2; uint32_t reserved_2:30; @@ -232,10 +222,8 @@ typedef union { uint32_t val; } hp_apm_m1_status_reg_t; - -/** Group: M1 status clear register */ /** Type of m1_status_clr register - * M1 status clear register + * HP_APM_CTRL M1 status clear register */ typedef union { struct { @@ -248,23 +236,21 @@ typedef union { uint32_t val; } hp_apm_m1_status_clr_reg_t; - -/** Group: M1 exception_info0 register */ /** Type of m1_exception_info0 register - * M1 exception_info0 register + * HP_APM_CTRL M1 exception information register */ typedef union { struct { /** m1_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m1_exception_region:16; /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m1_exception_mode:2; /** m1_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m1_exception_id:5; uint32_t reserved_23:9; @@ -272,32 +258,28 @@ typedef union { uint32_t val; } hp_apm_m1_exception_info0_reg_t; - -/** Group: M1 exception_info1 register */ /** Type of m1_exception_info1 register - * M1 exception_info1 register + * HP_APM_CTRL M1 exception information register */ typedef union { struct { /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m1_exception_addr:32; }; uint32_t val; } hp_apm_m1_exception_info1_reg_t; - -/** Group: M2 status register */ /** Type of m2_status register - * M2 status register + * HP_APM_CTRL M2 status register */ typedef union { struct { /** m2_exception_status : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m2_exception_status:2; uint32_t reserved_2:30; @@ -305,10 +287,8 @@ typedef union { uint32_t val; } hp_apm_m2_status_reg_t; - -/** Group: M2 status clear register */ /** Type of m2_status_clr register - * M2 status clear register + * HP_APM_CTRL M2 status clear register */ typedef union { struct { @@ -321,23 +301,21 @@ typedef union { uint32_t val; } hp_apm_m2_status_clr_reg_t; - -/** Group: M2 exception_info0 register */ /** Type of m2_exception_info0 register - * M2 exception_info0 register + * HP_APM_CTRL M2 exception information register */ typedef union { struct { /** m2_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m2_exception_region:16; /** m2_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m2_exception_mode:2; /** m2_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m2_exception_id:5; uint32_t reserved_23:9; @@ -345,32 +323,28 @@ typedef union { uint32_t val; } hp_apm_m2_exception_info0_reg_t; - -/** Group: M2 exception_info1 register */ /** Type of m2_exception_info1 register - * M2 exception_info1 register + * HP_APM_CTRL M2 exception information register */ typedef union { struct { /** m2_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m2_exception_addr:32; }; uint32_t val; } hp_apm_m2_exception_info1_reg_t; - -/** Group: M3 status register */ /** Type of m3_status register - * M3 status register + * HP_APM_CTRL M3 status register */ typedef union { struct { /** m3_exception_status : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m3_exception_status:2; uint32_t reserved_2:30; @@ -378,10 +352,8 @@ typedef union { uint32_t val; } hp_apm_m3_status_reg_t; - -/** Group: M3 status clear register */ /** Type of m3_status_clr register - * M3 status clear register + * HP_APM_CTRL M3 status clear register */ typedef union { struct { @@ -394,23 +366,21 @@ typedef union { uint32_t val; } hp_apm_m3_status_clr_reg_t; - -/** Group: M3 exception_info0 register */ /** Type of m3_exception_info0 register - * M3 exception_info0 register + * HP_APM_CTRL M3 exception information register */ typedef union { struct { /** m3_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m3_exception_region:16; /** m3_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m3_exception_mode:2; /** m3_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m3_exception_id:5; uint32_t reserved_23:9; @@ -418,32 +388,28 @@ typedef union { uint32_t val; } hp_apm_m3_exception_info0_reg_t; - -/** Group: M3 exception_info1 register */ /** Type of m3_exception_info1 register - * M3 exception_info1 register + * HP_APM_CTRL M3 exception information register */ typedef union { struct { /** m3_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m3_exception_addr:32; }; uint32_t val; } hp_apm_m3_exception_info1_reg_t; - -/** Group: M4 status register */ /** Type of m4_status register - * M4 status register + * HP_APM_CTRL M4 status register */ typedef union { struct { /** m4_exception_status : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m4_exception_status:2; uint32_t reserved_2:30; @@ -451,10 +417,8 @@ typedef union { uint32_t val; } hp_apm_m4_status_reg_t; - -/** Group: M4 status clear register */ /** Type of m4_status_clr register - * M4 status clear register + * HP_APM_CTRL M4 status clear register */ typedef union { struct { @@ -467,23 +431,21 @@ typedef union { uint32_t val; } hp_apm_m4_status_clr_reg_t; - -/** Group: M4 exception_info0 register */ /** Type of m4_exception_info0 register - * M4 exception_info0 register + * HP_APM_CTRL M4 exception information register */ typedef union { struct { /** m4_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m4_exception_region:16; /** m4_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m4_exception_mode:2; /** m4_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m4_exception_id:5; uint32_t reserved_23:9; @@ -491,15 +453,13 @@ typedef union { uint32_t val; } hp_apm_m4_exception_info0_reg_t; - -/** Group: M4 exception_info1 register */ /** Type of m4_exception_info1 register - * M4 exception_info1 register + * HP_APM_CTRL M4 exception information register */ typedef union { struct { /** m4_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m4_exception_addr:32; }; @@ -507,40 +467,40 @@ typedef union { } hp_apm_m4_exception_info1_reg_t; -/** Group: APM interrupt enable register */ +/** Group: Interrupt Registers */ /** Type of int_en register - * APM interrupt enable register + * HP_APM_CTRL M0/1/2/3/4 interrupt enable register */ typedef union { struct { /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; - * Configures to enable APM M0 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m0_apm_int_en:1; /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; - * Configures to enable APM M1 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M1 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m1_apm_int_en:1; /** m2_apm_int_en : R/W; bitpos: [2]; default: 0; - * Configures to enable APM M2 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M2 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m2_apm_int_en:1; /** m3_apm_int_en : R/W; bitpos: [3]; default: 0; - * Configures to enable APM M3 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M3 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m3_apm_int_en:1; /** m4_apm_int_en : R/W; bitpos: [4]; default: 0; - * Configures to enable APM M4 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M4 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m4_apm_int_en:1; uint32_t reserved_5:27; @@ -549,16 +509,16 @@ typedef union { } hp_apm_int_en_reg_t; -/** Group: Clock gating register */ +/** Group: Clock Gating Registers */ /** Type of clock_gate register * Clock gating register */ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; - * Configures whether to keep the clock always on.\\ - * 0: enable automatic clock gating \\ - * 1: keep the clock always on \\ + * Configures whether to keep the clock always on. + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -567,7 +527,7 @@ typedef union { } hp_apm_clock_gate_reg_t; -/** Group: Version control register */ +/** Group: Version Control Registers */ /** Type of date register * Version control register */ diff --git a/components/soc/esp32c5/register/soc/lp_apm0_reg.h b/components/soc/esp32c5/register/soc/lp_apm0_reg.h index 789db5cd27..c9850a0f10 100644 --- a/components/soc/esp32c5/register/soc/lp_apm0_reg.h +++ b/components/soc/esp32c5/register/soc/lp_apm0_reg.h @@ -12,13 +12,13 @@ extern "C" { #endif /** LP_APM0_REGION_FILTER_EN_REG register - * Region filter enable register + * Region enable register */ #define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0) /** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1; - * Configure bit $n(0-7) to enable region $n. - * 0: disable - * 1: enable + * Configure bit $n (0-7) to enable region $n (0-7). + * 0: Disable + * 1: Enable */ #define LP_APM0_REGION_FILTER_EN 0x000000FFU #define LP_APM0_REGION_FILTER_EN_M (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S) @@ -30,7 +30,7 @@ extern "C" { */ #define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4) /** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 0 + * Configures the start address of region 0. */ #define LP_APM0_REGION0_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION0_ADDR_START_M (LP_APM0_REGION0_ADDR_START_V << LP_APM0_REGION0_ADDR_START_S) @@ -42,7 +42,7 @@ extern "C" { */ #define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x8) /** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 0 + * Configures the end address of region 0. */ #define LP_APM0_REGION0_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION0_ADDR_END_M (LP_APM0_REGION0_ADDR_END_V << LP_APM0_REGION0_ADDR_END_S) @@ -50,74 +50,78 @@ extern "C" { #define LP_APM0_REGION0_ADDR_END_S 0 /** LP_APM0_REGION0_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION0_ATTR_REG (DR_REG_LP_APM0_BASE + 0xc) /** LP_APM0_REGION0_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 0. + * Configures the execution permission in region 0 in REE0 mode. */ #define LP_APM0_REGION0_R0_X (BIT(0)) #define LP_APM0_REGION0_R0_X_M (LP_APM0_REGION0_R0_X_V << LP_APM0_REGION0_R0_X_S) #define LP_APM0_REGION0_R0_X_V 0x00000001U #define LP_APM0_REGION0_R0_X_S 0 /** LP_APM0_REGION0_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 0. + * Configures the write permission in region 0 in REE0 mode. */ #define LP_APM0_REGION0_R0_W (BIT(1)) #define LP_APM0_REGION0_R0_W_M (LP_APM0_REGION0_R0_W_V << LP_APM0_REGION0_R0_W_S) #define LP_APM0_REGION0_R0_W_V 0x00000001U #define LP_APM0_REGION0_R0_W_S 1 /** LP_APM0_REGION0_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 0. + * Configures the read permission in region 0 in REE0 mode. */ #define LP_APM0_REGION0_R0_R (BIT(2)) #define LP_APM0_REGION0_R0_R_M (LP_APM0_REGION0_R0_R_V << LP_APM0_REGION0_R0_R_S) #define LP_APM0_REGION0_R0_R_V 0x00000001U #define LP_APM0_REGION0_R0_R_S 2 /** LP_APM0_REGION0_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 0. + * Configures the execution permission in region 0 in REE1 mode. */ #define LP_APM0_REGION0_R1_X (BIT(4)) #define LP_APM0_REGION0_R1_X_M (LP_APM0_REGION0_R1_X_V << LP_APM0_REGION0_R1_X_S) #define LP_APM0_REGION0_R1_X_V 0x00000001U #define LP_APM0_REGION0_R1_X_S 4 /** LP_APM0_REGION0_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 0. + * Configures the write permission in region 0 in REE1 mode. */ #define LP_APM0_REGION0_R1_W (BIT(5)) #define LP_APM0_REGION0_R1_W_M (LP_APM0_REGION0_R1_W_V << LP_APM0_REGION0_R1_W_S) #define LP_APM0_REGION0_R1_W_V 0x00000001U #define LP_APM0_REGION0_R1_W_S 5 /** LP_APM0_REGION0_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 0. + * Configures the read permission in region 0 in REE1 mode. */ #define LP_APM0_REGION0_R1_R (BIT(6)) #define LP_APM0_REGION0_R1_R_M (LP_APM0_REGION0_R1_R_V << LP_APM0_REGION0_R1_R_S) #define LP_APM0_REGION0_R1_R_V 0x00000001U #define LP_APM0_REGION0_R1_R_S 6 /** LP_APM0_REGION0_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 0. + * Configures the execution permission in region 0 in REE2 mode. */ #define LP_APM0_REGION0_R2_X (BIT(8)) #define LP_APM0_REGION0_R2_X_M (LP_APM0_REGION0_R2_X_V << LP_APM0_REGION0_R2_X_S) #define LP_APM0_REGION0_R2_X_V 0x00000001U #define LP_APM0_REGION0_R2_X_S 8 /** LP_APM0_REGION0_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 0. + * Configures the write permission in region 0 in REE2 mode. */ #define LP_APM0_REGION0_R2_W (BIT(9)) #define LP_APM0_REGION0_R2_W_M (LP_APM0_REGION0_R2_W_V << LP_APM0_REGION0_R2_W_S) #define LP_APM0_REGION0_R2_W_V 0x00000001U #define LP_APM0_REGION0_R2_W_S 9 /** LP_APM0_REGION0_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 0. + * Configures the read permission in region 0 in REE2 mode. */ #define LP_APM0_REGION0_R2_R (BIT(10)) #define LP_APM0_REGION0_R2_R_M (LP_APM0_REGION0_R2_R_V << LP_APM0_REGION0_R2_R_S) #define LP_APM0_REGION0_R2_R_V 0x00000001U #define LP_APM0_REGION0_R2_R_S 10 /** LP_APM0_REGION0_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 0 configuration registers + * (LP_APM0_REGION0_ADDR_START_REG, LP_APM0_REGION0_ADDR_END_REG and + * LP_APM0_REGION0_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION0_LOCK (BIT(11)) #define LP_APM0_REGION0_LOCK_M (LP_APM0_REGION0_LOCK_V << LP_APM0_REGION0_LOCK_S) @@ -129,7 +133,7 @@ extern "C" { */ #define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x10) /** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 1 + * Configures the start address of region 1. */ #define LP_APM0_REGION1_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION1_ADDR_START_M (LP_APM0_REGION1_ADDR_START_V << LP_APM0_REGION1_ADDR_START_S) @@ -141,7 +145,7 @@ extern "C" { */ #define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x14) /** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 1 + * Configures the end address of region 1. */ #define LP_APM0_REGION1_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION1_ADDR_END_M (LP_APM0_REGION1_ADDR_END_V << LP_APM0_REGION1_ADDR_END_S) @@ -149,74 +153,78 @@ extern "C" { #define LP_APM0_REGION1_ADDR_END_S 0 /** LP_APM0_REGION1_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION1_ATTR_REG (DR_REG_LP_APM0_BASE + 0x18) /** LP_APM0_REGION1_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 1. + * Configures the execution permission in region 1 in REE0 mode. */ #define LP_APM0_REGION1_R0_X (BIT(0)) #define LP_APM0_REGION1_R0_X_M (LP_APM0_REGION1_R0_X_V << LP_APM0_REGION1_R0_X_S) #define LP_APM0_REGION1_R0_X_V 0x00000001U #define LP_APM0_REGION1_R0_X_S 0 /** LP_APM0_REGION1_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 1. + * Configures the write permission in region 1 in REE0 mode. */ #define LP_APM0_REGION1_R0_W (BIT(1)) #define LP_APM0_REGION1_R0_W_M (LP_APM0_REGION1_R0_W_V << LP_APM0_REGION1_R0_W_S) #define LP_APM0_REGION1_R0_W_V 0x00000001U #define LP_APM0_REGION1_R0_W_S 1 /** LP_APM0_REGION1_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 1. + * Configures the read permission in region 1 in REE0 mode. */ #define LP_APM0_REGION1_R0_R (BIT(2)) #define LP_APM0_REGION1_R0_R_M (LP_APM0_REGION1_R0_R_V << LP_APM0_REGION1_R0_R_S) #define LP_APM0_REGION1_R0_R_V 0x00000001U #define LP_APM0_REGION1_R0_R_S 2 /** LP_APM0_REGION1_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 1. + * Configures the execution permission in region 1 in REE1 mode. */ #define LP_APM0_REGION1_R1_X (BIT(4)) #define LP_APM0_REGION1_R1_X_M (LP_APM0_REGION1_R1_X_V << LP_APM0_REGION1_R1_X_S) #define LP_APM0_REGION1_R1_X_V 0x00000001U #define LP_APM0_REGION1_R1_X_S 4 /** LP_APM0_REGION1_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 1. + * Configures the write permission in region 1 in REE1 mode. */ #define LP_APM0_REGION1_R1_W (BIT(5)) #define LP_APM0_REGION1_R1_W_M (LP_APM0_REGION1_R1_W_V << LP_APM0_REGION1_R1_W_S) #define LP_APM0_REGION1_R1_W_V 0x00000001U #define LP_APM0_REGION1_R1_W_S 5 /** LP_APM0_REGION1_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 1. + * Configures the read permission in region 1 in REE1 mode. */ #define LP_APM0_REGION1_R1_R (BIT(6)) #define LP_APM0_REGION1_R1_R_M (LP_APM0_REGION1_R1_R_V << LP_APM0_REGION1_R1_R_S) #define LP_APM0_REGION1_R1_R_V 0x00000001U #define LP_APM0_REGION1_R1_R_S 6 /** LP_APM0_REGION1_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 1. + * Configures the execution permission in region 1 in REE2 mode. */ #define LP_APM0_REGION1_R2_X (BIT(8)) #define LP_APM0_REGION1_R2_X_M (LP_APM0_REGION1_R2_X_V << LP_APM0_REGION1_R2_X_S) #define LP_APM0_REGION1_R2_X_V 0x00000001U #define LP_APM0_REGION1_R2_X_S 8 /** LP_APM0_REGION1_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 1. + * Configures the write permission in region 1 in REE2 mode. */ #define LP_APM0_REGION1_R2_W (BIT(9)) #define LP_APM0_REGION1_R2_W_M (LP_APM0_REGION1_R2_W_V << LP_APM0_REGION1_R2_W_S) #define LP_APM0_REGION1_R2_W_V 0x00000001U #define LP_APM0_REGION1_R2_W_S 9 /** LP_APM0_REGION1_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 1. + * Configures the read permission in region 1 in REE2 mode. */ #define LP_APM0_REGION1_R2_R (BIT(10)) #define LP_APM0_REGION1_R2_R_M (LP_APM0_REGION1_R2_R_V << LP_APM0_REGION1_R2_R_S) #define LP_APM0_REGION1_R2_R_V 0x00000001U #define LP_APM0_REGION1_R2_R_S 10 /** LP_APM0_REGION1_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 1 configuration registers + * (LP_APM0_REGION1_ADDR_START_REG, LP_APM0_REGION1_ADDR_END_REG and + * LP_APM0_REGION1_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION1_LOCK (BIT(11)) #define LP_APM0_REGION1_LOCK_M (LP_APM0_REGION1_LOCK_V << LP_APM0_REGION1_LOCK_S) @@ -228,7 +236,7 @@ extern "C" { */ #define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x1c) /** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 2 + * Configures the start address of region 2. */ #define LP_APM0_REGION2_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION2_ADDR_START_M (LP_APM0_REGION2_ADDR_START_V << LP_APM0_REGION2_ADDR_START_S) @@ -240,7 +248,7 @@ extern "C" { */ #define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x20) /** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 2 + * Configures the end address of region 2. */ #define LP_APM0_REGION2_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION2_ADDR_END_M (LP_APM0_REGION2_ADDR_END_V << LP_APM0_REGION2_ADDR_END_S) @@ -248,74 +256,78 @@ extern "C" { #define LP_APM0_REGION2_ADDR_END_S 0 /** LP_APM0_REGION2_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION2_ATTR_REG (DR_REG_LP_APM0_BASE + 0x24) /** LP_APM0_REGION2_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 2. + * Configures the execution permission in region 2 in REE0 mode. */ #define LP_APM0_REGION2_R0_X (BIT(0)) #define LP_APM0_REGION2_R0_X_M (LP_APM0_REGION2_R0_X_V << LP_APM0_REGION2_R0_X_S) #define LP_APM0_REGION2_R0_X_V 0x00000001U #define LP_APM0_REGION2_R0_X_S 0 /** LP_APM0_REGION2_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 2. + * Configures the write permission in region 2 in REE0 mode. */ #define LP_APM0_REGION2_R0_W (BIT(1)) #define LP_APM0_REGION2_R0_W_M (LP_APM0_REGION2_R0_W_V << LP_APM0_REGION2_R0_W_S) #define LP_APM0_REGION2_R0_W_V 0x00000001U #define LP_APM0_REGION2_R0_W_S 1 /** LP_APM0_REGION2_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 2. + * Configures the read permission in region 2 in REE0 mode. */ #define LP_APM0_REGION2_R0_R (BIT(2)) #define LP_APM0_REGION2_R0_R_M (LP_APM0_REGION2_R0_R_V << LP_APM0_REGION2_R0_R_S) #define LP_APM0_REGION2_R0_R_V 0x00000001U #define LP_APM0_REGION2_R0_R_S 2 /** LP_APM0_REGION2_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 2. + * Configures the execution permission in region 2 in REE1 mode. */ #define LP_APM0_REGION2_R1_X (BIT(4)) #define LP_APM0_REGION2_R1_X_M (LP_APM0_REGION2_R1_X_V << LP_APM0_REGION2_R1_X_S) #define LP_APM0_REGION2_R1_X_V 0x00000001U #define LP_APM0_REGION2_R1_X_S 4 /** LP_APM0_REGION2_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 2. + * Configures the write permission in region 2 in REE1 mode. */ #define LP_APM0_REGION2_R1_W (BIT(5)) #define LP_APM0_REGION2_R1_W_M (LP_APM0_REGION2_R1_W_V << LP_APM0_REGION2_R1_W_S) #define LP_APM0_REGION2_R1_W_V 0x00000001U #define LP_APM0_REGION2_R1_W_S 5 /** LP_APM0_REGION2_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 2. + * Configures the read permission in region 2 in REE1 mode. */ #define LP_APM0_REGION2_R1_R (BIT(6)) #define LP_APM0_REGION2_R1_R_M (LP_APM0_REGION2_R1_R_V << LP_APM0_REGION2_R1_R_S) #define LP_APM0_REGION2_R1_R_V 0x00000001U #define LP_APM0_REGION2_R1_R_S 6 /** LP_APM0_REGION2_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 2. + * Configures the execution permission in region 2 in REE2 mode. */ #define LP_APM0_REGION2_R2_X (BIT(8)) #define LP_APM0_REGION2_R2_X_M (LP_APM0_REGION2_R2_X_V << LP_APM0_REGION2_R2_X_S) #define LP_APM0_REGION2_R2_X_V 0x00000001U #define LP_APM0_REGION2_R2_X_S 8 /** LP_APM0_REGION2_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 2. + * Configures the write permission in region 2 in REE2 mode. */ #define LP_APM0_REGION2_R2_W (BIT(9)) #define LP_APM0_REGION2_R2_W_M (LP_APM0_REGION2_R2_W_V << LP_APM0_REGION2_R2_W_S) #define LP_APM0_REGION2_R2_W_V 0x00000001U #define LP_APM0_REGION2_R2_W_S 9 /** LP_APM0_REGION2_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 2. + * Configures the read permission in region 2 in REE2 mode. */ #define LP_APM0_REGION2_R2_R (BIT(10)) #define LP_APM0_REGION2_R2_R_M (LP_APM0_REGION2_R2_R_V << LP_APM0_REGION2_R2_R_S) #define LP_APM0_REGION2_R2_R_V 0x00000001U #define LP_APM0_REGION2_R2_R_S 10 /** LP_APM0_REGION2_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 2 configuration registers + * (LP_APM0_REGION2_ADDR_START_REG, LP_APM0_REGION2_ADDR_END_REG and + * LP_APM0_REGION2_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION2_LOCK (BIT(11)) #define LP_APM0_REGION2_LOCK_M (LP_APM0_REGION2_LOCK_V << LP_APM0_REGION2_LOCK_S) @@ -327,7 +339,7 @@ extern "C" { */ #define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x28) /** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 3 + * Configures the start address of region 3. */ #define LP_APM0_REGION3_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION3_ADDR_START_M (LP_APM0_REGION3_ADDR_START_V << LP_APM0_REGION3_ADDR_START_S) @@ -339,7 +351,7 @@ extern "C" { */ #define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x2c) /** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 3 + * Configures the end address of region 3. */ #define LP_APM0_REGION3_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION3_ADDR_END_M (LP_APM0_REGION3_ADDR_END_V << LP_APM0_REGION3_ADDR_END_S) @@ -347,74 +359,78 @@ extern "C" { #define LP_APM0_REGION3_ADDR_END_S 0 /** LP_APM0_REGION3_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION3_ATTR_REG (DR_REG_LP_APM0_BASE + 0x30) /** LP_APM0_REGION3_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 3. + * Configures the execution permission in region 3 in REE0 mode. */ #define LP_APM0_REGION3_R0_X (BIT(0)) #define LP_APM0_REGION3_R0_X_M (LP_APM0_REGION3_R0_X_V << LP_APM0_REGION3_R0_X_S) #define LP_APM0_REGION3_R0_X_V 0x00000001U #define LP_APM0_REGION3_R0_X_S 0 /** LP_APM0_REGION3_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 3. + * Configures the write permission in region 3 in REE0 mode. */ #define LP_APM0_REGION3_R0_W (BIT(1)) #define LP_APM0_REGION3_R0_W_M (LP_APM0_REGION3_R0_W_V << LP_APM0_REGION3_R0_W_S) #define LP_APM0_REGION3_R0_W_V 0x00000001U #define LP_APM0_REGION3_R0_W_S 1 /** LP_APM0_REGION3_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 3. + * Configures the read permission in region 3 in REE0 mode. */ #define LP_APM0_REGION3_R0_R (BIT(2)) #define LP_APM0_REGION3_R0_R_M (LP_APM0_REGION3_R0_R_V << LP_APM0_REGION3_R0_R_S) #define LP_APM0_REGION3_R0_R_V 0x00000001U #define LP_APM0_REGION3_R0_R_S 2 /** LP_APM0_REGION3_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 3. + * Configures the execution permission in region 3 in REE1 mode. */ #define LP_APM0_REGION3_R1_X (BIT(4)) #define LP_APM0_REGION3_R1_X_M (LP_APM0_REGION3_R1_X_V << LP_APM0_REGION3_R1_X_S) #define LP_APM0_REGION3_R1_X_V 0x00000001U #define LP_APM0_REGION3_R1_X_S 4 /** LP_APM0_REGION3_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 3. + * Configures the write permission in region 3 in REE1 mode. */ #define LP_APM0_REGION3_R1_W (BIT(5)) #define LP_APM0_REGION3_R1_W_M (LP_APM0_REGION3_R1_W_V << LP_APM0_REGION3_R1_W_S) #define LP_APM0_REGION3_R1_W_V 0x00000001U #define LP_APM0_REGION3_R1_W_S 5 /** LP_APM0_REGION3_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 3. + * Configures the read permission in region 3 in REE1 mode. */ #define LP_APM0_REGION3_R1_R (BIT(6)) #define LP_APM0_REGION3_R1_R_M (LP_APM0_REGION3_R1_R_V << LP_APM0_REGION3_R1_R_S) #define LP_APM0_REGION3_R1_R_V 0x00000001U #define LP_APM0_REGION3_R1_R_S 6 /** LP_APM0_REGION3_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 3. + * Configures the execution permission in region 3 in REE2 mode. */ #define LP_APM0_REGION3_R2_X (BIT(8)) #define LP_APM0_REGION3_R2_X_M (LP_APM0_REGION3_R2_X_V << LP_APM0_REGION3_R2_X_S) #define LP_APM0_REGION3_R2_X_V 0x00000001U #define LP_APM0_REGION3_R2_X_S 8 /** LP_APM0_REGION3_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 3. + * Configures the write permission in region 3 in REE2 mode. */ #define LP_APM0_REGION3_R2_W (BIT(9)) #define LP_APM0_REGION3_R2_W_M (LP_APM0_REGION3_R2_W_V << LP_APM0_REGION3_R2_W_S) #define LP_APM0_REGION3_R2_W_V 0x00000001U #define LP_APM0_REGION3_R2_W_S 9 /** LP_APM0_REGION3_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 3. + * Configures the read permission in region 3 in REE2 mode. */ #define LP_APM0_REGION3_R2_R (BIT(10)) #define LP_APM0_REGION3_R2_R_M (LP_APM0_REGION3_R2_R_V << LP_APM0_REGION3_R2_R_S) #define LP_APM0_REGION3_R2_R_V 0x00000001U #define LP_APM0_REGION3_R2_R_S 10 /** LP_APM0_REGION3_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 3 configuration registers + * (LP_APM0_REGION3_ADDR_START_REG, LP_APM0_REGION3_ADDR_END_REG and + * LP_APM0_REGION3_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION3_LOCK (BIT(11)) #define LP_APM0_REGION3_LOCK_M (LP_APM0_REGION3_LOCK_V << LP_APM0_REGION3_LOCK_S) @@ -426,7 +442,7 @@ extern "C" { */ #define LP_APM0_REGION4_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x34) /** LP_APM0_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 4 + * Configures the start address of region 4. */ #define LP_APM0_REGION4_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION4_ADDR_START_M (LP_APM0_REGION4_ADDR_START_V << LP_APM0_REGION4_ADDR_START_S) @@ -438,7 +454,7 @@ extern "C" { */ #define LP_APM0_REGION4_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x38) /** LP_APM0_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 4 + * Configures the end address of region 4. */ #define LP_APM0_REGION4_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION4_ADDR_END_M (LP_APM0_REGION4_ADDR_END_V << LP_APM0_REGION4_ADDR_END_S) @@ -446,74 +462,78 @@ extern "C" { #define LP_APM0_REGION4_ADDR_END_S 0 /** LP_APM0_REGION4_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION4_ATTR_REG (DR_REG_LP_APM0_BASE + 0x3c) /** LP_APM0_REGION4_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 4. + * Configures the execution permission in region 4 in REE0 mode. */ #define LP_APM0_REGION4_R0_X (BIT(0)) #define LP_APM0_REGION4_R0_X_M (LP_APM0_REGION4_R0_X_V << LP_APM0_REGION4_R0_X_S) #define LP_APM0_REGION4_R0_X_V 0x00000001U #define LP_APM0_REGION4_R0_X_S 0 /** LP_APM0_REGION4_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 4. + * Configures the write permission in region 4 in REE0 mode. */ #define LP_APM0_REGION4_R0_W (BIT(1)) #define LP_APM0_REGION4_R0_W_M (LP_APM0_REGION4_R0_W_V << LP_APM0_REGION4_R0_W_S) #define LP_APM0_REGION4_R0_W_V 0x00000001U #define LP_APM0_REGION4_R0_W_S 1 /** LP_APM0_REGION4_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 4. + * Configures the read permission in region 4 in REE0 mode. */ #define LP_APM0_REGION4_R0_R (BIT(2)) #define LP_APM0_REGION4_R0_R_M (LP_APM0_REGION4_R0_R_V << LP_APM0_REGION4_R0_R_S) #define LP_APM0_REGION4_R0_R_V 0x00000001U #define LP_APM0_REGION4_R0_R_S 2 /** LP_APM0_REGION4_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 4. + * Configures the execution permission in region 4 in REE1 mode. */ #define LP_APM0_REGION4_R1_X (BIT(4)) #define LP_APM0_REGION4_R1_X_M (LP_APM0_REGION4_R1_X_V << LP_APM0_REGION4_R1_X_S) #define LP_APM0_REGION4_R1_X_V 0x00000001U #define LP_APM0_REGION4_R1_X_S 4 /** LP_APM0_REGION4_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 4. + * Configures the write permission in region 4 in REE1 mode. */ #define LP_APM0_REGION4_R1_W (BIT(5)) #define LP_APM0_REGION4_R1_W_M (LP_APM0_REGION4_R1_W_V << LP_APM0_REGION4_R1_W_S) #define LP_APM0_REGION4_R1_W_V 0x00000001U #define LP_APM0_REGION4_R1_W_S 5 /** LP_APM0_REGION4_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 4. + * Configures the read permission in region 4 in REE1 mode. */ #define LP_APM0_REGION4_R1_R (BIT(6)) #define LP_APM0_REGION4_R1_R_M (LP_APM0_REGION4_R1_R_V << LP_APM0_REGION4_R1_R_S) #define LP_APM0_REGION4_R1_R_V 0x00000001U #define LP_APM0_REGION4_R1_R_S 6 /** LP_APM0_REGION4_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 4. + * Configures the execution permission in region 4 in REE2 mode. */ #define LP_APM0_REGION4_R2_X (BIT(8)) #define LP_APM0_REGION4_R2_X_M (LP_APM0_REGION4_R2_X_V << LP_APM0_REGION4_R2_X_S) #define LP_APM0_REGION4_R2_X_V 0x00000001U #define LP_APM0_REGION4_R2_X_S 8 /** LP_APM0_REGION4_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 4. + * Configures the write permission in region 4 in REE2 mode. */ #define LP_APM0_REGION4_R2_W (BIT(9)) #define LP_APM0_REGION4_R2_W_M (LP_APM0_REGION4_R2_W_V << LP_APM0_REGION4_R2_W_S) #define LP_APM0_REGION4_R2_W_V 0x00000001U #define LP_APM0_REGION4_R2_W_S 9 /** LP_APM0_REGION4_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 4. + * Configures the read permission in region 4 in REE2 mode. */ #define LP_APM0_REGION4_R2_R (BIT(10)) #define LP_APM0_REGION4_R2_R_M (LP_APM0_REGION4_R2_R_V << LP_APM0_REGION4_R2_R_S) #define LP_APM0_REGION4_R2_R_V 0x00000001U #define LP_APM0_REGION4_R2_R_S 10 /** LP_APM0_REGION4_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 4 configuration registers + * (LP_APM0_REGION4_ADDR_START_REG, LP_APM0_REGION4_ADDR_END_REG and + * LP_APM0_REGION4_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION4_LOCK (BIT(11)) #define LP_APM0_REGION4_LOCK_M (LP_APM0_REGION4_LOCK_V << LP_APM0_REGION4_LOCK_S) @@ -525,7 +545,7 @@ extern "C" { */ #define LP_APM0_REGION5_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x40) /** LP_APM0_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 5 + * Configures the start address of region 5. */ #define LP_APM0_REGION5_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION5_ADDR_START_M (LP_APM0_REGION5_ADDR_START_V << LP_APM0_REGION5_ADDR_START_S) @@ -537,7 +557,7 @@ extern "C" { */ #define LP_APM0_REGION5_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x44) /** LP_APM0_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 5 + * Configures the end address of region 5. */ #define LP_APM0_REGION5_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION5_ADDR_END_M (LP_APM0_REGION5_ADDR_END_V << LP_APM0_REGION5_ADDR_END_S) @@ -545,74 +565,78 @@ extern "C" { #define LP_APM0_REGION5_ADDR_END_S 0 /** LP_APM0_REGION5_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION5_ATTR_REG (DR_REG_LP_APM0_BASE + 0x48) /** LP_APM0_REGION5_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 5. + * Configures the execution permission in region 5 in REE0 mode. */ #define LP_APM0_REGION5_R0_X (BIT(0)) #define LP_APM0_REGION5_R0_X_M (LP_APM0_REGION5_R0_X_V << LP_APM0_REGION5_R0_X_S) #define LP_APM0_REGION5_R0_X_V 0x00000001U #define LP_APM0_REGION5_R0_X_S 0 /** LP_APM0_REGION5_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 5. + * Configures the write permission in region 5 in REE0 mode. */ #define LP_APM0_REGION5_R0_W (BIT(1)) #define LP_APM0_REGION5_R0_W_M (LP_APM0_REGION5_R0_W_V << LP_APM0_REGION5_R0_W_S) #define LP_APM0_REGION5_R0_W_V 0x00000001U #define LP_APM0_REGION5_R0_W_S 1 /** LP_APM0_REGION5_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 5. + * Configures the read permission in region 5 in REE0 mode. */ #define LP_APM0_REGION5_R0_R (BIT(2)) #define LP_APM0_REGION5_R0_R_M (LP_APM0_REGION5_R0_R_V << LP_APM0_REGION5_R0_R_S) #define LP_APM0_REGION5_R0_R_V 0x00000001U #define LP_APM0_REGION5_R0_R_S 2 /** LP_APM0_REGION5_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 5. + * Configures the execution permission in region 5 in REE1 mode. */ #define LP_APM0_REGION5_R1_X (BIT(4)) #define LP_APM0_REGION5_R1_X_M (LP_APM0_REGION5_R1_X_V << LP_APM0_REGION5_R1_X_S) #define LP_APM0_REGION5_R1_X_V 0x00000001U #define LP_APM0_REGION5_R1_X_S 4 /** LP_APM0_REGION5_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 5. + * Configures the write permission in region 5 in REE1 mode. */ #define LP_APM0_REGION5_R1_W (BIT(5)) #define LP_APM0_REGION5_R1_W_M (LP_APM0_REGION5_R1_W_V << LP_APM0_REGION5_R1_W_S) #define LP_APM0_REGION5_R1_W_V 0x00000001U #define LP_APM0_REGION5_R1_W_S 5 /** LP_APM0_REGION5_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 5. + * Configures the read permission in region 5 in REE1 mode. */ #define LP_APM0_REGION5_R1_R (BIT(6)) #define LP_APM0_REGION5_R1_R_M (LP_APM0_REGION5_R1_R_V << LP_APM0_REGION5_R1_R_S) #define LP_APM0_REGION5_R1_R_V 0x00000001U #define LP_APM0_REGION5_R1_R_S 6 /** LP_APM0_REGION5_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 5. + * Configures the execution permission in region 5 in REE2 mode. */ #define LP_APM0_REGION5_R2_X (BIT(8)) #define LP_APM0_REGION5_R2_X_M (LP_APM0_REGION5_R2_X_V << LP_APM0_REGION5_R2_X_S) #define LP_APM0_REGION5_R2_X_V 0x00000001U #define LP_APM0_REGION5_R2_X_S 8 /** LP_APM0_REGION5_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 5. + * Configures the write permission in region 5 in REE2 mode. */ #define LP_APM0_REGION5_R2_W (BIT(9)) #define LP_APM0_REGION5_R2_W_M (LP_APM0_REGION5_R2_W_V << LP_APM0_REGION5_R2_W_S) #define LP_APM0_REGION5_R2_W_V 0x00000001U #define LP_APM0_REGION5_R2_W_S 9 /** LP_APM0_REGION5_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 5. + * Configures the read permission in region 5 in REE2 mode. */ #define LP_APM0_REGION5_R2_R (BIT(10)) #define LP_APM0_REGION5_R2_R_M (LP_APM0_REGION5_R2_R_V << LP_APM0_REGION5_R2_R_S) #define LP_APM0_REGION5_R2_R_V 0x00000001U #define LP_APM0_REGION5_R2_R_S 10 /** LP_APM0_REGION5_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 5 configuration registers + * (LP_APM0_REGION5_ADDR_START_REG, LP_APM0_REGION5_ADDR_END_REG and + * LP_APM0_REGION5_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION5_LOCK (BIT(11)) #define LP_APM0_REGION5_LOCK_M (LP_APM0_REGION5_LOCK_V << LP_APM0_REGION5_LOCK_S) @@ -624,7 +648,7 @@ extern "C" { */ #define LP_APM0_REGION6_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4c) /** LP_APM0_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 6 + * Configures the start address of region 6. */ #define LP_APM0_REGION6_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION6_ADDR_START_M (LP_APM0_REGION6_ADDR_START_V << LP_APM0_REGION6_ADDR_START_S) @@ -636,7 +660,7 @@ extern "C" { */ #define LP_APM0_REGION6_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x50) /** LP_APM0_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 6 + * Configures the end address of region 6. */ #define LP_APM0_REGION6_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION6_ADDR_END_M (LP_APM0_REGION6_ADDR_END_V << LP_APM0_REGION6_ADDR_END_S) @@ -644,74 +668,78 @@ extern "C" { #define LP_APM0_REGION6_ADDR_END_S 0 /** LP_APM0_REGION6_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION6_ATTR_REG (DR_REG_LP_APM0_BASE + 0x54) /** LP_APM0_REGION6_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 6. + * Configures the execution permission in region 6 in REE0 mode. */ #define LP_APM0_REGION6_R0_X (BIT(0)) #define LP_APM0_REGION6_R0_X_M (LP_APM0_REGION6_R0_X_V << LP_APM0_REGION6_R0_X_S) #define LP_APM0_REGION6_R0_X_V 0x00000001U #define LP_APM0_REGION6_R0_X_S 0 /** LP_APM0_REGION6_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 6. + * Configures the write permission in region 6 in REE0 mode. */ #define LP_APM0_REGION6_R0_W (BIT(1)) #define LP_APM0_REGION6_R0_W_M (LP_APM0_REGION6_R0_W_V << LP_APM0_REGION6_R0_W_S) #define LP_APM0_REGION6_R0_W_V 0x00000001U #define LP_APM0_REGION6_R0_W_S 1 /** LP_APM0_REGION6_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 6. + * Configures the read permission in region 6 in REE0 mode. */ #define LP_APM0_REGION6_R0_R (BIT(2)) #define LP_APM0_REGION6_R0_R_M (LP_APM0_REGION6_R0_R_V << LP_APM0_REGION6_R0_R_S) #define LP_APM0_REGION6_R0_R_V 0x00000001U #define LP_APM0_REGION6_R0_R_S 2 /** LP_APM0_REGION6_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 6. + * Configures the execution permission in region 6 in REE1 mode. */ #define LP_APM0_REGION6_R1_X (BIT(4)) #define LP_APM0_REGION6_R1_X_M (LP_APM0_REGION6_R1_X_V << LP_APM0_REGION6_R1_X_S) #define LP_APM0_REGION6_R1_X_V 0x00000001U #define LP_APM0_REGION6_R1_X_S 4 /** LP_APM0_REGION6_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 6. + * Configures the write permission in region 6 in REE1 mode. */ #define LP_APM0_REGION6_R1_W (BIT(5)) #define LP_APM0_REGION6_R1_W_M (LP_APM0_REGION6_R1_W_V << LP_APM0_REGION6_R1_W_S) #define LP_APM0_REGION6_R1_W_V 0x00000001U #define LP_APM0_REGION6_R1_W_S 5 /** LP_APM0_REGION6_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 6. + * Configures the read permission in region 6 in REE1 mode. */ #define LP_APM0_REGION6_R1_R (BIT(6)) #define LP_APM0_REGION6_R1_R_M (LP_APM0_REGION6_R1_R_V << LP_APM0_REGION6_R1_R_S) #define LP_APM0_REGION6_R1_R_V 0x00000001U #define LP_APM0_REGION6_R1_R_S 6 /** LP_APM0_REGION6_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 6. + * Configures the execution permission in region 6 in REE2 mode. */ #define LP_APM0_REGION6_R2_X (BIT(8)) #define LP_APM0_REGION6_R2_X_M (LP_APM0_REGION6_R2_X_V << LP_APM0_REGION6_R2_X_S) #define LP_APM0_REGION6_R2_X_V 0x00000001U #define LP_APM0_REGION6_R2_X_S 8 /** LP_APM0_REGION6_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 6. + * Configures the write permission in region 6 in REE2 mode. */ #define LP_APM0_REGION6_R2_W (BIT(9)) #define LP_APM0_REGION6_R2_W_M (LP_APM0_REGION6_R2_W_V << LP_APM0_REGION6_R2_W_S) #define LP_APM0_REGION6_R2_W_V 0x00000001U #define LP_APM0_REGION6_R2_W_S 9 /** LP_APM0_REGION6_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 6. + * Configures the read permission in region 6 in REE2 mode. */ #define LP_APM0_REGION6_R2_R (BIT(10)) #define LP_APM0_REGION6_R2_R_M (LP_APM0_REGION6_R2_R_V << LP_APM0_REGION6_R2_R_S) #define LP_APM0_REGION6_R2_R_V 0x00000001U #define LP_APM0_REGION6_R2_R_S 10 /** LP_APM0_REGION6_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 6 configuration registers + * (LP_APM0_REGION6_ADDR_START_REG, LP_APM0_REGION6_ADDR_END_REG and + * LP_APM0_REGION6_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION6_LOCK (BIT(11)) #define LP_APM0_REGION6_LOCK_M (LP_APM0_REGION6_LOCK_V << LP_APM0_REGION6_LOCK_S) @@ -723,7 +751,7 @@ extern "C" { */ #define LP_APM0_REGION7_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x58) /** LP_APM0_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 7 + * Configures the start address of region 7. */ #define LP_APM0_REGION7_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION7_ADDR_START_M (LP_APM0_REGION7_ADDR_START_V << LP_APM0_REGION7_ADDR_START_S) @@ -735,7 +763,7 @@ extern "C" { */ #define LP_APM0_REGION7_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x5c) /** LP_APM0_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 7 + * Configures the end address of region 7. */ #define LP_APM0_REGION7_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION7_ADDR_END_M (LP_APM0_REGION7_ADDR_END_V << LP_APM0_REGION7_ADDR_END_S) @@ -743,74 +771,78 @@ extern "C" { #define LP_APM0_REGION7_ADDR_END_S 0 /** LP_APM0_REGION7_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION7_ATTR_REG (DR_REG_LP_APM0_BASE + 0x60) /** LP_APM0_REGION7_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 7. + * Configures the execution permission in region 7 in REE0 mode. */ #define LP_APM0_REGION7_R0_X (BIT(0)) #define LP_APM0_REGION7_R0_X_M (LP_APM0_REGION7_R0_X_V << LP_APM0_REGION7_R0_X_S) #define LP_APM0_REGION7_R0_X_V 0x00000001U #define LP_APM0_REGION7_R0_X_S 0 /** LP_APM0_REGION7_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 7. + * Configures the write permission in region 7 in REE0 mode. */ #define LP_APM0_REGION7_R0_W (BIT(1)) #define LP_APM0_REGION7_R0_W_M (LP_APM0_REGION7_R0_W_V << LP_APM0_REGION7_R0_W_S) #define LP_APM0_REGION7_R0_W_V 0x00000001U #define LP_APM0_REGION7_R0_W_S 1 /** LP_APM0_REGION7_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 7. + * Configures the read permission in region 7 in REE0 mode. */ #define LP_APM0_REGION7_R0_R (BIT(2)) #define LP_APM0_REGION7_R0_R_M (LP_APM0_REGION7_R0_R_V << LP_APM0_REGION7_R0_R_S) #define LP_APM0_REGION7_R0_R_V 0x00000001U #define LP_APM0_REGION7_R0_R_S 2 /** LP_APM0_REGION7_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 7. + * Configures the execution permission in region 7 in REE1 mode. */ #define LP_APM0_REGION7_R1_X (BIT(4)) #define LP_APM0_REGION7_R1_X_M (LP_APM0_REGION7_R1_X_V << LP_APM0_REGION7_R1_X_S) #define LP_APM0_REGION7_R1_X_V 0x00000001U #define LP_APM0_REGION7_R1_X_S 4 /** LP_APM0_REGION7_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 7. + * Configures the write permission in region 7 in REE1 mode. */ #define LP_APM0_REGION7_R1_W (BIT(5)) #define LP_APM0_REGION7_R1_W_M (LP_APM0_REGION7_R1_W_V << LP_APM0_REGION7_R1_W_S) #define LP_APM0_REGION7_R1_W_V 0x00000001U #define LP_APM0_REGION7_R1_W_S 5 /** LP_APM0_REGION7_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 7. + * Configures the read permission in region 7 in REE1 mode. */ #define LP_APM0_REGION7_R1_R (BIT(6)) #define LP_APM0_REGION7_R1_R_M (LP_APM0_REGION7_R1_R_V << LP_APM0_REGION7_R1_R_S) #define LP_APM0_REGION7_R1_R_V 0x00000001U #define LP_APM0_REGION7_R1_R_S 6 /** LP_APM0_REGION7_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 7. + * Configures the execution permission in region 7 in REE2 mode. */ #define LP_APM0_REGION7_R2_X (BIT(8)) #define LP_APM0_REGION7_R2_X_M (LP_APM0_REGION7_R2_X_V << LP_APM0_REGION7_R2_X_S) #define LP_APM0_REGION7_R2_X_V 0x00000001U #define LP_APM0_REGION7_R2_X_S 8 /** LP_APM0_REGION7_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 7. + * Configures the write permission in region 7 in REE2 mode. */ #define LP_APM0_REGION7_R2_W (BIT(9)) #define LP_APM0_REGION7_R2_W_M (LP_APM0_REGION7_R2_W_V << LP_APM0_REGION7_R2_W_S) #define LP_APM0_REGION7_R2_W_V 0x00000001U #define LP_APM0_REGION7_R2_W_S 9 /** LP_APM0_REGION7_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 7. + * Configures the read permission in region 7 in REE2 mode. */ #define LP_APM0_REGION7_R2_R (BIT(10)) #define LP_APM0_REGION7_R2_R_M (LP_APM0_REGION7_R2_R_V << LP_APM0_REGION7_R2_R_S) #define LP_APM0_REGION7_R2_R_V 0x00000001U #define LP_APM0_REGION7_R2_R_S 10 /** LP_APM0_REGION7_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 7 configuration registers + * (LP_APM0_REGION7_ADDR_START_REG, LP_APM0_REGION7_ADDR_END_REG and + * LP_APM0_REGION7_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION7_LOCK (BIT(11)) #define LP_APM0_REGION7_LOCK_M (LP_APM0_REGION7_LOCK_V << LP_APM0_REGION7_LOCK_S) @@ -818,11 +850,11 @@ extern "C" { #define LP_APM0_REGION7_LOCK_S 11 /** LP_APM0_FUNC_CTRL_REG register - * APM function control register + * APM access path permission management register */ #define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_APM0_BASE + 0xc4) /** LP_APM0_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures to enable permission management for LP_APM0_CTRL M0. */ #define LP_APM0_M0_FUNC_EN (BIT(0)) #define LP_APM0_M0_FUNC_EN_M (LP_APM0_M0_FUNC_EN_V << LP_APM0_M0_FUNC_EN_S) @@ -830,13 +862,13 @@ extern "C" { #define LP_APM0_M0_FUNC_EN_S 0 /** LP_APM0_M0_STATUS_REG register - * M0 status register + * LP_APM0_CTRL M0 status register */ #define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8) /** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define LP_APM0_M0_EXCEPTION_STATUS 0x00000003U #define LP_APM0_M0_EXCEPTION_STATUS_M (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S) @@ -844,11 +876,11 @@ extern "C" { #define LP_APM0_M0_EXCEPTION_STATUS_S 0 /** LP_APM0_M0_STATUS_CLR_REG register - * M0 status clear register + * LP_APM0_CTRL M0 status clear register */ #define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_APM0_BASE + 0xcc) /** LP_APM0_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; - * Configures to clear exception status + * Configures to clear exception status. */ #define LP_APM0_M0_EXCEPTION_STATUS_CLR (BIT(0)) #define LP_APM0_M0_EXCEPTION_STATUS_CLR_M (LP_APM0_M0_EXCEPTION_STATUS_CLR_V << LP_APM0_M0_EXCEPTION_STATUS_CLR_S) @@ -856,25 +888,25 @@ extern "C" { #define LP_APM0_M0_EXCEPTION_STATUS_CLR_S 0 /** LP_APM0_M0_EXCEPTION_INFO0_REG register - * M0 exception_info0 register + * LP_APM0_CTRL M0 exception information register */ #define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0) /** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0; - * Represents exception region + * Represents the region where an exception occurs. */ #define LP_APM0_M0_EXCEPTION_REGION 0x000000FFU #define LP_APM0_M0_EXCEPTION_REGION_M (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S) #define LP_APM0_M0_EXCEPTION_REGION_V 0x000000FFU #define LP_APM0_M0_EXCEPTION_REGION_S 0 /** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode + * Represents the master's security mode when an exception occurs. */ #define LP_APM0_M0_EXCEPTION_MODE 0x00000003U #define LP_APM0_M0_EXCEPTION_MODE_M (LP_APM0_M0_EXCEPTION_MODE_V << LP_APM0_M0_EXCEPTION_MODE_S) #define LP_APM0_M0_EXCEPTION_MODE_V 0x00000003U #define LP_APM0_M0_EXCEPTION_MODE_S 16 /** LP_APM0_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information + * Represents master ID when an exception occurs. */ #define LP_APM0_M0_EXCEPTION_ID 0x0000001FU #define LP_APM0_M0_EXCEPTION_ID_M (LP_APM0_M0_EXCEPTION_ID_V << LP_APM0_M0_EXCEPTION_ID_S) @@ -882,11 +914,11 @@ extern "C" { #define LP_APM0_M0_EXCEPTION_ID_S 18 /** LP_APM0_M0_EXCEPTION_INFO1_REG register - * M0 exception_info1 register + * LP_APM0_CTRL M0 exception information register */ #define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM0_BASE + 0xd4) /** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr + * Represents the access address when an exception occurs. */ #define LP_APM0_M0_EXCEPTION_ADDR 0xFFFFFFFFU #define LP_APM0_M0_EXCEPTION_ADDR_M (LP_APM0_M0_EXCEPTION_ADDR_V << LP_APM0_M0_EXCEPTION_ADDR_S) @@ -894,13 +926,13 @@ extern "C" { #define LP_APM0_M0_EXCEPTION_ADDR_S 0 /** LP_APM0_INT_EN_REG register - * APM interrupt enable register + * LP_APM0_CTRL interrupt enable register */ #define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8) /** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; - * Configures APM M0 interrupt enable. - * 0: disable - * 1: enable + * Configures to enable LP_APM0_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ #define LP_APM0_M0_APM_INT_EN (BIT(0)) #define LP_APM0_M0_APM_INT_EN_M (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S) @@ -913,8 +945,8 @@ extern "C" { #define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc) /** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ #define LP_APM0_CLK_EN (BIT(0)) #define LP_APM0_CLK_EN_M (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S) @@ -926,7 +958,7 @@ extern "C" { */ #define LP_APM0_DATE_REG (DR_REG_LP_APM0_BASE + 0x7fc) /** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35725664; - * Version control register + * Version control register. */ #define LP_APM0_DATE 0x0FFFFFFFU #define LP_APM0_DATE_M (LP_APM0_DATE_V << LP_APM0_DATE_S) diff --git a/components/soc/esp32c5/register/soc/lp_apm0_struct.h b/components/soc/esp32c5/register/soc/lp_apm0_struct.h index 542cbede30..bc09871187 100644 --- a/components/soc/esp32c5/register/soc/lp_apm0_struct.h +++ b/components/soc/esp32c5/register/soc/lp_apm0_struct.h @@ -10,16 +10,16 @@ extern "C" { #endif -/** Group: Region filter enable register */ +/** Group: Configuration Registers */ /** Type of region_filter_en register - * Region filter enable register + * Region enable register */ typedef union { struct { /** region_filter_en : R/W; bitpos: [7:0]; default: 1; - * Configure bit $n(0-7) to enable region $n. - * 0: disable - * 1: enable + * Configure bit $n (0-7) to enable region $n (0-7). + * 0: Disable + * 1: Enable */ uint32_t region_filter_en:8; uint32_t reserved_8:24; @@ -27,15 +27,13 @@ typedef union { uint32_t val; } lp_apm0_region_filter_en_reg_t; - -/** Group: Region address register */ /** Type of regionn_addr_start register * Region address register */ typedef union { struct { /** regionn_addr_start : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region n + * Configures the start address of region n. */ uint32_t regionn_addr_start:32; }; @@ -48,60 +46,62 @@ typedef union { typedef union { struct { /** regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region n + * Configures the end address of region n. */ uint32_t regionn_addr_end:32; }; uint32_t val; } lp_apm0_regionn_addr_end_reg_t; - -/** Group: Region access authority attribute register */ /** Type of regionn_attr register - * Region access authority attribute register + * Region access permissions configuration register */ typedef union { struct { /** regionn_r0_x : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region n. + * Configures the execution permission in region n in REE0 mode. */ uint32_t regionn_r0_x:1; /** regionn_r0_w : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region n. + * Configures the write permission in region n in REE0 mode. */ uint32_t regionn_r0_w:1; /** regionn_r0_r : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region n. + * Configures the read permission in region n in REE0 mode. */ uint32_t regionn_r0_r:1; uint32_t reserved_3:1; /** regionn_r1_x : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region n. + * Configures the execution permission in region n in REE1 mode. */ uint32_t regionn_r1_x:1; /** regionn_r1_w : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region n. + * Configures the write permission in region n in REE1 mode. */ uint32_t regionn_r1_w:1; /** regionn_r1_r : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region n. + * Configures the read permission in region n in REE1 mode. */ uint32_t regionn_r1_r:1; uint32_t reserved_7:1; /** regionn_r2_x : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region n. + * Configures the execution permission in region n in REE2 mode. */ uint32_t regionn_r2_x:1; /** regionn_r2_w : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region n. + * Configures the write permission in region n in REE2 mode. */ uint32_t regionn_r2_w:1; /** regionn_r2_r : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region n. + * Configures the read permission in region n in REE2 mode. */ uint32_t regionn_r2_r:1; /** regionn_lock : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region n configuration registers + * (LP_APM0_REGIONn_ADDR_START_REG, LP_APM0_REGIONn_ADDR_END_REG and + * LP_APM0_REGIONn_ATTR_REG). + * 0: Do not lock + * 1: Lock */ uint32_t regionn_lock:1; uint32_t reserved_12:20; @@ -109,15 +109,13 @@ typedef union { uint32_t val; } lp_apm0_regionn_attr_reg_t; - -/** Group: APM function control register */ /** Type of func_ctrl register - * APM function control register + * APM access path permission management register */ typedef union { struct { /** m0_func_en : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures to enable permission management for LP_APM0_CTRL M0. */ uint32_t m0_func_en:1; uint32_t reserved_1:31; @@ -126,16 +124,16 @@ typedef union { } lp_apm0_func_ctrl_reg_t; -/** Group: M0 status register */ +/** Group: Status Registers */ /** Type of m0_status register - * M0 status register + * LP_APM0_CTRL M0 status register */ typedef union { struct { /** m0_exception_status : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m0_exception_status:2; uint32_t reserved_2:30; @@ -143,15 +141,13 @@ typedef union { uint32_t val; } lp_apm0_m0_status_reg_t; - -/** Group: M0 status clear register */ /** Type of m0_status_clr register - * M0 status clear register + * LP_APM0_CTRL M0 status clear register */ typedef union { struct { /** m0_exception_status_clr : WT; bitpos: [0]; default: 0; - * Configures to clear exception status + * Configures to clear exception status. */ uint32_t m0_exception_status_clr:1; uint32_t reserved_1:31; @@ -159,24 +155,22 @@ typedef union { uint32_t val; } lp_apm0_m0_status_clr_reg_t; - -/** Group: M0 exception_info0 register */ /** Type of m0_exception_info0 register - * M0 exception_info0 register + * LP_APM0_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_region : RO; bitpos: [7:0]; default: 0; - * Represents exception region + * Represents the region where an exception occurs. */ uint32_t m0_exception_region:8; uint32_t reserved_8:8; /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode + * Represents the master's security mode when an exception occurs. */ uint32_t m0_exception_mode:2; /** m0_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information + * Represents master ID when an exception occurs. */ uint32_t m0_exception_id:5; uint32_t reserved_23:9; @@ -184,15 +178,13 @@ typedef union { uint32_t val; } lp_apm0_m0_exception_info0_reg_t; - -/** Group: M0 exception_info1 register */ /** Type of m0_exception_info1 register - * M0 exception_info1 register + * LP_APM0_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr + * Represents the access address when an exception occurs. */ uint32_t m0_exception_addr:32; }; @@ -200,16 +192,16 @@ typedef union { } lp_apm0_m0_exception_info1_reg_t; -/** Group: APM interrupt enable register */ +/** Group: Interrupt Registers */ /** Type of int_en register - * APM interrupt enable register + * LP_APM0_CTRL interrupt enable register */ typedef union { struct { /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; - * Configures APM M0 interrupt enable. - * 0: disable - * 1: enable + * Configures to enable LP_APM0_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m0_apm_int_en:1; uint32_t reserved_1:31; @@ -218,7 +210,7 @@ typedef union { } lp_apm0_int_en_reg_t; -/** Group: Clock gating register */ +/** Group: Clock Gating Registers */ /** Type of clock_gate register * Clock gating register */ @@ -226,8 +218,8 @@ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -236,14 +228,14 @@ typedef union { } lp_apm0_clock_gate_reg_t; -/** Group: Version control register */ +/** Group: Version Control Registers */ /** Type of date register * Version control register */ typedef union { struct { /** date : R/W; bitpos: [27:0]; default: 35725664; - * Version control register + * Version control register. */ uint32_t date:28; uint32_t reserved_28:4; diff --git a/components/soc/esp32c5/register/soc/lp_apm_reg.h b/components/soc/esp32c5/register/soc/lp_apm_reg.h index 9e4e42c55e..2a91284eca 100644 --- a/components/soc/esp32c5/register/soc/lp_apm_reg.h +++ b/components/soc/esp32c5/register/soc/lp_apm_reg.h @@ -12,13 +12,13 @@ extern "C" { #endif /** LP_APM_REGION_FILTER_EN_REG register - * Region filter enable register + * Region enable register */ #define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0) /** LP_APM_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1; - * Configure bit $n (0-7) to enable region $n. - * 0: disable - * 1: enable + * Configure bit $n (0-7) to enable region $n (0-7). + * 0: Disable + * 1: Enable */ #define LP_APM_REGION_FILTER_EN 0x000000FFU #define LP_APM_REGION_FILTER_EN_M (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S) @@ -30,7 +30,7 @@ extern "C" { */ #define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4) /** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 0. + * Configures the start address of region 0. */ #define LP_APM_REGION0_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION0_ADDR_START_M (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S) @@ -42,7 +42,7 @@ extern "C" { */ #define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8) /** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 0. + * Configures the end address of region 0. */ #define LP_APM_REGION0_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION0_ADDR_END_M (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S) @@ -50,74 +50,78 @@ extern "C" { #define LP_APM_REGION0_ADDR_END_S 0 /** LP_APM_REGION0_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION0_ATTR_REG (DR_REG_LP_APM_BASE + 0xc) /** LP_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 0. + * Configures the execution permission in region 0 in REE0 mode. */ #define LP_APM_REGION0_R0_X (BIT(0)) #define LP_APM_REGION0_R0_X_M (LP_APM_REGION0_R0_X_V << LP_APM_REGION0_R0_X_S) #define LP_APM_REGION0_R0_X_V 0x00000001U #define LP_APM_REGION0_R0_X_S 0 /** LP_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 0. + * Configures the write permission in region 0 in REE0 mode. */ #define LP_APM_REGION0_R0_W (BIT(1)) #define LP_APM_REGION0_R0_W_M (LP_APM_REGION0_R0_W_V << LP_APM_REGION0_R0_W_S) #define LP_APM_REGION0_R0_W_V 0x00000001U #define LP_APM_REGION0_R0_W_S 1 /** LP_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 0. + * Configures the read permission in region 0 in REE0 mode. */ #define LP_APM_REGION0_R0_R (BIT(2)) #define LP_APM_REGION0_R0_R_M (LP_APM_REGION0_R0_R_V << LP_APM_REGION0_R0_R_S) #define LP_APM_REGION0_R0_R_V 0x00000001U #define LP_APM_REGION0_R0_R_S 2 /** LP_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 0. + * Configures the execution permission in region 0 in REE1 mode. */ #define LP_APM_REGION0_R1_X (BIT(4)) #define LP_APM_REGION0_R1_X_M (LP_APM_REGION0_R1_X_V << LP_APM_REGION0_R1_X_S) #define LP_APM_REGION0_R1_X_V 0x00000001U #define LP_APM_REGION0_R1_X_S 4 /** LP_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 0. + * Configures the write permission in region 0 in REE1 mode. */ #define LP_APM_REGION0_R1_W (BIT(5)) #define LP_APM_REGION0_R1_W_M (LP_APM_REGION0_R1_W_V << LP_APM_REGION0_R1_W_S) #define LP_APM_REGION0_R1_W_V 0x00000001U #define LP_APM_REGION0_R1_W_S 5 /** LP_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 0. + * Configures the read permission in region 0 in REE1 mode. */ #define LP_APM_REGION0_R1_R (BIT(6)) #define LP_APM_REGION0_R1_R_M (LP_APM_REGION0_R1_R_V << LP_APM_REGION0_R1_R_S) #define LP_APM_REGION0_R1_R_V 0x00000001U #define LP_APM_REGION0_R1_R_S 6 /** LP_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 0. + * Configures the execution permission in region 0 in REE1 mode. */ #define LP_APM_REGION0_R2_X (BIT(8)) #define LP_APM_REGION0_R2_X_M (LP_APM_REGION0_R2_X_V << LP_APM_REGION0_R2_X_S) #define LP_APM_REGION0_R2_X_V 0x00000001U #define LP_APM_REGION0_R2_X_S 8 /** LP_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 0. + * Configures the write permission in region 0 in REE2 mode. */ #define LP_APM_REGION0_R2_W (BIT(9)) #define LP_APM_REGION0_R2_W_M (LP_APM_REGION0_R2_W_V << LP_APM_REGION0_R2_W_S) #define LP_APM_REGION0_R2_W_V 0x00000001U #define LP_APM_REGION0_R2_W_S 9 /** LP_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 0. + * Configures the read permission in region 0 in REE2 mode. */ #define LP_APM_REGION0_R2_R (BIT(10)) #define LP_APM_REGION0_R2_R_M (LP_APM_REGION0_R2_R_V << LP_APM_REGION0_R2_R_S) #define LP_APM_REGION0_R2_R_V 0x00000001U #define LP_APM_REGION0_R2_R_S 10 /** LP_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 0 configuration registers + * (LP_APM_REGION0_ADDR_START_REG, LP_APM_REGION0_ADDR_END_REG and + * LP_APM_REGION0_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION0_LOCK (BIT(11)) #define LP_APM_REGION0_LOCK_M (LP_APM_REGION0_LOCK_V << LP_APM_REGION0_LOCK_S) @@ -129,7 +133,7 @@ extern "C" { */ #define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10) /** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 1. + * Configures the start address of region 1. */ #define LP_APM_REGION1_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION1_ADDR_START_M (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S) @@ -141,7 +145,7 @@ extern "C" { */ #define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14) /** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 1. + * Configures the end address of region 1. */ #define LP_APM_REGION1_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION1_ADDR_END_M (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S) @@ -149,74 +153,78 @@ extern "C" { #define LP_APM_REGION1_ADDR_END_S 0 /** LP_APM_REGION1_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION1_ATTR_REG (DR_REG_LP_APM_BASE + 0x18) /** LP_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 1. + * Configures the execution permission in region 1 in REE0 mode. */ #define LP_APM_REGION1_R0_X (BIT(0)) #define LP_APM_REGION1_R0_X_M (LP_APM_REGION1_R0_X_V << LP_APM_REGION1_R0_X_S) #define LP_APM_REGION1_R0_X_V 0x00000001U #define LP_APM_REGION1_R0_X_S 0 /** LP_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 1. + * Configures the write permission in region 1 in REE0 mode. */ #define LP_APM_REGION1_R0_W (BIT(1)) #define LP_APM_REGION1_R0_W_M (LP_APM_REGION1_R0_W_V << LP_APM_REGION1_R0_W_S) #define LP_APM_REGION1_R0_W_V 0x00000001U #define LP_APM_REGION1_R0_W_S 1 /** LP_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 1. + * Configures the read permission in region 1 in REE0 mode. */ #define LP_APM_REGION1_R0_R (BIT(2)) #define LP_APM_REGION1_R0_R_M (LP_APM_REGION1_R0_R_V << LP_APM_REGION1_R0_R_S) #define LP_APM_REGION1_R0_R_V 0x00000001U #define LP_APM_REGION1_R0_R_S 2 /** LP_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 1. + * Configures the execution permission in region 1 in REE1 mode. */ #define LP_APM_REGION1_R1_X (BIT(4)) #define LP_APM_REGION1_R1_X_M (LP_APM_REGION1_R1_X_V << LP_APM_REGION1_R1_X_S) #define LP_APM_REGION1_R1_X_V 0x00000001U #define LP_APM_REGION1_R1_X_S 4 /** LP_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 1. + * Configures the write permission in region 1 in REE1 mode. */ #define LP_APM_REGION1_R1_W (BIT(5)) #define LP_APM_REGION1_R1_W_M (LP_APM_REGION1_R1_W_V << LP_APM_REGION1_R1_W_S) #define LP_APM_REGION1_R1_W_V 0x00000001U #define LP_APM_REGION1_R1_W_S 5 /** LP_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 1. + * Configures the read permission in region 1 in REE1 mode. */ #define LP_APM_REGION1_R1_R (BIT(6)) #define LP_APM_REGION1_R1_R_M (LP_APM_REGION1_R1_R_V << LP_APM_REGION1_R1_R_S) #define LP_APM_REGION1_R1_R_V 0x00000001U #define LP_APM_REGION1_R1_R_S 6 /** LP_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 1. + * Configures the execution permission in region 1 in REE1 mode. */ #define LP_APM_REGION1_R2_X (BIT(8)) #define LP_APM_REGION1_R2_X_M (LP_APM_REGION1_R2_X_V << LP_APM_REGION1_R2_X_S) #define LP_APM_REGION1_R2_X_V 0x00000001U #define LP_APM_REGION1_R2_X_S 8 /** LP_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 1. + * Configures the write permission in region 1 in REE2 mode. */ #define LP_APM_REGION1_R2_W (BIT(9)) #define LP_APM_REGION1_R2_W_M (LP_APM_REGION1_R2_W_V << LP_APM_REGION1_R2_W_S) #define LP_APM_REGION1_R2_W_V 0x00000001U #define LP_APM_REGION1_R2_W_S 9 /** LP_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 1. + * Configures the read permission in region 1 in REE2 mode. */ #define LP_APM_REGION1_R2_R (BIT(10)) #define LP_APM_REGION1_R2_R_M (LP_APM_REGION1_R2_R_V << LP_APM_REGION1_R2_R_S) #define LP_APM_REGION1_R2_R_V 0x00000001U #define LP_APM_REGION1_R2_R_S 10 /** LP_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 1 configuration registers + * (LP_APM_REGION1_ADDR_START_REG, LP_APM_REGION1_ADDR_END_REG and + * LP_APM_REGION1_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION1_LOCK (BIT(11)) #define LP_APM_REGION1_LOCK_M (LP_APM_REGION1_LOCK_V << LP_APM_REGION1_LOCK_S) @@ -228,7 +236,7 @@ extern "C" { */ #define LP_APM_REGION2_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x1c) /** LP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 2. + * Configures the start address of region 2. */ #define LP_APM_REGION2_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION2_ADDR_START_M (LP_APM_REGION2_ADDR_START_V << LP_APM_REGION2_ADDR_START_S) @@ -240,7 +248,7 @@ extern "C" { */ #define LP_APM_REGION2_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x20) /** LP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 2. + * Configures the end address of region 2. */ #define LP_APM_REGION2_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION2_ADDR_END_M (LP_APM_REGION2_ADDR_END_V << LP_APM_REGION2_ADDR_END_S) @@ -248,74 +256,78 @@ extern "C" { #define LP_APM_REGION2_ADDR_END_S 0 /** LP_APM_REGION2_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION2_ATTR_REG (DR_REG_LP_APM_BASE + 0x24) /** LP_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 2. + * Configures the execution permission in region 2 in REE0 mode. */ #define LP_APM_REGION2_R0_X (BIT(0)) #define LP_APM_REGION2_R0_X_M (LP_APM_REGION2_R0_X_V << LP_APM_REGION2_R0_X_S) #define LP_APM_REGION2_R0_X_V 0x00000001U #define LP_APM_REGION2_R0_X_S 0 /** LP_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 2. + * Configures the write permission in region 2 in REE0 mode. */ #define LP_APM_REGION2_R0_W (BIT(1)) #define LP_APM_REGION2_R0_W_M (LP_APM_REGION2_R0_W_V << LP_APM_REGION2_R0_W_S) #define LP_APM_REGION2_R0_W_V 0x00000001U #define LP_APM_REGION2_R0_W_S 1 /** LP_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 2. + * Configures the read permission in region 2 in REE0 mode. */ #define LP_APM_REGION2_R0_R (BIT(2)) #define LP_APM_REGION2_R0_R_M (LP_APM_REGION2_R0_R_V << LP_APM_REGION2_R0_R_S) #define LP_APM_REGION2_R0_R_V 0x00000001U #define LP_APM_REGION2_R0_R_S 2 /** LP_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 2. + * Configures the execution permission in region 2 in REE1 mode. */ #define LP_APM_REGION2_R1_X (BIT(4)) #define LP_APM_REGION2_R1_X_M (LP_APM_REGION2_R1_X_V << LP_APM_REGION2_R1_X_S) #define LP_APM_REGION2_R1_X_V 0x00000001U #define LP_APM_REGION2_R1_X_S 4 /** LP_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 2. + * Configures the write permission in region 2 in REE1 mode. */ #define LP_APM_REGION2_R1_W (BIT(5)) #define LP_APM_REGION2_R1_W_M (LP_APM_REGION2_R1_W_V << LP_APM_REGION2_R1_W_S) #define LP_APM_REGION2_R1_W_V 0x00000001U #define LP_APM_REGION2_R1_W_S 5 /** LP_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 2. + * Configures the read permission in region 2 in REE1 mode. */ #define LP_APM_REGION2_R1_R (BIT(6)) #define LP_APM_REGION2_R1_R_M (LP_APM_REGION2_R1_R_V << LP_APM_REGION2_R1_R_S) #define LP_APM_REGION2_R1_R_V 0x00000001U #define LP_APM_REGION2_R1_R_S 6 /** LP_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 2. + * Configures the execution permission in region 2 in REE1 mode. */ #define LP_APM_REGION2_R2_X (BIT(8)) #define LP_APM_REGION2_R2_X_M (LP_APM_REGION2_R2_X_V << LP_APM_REGION2_R2_X_S) #define LP_APM_REGION2_R2_X_V 0x00000001U #define LP_APM_REGION2_R2_X_S 8 /** LP_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 2. + * Configures the write permission in region 2 in REE2 mode. */ #define LP_APM_REGION2_R2_W (BIT(9)) #define LP_APM_REGION2_R2_W_M (LP_APM_REGION2_R2_W_V << LP_APM_REGION2_R2_W_S) #define LP_APM_REGION2_R2_W_V 0x00000001U #define LP_APM_REGION2_R2_W_S 9 /** LP_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 2. + * Configures the read permission in region 2 in REE2 mode. */ #define LP_APM_REGION2_R2_R (BIT(10)) #define LP_APM_REGION2_R2_R_M (LP_APM_REGION2_R2_R_V << LP_APM_REGION2_R2_R_S) #define LP_APM_REGION2_R2_R_V 0x00000001U #define LP_APM_REGION2_R2_R_S 10 /** LP_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 2 configuration registers + * (LP_APM_REGION2_ADDR_START_REG, LP_APM_REGION2_ADDR_END_REG and + * LP_APM_REGION2_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION2_LOCK (BIT(11)) #define LP_APM_REGION2_LOCK_M (LP_APM_REGION2_LOCK_V << LP_APM_REGION2_LOCK_S) @@ -327,7 +339,7 @@ extern "C" { */ #define LP_APM_REGION3_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x28) /** LP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 3. + * Configures the start address of region 3. */ #define LP_APM_REGION3_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION3_ADDR_START_M (LP_APM_REGION3_ADDR_START_V << LP_APM_REGION3_ADDR_START_S) @@ -339,7 +351,7 @@ extern "C" { */ #define LP_APM_REGION3_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x2c) /** LP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 3. + * Configures the end address of region 3. */ #define LP_APM_REGION3_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION3_ADDR_END_M (LP_APM_REGION3_ADDR_END_V << LP_APM_REGION3_ADDR_END_S) @@ -347,74 +359,78 @@ extern "C" { #define LP_APM_REGION3_ADDR_END_S 0 /** LP_APM_REGION3_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION3_ATTR_REG (DR_REG_LP_APM_BASE + 0x30) /** LP_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 3. + * Configures the execution permission in region 3 in REE0 mode. */ #define LP_APM_REGION3_R0_X (BIT(0)) #define LP_APM_REGION3_R0_X_M (LP_APM_REGION3_R0_X_V << LP_APM_REGION3_R0_X_S) #define LP_APM_REGION3_R0_X_V 0x00000001U #define LP_APM_REGION3_R0_X_S 0 /** LP_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 3. + * Configures the write permission in region 3 in REE0 mode. */ #define LP_APM_REGION3_R0_W (BIT(1)) #define LP_APM_REGION3_R0_W_M (LP_APM_REGION3_R0_W_V << LP_APM_REGION3_R0_W_S) #define LP_APM_REGION3_R0_W_V 0x00000001U #define LP_APM_REGION3_R0_W_S 1 /** LP_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 3. + * Configures the read permission in region 3 in REE0 mode. */ #define LP_APM_REGION3_R0_R (BIT(2)) #define LP_APM_REGION3_R0_R_M (LP_APM_REGION3_R0_R_V << LP_APM_REGION3_R0_R_S) #define LP_APM_REGION3_R0_R_V 0x00000001U #define LP_APM_REGION3_R0_R_S 2 /** LP_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 3. + * Configures the execution permission in region 3 in REE1 mode. */ #define LP_APM_REGION3_R1_X (BIT(4)) #define LP_APM_REGION3_R1_X_M (LP_APM_REGION3_R1_X_V << LP_APM_REGION3_R1_X_S) #define LP_APM_REGION3_R1_X_V 0x00000001U #define LP_APM_REGION3_R1_X_S 4 /** LP_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 3. + * Configures the write permission in region 3 in REE1 mode. */ #define LP_APM_REGION3_R1_W (BIT(5)) #define LP_APM_REGION3_R1_W_M (LP_APM_REGION3_R1_W_V << LP_APM_REGION3_R1_W_S) #define LP_APM_REGION3_R1_W_V 0x00000001U #define LP_APM_REGION3_R1_W_S 5 /** LP_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 3. + * Configures the read permission in region 3 in REE1 mode. */ #define LP_APM_REGION3_R1_R (BIT(6)) #define LP_APM_REGION3_R1_R_M (LP_APM_REGION3_R1_R_V << LP_APM_REGION3_R1_R_S) #define LP_APM_REGION3_R1_R_V 0x00000001U #define LP_APM_REGION3_R1_R_S 6 /** LP_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 3. + * Configures the execution permission in region 3 in REE1 mode. */ #define LP_APM_REGION3_R2_X (BIT(8)) #define LP_APM_REGION3_R2_X_M (LP_APM_REGION3_R2_X_V << LP_APM_REGION3_R2_X_S) #define LP_APM_REGION3_R2_X_V 0x00000001U #define LP_APM_REGION3_R2_X_S 8 /** LP_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 3. + * Configures the write permission in region 3 in REE2 mode. */ #define LP_APM_REGION3_R2_W (BIT(9)) #define LP_APM_REGION3_R2_W_M (LP_APM_REGION3_R2_W_V << LP_APM_REGION3_R2_W_S) #define LP_APM_REGION3_R2_W_V 0x00000001U #define LP_APM_REGION3_R2_W_S 9 /** LP_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 3. + * Configures the read permission in region 3 in REE2 mode. */ #define LP_APM_REGION3_R2_R (BIT(10)) #define LP_APM_REGION3_R2_R_M (LP_APM_REGION3_R2_R_V << LP_APM_REGION3_R2_R_S) #define LP_APM_REGION3_R2_R_V 0x00000001U #define LP_APM_REGION3_R2_R_S 10 /** LP_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 3 configuration registers + * (LP_APM_REGION3_ADDR_START_REG, LP_APM_REGION3_ADDR_END_REG and + * LP_APM_REGION3_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION3_LOCK (BIT(11)) #define LP_APM_REGION3_LOCK_M (LP_APM_REGION3_LOCK_V << LP_APM_REGION3_LOCK_S) @@ -426,7 +442,7 @@ extern "C" { */ #define LP_APM_REGION4_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x34) /** LP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 4. + * Configures the start address of region 4. */ #define LP_APM_REGION4_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION4_ADDR_START_M (LP_APM_REGION4_ADDR_START_V << LP_APM_REGION4_ADDR_START_S) @@ -438,7 +454,7 @@ extern "C" { */ #define LP_APM_REGION4_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x38) /** LP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 4. + * Configures the end address of region 4. */ #define LP_APM_REGION4_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION4_ADDR_END_M (LP_APM_REGION4_ADDR_END_V << LP_APM_REGION4_ADDR_END_S) @@ -446,74 +462,78 @@ extern "C" { #define LP_APM_REGION4_ADDR_END_S 0 /** LP_APM_REGION4_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION4_ATTR_REG (DR_REG_LP_APM_BASE + 0x3c) /** LP_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 4. + * Configures the execution permission in region 4 in REE0 mode. */ #define LP_APM_REGION4_R0_X (BIT(0)) #define LP_APM_REGION4_R0_X_M (LP_APM_REGION4_R0_X_V << LP_APM_REGION4_R0_X_S) #define LP_APM_REGION4_R0_X_V 0x00000001U #define LP_APM_REGION4_R0_X_S 0 /** LP_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 4. + * Configures the write permission in region 4 in REE0 mode. */ #define LP_APM_REGION4_R0_W (BIT(1)) #define LP_APM_REGION4_R0_W_M (LP_APM_REGION4_R0_W_V << LP_APM_REGION4_R0_W_S) #define LP_APM_REGION4_R0_W_V 0x00000001U #define LP_APM_REGION4_R0_W_S 1 /** LP_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 4. + * Configures the read permission in region 4 in REE0 mode. */ #define LP_APM_REGION4_R0_R (BIT(2)) #define LP_APM_REGION4_R0_R_M (LP_APM_REGION4_R0_R_V << LP_APM_REGION4_R0_R_S) #define LP_APM_REGION4_R0_R_V 0x00000001U #define LP_APM_REGION4_R0_R_S 2 /** LP_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 4. + * Configures the execution permission in region 4 in REE1 mode. */ #define LP_APM_REGION4_R1_X (BIT(4)) #define LP_APM_REGION4_R1_X_M (LP_APM_REGION4_R1_X_V << LP_APM_REGION4_R1_X_S) #define LP_APM_REGION4_R1_X_V 0x00000001U #define LP_APM_REGION4_R1_X_S 4 /** LP_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 4. + * Configures the write permission in region 4 in REE1 mode. */ #define LP_APM_REGION4_R1_W (BIT(5)) #define LP_APM_REGION4_R1_W_M (LP_APM_REGION4_R1_W_V << LP_APM_REGION4_R1_W_S) #define LP_APM_REGION4_R1_W_V 0x00000001U #define LP_APM_REGION4_R1_W_S 5 /** LP_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 4. + * Configures the read permission in region 4 in REE1 mode. */ #define LP_APM_REGION4_R1_R (BIT(6)) #define LP_APM_REGION4_R1_R_M (LP_APM_REGION4_R1_R_V << LP_APM_REGION4_R1_R_S) #define LP_APM_REGION4_R1_R_V 0x00000001U #define LP_APM_REGION4_R1_R_S 6 /** LP_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 4. + * Configures the execution permission in region 4 in REE1 mode. */ #define LP_APM_REGION4_R2_X (BIT(8)) #define LP_APM_REGION4_R2_X_M (LP_APM_REGION4_R2_X_V << LP_APM_REGION4_R2_X_S) #define LP_APM_REGION4_R2_X_V 0x00000001U #define LP_APM_REGION4_R2_X_S 8 /** LP_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 4. + * Configures the write permission in region 4 in REE2 mode. */ #define LP_APM_REGION4_R2_W (BIT(9)) #define LP_APM_REGION4_R2_W_M (LP_APM_REGION4_R2_W_V << LP_APM_REGION4_R2_W_S) #define LP_APM_REGION4_R2_W_V 0x00000001U #define LP_APM_REGION4_R2_W_S 9 /** LP_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 4. + * Configures the read permission in region 4 in REE2 mode. */ #define LP_APM_REGION4_R2_R (BIT(10)) #define LP_APM_REGION4_R2_R_M (LP_APM_REGION4_R2_R_V << LP_APM_REGION4_R2_R_S) #define LP_APM_REGION4_R2_R_V 0x00000001U #define LP_APM_REGION4_R2_R_S 10 /** LP_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 4 configuration registers + * (LP_APM_REGION4_ADDR_START_REG, LP_APM_REGION4_ADDR_END_REG and + * LP_APM_REGION4_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION4_LOCK (BIT(11)) #define LP_APM_REGION4_LOCK_M (LP_APM_REGION4_LOCK_V << LP_APM_REGION4_LOCK_S) @@ -525,7 +545,7 @@ extern "C" { */ #define LP_APM_REGION5_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x40) /** LP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 5. + * Configures the start address of region 5. */ #define LP_APM_REGION5_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION5_ADDR_START_M (LP_APM_REGION5_ADDR_START_V << LP_APM_REGION5_ADDR_START_S) @@ -537,7 +557,7 @@ extern "C" { */ #define LP_APM_REGION5_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x44) /** LP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 5. + * Configures the end address of region 5. */ #define LP_APM_REGION5_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION5_ADDR_END_M (LP_APM_REGION5_ADDR_END_V << LP_APM_REGION5_ADDR_END_S) @@ -545,74 +565,78 @@ extern "C" { #define LP_APM_REGION5_ADDR_END_S 0 /** LP_APM_REGION5_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION5_ATTR_REG (DR_REG_LP_APM_BASE + 0x48) /** LP_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 5. + * Configures the execution permission in region 5 in REE0 mode. */ #define LP_APM_REGION5_R0_X (BIT(0)) #define LP_APM_REGION5_R0_X_M (LP_APM_REGION5_R0_X_V << LP_APM_REGION5_R0_X_S) #define LP_APM_REGION5_R0_X_V 0x00000001U #define LP_APM_REGION5_R0_X_S 0 /** LP_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 5. + * Configures the write permission in region 5 in REE0 mode. */ #define LP_APM_REGION5_R0_W (BIT(1)) #define LP_APM_REGION5_R0_W_M (LP_APM_REGION5_R0_W_V << LP_APM_REGION5_R0_W_S) #define LP_APM_REGION5_R0_W_V 0x00000001U #define LP_APM_REGION5_R0_W_S 1 /** LP_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 5. + * Configures the read permission in region 5 in REE0 mode. */ #define LP_APM_REGION5_R0_R (BIT(2)) #define LP_APM_REGION5_R0_R_M (LP_APM_REGION5_R0_R_V << LP_APM_REGION5_R0_R_S) #define LP_APM_REGION5_R0_R_V 0x00000001U #define LP_APM_REGION5_R0_R_S 2 /** LP_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 5. + * Configures the execution permission in region 5 in REE1 mode. */ #define LP_APM_REGION5_R1_X (BIT(4)) #define LP_APM_REGION5_R1_X_M (LP_APM_REGION5_R1_X_V << LP_APM_REGION5_R1_X_S) #define LP_APM_REGION5_R1_X_V 0x00000001U #define LP_APM_REGION5_R1_X_S 4 /** LP_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 5. + * Configures the write permission in region 5 in REE1 mode. */ #define LP_APM_REGION5_R1_W (BIT(5)) #define LP_APM_REGION5_R1_W_M (LP_APM_REGION5_R1_W_V << LP_APM_REGION5_R1_W_S) #define LP_APM_REGION5_R1_W_V 0x00000001U #define LP_APM_REGION5_R1_W_S 5 /** LP_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 5. + * Configures the read permission in region 5 in REE1 mode. */ #define LP_APM_REGION5_R1_R (BIT(6)) #define LP_APM_REGION5_R1_R_M (LP_APM_REGION5_R1_R_V << LP_APM_REGION5_R1_R_S) #define LP_APM_REGION5_R1_R_V 0x00000001U #define LP_APM_REGION5_R1_R_S 6 /** LP_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 5. + * Configures the execution permission in region 5 in REE1 mode. */ #define LP_APM_REGION5_R2_X (BIT(8)) #define LP_APM_REGION5_R2_X_M (LP_APM_REGION5_R2_X_V << LP_APM_REGION5_R2_X_S) #define LP_APM_REGION5_R2_X_V 0x00000001U #define LP_APM_REGION5_R2_X_S 8 /** LP_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 5. + * Configures the write permission in region 5 in REE2 mode. */ #define LP_APM_REGION5_R2_W (BIT(9)) #define LP_APM_REGION5_R2_W_M (LP_APM_REGION5_R2_W_V << LP_APM_REGION5_R2_W_S) #define LP_APM_REGION5_R2_W_V 0x00000001U #define LP_APM_REGION5_R2_W_S 9 /** LP_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 5. + * Configures the read permission in region 5 in REE2 mode. */ #define LP_APM_REGION5_R2_R (BIT(10)) #define LP_APM_REGION5_R2_R_M (LP_APM_REGION5_R2_R_V << LP_APM_REGION5_R2_R_S) #define LP_APM_REGION5_R2_R_V 0x00000001U #define LP_APM_REGION5_R2_R_S 10 /** LP_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 5 configuration registers + * (LP_APM_REGION5_ADDR_START_REG, LP_APM_REGION5_ADDR_END_REG and + * LP_APM_REGION5_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION5_LOCK (BIT(11)) #define LP_APM_REGION5_LOCK_M (LP_APM_REGION5_LOCK_V << LP_APM_REGION5_LOCK_S) @@ -624,7 +648,7 @@ extern "C" { */ #define LP_APM_REGION6_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4c) /** LP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 6. + * Configures the start address of region 6. */ #define LP_APM_REGION6_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION6_ADDR_START_M (LP_APM_REGION6_ADDR_START_V << LP_APM_REGION6_ADDR_START_S) @@ -636,7 +660,7 @@ extern "C" { */ #define LP_APM_REGION6_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x50) /** LP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 6. + * Configures the end address of region 6. */ #define LP_APM_REGION6_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION6_ADDR_END_M (LP_APM_REGION6_ADDR_END_V << LP_APM_REGION6_ADDR_END_S) @@ -644,74 +668,78 @@ extern "C" { #define LP_APM_REGION6_ADDR_END_S 0 /** LP_APM_REGION6_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION6_ATTR_REG (DR_REG_LP_APM_BASE + 0x54) /** LP_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 6. + * Configures the execution permission in region 6 in REE0 mode. */ #define LP_APM_REGION6_R0_X (BIT(0)) #define LP_APM_REGION6_R0_X_M (LP_APM_REGION6_R0_X_V << LP_APM_REGION6_R0_X_S) #define LP_APM_REGION6_R0_X_V 0x00000001U #define LP_APM_REGION6_R0_X_S 0 /** LP_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 6. + * Configures the write permission in region 6 in REE0 mode. */ #define LP_APM_REGION6_R0_W (BIT(1)) #define LP_APM_REGION6_R0_W_M (LP_APM_REGION6_R0_W_V << LP_APM_REGION6_R0_W_S) #define LP_APM_REGION6_R0_W_V 0x00000001U #define LP_APM_REGION6_R0_W_S 1 /** LP_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 6. + * Configures the read permission in region 6 in REE0 mode. */ #define LP_APM_REGION6_R0_R (BIT(2)) #define LP_APM_REGION6_R0_R_M (LP_APM_REGION6_R0_R_V << LP_APM_REGION6_R0_R_S) #define LP_APM_REGION6_R0_R_V 0x00000001U #define LP_APM_REGION6_R0_R_S 2 /** LP_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 6. + * Configures the execution permission in region 6 in REE1 mode. */ #define LP_APM_REGION6_R1_X (BIT(4)) #define LP_APM_REGION6_R1_X_M (LP_APM_REGION6_R1_X_V << LP_APM_REGION6_R1_X_S) #define LP_APM_REGION6_R1_X_V 0x00000001U #define LP_APM_REGION6_R1_X_S 4 /** LP_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 6. + * Configures the write permission in region 6 in REE1 mode. */ #define LP_APM_REGION6_R1_W (BIT(5)) #define LP_APM_REGION6_R1_W_M (LP_APM_REGION6_R1_W_V << LP_APM_REGION6_R1_W_S) #define LP_APM_REGION6_R1_W_V 0x00000001U #define LP_APM_REGION6_R1_W_S 5 /** LP_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 6. + * Configures the read permission in region 6 in REE1 mode. */ #define LP_APM_REGION6_R1_R (BIT(6)) #define LP_APM_REGION6_R1_R_M (LP_APM_REGION6_R1_R_V << LP_APM_REGION6_R1_R_S) #define LP_APM_REGION6_R1_R_V 0x00000001U #define LP_APM_REGION6_R1_R_S 6 /** LP_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 6. + * Configures the execution permission in region 6 in REE1 mode. */ #define LP_APM_REGION6_R2_X (BIT(8)) #define LP_APM_REGION6_R2_X_M (LP_APM_REGION6_R2_X_V << LP_APM_REGION6_R2_X_S) #define LP_APM_REGION6_R2_X_V 0x00000001U #define LP_APM_REGION6_R2_X_S 8 /** LP_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 6. + * Configures the write permission in region 6 in REE2 mode. */ #define LP_APM_REGION6_R2_W (BIT(9)) #define LP_APM_REGION6_R2_W_M (LP_APM_REGION6_R2_W_V << LP_APM_REGION6_R2_W_S) #define LP_APM_REGION6_R2_W_V 0x00000001U #define LP_APM_REGION6_R2_W_S 9 /** LP_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 6. + * Configures the read permission in region 6 in REE2 mode. */ #define LP_APM_REGION6_R2_R (BIT(10)) #define LP_APM_REGION6_R2_R_M (LP_APM_REGION6_R2_R_V << LP_APM_REGION6_R2_R_S) #define LP_APM_REGION6_R2_R_V 0x00000001U #define LP_APM_REGION6_R2_R_S 10 /** LP_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 6 configuration registers + * (LP_APM_REGION6_ADDR_START_REG, LP_APM_REGION6_ADDR_END_REG and + * LP_APM_REGION6_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION6_LOCK (BIT(11)) #define LP_APM_REGION6_LOCK_M (LP_APM_REGION6_LOCK_V << LP_APM_REGION6_LOCK_S) @@ -723,7 +751,7 @@ extern "C" { */ #define LP_APM_REGION7_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x58) /** LP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 7. + * Configures the start address of region 7. */ #define LP_APM_REGION7_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION7_ADDR_START_M (LP_APM_REGION7_ADDR_START_V << LP_APM_REGION7_ADDR_START_S) @@ -735,7 +763,7 @@ extern "C" { */ #define LP_APM_REGION7_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x5c) /** LP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 7. + * Configures the end address of region 7. */ #define LP_APM_REGION7_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION7_ADDR_END_M (LP_APM_REGION7_ADDR_END_V << LP_APM_REGION7_ADDR_END_S) @@ -743,74 +771,78 @@ extern "C" { #define LP_APM_REGION7_ADDR_END_S 0 /** LP_APM_REGION7_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION7_ATTR_REG (DR_REG_LP_APM_BASE + 0x60) /** LP_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 7. + * Configures the execution permission in region 7 in REE0 mode. */ #define LP_APM_REGION7_R0_X (BIT(0)) #define LP_APM_REGION7_R0_X_M (LP_APM_REGION7_R0_X_V << LP_APM_REGION7_R0_X_S) #define LP_APM_REGION7_R0_X_V 0x00000001U #define LP_APM_REGION7_R0_X_S 0 /** LP_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 7. + * Configures the write permission in region 7 in REE0 mode. */ #define LP_APM_REGION7_R0_W (BIT(1)) #define LP_APM_REGION7_R0_W_M (LP_APM_REGION7_R0_W_V << LP_APM_REGION7_R0_W_S) #define LP_APM_REGION7_R0_W_V 0x00000001U #define LP_APM_REGION7_R0_W_S 1 /** LP_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 7. + * Configures the read permission in region 7 in REE0 mode. */ #define LP_APM_REGION7_R0_R (BIT(2)) #define LP_APM_REGION7_R0_R_M (LP_APM_REGION7_R0_R_V << LP_APM_REGION7_R0_R_S) #define LP_APM_REGION7_R0_R_V 0x00000001U #define LP_APM_REGION7_R0_R_S 2 /** LP_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 7. + * Configures the execution permission in region 7 in REE1 mode. */ #define LP_APM_REGION7_R1_X (BIT(4)) #define LP_APM_REGION7_R1_X_M (LP_APM_REGION7_R1_X_V << LP_APM_REGION7_R1_X_S) #define LP_APM_REGION7_R1_X_V 0x00000001U #define LP_APM_REGION7_R1_X_S 4 /** LP_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 7. + * Configures the write permission in region 7 in REE1 mode. */ #define LP_APM_REGION7_R1_W (BIT(5)) #define LP_APM_REGION7_R1_W_M (LP_APM_REGION7_R1_W_V << LP_APM_REGION7_R1_W_S) #define LP_APM_REGION7_R1_W_V 0x00000001U #define LP_APM_REGION7_R1_W_S 5 /** LP_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 7. + * Configures the read permission in region 7 in REE1 mode. */ #define LP_APM_REGION7_R1_R (BIT(6)) #define LP_APM_REGION7_R1_R_M (LP_APM_REGION7_R1_R_V << LP_APM_REGION7_R1_R_S) #define LP_APM_REGION7_R1_R_V 0x00000001U #define LP_APM_REGION7_R1_R_S 6 /** LP_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 7. + * Configures the execution permission in region 7 in REE1 mode. */ #define LP_APM_REGION7_R2_X (BIT(8)) #define LP_APM_REGION7_R2_X_M (LP_APM_REGION7_R2_X_V << LP_APM_REGION7_R2_X_S) #define LP_APM_REGION7_R2_X_V 0x00000001U #define LP_APM_REGION7_R2_X_S 8 /** LP_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 7. + * Configures the write permission in region 7 in REE2 mode. */ #define LP_APM_REGION7_R2_W (BIT(9)) #define LP_APM_REGION7_R2_W_M (LP_APM_REGION7_R2_W_V << LP_APM_REGION7_R2_W_S) #define LP_APM_REGION7_R2_W_V 0x00000001U #define LP_APM_REGION7_R2_W_S 9 /** LP_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 7. + * Configures the read permission in region 7 in REE2 mode. */ #define LP_APM_REGION7_R2_R (BIT(10)) #define LP_APM_REGION7_R2_R_M (LP_APM_REGION7_R2_R_V << LP_APM_REGION7_R2_R_S) #define LP_APM_REGION7_R2_R_V 0x00000001U #define LP_APM_REGION7_R2_R_S 10 /** LP_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 7 configuration registers + * (LP_APM_REGION7_ADDR_START_REG, LP_APM_REGION7_ADDR_END_REG and + * LP_APM_REGION7_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION7_LOCK (BIT(11)) #define LP_APM_REGION7_LOCK_M (LP_APM_REGION7_LOCK_V << LP_APM_REGION7_LOCK_S) @@ -818,18 +850,18 @@ extern "C" { #define LP_APM_REGION7_LOCK_S 11 /** LP_APM_FUNC_CTRL_REG register - * APM function control register + * APM access path permission management register */ #define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4) /** LP_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures to enable permission management for LP_APM_CTRL M0. */ #define LP_APM_M0_FUNC_EN (BIT(0)) #define LP_APM_M0_FUNC_EN_M (LP_APM_M0_FUNC_EN_V << LP_APM_M0_FUNC_EN_S) #define LP_APM_M0_FUNC_EN_V 0x00000001U #define LP_APM_M0_FUNC_EN_S 0 /** LP_APM_M1_FUNC_EN : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable + * Configures to enable permission management for LP_APM_CTRL M1. */ #define LP_APM_M1_FUNC_EN (BIT(1)) #define LP_APM_M1_FUNC_EN_M (LP_APM_M1_FUNC_EN_V << LP_APM_M1_FUNC_EN_S) @@ -837,13 +869,13 @@ extern "C" { #define LP_APM_M1_FUNC_EN_S 1 /** LP_APM_M0_STATUS_REG register - * M0 status register + * LP_APM_CTRL M0 status register */ #define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8) /** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define LP_APM_M0_EXCEPTION_STATUS 0x00000003U #define LP_APM_M0_EXCEPTION_STATUS_M (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S) @@ -851,7 +883,7 @@ extern "C" { #define LP_APM_M0_EXCEPTION_STATUS_S 0 /** LP_APM_M0_STATUS_CLR_REG register - * M0 status clear register + * LP_APM_CTRL M0 status clear register */ #define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc) /** LP_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -863,25 +895,25 @@ extern "C" { #define LP_APM_M0_EXCEPTION_STATUS_CLR_S 0 /** LP_APM_M0_EXCEPTION_INFO0_REG register - * M0 exception_info0 register + * LP_APM_CTRL M0 exception information register */ #define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0) /** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define LP_APM_M0_EXCEPTION_REGION 0x000000FFU #define LP_APM_M0_EXCEPTION_REGION_M (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S) #define LP_APM_M0_EXCEPTION_REGION_V 0x000000FFU #define LP_APM_M0_EXCEPTION_REGION_S 0 /** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define LP_APM_M0_EXCEPTION_MODE 0x00000003U #define LP_APM_M0_EXCEPTION_MODE_M (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S) #define LP_APM_M0_EXCEPTION_MODE_V 0x00000003U #define LP_APM_M0_EXCEPTION_MODE_S 16 /** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define LP_APM_M0_EXCEPTION_ID 0x0000001FU #define LP_APM_M0_EXCEPTION_ID_M (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S) @@ -889,11 +921,11 @@ extern "C" { #define LP_APM_M0_EXCEPTION_ID_S 18 /** LP_APM_M0_EXCEPTION_INFO1_REG register - * M0 exception_info1 register + * LP_APM_CTRL M0 exception information register */ #define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4) /** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define LP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU #define LP_APM_M0_EXCEPTION_ADDR_M (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S) @@ -901,13 +933,13 @@ extern "C" { #define LP_APM_M0_EXCEPTION_ADDR_S 0 /** LP_APM_M1_STATUS_REG register - * M1 status register + * LP_APM_CTRL M1 status register */ #define LP_APM_M1_STATUS_REG (DR_REG_LP_APM_BASE + 0xd8) /** LP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define LP_APM_M1_EXCEPTION_STATUS 0x00000003U #define LP_APM_M1_EXCEPTION_STATUS_M (LP_APM_M1_EXCEPTION_STATUS_V << LP_APM_M1_EXCEPTION_STATUS_S) @@ -915,7 +947,7 @@ extern "C" { #define LP_APM_M1_EXCEPTION_STATUS_S 0 /** LP_APM_M1_STATUS_CLR_REG register - * M1 status clear register + * LP_APM_CTRL M1 status clear register */ #define LP_APM_M1_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xdc) /** LP_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -927,25 +959,25 @@ extern "C" { #define LP_APM_M1_EXCEPTION_STATUS_CLR_S 0 /** LP_APM_M1_EXCEPTION_INFO0_REG register - * M1 exception_info0 register + * LP_APM_CTRL M1 exception information register */ #define LP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xe0) /** LP_APM_M1_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define LP_APM_M1_EXCEPTION_REGION 0x000000FFU #define LP_APM_M1_EXCEPTION_REGION_M (LP_APM_M1_EXCEPTION_REGION_V << LP_APM_M1_EXCEPTION_REGION_S) #define LP_APM_M1_EXCEPTION_REGION_V 0x000000FFU #define LP_APM_M1_EXCEPTION_REGION_S 0 /** LP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define LP_APM_M1_EXCEPTION_MODE 0x00000003U #define LP_APM_M1_EXCEPTION_MODE_M (LP_APM_M1_EXCEPTION_MODE_V << LP_APM_M1_EXCEPTION_MODE_S) #define LP_APM_M1_EXCEPTION_MODE_V 0x00000003U #define LP_APM_M1_EXCEPTION_MODE_S 16 /** LP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define LP_APM_M1_EXCEPTION_ID 0x0000001FU #define LP_APM_M1_EXCEPTION_ID_M (LP_APM_M1_EXCEPTION_ID_V << LP_APM_M1_EXCEPTION_ID_S) @@ -953,11 +985,11 @@ extern "C" { #define LP_APM_M1_EXCEPTION_ID_S 18 /** LP_APM_M1_EXCEPTION_INFO1_REG register - * M1 exception_info1 register + * LP_APM_CTRL M1 exception information register */ #define LP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xe4) /** LP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define LP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU #define LP_APM_M1_EXCEPTION_ADDR_M (LP_APM_M1_EXCEPTION_ADDR_V << LP_APM_M1_EXCEPTION_ADDR_S) @@ -965,22 +997,22 @@ extern "C" { #define LP_APM_M1_EXCEPTION_ADDR_S 0 /** LP_APM_INT_EN_REG register - * APM interrupt enable register + * LP_APM_CTRL M0/1 interrupt enable register */ #define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8) /** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; - * Configures to enable APM M0 interrupt. - * 0: disable - * 1: enable + * Configures to enable LP_APM_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ #define LP_APM_M0_APM_INT_EN (BIT(0)) #define LP_APM_M0_APM_INT_EN_M (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S) #define LP_APM_M0_APM_INT_EN_V 0x00000001U #define LP_APM_M0_APM_INT_EN_S 0 /** LP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; - * Configures to enable APM M1 interrupt. - * 0: disable - * 1: enable + * Configures to enable LP_APM_CTRL M1 interrupt. + * 0: Disable + * 1: Enable */ #define LP_APM_M1_APM_INT_EN (BIT(1)) #define LP_APM_M1_APM_INT_EN_M (LP_APM_M1_APM_INT_EN_V << LP_APM_M1_APM_INT_EN_S) @@ -988,13 +1020,13 @@ extern "C" { #define LP_APM_M1_APM_INT_EN_S 1 /** LP_APM_CLOCK_GATE_REG register - * clock gating register + * Clock gating register */ #define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec) /** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ #define LP_APM_CLK_EN (BIT(0)) #define LP_APM_CLK_EN_M (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S) diff --git a/components/soc/esp32c5/register/soc/lp_apm_struct.h b/components/soc/esp32c5/register/soc/lp_apm_struct.h index 3c7bc3fcc2..fe0bddb019 100644 --- a/components/soc/esp32c5/register/soc/lp_apm_struct.h +++ b/components/soc/esp32c5/register/soc/lp_apm_struct.h @@ -10,16 +10,16 @@ extern "C" { #endif -/** Group: Region filter enable register */ +/** Group: Configuration Registers */ /** Type of region_filter_en register - * Region filter enable register + * Region enable register */ typedef union { struct { /** region_filter_en : R/W; bitpos: [7:0]; default: 1; - * Configure bit $n (0-7) to enable region $n. - * 0: disable - * 1: enable + * Configure bit $n (0-7) to enable region $n (0-7). + * 0: Disable + * 1: Enable */ uint32_t region_filter_en:8; uint32_t reserved_8:24; @@ -27,15 +27,13 @@ typedef union { uint32_t val; } lp_apm_region_filter_en_reg_t; - -/** Group: Region address register */ /** Type of regionn_addr_start register * Region address register */ typedef union { struct { /** regionn_addr_start : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region n. + * Configures the start address of region n. */ uint32_t regionn_addr_start:32; }; @@ -48,60 +46,62 @@ typedef union { typedef union { struct { /** regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region n. + * Configures the end address of region n. */ uint32_t regionn_addr_end:32; }; uint32_t val; } lp_apm_regionn_addr_end_reg_t; - -/** Group: Region access authority attribute register */ /** Type of regionn_attr register - * Region access authority attribute register + * Region access permissions configuration register */ typedef union { struct { /** regionn_r0_x : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region n. + * Configures the execution permission in region n in REE0 mode. */ uint32_t regionn_r0_x:1; /** regionn_r0_w : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region n. + * Configures the write permission in region n in REE0 mode. */ uint32_t regionn_r0_w:1; /** regionn_r0_r : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region n. + * Configures the read permission in region n in REE0 mode. */ uint32_t regionn_r0_r:1; uint32_t reserved_3:1; /** regionn_r1_x : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region n. + * Configures the execution permission in region n in REE1 mode. */ uint32_t regionn_r1_x:1; /** regionn_r1_w : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region n. + * Configures the write permission in region n in REE1 mode. */ uint32_t regionn_r1_w:1; /** regionn_r1_r : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region n. + * Configures the read permission in region n in REE1 mode. */ uint32_t regionn_r1_r:1; uint32_t reserved_7:1; /** regionn_r2_x : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region n. + * Configures the execution permission in region n in REE1 mode. */ uint32_t regionn_r2_x:1; /** regionn_r2_w : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region n. + * Configures the write permission in region n in REE2 mode. */ uint32_t regionn_r2_w:1; /** regionn_r2_r : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region n. + * Configures the read permission in region n in REE2 mode. */ uint32_t regionn_r2_r:1; /** regionn_lock : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region n configuration registers + * (LP_APM_REGIONn_ADDR_START_REG, LP_APM_REGIONn_ADDR_END_REG and + * LP_APM_REGIONn_ATTR_REG). + * 0: Do not lock + * 1: Lock */ uint32_t regionn_lock:1; uint32_t reserved_12:20; @@ -109,19 +109,17 @@ typedef union { uint32_t val; } lp_apm_regionn_attr_reg_t; - -/** Group: function control register */ /** Type of func_ctrl register - * APM function control register + * APM access path permission management register */ typedef union { struct { /** m0_func_en : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures to enable permission management for LP_APM_CTRL M0. */ uint32_t m0_func_en:1; /** m1_func_en : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable + * Configures to enable permission management for LP_APM_CTRL M1. */ uint32_t m1_func_en:1; uint32_t reserved_2:30; @@ -130,16 +128,16 @@ typedef union { } lp_apm_func_ctrl_reg_t; -/** Group: M0 status register */ +/** Group: Status Registers */ /** Type of m0_status register - * M0 status register + * LP_APM_CTRL M0 status register */ typedef union { struct { /** m0_exception_status : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m0_exception_status:2; uint32_t reserved_2:30; @@ -147,10 +145,8 @@ typedef union { uint32_t val; } lp_apm_m0_status_reg_t; - -/** Group: M0 status clear register */ /** Type of m0_status_clr register - * M0 status clear register + * LP_APM_CTRL M0 status clear register */ typedef union { struct { @@ -163,24 +159,22 @@ typedef union { uint32_t val; } lp_apm_m0_status_clr_reg_t; - -/** Group: M0 exception_info0 register */ /** Type of m0_exception_info0 register - * M0 exception_info0 register + * LP_APM_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_region : RO; bitpos: [7:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m0_exception_region:8; uint32_t reserved_8:8; /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m0_exception_mode:2; /** m0_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m0_exception_id:5; uint32_t reserved_23:9; @@ -188,32 +182,28 @@ typedef union { uint32_t val; } lp_apm_m0_exception_info0_reg_t; - -/** Group: M0 exception_info1 register */ /** Type of m0_exception_info1 register - * M0 exception_info1 register + * LP_APM_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m0_exception_addr:32; }; uint32_t val; } lp_apm_m0_exception_info1_reg_t; - -/** Group: M1 status register */ /** Type of m1_status register - * M1 status register + * LP_APM_CTRL M1 status register */ typedef union { struct { /** m1_exception_status : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m1_exception_status:2; uint32_t reserved_2:30; @@ -221,10 +211,8 @@ typedef union { uint32_t val; } lp_apm_m1_status_reg_t; - -/** Group: M1 status clear register */ /** Type of m1_status_clr register - * M1 status clear register + * LP_APM_CTRL M1 status clear register */ typedef union { struct { @@ -237,24 +225,22 @@ typedef union { uint32_t val; } lp_apm_m1_status_clr_reg_t; - -/** Group: M1 exception_info0 register */ /** Type of m1_exception_info0 register - * M1 exception_info0 register + * LP_APM_CTRL M1 exception information register */ typedef union { struct { /** m1_exception_region : RO; bitpos: [7:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m1_exception_region:8; uint32_t reserved_8:8; /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m1_exception_mode:2; /** m1_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m1_exception_id:5; uint32_t reserved_23:9; @@ -262,15 +248,13 @@ typedef union { uint32_t val; } lp_apm_m1_exception_info0_reg_t; - -/** Group: M1 exception_info1 register */ /** Type of m1_exception_info1 register - * M1 exception_info1 register + * LP_APM_CTRL M1 exception information register */ typedef union { struct { /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m1_exception_addr:32; }; @@ -278,22 +262,22 @@ typedef union { } lp_apm_m1_exception_info1_reg_t; -/** Group: APM interrupt enable register */ +/** Group: Interrupt Registers */ /** Type of int_en register - * APM interrupt enable register + * LP_APM_CTRL M0/1 interrupt enable register */ typedef union { struct { /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; - * Configures to enable APM M0 interrupt. - * 0: disable - * 1: enable + * Configures to enable LP_APM_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m0_apm_int_en:1; /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; - * Configures to enable APM M1 interrupt. - * 0: disable - * 1: enable + * Configures to enable LP_APM_CTRL M1 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m1_apm_int_en:1; uint32_t reserved_2:30; @@ -302,16 +286,16 @@ typedef union { } lp_apm_int_en_reg_t; -/** Group: clock gating register */ +/** Group: Clock Gating Registers */ /** Type of clock_gate register - * clock gating register + * Clock gating register */ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -320,7 +304,7 @@ typedef union { } lp_apm_clock_gate_reg_t; -/** Group: Version control register */ +/** Group: Version Control Registers */ /** Type of date register * Version control register */ diff --git a/components/soc/esp32c5/register/soc/lp_tee_reg.h b/components/soc/esp32c5/register/soc/lp_tee_reg.h index e9eb72abe8..77abd8f4a9 100644 --- a/components/soc/esp32c5/register/soc/lp_tee_reg.h +++ b/components/soc/esp32c5/register/soc/lp_tee_reg.h @@ -12,22 +12,24 @@ extern "C" { #endif /** LP_TEE_M0_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define LP_TEE_M0_MODE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0) /** LP_TEE_M0_MODE : R/W; bitpos: [1:0]; default: 3; - * Configures M0 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for LP CPU. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define LP_TEE_M0_MODE 0x00000003U #define LP_TEE_M0_MODE_M (LP_TEE_M0_MODE_V << LP_TEE_M0_MODE_S) #define LP_TEE_M0_MODE_V 0x00000003U #define LP_TEE_M0_MODE_S 0 /** LP_TEE_M0_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures to lock the value of LP_TEE_M0_MODE. + * 0: Do not lock + * 1: Lock */ #define LP_TEE_M0_LOCK (BIT(2)) #define LP_TEE_M0_LOCK_M (LP_TEE_M0_LOCK_V << LP_TEE_M0_LOCK_S) @@ -35,7 +37,7 @@ extern "C" { #define LP_TEE_M0_LOCK_S 2 /** LP_TEE_EFUSE_CTRL_REG register - * efuse read/write control register + * eFuse read/write control register */ #define LP_TEE_EFUSE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x4) /** LP_TEE_READ_TEE_EFUSE : R/W; bitpos: [0]; default: 1; @@ -112,7 +114,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_EFUSE_S 7 /** LP_TEE_PMU_CTRL_REG register - * pmu read/write control register + * PMU read/write control register */ #define LP_TEE_PMU_CTRL_REG (DR_REG_LP_TEE_BASE + 0x8) /** LP_TEE_READ_TEE_PMU : R/W; bitpos: [0]; default: 1; @@ -189,7 +191,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_PMU_S 7 /** LP_TEE_CLKRST_CTRL_REG register - * clkrst read/write control register + * LP_CLKRST read/write control register */ #define LP_TEE_CLKRST_CTRL_REG (DR_REG_LP_TEE_BASE + 0xc) /** LP_TEE_READ_TEE_CLKRST : R/W; bitpos: [0]; default: 1; @@ -266,7 +268,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_CLKRST_S 7 /** LP_TEE_LP_AON_CTRL_CTRL_REG register - * lp_aon_ctrl read/write control register + * LP_AON read/write control register */ #define LP_TEE_LP_AON_CTRL_CTRL_REG (DR_REG_LP_TEE_BASE + 0x10) /** LP_TEE_READ_TEE_LP_AON_CTRL : R/W; bitpos: [0]; default: 1; @@ -343,7 +345,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_AON_CTRL_S 7 /** LP_TEE_LP_TIMER_CTRL_REG register - * lp_timer read/write control register + * LP_TIMER read/write control register */ #define LP_TEE_LP_TIMER_CTRL_REG (DR_REG_LP_TEE_BASE + 0x14) /** LP_TEE_READ_TEE_LP_TIMER : R/W; bitpos: [0]; default: 1; @@ -420,7 +422,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_TIMER_S 7 /** LP_TEE_LP_WDT_CTRL_REG register - * lp_wdt read/write control register + * LP_WDT read/write control register */ #define LP_TEE_LP_WDT_CTRL_REG (DR_REG_LP_TEE_BASE + 0x18) /** LP_TEE_READ_TEE_LP_WDT : R/W; bitpos: [0]; default: 1; @@ -497,7 +499,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_WDT_S 7 /** LP_TEE_LP_PERI_CTRL_REG register - * lp_peri read/write control register + * LPPERI read/write control register */ #define LP_TEE_LP_PERI_CTRL_REG (DR_REG_LP_TEE_BASE + 0x1c) /** LP_TEE_READ_TEE_LP_PERI : R/W; bitpos: [0]; default: 1; @@ -574,7 +576,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_PERI_S 7 /** LP_TEE_LP_ANA_PERI_CTRL_REG register - * lp_ana_peri read/write control register + * LP_ANA_PERI read/write control register */ #define LP_TEE_LP_ANA_PERI_CTRL_REG (DR_REG_LP_TEE_BASE + 0x20) /** LP_TEE_READ_TEE_LP_ANA_PERI : R/W; bitpos: [0]; default: 1; @@ -651,7 +653,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_ANA_PERI_S 7 /** LP_TEE_LP_IO_CTRL_REG register - * lp_io read/write control register + * LP_GPIO and LP_IO_MUX read/write control register */ #define LP_TEE_LP_IO_CTRL_REG (DR_REG_LP_TEE_BASE + 0x2c) /** LP_TEE_READ_TEE_LP_IO : R/W; bitpos: [0]; default: 1; @@ -728,7 +730,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_IO_S 7 /** LP_TEE_LP_TEE_CTRL_REG register - * lp_tee read/write control register + * LP_TEE read/write control register */ #define LP_TEE_LP_TEE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x34) /** LP_TEE_READ_TEE_LP_TEE : R/W; bitpos: [0]; default: 1; @@ -805,7 +807,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_TEE_S 7 /** LP_TEE_UART_CTRL_REG register - * uart read/write control register + * LP_UART read/write control register */ #define LP_TEE_UART_CTRL_REG (DR_REG_LP_TEE_BASE + 0x38) /** LP_TEE_READ_TEE_UART : R/W; bitpos: [0]; default: 1; @@ -882,7 +884,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_UART_S 7 /** LP_TEE_I2C_EXT_CTRL_REG register - * i2c_ext read/write control register + * LP_I2C read/write control register */ #define LP_TEE_I2C_EXT_CTRL_REG (DR_REG_LP_TEE_BASE + 0x40) /** LP_TEE_READ_TEE_I2C_EXT : R/W; bitpos: [0]; default: 1; @@ -959,7 +961,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_I2C_EXT_S 7 /** LP_TEE_I2C_ANA_MST_CTRL_REG register - * i2c_ana_mst read/write control register + * I2C_ANA_MST read/write control register */ #define LP_TEE_I2C_ANA_MST_CTRL_REG (DR_REG_LP_TEE_BASE + 0x44) /** LP_TEE_READ_TEE_I2C_ANA_MST : R/W; bitpos: [0]; default: 1; @@ -1035,85 +1037,8 @@ extern "C" { #define LP_TEE_WRITE_REE2_I2C_ANA_MST_V 0x00000001U #define LP_TEE_WRITE_REE2_I2C_ANA_MST_S 7 -/** LP_TEE_HUK_CTRL_REG register - * huk read/write control register - */ -#define LP_TEE_HUK_CTRL_REG (DR_REG_LP_TEE_BASE + 0x48) -/** LP_TEE_READ_TEE_HUK : R/W; bitpos: [0]; default: 1; - * Configures huk registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define LP_TEE_READ_TEE_HUK (BIT(0)) -#define LP_TEE_READ_TEE_HUK_M (LP_TEE_READ_TEE_HUK_V << LP_TEE_READ_TEE_HUK_S) -#define LP_TEE_READ_TEE_HUK_V 0x00000001U -#define LP_TEE_READ_TEE_HUK_S 0 -/** LP_TEE_READ_REE0_HUK : R/W; bitpos: [1]; default: 0; - * Configures huk registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define LP_TEE_READ_REE0_HUK (BIT(1)) -#define LP_TEE_READ_REE0_HUK_M (LP_TEE_READ_REE0_HUK_V << LP_TEE_READ_REE0_HUK_S) -#define LP_TEE_READ_REE0_HUK_V 0x00000001U -#define LP_TEE_READ_REE0_HUK_S 1 -/** LP_TEE_READ_REE1_HUK : R/W; bitpos: [2]; default: 0; - * Configures huk registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define LP_TEE_READ_REE1_HUK (BIT(2)) -#define LP_TEE_READ_REE1_HUK_M (LP_TEE_READ_REE1_HUK_V << LP_TEE_READ_REE1_HUK_S) -#define LP_TEE_READ_REE1_HUK_V 0x00000001U -#define LP_TEE_READ_REE1_HUK_S 2 -/** LP_TEE_READ_REE2_HUK : R/W; bitpos: [3]; default: 0; - * Configures huk registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define LP_TEE_READ_REE2_HUK (BIT(3)) -#define LP_TEE_READ_REE2_HUK_M (LP_TEE_READ_REE2_HUK_V << LP_TEE_READ_REE2_HUK_S) -#define LP_TEE_READ_REE2_HUK_V 0x00000001U -#define LP_TEE_READ_REE2_HUK_S 3 -/** LP_TEE_WRITE_TEE_HUK : R/W; bitpos: [4]; default: 1; - * Configures huk registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define LP_TEE_WRITE_TEE_HUK (BIT(4)) -#define LP_TEE_WRITE_TEE_HUK_M (LP_TEE_WRITE_TEE_HUK_V << LP_TEE_WRITE_TEE_HUK_S) -#define LP_TEE_WRITE_TEE_HUK_V 0x00000001U -#define LP_TEE_WRITE_TEE_HUK_S 4 -/** LP_TEE_WRITE_REE0_HUK : R/W; bitpos: [5]; default: 0; - * Configures huk registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define LP_TEE_WRITE_REE0_HUK (BIT(5)) -#define LP_TEE_WRITE_REE0_HUK_M (LP_TEE_WRITE_REE0_HUK_V << LP_TEE_WRITE_REE0_HUK_S) -#define LP_TEE_WRITE_REE0_HUK_V 0x00000001U -#define LP_TEE_WRITE_REE0_HUK_S 5 -/** LP_TEE_WRITE_REE1_HUK : R/W; bitpos: [6]; default: 0; - * Configures huk registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define LP_TEE_WRITE_REE1_HUK (BIT(6)) -#define LP_TEE_WRITE_REE1_HUK_M (LP_TEE_WRITE_REE1_HUK_V << LP_TEE_WRITE_REE1_HUK_S) -#define LP_TEE_WRITE_REE1_HUK_V 0x00000001U -#define LP_TEE_WRITE_REE1_HUK_S 6 -/** LP_TEE_WRITE_REE2_HUK : R/W; bitpos: [7]; default: 0; - * Configures huk registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define LP_TEE_WRITE_REE2_HUK (BIT(7)) -#define LP_TEE_WRITE_REE2_HUK_M (LP_TEE_WRITE_REE2_HUK_V << LP_TEE_WRITE_REE2_HUK_S) -#define LP_TEE_WRITE_REE2_HUK_V 0x00000001U -#define LP_TEE_WRITE_REE2_HUK_S 7 - /** LP_TEE_LP_APM_CTRL_REG register - * lp_apm read/write control register + * LP_APM read/write control register */ #define LP_TEE_LP_APM_CTRL_REG (DR_REG_LP_TEE_BASE + 0x4c) /** LP_TEE_READ_TEE_LP_APM : R/W; bitpos: [0]; default: 1; @@ -1190,14 +1115,14 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_APM_S 7 /** LP_TEE_FORCE_ACC_HP_REG register - * Force access to hpmem configuration register + * Force access to HP SRAM configuration register */ #define LP_TEE_FORCE_ACC_HP_REG (DR_REG_LP_TEE_BASE + 0x90) /** LP_TEE_FORCE_ACC_HPMEM_EN : R/W; bitpos: [0]; default: 0; - * Configures whether to allow LP CPU to force access to HP_MEM regardless of + * Configures whether to allow LP CPU to forcibly access HP SRAM regardless of * permission management. - * 0: disable force access HP_MEM - * 1: enable force access HP_MEM + * 0: Disable force access to HP SRAM + * 1: Enable force access to HP SRAM */ #define LP_TEE_FORCE_ACC_HPMEM_EN (BIT(0)) #define LP_TEE_FORCE_ACC_HPMEM_EN_M (LP_TEE_FORCE_ACC_HPMEM_EN_V << LP_TEE_FORCE_ACC_HPMEM_EN_S) @@ -1205,13 +1130,13 @@ extern "C" { #define LP_TEE_FORCE_ACC_HPMEM_EN_S 0 /** LP_TEE_BUS_ERR_CONF_REG register - * Clock gating register + * Error message return configuration register */ #define LP_TEE_BUS_ERR_CONF_REG (DR_REG_LP_TEE_BASE + 0xf0) /** LP_TEE_BUS_ERR_RESP_EN : R/W; bitpos: [0]; default: 0; - * Configures whether return error response to cpu when access blocked - * 0: disable error response - * 1: enable error response + * Configures whether to return error message to CPU when access is blocked. + * 0: Disable + * 1: Enable */ #define LP_TEE_BUS_ERR_RESP_EN (BIT(0)) #define LP_TEE_BUS_ERR_RESP_EN_M (LP_TEE_BUS_ERR_RESP_EN_V << LP_TEE_BUS_ERR_RESP_EN_S) @@ -1224,8 +1149,8 @@ extern "C" { #define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0xf8) /** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ #define LP_TEE_CLK_EN (BIT(0)) #define LP_TEE_CLK_EN_M (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S) @@ -1237,7 +1162,7 @@ extern "C" { */ #define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc) /** LP_TEE_DATE : R/W; bitpos: [27:0]; default: 2363416; - * Version control register + * Version control register. */ #define LP_TEE_DATE 0x0FFFFFFFU #define LP_TEE_DATE_M (LP_TEE_DATE_V << LP_TEE_DATE_S) diff --git a/components/soc/esp32c5/register/soc/lp_tee_struct.h b/components/soc/esp32c5/register/soc/lp_tee_struct.h index 8158b54d22..e344cec804 100644 --- a/components/soc/esp32c5/register/soc/lp_tee_struct.h +++ b/components/soc/esp32c5/register/soc/lp_tee_struct.h @@ -10,22 +10,24 @@ extern "C" { #endif -/** Group: Tee mode control register */ +/** Group: Configuration Registers */ /** Type of m0_mode_ctrl register - * TEE mode control register + * Security mode configuration register */ typedef union { struct { /** m0_mode : R/W; bitpos: [1:0]; default: 3; - * Configures M0 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for LP CPU. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ uint32_t m0_mode:2; /** m0_lock : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures to lock the value of LP_TEE_M0_MODE. + * 0: Do not lock + * 1: Lock */ uint32_t m0_lock:1; uint32_t reserved_3:29; @@ -34,9 +36,9 @@ typedef union { } lp_tee_m0_mode_ctrl_reg_t; -/** Group: read write control register */ +/** Group: Peripheral Read/Write Control Register */ /** Type of efuse_ctrl register - * efuse read/write control register + * eFuse read/write control register */ typedef union { struct { @@ -94,7 +96,7 @@ typedef union { } lp_tee_efuse_ctrl_reg_t; /** Type of pmu_ctrl register - * pmu read/write control register + * PMU read/write control register */ typedef union { struct { @@ -152,7 +154,7 @@ typedef union { } lp_tee_pmu_ctrl_reg_t; /** Type of clkrst_ctrl register - * clkrst read/write control register + * LP_CLKRST read/write control register */ typedef union { struct { @@ -210,7 +212,7 @@ typedef union { } lp_tee_clkrst_ctrl_reg_t; /** Type of lp_aon_ctrl_ctrl register - * lp_aon_ctrl read/write control register + * LP_AON read/write control register */ typedef union { struct { @@ -268,7 +270,7 @@ typedef union { } lp_tee_lp_aon_ctrl_ctrl_reg_t; /** Type of lp_timer_ctrl register - * lp_timer read/write control register + * LP_TIMER read/write control register */ typedef union { struct { @@ -326,7 +328,7 @@ typedef union { } lp_tee_lp_timer_ctrl_reg_t; /** Type of lp_wdt_ctrl register - * lp_wdt read/write control register + * LP_WDT read/write control register */ typedef union { struct { @@ -384,7 +386,7 @@ typedef union { } lp_tee_lp_wdt_ctrl_reg_t; /** Type of lp_peri_ctrl register - * lp_peri read/write control register + * LPPERI read/write control register */ typedef union { struct { @@ -442,7 +444,7 @@ typedef union { } lp_tee_lp_peri_ctrl_reg_t; /** Type of lp_ana_peri_ctrl register - * lp_ana_peri read/write control register + * LP_ANA_PERI read/write control register */ typedef union { struct { @@ -500,7 +502,7 @@ typedef union { } lp_tee_lp_ana_peri_ctrl_reg_t; /** Type of lp_io_ctrl register - * lp_io read/write control register + * LP_GPIO and LP_IO_MUX read/write control register */ typedef union { struct { @@ -558,7 +560,7 @@ typedef union { } lp_tee_lp_io_ctrl_reg_t; /** Type of lp_tee_ctrl register - * lp_tee read/write control register + * LP_TEE read/write control register */ typedef union { struct { @@ -616,7 +618,7 @@ typedef union { } lp_tee_lp_tee_ctrl_reg_t; /** Type of uart_ctrl register - * uart read/write control register + * LP_UART read/write control register */ typedef union { struct { @@ -674,7 +676,7 @@ typedef union { } lp_tee_uart_ctrl_reg_t; /** Type of i2c_ext_ctrl register - * i2c_ext read/write control register + * LP_I2C read/write control register */ typedef union { struct { @@ -732,7 +734,7 @@ typedef union { } lp_tee_i2c_ext_ctrl_reg_t; /** Type of i2c_ana_mst_ctrl register - * i2c_ana_mst read/write control register + * I2C_ANA_MST read/write control register */ typedef union { struct { @@ -789,66 +791,8 @@ typedef union { uint32_t val; } lp_tee_i2c_ana_mst_ctrl_reg_t; -/** Type of huk_ctrl register - * huk read/write control register - */ -typedef union { - struct { - /** read_tee_huk : R/W; bitpos: [0]; default: 1; - * Configures huk registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_huk:1; - /** read_ree0_huk : R/W; bitpos: [1]; default: 0; - * Configures huk registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_huk:1; - /** read_ree1_huk : R/W; bitpos: [2]; default: 0; - * Configures huk registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_huk:1; - /** read_ree2_huk : R/W; bitpos: [3]; default: 0; - * Configures huk registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_huk:1; - /** write_tee_huk : R/W; bitpos: [4]; default: 1; - * Configures huk registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_huk:1; - /** write_ree0_huk : R/W; bitpos: [5]; default: 0; - * Configures huk registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_huk:1; - /** write_ree1_huk : R/W; bitpos: [6]; default: 0; - * Configures huk registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_huk:1; - /** write_ree2_huk : R/W; bitpos: [7]; default: 0; - * Configures huk registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_huk:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} lp_tee_huk_ctrl_reg_t; - /** Type of lp_apm_ctrl register - * lp_apm read/write control register + * LP_APM read/write control register */ typedef union { struct { @@ -905,18 +849,16 @@ typedef union { uint32_t val; } lp_tee_lp_apm_ctrl_reg_t; - -/** Group: Force access to hpmem configuration register */ /** Type of force_acc_hp register - * Force access to hpmem configuration register + * Force access to HP SRAM configuration register */ typedef union { struct { /** force_acc_hpmem_en : R/W; bitpos: [0]; default: 0; - * Configures whether to allow LP CPU to force access to HP_MEM regardless of + * Configures whether to allow LP CPU to forcibly access HP SRAM regardless of * permission management. - * 0: disable force access HP_MEM - * 1: enable force access HP_MEM + * 0: Disable force access to HP SRAM + * 1: Enable force access to HP SRAM */ uint32_t force_acc_hpmem_en:1; uint32_t reserved_1:31; @@ -924,17 +866,15 @@ typedef union { uint32_t val; } lp_tee_force_acc_hp_reg_t; - -/** Group: config register */ /** Type of bus_err_conf register - * Clock gating register + * Error message return configuration register */ typedef union { struct { /** bus_err_resp_en : R/W; bitpos: [0]; default: 0; - * Configures whether return error response to cpu when access blocked - * 0: disable error response - * 1: enable error response + * Configures whether to return error message to CPU when access is blocked. + * 0: Disable + * 1: Enable */ uint32_t bus_err_resp_en:1; uint32_t reserved_1:31; @@ -943,7 +883,7 @@ typedef union { } lp_tee_bus_err_conf_reg_t; -/** Group: clock gating register */ +/** Group: Clock Gating Registers */ /** Type of clock_gate register * Clock gating register */ @@ -951,8 +891,8 @@ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -961,14 +901,14 @@ typedef union { } lp_tee_clock_gate_reg_t; -/** Group: Version control register */ +/** Group: Version Control Registers */ /** Type of date register * Version control register */ typedef union { struct { /** date : R/W; bitpos: [27:0]; default: 2363416; - * Version control register + * Version control register. */ uint32_t date:28; uint32_t reserved_28:4; @@ -995,7 +935,7 @@ typedef struct { uint32_t reserved_03c; volatile lp_tee_i2c_ext_ctrl_reg_t i2c_ext_ctrl; volatile lp_tee_i2c_ana_mst_ctrl_reg_t i2c_ana_mst_ctrl; - volatile lp_tee_huk_ctrl_reg_t huk_ctrl; + uint32_t reserved_048; volatile lp_tee_lp_apm_ctrl_reg_t lp_apm_ctrl; uint32_t reserved_050[16]; volatile lp_tee_force_acc_hp_reg_t force_acc_hp; diff --git a/components/soc/esp32c5/register/soc/tee_reg.h b/components/soc/esp32c5/register/soc/tee_reg.h index 48caf26c3d..398d4bc235 100644 --- a/components/soc/esp32c5/register/soc/tee_reg.h +++ b/components/soc/esp32c5/register/soc/tee_reg.h @@ -12,22 +12,24 @@ extern "C" { #endif /** TEE_M0_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M0_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x0) /** TEE_M0_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M0 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 0. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M0_MODE 0x00000003U #define TEE_M0_MODE_M (TEE_M0_MODE_V << TEE_M0_MODE_S) #define TEE_M0_MODE_V 0x00000003U #define TEE_M0_MODE_S 0 /** TEE_M0_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M0_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M0_LOCK (BIT(2)) #define TEE_M0_LOCK_M (TEE_M0_LOCK_V << TEE_M0_LOCK_S) @@ -35,22 +37,24 @@ extern "C" { #define TEE_M0_LOCK_S 2 /** TEE_M1_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M1_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4) /** TEE_M1_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M1 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 1. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M1_MODE 0x00000003U #define TEE_M1_MODE_M (TEE_M1_MODE_V << TEE_M1_MODE_S) #define TEE_M1_MODE_V 0x00000003U #define TEE_M1_MODE_S 0 /** TEE_M1_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M1_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M1_LOCK (BIT(2)) #define TEE_M1_LOCK_M (TEE_M1_LOCK_V << TEE_M1_LOCK_S) @@ -58,22 +62,24 @@ extern "C" { #define TEE_M1_LOCK_S 2 /** TEE_M2_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M2_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x8) /** TEE_M2_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M2 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 2. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M2_MODE 0x00000003U #define TEE_M2_MODE_M (TEE_M2_MODE_V << TEE_M2_MODE_S) #define TEE_M2_MODE_V 0x00000003U #define TEE_M2_MODE_S 0 /** TEE_M2_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M2_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M2_LOCK (BIT(2)) #define TEE_M2_LOCK_M (TEE_M2_LOCK_V << TEE_M2_LOCK_S) @@ -81,22 +87,24 @@ extern "C" { #define TEE_M2_LOCK_S 2 /** TEE_M3_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M3_MODE_CTRL_REG (DR_REG_TEE_BASE + 0xc) /** TEE_M3_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M3 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 3. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M3_MODE 0x00000003U #define TEE_M3_MODE_M (TEE_M3_MODE_V << TEE_M3_MODE_S) #define TEE_M3_MODE_V 0x00000003U #define TEE_M3_MODE_S 0 /** TEE_M3_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M3_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M3_LOCK (BIT(2)) #define TEE_M3_LOCK_M (TEE_M3_LOCK_V << TEE_M3_LOCK_S) @@ -104,22 +112,24 @@ extern "C" { #define TEE_M3_LOCK_S 2 /** TEE_M4_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M4_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x10) /** TEE_M4_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M4 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 4. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M4_MODE 0x00000003U #define TEE_M4_MODE_M (TEE_M4_MODE_V << TEE_M4_MODE_S) #define TEE_M4_MODE_V 0x00000003U #define TEE_M4_MODE_S 0 /** TEE_M4_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M4_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M4_LOCK (BIT(2)) #define TEE_M4_LOCK_M (TEE_M4_LOCK_V << TEE_M4_LOCK_S) @@ -127,22 +137,24 @@ extern "C" { #define TEE_M4_LOCK_S 2 /** TEE_M5_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M5_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x14) /** TEE_M5_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M5 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 5. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M5_MODE 0x00000003U #define TEE_M5_MODE_M (TEE_M5_MODE_V << TEE_M5_MODE_S) #define TEE_M5_MODE_V 0x00000003U #define TEE_M5_MODE_S 0 /** TEE_M5_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M5_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M5_LOCK (BIT(2)) #define TEE_M5_LOCK_M (TEE_M5_LOCK_V << TEE_M5_LOCK_S) @@ -150,22 +162,24 @@ extern "C" { #define TEE_M5_LOCK_S 2 /** TEE_M6_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M6_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x18) /** TEE_M6_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M6 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 6. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M6_MODE 0x00000003U #define TEE_M6_MODE_M (TEE_M6_MODE_V << TEE_M6_MODE_S) #define TEE_M6_MODE_V 0x00000003U #define TEE_M6_MODE_S 0 /** TEE_M6_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M6_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M6_LOCK (BIT(2)) #define TEE_M6_LOCK_M (TEE_M6_LOCK_V << TEE_M6_LOCK_S) @@ -173,22 +187,24 @@ extern "C" { #define TEE_M6_LOCK_S 2 /** TEE_M7_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M7_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x1c) /** TEE_M7_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M7 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 7. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M7_MODE 0x00000003U #define TEE_M7_MODE_M (TEE_M7_MODE_V << TEE_M7_MODE_S) #define TEE_M7_MODE_V 0x00000003U #define TEE_M7_MODE_S 0 /** TEE_M7_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M7_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M7_LOCK (BIT(2)) #define TEE_M7_LOCK_M (TEE_M7_LOCK_V << TEE_M7_LOCK_S) @@ -196,22 +212,24 @@ extern "C" { #define TEE_M7_LOCK_S 2 /** TEE_M8_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M8_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x20) /** TEE_M8_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M8 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 8. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M8_MODE 0x00000003U #define TEE_M8_MODE_M (TEE_M8_MODE_V << TEE_M8_MODE_S) #define TEE_M8_MODE_V 0x00000003U #define TEE_M8_MODE_S 0 /** TEE_M8_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M8_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M8_LOCK (BIT(2)) #define TEE_M8_LOCK_M (TEE_M8_LOCK_V << TEE_M8_LOCK_S) @@ -219,22 +237,24 @@ extern "C" { #define TEE_M8_LOCK_S 2 /** TEE_M9_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M9_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x24) /** TEE_M9_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M9 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 9. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M9_MODE 0x00000003U #define TEE_M9_MODE_M (TEE_M9_MODE_V << TEE_M9_MODE_S) #define TEE_M9_MODE_V 0x00000003U #define TEE_M9_MODE_S 0 /** TEE_M9_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M9_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M9_LOCK (BIT(2)) #define TEE_M9_LOCK_M (TEE_M9_LOCK_V << TEE_M9_LOCK_S) @@ -242,22 +262,24 @@ extern "C" { #define TEE_M9_LOCK_S 2 /** TEE_M10_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M10_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x28) /** TEE_M10_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M10 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 10. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M10_MODE 0x00000003U #define TEE_M10_MODE_M (TEE_M10_MODE_V << TEE_M10_MODE_S) #define TEE_M10_MODE_V 0x00000003U #define TEE_M10_MODE_S 0 /** TEE_M10_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M10_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M10_LOCK (BIT(2)) #define TEE_M10_LOCK_M (TEE_M10_LOCK_V << TEE_M10_LOCK_S) @@ -265,22 +287,24 @@ extern "C" { #define TEE_M10_LOCK_S 2 /** TEE_M11_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M11_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x2c) /** TEE_M11_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M11 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 11. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M11_MODE 0x00000003U #define TEE_M11_MODE_M (TEE_M11_MODE_V << TEE_M11_MODE_S) #define TEE_M11_MODE_V 0x00000003U #define TEE_M11_MODE_S 0 /** TEE_M11_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M11_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M11_LOCK (BIT(2)) #define TEE_M11_LOCK_M (TEE_M11_LOCK_V << TEE_M11_LOCK_S) @@ -288,22 +312,24 @@ extern "C" { #define TEE_M11_LOCK_S 2 /** TEE_M12_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M12_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x30) /** TEE_M12_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M12 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 12. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M12_MODE 0x00000003U #define TEE_M12_MODE_M (TEE_M12_MODE_V << TEE_M12_MODE_S) #define TEE_M12_MODE_V 0x00000003U #define TEE_M12_MODE_S 0 /** TEE_M12_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M12_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M12_LOCK (BIT(2)) #define TEE_M12_LOCK_M (TEE_M12_LOCK_V << TEE_M12_LOCK_S) @@ -311,22 +337,24 @@ extern "C" { #define TEE_M12_LOCK_S 2 /** TEE_M13_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M13_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x34) /** TEE_M13_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M13 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 13. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M13_MODE 0x00000003U #define TEE_M13_MODE_M (TEE_M13_MODE_V << TEE_M13_MODE_S) #define TEE_M13_MODE_V 0x00000003U #define TEE_M13_MODE_S 0 /** TEE_M13_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M13_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M13_LOCK (BIT(2)) #define TEE_M13_LOCK_M (TEE_M13_LOCK_V << TEE_M13_LOCK_S) @@ -334,22 +362,24 @@ extern "C" { #define TEE_M13_LOCK_S 2 /** TEE_M14_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M14_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x38) /** TEE_M14_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M14 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 14. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M14_MODE 0x00000003U #define TEE_M14_MODE_M (TEE_M14_MODE_V << TEE_M14_MODE_S) #define TEE_M14_MODE_V 0x00000003U #define TEE_M14_MODE_S 0 /** TEE_M14_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M14_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M14_LOCK (BIT(2)) #define TEE_M14_LOCK_M (TEE_M14_LOCK_V << TEE_M14_LOCK_S) @@ -357,22 +387,24 @@ extern "C" { #define TEE_M14_LOCK_S 2 /** TEE_M15_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M15_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x3c) /** TEE_M15_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M15 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 15. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M15_MODE 0x00000003U #define TEE_M15_MODE_M (TEE_M15_MODE_V << TEE_M15_MODE_S) #define TEE_M15_MODE_V 0x00000003U #define TEE_M15_MODE_S 0 /** TEE_M15_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M15_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M15_LOCK (BIT(2)) #define TEE_M15_LOCK_M (TEE_M15_LOCK_V << TEE_M15_LOCK_S) @@ -380,22 +412,24 @@ extern "C" { #define TEE_M15_LOCK_S 2 /** TEE_M16_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M16_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x40) /** TEE_M16_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M16 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 16. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M16_MODE 0x00000003U #define TEE_M16_MODE_M (TEE_M16_MODE_V << TEE_M16_MODE_S) #define TEE_M16_MODE_V 0x00000003U #define TEE_M16_MODE_S 0 /** TEE_M16_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M16_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M16_LOCK (BIT(2)) #define TEE_M16_LOCK_M (TEE_M16_LOCK_V << TEE_M16_LOCK_S) @@ -403,22 +437,24 @@ extern "C" { #define TEE_M16_LOCK_S 2 /** TEE_M17_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M17_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x44) /** TEE_M17_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M17 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 17. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M17_MODE 0x00000003U #define TEE_M17_MODE_M (TEE_M17_MODE_V << TEE_M17_MODE_S) #define TEE_M17_MODE_V 0x00000003U #define TEE_M17_MODE_S 0 /** TEE_M17_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M17_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M17_LOCK (BIT(2)) #define TEE_M17_LOCK_M (TEE_M17_LOCK_V << TEE_M17_LOCK_S) @@ -426,22 +462,24 @@ extern "C" { #define TEE_M17_LOCK_S 2 /** TEE_M18_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M18_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x48) /** TEE_M18_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M18 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 18. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M18_MODE 0x00000003U #define TEE_M18_MODE_M (TEE_M18_MODE_V << TEE_M18_MODE_S) #define TEE_M18_MODE_V 0x00000003U #define TEE_M18_MODE_S 0 /** TEE_M18_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M18_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M18_LOCK (BIT(2)) #define TEE_M18_LOCK_M (TEE_M18_LOCK_V << TEE_M18_LOCK_S) @@ -449,22 +487,24 @@ extern "C" { #define TEE_M18_LOCK_S 2 /** TEE_M19_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M19_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4c) /** TEE_M19_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M19 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 19. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M19_MODE 0x00000003U #define TEE_M19_MODE_M (TEE_M19_MODE_V << TEE_M19_MODE_S) #define TEE_M19_MODE_V 0x00000003U #define TEE_M19_MODE_S 0 /** TEE_M19_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M19_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M19_LOCK (BIT(2)) #define TEE_M19_LOCK_M (TEE_M19_LOCK_V << TEE_M19_LOCK_S) @@ -472,22 +512,24 @@ extern "C" { #define TEE_M19_LOCK_S 2 /** TEE_M20_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M20_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x50) /** TEE_M20_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M20 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 20. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M20_MODE 0x00000003U #define TEE_M20_MODE_M (TEE_M20_MODE_V << TEE_M20_MODE_S) #define TEE_M20_MODE_V 0x00000003U #define TEE_M20_MODE_S 0 /** TEE_M20_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M20_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M20_LOCK (BIT(2)) #define TEE_M20_LOCK_M (TEE_M20_LOCK_V << TEE_M20_LOCK_S) @@ -495,22 +537,24 @@ extern "C" { #define TEE_M20_LOCK_S 2 /** TEE_M21_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M21_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x54) /** TEE_M21_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M21 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 21. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M21_MODE 0x00000003U #define TEE_M21_MODE_M (TEE_M21_MODE_V << TEE_M21_MODE_S) #define TEE_M21_MODE_V 0x00000003U #define TEE_M21_MODE_S 0 /** TEE_M21_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M21_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M21_LOCK (BIT(2)) #define TEE_M21_LOCK_M (TEE_M21_LOCK_V << TEE_M21_LOCK_S) @@ -518,22 +562,24 @@ extern "C" { #define TEE_M21_LOCK_S 2 /** TEE_M22_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M22_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x58) /** TEE_M22_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M22 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 22. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M22_MODE 0x00000003U #define TEE_M22_MODE_M (TEE_M22_MODE_V << TEE_M22_MODE_S) #define TEE_M22_MODE_V 0x00000003U #define TEE_M22_MODE_S 0 /** TEE_M22_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M22_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M22_LOCK (BIT(2)) #define TEE_M22_LOCK_M (TEE_M22_LOCK_V << TEE_M22_LOCK_S) @@ -541,22 +587,24 @@ extern "C" { #define TEE_M22_LOCK_S 2 /** TEE_M23_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M23_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x5c) /** TEE_M23_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M23 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 23. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M23_MODE 0x00000003U #define TEE_M23_MODE_M (TEE_M23_MODE_V << TEE_M23_MODE_S) #define TEE_M23_MODE_V 0x00000003U #define TEE_M23_MODE_S 0 /** TEE_M23_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M23_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M23_LOCK (BIT(2)) #define TEE_M23_LOCK_M (TEE_M23_LOCK_V << TEE_M23_LOCK_S) @@ -564,22 +612,24 @@ extern "C" { #define TEE_M23_LOCK_S 2 /** TEE_M24_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M24_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x60) /** TEE_M24_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M24 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 24. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M24_MODE 0x00000003U #define TEE_M24_MODE_M (TEE_M24_MODE_V << TEE_M24_MODE_S) #define TEE_M24_MODE_V 0x00000003U #define TEE_M24_MODE_S 0 /** TEE_M24_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M24_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M24_LOCK (BIT(2)) #define TEE_M24_LOCK_M (TEE_M24_LOCK_V << TEE_M24_LOCK_S) @@ -587,22 +637,24 @@ extern "C" { #define TEE_M24_LOCK_S 2 /** TEE_M25_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M25_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x64) /** TEE_M25_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M25 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 25. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M25_MODE 0x00000003U #define TEE_M25_MODE_M (TEE_M25_MODE_V << TEE_M25_MODE_S) #define TEE_M25_MODE_V 0x00000003U #define TEE_M25_MODE_S 0 /** TEE_M25_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M25_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M25_LOCK (BIT(2)) #define TEE_M25_LOCK_M (TEE_M25_LOCK_V << TEE_M25_LOCK_S) @@ -610,22 +662,24 @@ extern "C" { #define TEE_M25_LOCK_S 2 /** TEE_M26_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M26_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x68) /** TEE_M26_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M26 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 26. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M26_MODE 0x00000003U #define TEE_M26_MODE_M (TEE_M26_MODE_V << TEE_M26_MODE_S) #define TEE_M26_MODE_V 0x00000003U #define TEE_M26_MODE_S 0 /** TEE_M26_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M26_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M26_LOCK (BIT(2)) #define TEE_M26_LOCK_M (TEE_M26_LOCK_V << TEE_M26_LOCK_S) @@ -633,22 +687,24 @@ extern "C" { #define TEE_M26_LOCK_S 2 /** TEE_M27_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M27_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x6c) /** TEE_M27_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M27 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 27. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M27_MODE 0x00000003U #define TEE_M27_MODE_M (TEE_M27_MODE_V << TEE_M27_MODE_S) #define TEE_M27_MODE_V 0x00000003U #define TEE_M27_MODE_S 0 /** TEE_M27_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M27_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M27_LOCK (BIT(2)) #define TEE_M27_LOCK_M (TEE_M27_LOCK_V << TEE_M27_LOCK_S) @@ -656,22 +712,24 @@ extern "C" { #define TEE_M27_LOCK_S 2 /** TEE_M28_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M28_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x70) /** TEE_M28_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M28 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 28. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M28_MODE 0x00000003U #define TEE_M28_MODE_M (TEE_M28_MODE_V << TEE_M28_MODE_S) #define TEE_M28_MODE_V 0x00000003U #define TEE_M28_MODE_S 0 /** TEE_M28_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M28_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M28_LOCK (BIT(2)) #define TEE_M28_LOCK_M (TEE_M28_LOCK_V << TEE_M28_LOCK_S) @@ -679,22 +737,24 @@ extern "C" { #define TEE_M28_LOCK_S 2 /** TEE_M29_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M29_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x74) /** TEE_M29_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M29 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 29. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M29_MODE 0x00000003U #define TEE_M29_MODE_M (TEE_M29_MODE_V << TEE_M29_MODE_S) #define TEE_M29_MODE_V 0x00000003U #define TEE_M29_MODE_S 0 /** TEE_M29_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M29_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M29_LOCK (BIT(2)) #define TEE_M29_LOCK_M (TEE_M29_LOCK_V << TEE_M29_LOCK_S) @@ -702,22 +762,24 @@ extern "C" { #define TEE_M29_LOCK_S 2 /** TEE_M30_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M30_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x78) /** TEE_M30_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M30 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 30. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M30_MODE 0x00000003U #define TEE_M30_MODE_M (TEE_M30_MODE_V << TEE_M30_MODE_S) #define TEE_M30_MODE_V 0x00000003U #define TEE_M30_MODE_S 0 /** TEE_M30_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M30_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M30_LOCK (BIT(2)) #define TEE_M30_LOCK_M (TEE_M30_LOCK_V << TEE_M30_LOCK_S) @@ -725,22 +787,24 @@ extern "C" { #define TEE_M30_LOCK_S 2 /** TEE_M31_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M31_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x7c) /** TEE_M31_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M31 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 31. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M31_MODE 0x00000003U #define TEE_M31_MODE_M (TEE_M31_MODE_V << TEE_M31_MODE_S) #define TEE_M31_MODE_V 0x00000003U #define TEE_M31_MODE_S 0 /** TEE_M31_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M31_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M31_LOCK (BIT(2)) #define TEE_M31_LOCK_M (TEE_M31_LOCK_V << TEE_M31_LOCK_S) @@ -748,7 +812,7 @@ extern "C" { #define TEE_M31_LOCK_S 2 /** TEE_UART0_CTRL_REG register - * uart0 read/write control register + * UART0 read/write control register */ #define TEE_UART0_CTRL_REG (DR_REG_TEE_BASE + 0x88) /** TEE_READ_TEE_UART0 : R/W; bitpos: [0]; default: 1; @@ -825,7 +889,7 @@ extern "C" { #define TEE_WRITE_REE2_UART0_S 7 /** TEE_UART1_CTRL_REG register - * uart1 read/write control register + * UART1 read/write control register */ #define TEE_UART1_CTRL_REG (DR_REG_TEE_BASE + 0x8c) /** TEE_READ_TEE_UART1 : R/W; bitpos: [0]; default: 1; @@ -902,7 +966,7 @@ extern "C" { #define TEE_WRITE_REE2_UART1_S 7 /** TEE_UHCI0_CTRL_REG register - * uhci0 read/write control register + * UHCI read/write control register */ #define TEE_UHCI0_CTRL_REG (DR_REG_TEE_BASE + 0x90) /** TEE_READ_TEE_UHCI0 : R/W; bitpos: [0]; default: 1; @@ -979,7 +1043,7 @@ extern "C" { #define TEE_WRITE_REE2_UHCI0_S 7 /** TEE_I2C_EXT0_CTRL_REG register - * i2c_ext0 read/write control register + * I2C read/write control register */ #define TEE_I2C_EXT0_CTRL_REG (DR_REG_TEE_BASE + 0x94) /** TEE_READ_TEE_I2C_EXT0 : R/W; bitpos: [0]; default: 1; @@ -1056,7 +1120,7 @@ extern "C" { #define TEE_WRITE_REE2_I2C_EXT0_S 7 /** TEE_I2S_CTRL_REG register - * i2s read/write control register + * I2S read/write control register */ #define TEE_I2S_CTRL_REG (DR_REG_TEE_BASE + 0x9c) /** TEE_READ_TEE_I2S : R/W; bitpos: [0]; default: 1; @@ -1133,7 +1197,7 @@ extern "C" { #define TEE_WRITE_REE2_I2S_S 7 /** TEE_PARL_IO_CTRL_REG register - * parl_io read/write control register + * PARL_IO read/write control register */ #define TEE_PARL_IO_CTRL_REG (DR_REG_TEE_BASE + 0xa0) /** TEE_READ_TEE_PARL_IO : R/W; bitpos: [0]; default: 1; @@ -1210,7 +1274,7 @@ extern "C" { #define TEE_WRITE_REE2_PARL_IO_S 7 /** TEE_PWM_CTRL_REG register - * pwm read/write control register + * MCPWM read/write control register */ #define TEE_PWM_CTRL_REG (DR_REG_TEE_BASE + 0xa4) /** TEE_READ_TEE_PWM : R/W; bitpos: [0]; default: 1; @@ -1287,7 +1351,7 @@ extern "C" { #define TEE_WRITE_REE2_PWM_S 7 /** TEE_LEDC_CTRL_REG register - * ledc read/write control register + * LEDC read/write control register */ #define TEE_LEDC_CTRL_REG (DR_REG_TEE_BASE + 0xac) /** TEE_READ_TEE_LEDC : R/W; bitpos: [0]; default: 1; @@ -1363,162 +1427,162 @@ extern "C" { #define TEE_WRITE_REE2_LEDC_V 0x00000001U #define TEE_WRITE_REE2_LEDC_S 7 -/** TEE_CAN0_CTRL_REG register - * can read/write control register +/** TEE_TWAI0_CTRL_REG register + * TWAI0 read/write control register */ -#define TEE_CAN0_CTRL_REG (DR_REG_TEE_BASE + 0xb0) -/** TEE_READ_TEE_CAN0 : R/W; bitpos: [0]; default: 1; +#define TEE_TWAI0_CTRL_REG (DR_REG_TEE_BASE + 0xb0) +/** TEE_READ_TEE_TWAI0 : R/W; bitpos: [0]; default: 1; * Configures can0 registers read permission in tee mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_TEE_CAN0 (BIT(0)) -#define TEE_READ_TEE_CAN0_M (TEE_READ_TEE_CAN0_V << TEE_READ_TEE_CAN0_S) -#define TEE_READ_TEE_CAN0_V 0x00000001U -#define TEE_READ_TEE_CAN0_S 0 -/** TEE_READ_REE0_CAN0 : R/W; bitpos: [1]; default: 0; +#define TEE_READ_TEE_TWAI0 (BIT(0)) +#define TEE_READ_TEE_TWAI0_M (TEE_READ_TEE_TWAI0_V << TEE_READ_TEE_TWAI0_S) +#define TEE_READ_TEE_TWAI0_V 0x00000001U +#define TEE_READ_TEE_TWAI0_S 0 +/** TEE_READ_REE0_TWAI0 : R/W; bitpos: [1]; default: 0; * Configures can0 registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE0_CAN0 (BIT(1)) -#define TEE_READ_REE0_CAN0_M (TEE_READ_REE0_CAN0_V << TEE_READ_REE0_CAN0_S) -#define TEE_READ_REE0_CAN0_V 0x00000001U -#define TEE_READ_REE0_CAN0_S 1 -/** TEE_READ_REE1_CAN0 : R/W; bitpos: [2]; default: 0; +#define TEE_READ_REE0_TWAI0 (BIT(1)) +#define TEE_READ_REE0_TWAI0_M (TEE_READ_REE0_TWAI0_V << TEE_READ_REE0_TWAI0_S) +#define TEE_READ_REE0_TWAI0_V 0x00000001U +#define TEE_READ_REE0_TWAI0_S 1 +/** TEE_READ_REE1_TWAI0 : R/W; bitpos: [2]; default: 0; * Configures can0 registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE1_CAN0 (BIT(2)) -#define TEE_READ_REE1_CAN0_M (TEE_READ_REE1_CAN0_V << TEE_READ_REE1_CAN0_S) -#define TEE_READ_REE1_CAN0_V 0x00000001U -#define TEE_READ_REE1_CAN0_S 2 -/** TEE_READ_REE2_CAN0 : R/W; bitpos: [3]; default: 0; +#define TEE_READ_REE1_TWAI0 (BIT(2)) +#define TEE_READ_REE1_TWAI0_M (TEE_READ_REE1_TWAI0_V << TEE_READ_REE1_TWAI0_S) +#define TEE_READ_REE1_TWAI0_V 0x00000001U +#define TEE_READ_REE1_TWAI0_S 2 +/** TEE_READ_REE2_TWAI0 : R/W; bitpos: [3]; default: 0; * Configures can0 registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE2_CAN0 (BIT(3)) -#define TEE_READ_REE2_CAN0_M (TEE_READ_REE2_CAN0_V << TEE_READ_REE2_CAN0_S) -#define TEE_READ_REE2_CAN0_V 0x00000001U -#define TEE_READ_REE2_CAN0_S 3 -/** TEE_WRITE_TEE_CAN0 : R/W; bitpos: [4]; default: 1; +#define TEE_READ_REE2_TWAI0 (BIT(3)) +#define TEE_READ_REE2_TWAI0_M (TEE_READ_REE2_TWAI0_V << TEE_READ_REE2_TWAI0_S) +#define TEE_READ_REE2_TWAI0_V 0x00000001U +#define TEE_READ_REE2_TWAI0_S 3 +/** TEE_WRITE_TEE_TWAI0 : R/W; bitpos: [4]; default: 1; * Configures can0 registers write permission in tee mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_TEE_CAN0 (BIT(4)) -#define TEE_WRITE_TEE_CAN0_M (TEE_WRITE_TEE_CAN0_V << TEE_WRITE_TEE_CAN0_S) -#define TEE_WRITE_TEE_CAN0_V 0x00000001U -#define TEE_WRITE_TEE_CAN0_S 4 -/** TEE_WRITE_REE0_CAN0 : R/W; bitpos: [5]; default: 0; +#define TEE_WRITE_TEE_TWAI0 (BIT(4)) +#define TEE_WRITE_TEE_TWAI0_M (TEE_WRITE_TEE_TWAI0_V << TEE_WRITE_TEE_TWAI0_S) +#define TEE_WRITE_TEE_TWAI0_V 0x00000001U +#define TEE_WRITE_TEE_TWAI0_S 4 +/** TEE_WRITE_REE0_TWAI0 : R/W; bitpos: [5]; default: 0; * Configures can0 registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE0_CAN0 (BIT(5)) -#define TEE_WRITE_REE0_CAN0_M (TEE_WRITE_REE0_CAN0_V << TEE_WRITE_REE0_CAN0_S) -#define TEE_WRITE_REE0_CAN0_V 0x00000001U -#define TEE_WRITE_REE0_CAN0_S 5 -/** TEE_WRITE_REE1_CAN0 : R/W; bitpos: [6]; default: 0; +#define TEE_WRITE_REE0_TWAI0 (BIT(5)) +#define TEE_WRITE_REE0_TWAI0_M (TEE_WRITE_REE0_TWAI0_V << TEE_WRITE_REE0_TWAI0_S) +#define TEE_WRITE_REE0_TWAI0_V 0x00000001U +#define TEE_WRITE_REE0_TWAI0_S 5 +/** TEE_WRITE_REE1_TWAI0 : R/W; bitpos: [6]; default: 0; * Configures can0 registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE1_CAN0 (BIT(6)) -#define TEE_WRITE_REE1_CAN0_M (TEE_WRITE_REE1_CAN0_V << TEE_WRITE_REE1_CAN0_S) -#define TEE_WRITE_REE1_CAN0_V 0x00000001U -#define TEE_WRITE_REE1_CAN0_S 6 -/** TEE_WRITE_REE2_CAN0 : R/W; bitpos: [7]; default: 0; +#define TEE_WRITE_REE1_TWAI0 (BIT(6)) +#define TEE_WRITE_REE1_TWAI0_M (TEE_WRITE_REE1_TWAI0_V << TEE_WRITE_REE1_TWAI0_S) +#define TEE_WRITE_REE1_TWAI0_V 0x00000001U +#define TEE_WRITE_REE1_TWAI0_S 6 +/** TEE_WRITE_REE2_TWAI0 : R/W; bitpos: [7]; default: 0; * Configures can0 registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE2_CAN0 (BIT(7)) -#define TEE_WRITE_REE2_CAN0_M (TEE_WRITE_REE2_CAN0_V << TEE_WRITE_REE2_CAN0_S) -#define TEE_WRITE_REE2_CAN0_V 0x00000001U -#define TEE_WRITE_REE2_CAN0_S 7 +#define TEE_WRITE_REE2_TWAI0 (BIT(7)) +#define TEE_WRITE_REE2_TWAI0_M (TEE_WRITE_REE2_TWAI0_V << TEE_WRITE_REE2_TWAI0_S) +#define TEE_WRITE_REE2_TWAI0_V 0x00000001U +#define TEE_WRITE_REE2_TWAI0_S 7 -/** TEE_USB_DEVICE_CTRL_REG register - * usb_device read/write control register +/** TEE_USB_SERIAL_JTAG_CTRL_REG register + * USB_SERIAL_JTAG read/write control register */ -#define TEE_USB_DEVICE_CTRL_REG (DR_REG_TEE_BASE + 0xb4) -/** TEE_READ_TEE_USB_DEVICE : R/W; bitpos: [0]; default: 1; +#define TEE_USB_SERIAL_JTAG_CTRL_REG (DR_REG_TEE_BASE + 0xb4) +/** TEE_READ_TEE_USB_SERIAL_JTAG : R/W; bitpos: [0]; default: 1; * Configures usb_device registers read permission in tee mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_TEE_USB_DEVICE (BIT(0)) -#define TEE_READ_TEE_USB_DEVICE_M (TEE_READ_TEE_USB_DEVICE_V << TEE_READ_TEE_USB_DEVICE_S) -#define TEE_READ_TEE_USB_DEVICE_V 0x00000001U -#define TEE_READ_TEE_USB_DEVICE_S 0 -/** TEE_READ_REE0_USB_DEVICE : R/W; bitpos: [1]; default: 0; +#define TEE_READ_TEE_USB_SERIAL_JTAG (BIT(0)) +#define TEE_READ_TEE_USB_SERIAL_JTAG_M (TEE_READ_TEE_USB_SERIAL_JTAG_V << TEE_READ_TEE_USB_SERIAL_JTAG_S) +#define TEE_READ_TEE_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_READ_TEE_USB_SERIAL_JTAG_S 0 +/** TEE_READ_REE0_USB_SERIAL_JTAG : R/W; bitpos: [1]; default: 0; * Configures usb_device registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE0_USB_DEVICE (BIT(1)) -#define TEE_READ_REE0_USB_DEVICE_M (TEE_READ_REE0_USB_DEVICE_V << TEE_READ_REE0_USB_DEVICE_S) -#define TEE_READ_REE0_USB_DEVICE_V 0x00000001U -#define TEE_READ_REE0_USB_DEVICE_S 1 -/** TEE_READ_REE1_USB_DEVICE : R/W; bitpos: [2]; default: 0; +#define TEE_READ_REE0_USB_SERIAL_JTAG (BIT(1)) +#define TEE_READ_REE0_USB_SERIAL_JTAG_M (TEE_READ_REE0_USB_SERIAL_JTAG_V << TEE_READ_REE0_USB_SERIAL_JTAG_S) +#define TEE_READ_REE0_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_READ_REE0_USB_SERIAL_JTAG_S 1 +/** TEE_READ_REE1_USB_SERIAL_JTAG : R/W; bitpos: [2]; default: 0; * Configures usb_device registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE1_USB_DEVICE (BIT(2)) -#define TEE_READ_REE1_USB_DEVICE_M (TEE_READ_REE1_USB_DEVICE_V << TEE_READ_REE1_USB_DEVICE_S) -#define TEE_READ_REE1_USB_DEVICE_V 0x00000001U -#define TEE_READ_REE1_USB_DEVICE_S 2 -/** TEE_READ_REE2_USB_DEVICE : R/W; bitpos: [3]; default: 0; +#define TEE_READ_REE1_USB_SERIAL_JTAG (BIT(2)) +#define TEE_READ_REE1_USB_SERIAL_JTAG_M (TEE_READ_REE1_USB_SERIAL_JTAG_V << TEE_READ_REE1_USB_SERIAL_JTAG_S) +#define TEE_READ_REE1_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_READ_REE1_USB_SERIAL_JTAG_S 2 +/** TEE_READ_REE2_USB_SERIAL_JTAG : R/W; bitpos: [3]; default: 0; * Configures usb_device registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE2_USB_DEVICE (BIT(3)) -#define TEE_READ_REE2_USB_DEVICE_M (TEE_READ_REE2_USB_DEVICE_V << TEE_READ_REE2_USB_DEVICE_S) -#define TEE_READ_REE2_USB_DEVICE_V 0x00000001U -#define TEE_READ_REE2_USB_DEVICE_S 3 -/** TEE_WRITE_TEE_USB_DEVICE : R/W; bitpos: [4]; default: 1; +#define TEE_READ_REE2_USB_SERIAL_JTAG (BIT(3)) +#define TEE_READ_REE2_USB_SERIAL_JTAG_M (TEE_READ_REE2_USB_SERIAL_JTAG_V << TEE_READ_REE2_USB_SERIAL_JTAG_S) +#define TEE_READ_REE2_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_READ_REE2_USB_SERIAL_JTAG_S 3 +/** TEE_WRITE_TEE_USB_SERIAL_JTAG : R/W; bitpos: [4]; default: 1; * Configures usb_device registers write permission in tee mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_TEE_USB_DEVICE (BIT(4)) -#define TEE_WRITE_TEE_USB_DEVICE_M (TEE_WRITE_TEE_USB_DEVICE_V << TEE_WRITE_TEE_USB_DEVICE_S) -#define TEE_WRITE_TEE_USB_DEVICE_V 0x00000001U -#define TEE_WRITE_TEE_USB_DEVICE_S 4 -/** TEE_WRITE_REE0_USB_DEVICE : R/W; bitpos: [5]; default: 0; +#define TEE_WRITE_TEE_USB_SERIAL_JTAG (BIT(4)) +#define TEE_WRITE_TEE_USB_SERIAL_JTAG_M (TEE_WRITE_TEE_USB_SERIAL_JTAG_V << TEE_WRITE_TEE_USB_SERIAL_JTAG_S) +#define TEE_WRITE_TEE_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_WRITE_TEE_USB_SERIAL_JTAG_S 4 +/** TEE_WRITE_REE0_USB_SERIAL_JTAG : R/W; bitpos: [5]; default: 0; * Configures usb_device registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE0_USB_DEVICE (BIT(5)) -#define TEE_WRITE_REE0_USB_DEVICE_M (TEE_WRITE_REE0_USB_DEVICE_V << TEE_WRITE_REE0_USB_DEVICE_S) -#define TEE_WRITE_REE0_USB_DEVICE_V 0x00000001U -#define TEE_WRITE_REE0_USB_DEVICE_S 5 -/** TEE_WRITE_REE1_USB_DEVICE : R/W; bitpos: [6]; default: 0; +#define TEE_WRITE_REE0_USB_SERIAL_JTAG (BIT(5)) +#define TEE_WRITE_REE0_USB_SERIAL_JTAG_M (TEE_WRITE_REE0_USB_SERIAL_JTAG_V << TEE_WRITE_REE0_USB_SERIAL_JTAG_S) +#define TEE_WRITE_REE0_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_WRITE_REE0_USB_SERIAL_JTAG_S 5 +/** TEE_WRITE_REE1_USB_SERIAL_JTAG : R/W; bitpos: [6]; default: 0; * Configures usb_device registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE1_USB_DEVICE (BIT(6)) -#define TEE_WRITE_REE1_USB_DEVICE_M (TEE_WRITE_REE1_USB_DEVICE_V << TEE_WRITE_REE1_USB_DEVICE_S) -#define TEE_WRITE_REE1_USB_DEVICE_V 0x00000001U -#define TEE_WRITE_REE1_USB_DEVICE_S 6 -/** TEE_WRITE_REE2_USB_DEVICE : R/W; bitpos: [7]; default: 0; +#define TEE_WRITE_REE1_USB_SERIAL_JTAG (BIT(6)) +#define TEE_WRITE_REE1_USB_SERIAL_JTAG_M (TEE_WRITE_REE1_USB_SERIAL_JTAG_V << TEE_WRITE_REE1_USB_SERIAL_JTAG_S) +#define TEE_WRITE_REE1_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_WRITE_REE1_USB_SERIAL_JTAG_S 6 +/** TEE_WRITE_REE2_USB_SERIAL_JTAG : R/W; bitpos: [7]; default: 0; * Configures usb_device registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE2_USB_DEVICE (BIT(7)) -#define TEE_WRITE_REE2_USB_DEVICE_M (TEE_WRITE_REE2_USB_DEVICE_V << TEE_WRITE_REE2_USB_DEVICE_S) -#define TEE_WRITE_REE2_USB_DEVICE_V 0x00000001U -#define TEE_WRITE_REE2_USB_DEVICE_S 7 +#define TEE_WRITE_REE2_USB_SERIAL_JTAG (BIT(7)) +#define TEE_WRITE_REE2_USB_SERIAL_JTAG_M (TEE_WRITE_REE2_USB_SERIAL_JTAG_V << TEE_WRITE_REE2_USB_SERIAL_JTAG_S) +#define TEE_WRITE_REE2_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_WRITE_REE2_USB_SERIAL_JTAG_S 7 /** TEE_RMT_CTRL_REG register - * rmt read/write control register + * RMT read/write control register */ #define TEE_RMT_CTRL_REG (DR_REG_TEE_BASE + 0xb8) /** TEE_READ_TEE_RMT : R/W; bitpos: [0]; default: 1; @@ -1595,7 +1659,7 @@ extern "C" { #define TEE_WRITE_REE2_RMT_S 7 /** TEE_GDMA_CTRL_REG register - * gdma read/write control register + * GDMA read/write control register */ #define TEE_GDMA_CTRL_REG (DR_REG_TEE_BASE + 0xbc) /** TEE_READ_TEE_GDMA : R/W; bitpos: [0]; default: 1; @@ -1671,85 +1735,8 @@ extern "C" { #define TEE_WRITE_REE2_GDMA_V 0x00000001U #define TEE_WRITE_REE2_GDMA_S 7 -/** TEE_REGDMA_CTRL_REG register - * regdma read/write control register - */ -#define TEE_REGDMA_CTRL_REG (DR_REG_TEE_BASE + 0xc0) -/** TEE_READ_TEE_REGDMA : R/W; bitpos: [0]; default: 1; - * Configures regdma registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_REGDMA (BIT(0)) -#define TEE_READ_TEE_REGDMA_M (TEE_READ_TEE_REGDMA_V << TEE_READ_TEE_REGDMA_S) -#define TEE_READ_TEE_REGDMA_V 0x00000001U -#define TEE_READ_TEE_REGDMA_S 0 -/** TEE_READ_REE0_REGDMA : R/W; bitpos: [1]; default: 0; - * Configures regdma registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_REGDMA (BIT(1)) -#define TEE_READ_REE0_REGDMA_M (TEE_READ_REE0_REGDMA_V << TEE_READ_REE0_REGDMA_S) -#define TEE_READ_REE0_REGDMA_V 0x00000001U -#define TEE_READ_REE0_REGDMA_S 1 -/** TEE_READ_REE1_REGDMA : R/W; bitpos: [2]; default: 0; - * Configures regdma registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_REGDMA (BIT(2)) -#define TEE_READ_REE1_REGDMA_M (TEE_READ_REE1_REGDMA_V << TEE_READ_REE1_REGDMA_S) -#define TEE_READ_REE1_REGDMA_V 0x00000001U -#define TEE_READ_REE1_REGDMA_S 2 -/** TEE_READ_REE2_REGDMA : R/W; bitpos: [3]; default: 0; - * Configures regdma registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_REGDMA (BIT(3)) -#define TEE_READ_REE2_REGDMA_M (TEE_READ_REE2_REGDMA_V << TEE_READ_REE2_REGDMA_S) -#define TEE_READ_REE2_REGDMA_V 0x00000001U -#define TEE_READ_REE2_REGDMA_S 3 -/** TEE_WRITE_TEE_REGDMA : R/W; bitpos: [4]; default: 1; - * Configures regdma registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_REGDMA (BIT(4)) -#define TEE_WRITE_TEE_REGDMA_M (TEE_WRITE_TEE_REGDMA_V << TEE_WRITE_TEE_REGDMA_S) -#define TEE_WRITE_TEE_REGDMA_V 0x00000001U -#define TEE_WRITE_TEE_REGDMA_S 4 -/** TEE_WRITE_REE0_REGDMA : R/W; bitpos: [5]; default: 0; - * Configures regdma registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_REGDMA (BIT(5)) -#define TEE_WRITE_REE0_REGDMA_M (TEE_WRITE_REE0_REGDMA_V << TEE_WRITE_REE0_REGDMA_S) -#define TEE_WRITE_REE0_REGDMA_V 0x00000001U -#define TEE_WRITE_REE0_REGDMA_S 5 -/** TEE_WRITE_REE1_REGDMA : R/W; bitpos: [6]; default: 0; - * Configures regdma registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_REGDMA (BIT(6)) -#define TEE_WRITE_REE1_REGDMA_M (TEE_WRITE_REE1_REGDMA_V << TEE_WRITE_REE1_REGDMA_S) -#define TEE_WRITE_REE1_REGDMA_V 0x00000001U -#define TEE_WRITE_REE1_REGDMA_S 6 -/** TEE_WRITE_REE2_REGDMA : R/W; bitpos: [7]; default: 0; - * Configures regdma registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_REGDMA (BIT(7)) -#define TEE_WRITE_REE2_REGDMA_M (TEE_WRITE_REE2_REGDMA_V << TEE_WRITE_REE2_REGDMA_S) -#define TEE_WRITE_REE2_REGDMA_V 0x00000001U -#define TEE_WRITE_REE2_REGDMA_S 7 - /** TEE_ETM_CTRL_REG register - * etm read/write control register + * SOC_ETM read/write control register */ #define TEE_ETM_CTRL_REG (DR_REG_TEE_BASE + 0xc4) /** TEE_READ_TEE_ETM : R/W; bitpos: [0]; default: 1; @@ -1826,7 +1813,7 @@ extern "C" { #define TEE_WRITE_REE2_ETM_S 7 /** TEE_INTMTX_CTRL_REG register - * intmtx read/write control register + * INTMTX read/write control register */ #define TEE_INTMTX_CTRL_REG (DR_REG_TEE_BASE + 0xc8) /** TEE_READ_TEE_INTMTX_CORE : R/W; bitpos: [0]; default: 1; @@ -1903,7 +1890,7 @@ extern "C" { #define TEE_WRITE_REE2_INTMTX_CORE_S 7 /** TEE_APB_ADC_CTRL_REG register - * apb_adc read/write control register + * SAR ADC read/write control register */ #define TEE_APB_ADC_CTRL_REG (DR_REG_TEE_BASE + 0xd0) /** TEE_READ_TEE_APB_ADC : R/W; bitpos: [0]; default: 1; @@ -1980,7 +1967,7 @@ extern "C" { #define TEE_WRITE_REE2_APB_ADC_S 7 /** TEE_TIMERGROUP0_CTRL_REG register - * timergroup0 read/write control register + * TIMG0 read/write control register */ #define TEE_TIMERGROUP0_CTRL_REG (DR_REG_TEE_BASE + 0xd4) /** TEE_READ_TEE_TIMERGROUP0 : R/W; bitpos: [0]; default: 1; @@ -2057,7 +2044,7 @@ extern "C" { #define TEE_WRITE_REE2_TIMERGROUP0_S 7 /** TEE_TIMERGROUP1_CTRL_REG register - * timergroup1 read/write control register + * TIMG1 read/write control register */ #define TEE_TIMERGROUP1_CTRL_REG (DR_REG_TEE_BASE + 0xd8) /** TEE_READ_TEE_TIMERGROUP1 : R/W; bitpos: [0]; default: 1; @@ -2134,7 +2121,7 @@ extern "C" { #define TEE_WRITE_REE2_TIMERGROUP1_S 7 /** TEE_SYSTIMER_CTRL_REG register - * systimer read/write control register + * SYSTIMER read/write control register */ #define TEE_SYSTIMER_CTRL_REG (DR_REG_TEE_BASE + 0xdc) /** TEE_READ_TEE_SYSTIMER : R/W; bitpos: [0]; default: 1; @@ -2210,162 +2197,8 @@ extern "C" { #define TEE_WRITE_REE2_SYSTIMER_V 0x00000001U #define TEE_WRITE_REE2_SYSTIMER_S 7 -/** TEE_MISC_CTRL_REG register - * misc read/write control register - */ -#define TEE_MISC_CTRL_REG (DR_REG_TEE_BASE + 0xe0) -/** TEE_READ_TEE_MISC : R/W; bitpos: [0]; default: 1; - * Configures misc registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_MISC (BIT(0)) -#define TEE_READ_TEE_MISC_M (TEE_READ_TEE_MISC_V << TEE_READ_TEE_MISC_S) -#define TEE_READ_TEE_MISC_V 0x00000001U -#define TEE_READ_TEE_MISC_S 0 -/** TEE_READ_REE0_MISC : R/W; bitpos: [1]; default: 0; - * Configures misc registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_MISC (BIT(1)) -#define TEE_READ_REE0_MISC_M (TEE_READ_REE0_MISC_V << TEE_READ_REE0_MISC_S) -#define TEE_READ_REE0_MISC_V 0x00000001U -#define TEE_READ_REE0_MISC_S 1 -/** TEE_READ_REE1_MISC : R/W; bitpos: [2]; default: 0; - * Configures misc registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_MISC (BIT(2)) -#define TEE_READ_REE1_MISC_M (TEE_READ_REE1_MISC_V << TEE_READ_REE1_MISC_S) -#define TEE_READ_REE1_MISC_V 0x00000001U -#define TEE_READ_REE1_MISC_S 2 -/** TEE_READ_REE2_MISC : R/W; bitpos: [3]; default: 0; - * Configures misc registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_MISC (BIT(3)) -#define TEE_READ_REE2_MISC_M (TEE_READ_REE2_MISC_V << TEE_READ_REE2_MISC_S) -#define TEE_READ_REE2_MISC_V 0x00000001U -#define TEE_READ_REE2_MISC_S 3 -/** TEE_WRITE_TEE_MISC : R/W; bitpos: [4]; default: 1; - * Configures misc registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_MISC (BIT(4)) -#define TEE_WRITE_TEE_MISC_M (TEE_WRITE_TEE_MISC_V << TEE_WRITE_TEE_MISC_S) -#define TEE_WRITE_TEE_MISC_V 0x00000001U -#define TEE_WRITE_TEE_MISC_S 4 -/** TEE_WRITE_REE0_MISC : R/W; bitpos: [5]; default: 0; - * Configures misc registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_MISC (BIT(5)) -#define TEE_WRITE_REE0_MISC_M (TEE_WRITE_REE0_MISC_V << TEE_WRITE_REE0_MISC_S) -#define TEE_WRITE_REE0_MISC_V 0x00000001U -#define TEE_WRITE_REE0_MISC_S 5 -/** TEE_WRITE_REE1_MISC : R/W; bitpos: [6]; default: 0; - * Configures misc registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_MISC (BIT(6)) -#define TEE_WRITE_REE1_MISC_M (TEE_WRITE_REE1_MISC_V << TEE_WRITE_REE1_MISC_S) -#define TEE_WRITE_REE1_MISC_V 0x00000001U -#define TEE_WRITE_REE1_MISC_S 6 -/** TEE_WRITE_REE2_MISC : R/W; bitpos: [7]; default: 0; - * Configures misc registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_MISC (BIT(7)) -#define TEE_WRITE_REE2_MISC_M (TEE_WRITE_REE2_MISC_V << TEE_WRITE_REE2_MISC_S) -#define TEE_WRITE_REE2_MISC_V 0x00000001U -#define TEE_WRITE_REE2_MISC_S 7 - -/** TEE_PVT_MONITOR_CTRL_REG register - * pvt_monitor read/write control register - */ -#define TEE_PVT_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0xf0) -/** TEE_READ_TEE_PVT_MONITOR : R/W; bitpos: [0]; default: 1; - * Configures pvt_monitor registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_PVT_MONITOR (BIT(0)) -#define TEE_READ_TEE_PVT_MONITOR_M (TEE_READ_TEE_PVT_MONITOR_V << TEE_READ_TEE_PVT_MONITOR_S) -#define TEE_READ_TEE_PVT_MONITOR_V 0x00000001U -#define TEE_READ_TEE_PVT_MONITOR_S 0 -/** TEE_READ_REE0_PVT_MONITOR : R/W; bitpos: [1]; default: 0; - * Configures pvt_monitor registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_PVT_MONITOR (BIT(1)) -#define TEE_READ_REE0_PVT_MONITOR_M (TEE_READ_REE0_PVT_MONITOR_V << TEE_READ_REE0_PVT_MONITOR_S) -#define TEE_READ_REE0_PVT_MONITOR_V 0x00000001U -#define TEE_READ_REE0_PVT_MONITOR_S 1 -/** TEE_READ_REE1_PVT_MONITOR : R/W; bitpos: [2]; default: 0; - * Configures pvt_monitor registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_PVT_MONITOR (BIT(2)) -#define TEE_READ_REE1_PVT_MONITOR_M (TEE_READ_REE1_PVT_MONITOR_V << TEE_READ_REE1_PVT_MONITOR_S) -#define TEE_READ_REE1_PVT_MONITOR_V 0x00000001U -#define TEE_READ_REE1_PVT_MONITOR_S 2 -/** TEE_READ_REE2_PVT_MONITOR : R/W; bitpos: [3]; default: 0; - * Configures pvt_monitor registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_PVT_MONITOR (BIT(3)) -#define TEE_READ_REE2_PVT_MONITOR_M (TEE_READ_REE2_PVT_MONITOR_V << TEE_READ_REE2_PVT_MONITOR_S) -#define TEE_READ_REE2_PVT_MONITOR_V 0x00000001U -#define TEE_READ_REE2_PVT_MONITOR_S 3 -/** TEE_WRITE_TEE_PVT_MONITOR : R/W; bitpos: [4]; default: 1; - * Configures pvt_monitor registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_PVT_MONITOR (BIT(4)) -#define TEE_WRITE_TEE_PVT_MONITOR_M (TEE_WRITE_TEE_PVT_MONITOR_V << TEE_WRITE_TEE_PVT_MONITOR_S) -#define TEE_WRITE_TEE_PVT_MONITOR_V 0x00000001U -#define TEE_WRITE_TEE_PVT_MONITOR_S 4 -/** TEE_WRITE_REE0_PVT_MONITOR : R/W; bitpos: [5]; default: 0; - * Configures pvt_monitor registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_PVT_MONITOR (BIT(5)) -#define TEE_WRITE_REE0_PVT_MONITOR_M (TEE_WRITE_REE0_PVT_MONITOR_V << TEE_WRITE_REE0_PVT_MONITOR_S) -#define TEE_WRITE_REE0_PVT_MONITOR_V 0x00000001U -#define TEE_WRITE_REE0_PVT_MONITOR_S 5 -/** TEE_WRITE_REE1_PVT_MONITOR : R/W; bitpos: [6]; default: 0; - * Configures pvt_monitor registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_PVT_MONITOR (BIT(6)) -#define TEE_WRITE_REE1_PVT_MONITOR_M (TEE_WRITE_REE1_PVT_MONITOR_V << TEE_WRITE_REE1_PVT_MONITOR_S) -#define TEE_WRITE_REE1_PVT_MONITOR_V 0x00000001U -#define TEE_WRITE_REE1_PVT_MONITOR_S 6 -/** TEE_WRITE_REE2_PVT_MONITOR : R/W; bitpos: [7]; default: 0; - * Configures pvt_monitor registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_PVT_MONITOR (BIT(7)) -#define TEE_WRITE_REE2_PVT_MONITOR_M (TEE_WRITE_REE2_PVT_MONITOR_V << TEE_WRITE_REE2_PVT_MONITOR_S) -#define TEE_WRITE_REE2_PVT_MONITOR_V 0x00000001U -#define TEE_WRITE_REE2_PVT_MONITOR_S 7 - /** TEE_PCNT_CTRL_REG register - * pcnt read/write control register + * PCNT read/write control register */ #define TEE_PCNT_CTRL_REG (DR_REG_TEE_BASE + 0xf4) /** TEE_READ_TEE_PCNT : R/W; bitpos: [0]; default: 1; @@ -2442,7 +2275,7 @@ extern "C" { #define TEE_WRITE_REE2_PCNT_S 7 /** TEE_IOMUX_CTRL_REG register - * iomux read/write control register + * IO MUX read/write control register */ #define TEE_IOMUX_CTRL_REG (DR_REG_TEE_BASE + 0xf8) /** TEE_READ_TEE_IOMUX : R/W; bitpos: [0]; default: 1; @@ -2519,7 +2352,7 @@ extern "C" { #define TEE_WRITE_REE2_IOMUX_S 7 /** TEE_PSRAM_MEM_MONITOR_CTRL_REG register - * psram_mem_monitor read/write control register + * PSRAM_MEM_MONITOR read/write control register */ #define TEE_PSRAM_MEM_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0xfc) /** TEE_READ_TEE_PSRAM_MEM_MONITOR : R/W; bitpos: [0]; default: 1; @@ -2596,7 +2429,7 @@ extern "C" { #define TEE_WRITE_REE2_PSRAM_MEM_MONITOR_S 7 /** TEE_MEM_ACS_MONITOR_CTRL_REG register - * mem_acs_monitor read/write control register + * TCM_MEM_MONITOR read/write control register */ #define TEE_MEM_ACS_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0x100) /** TEE_READ_TEE_MEM_ACS_MONITOR : R/W; bitpos: [0]; default: 1; @@ -2673,7 +2506,7 @@ extern "C" { #define TEE_WRITE_REE2_MEM_ACS_MONITOR_S 7 /** TEE_HP_SYSTEM_REG_CTRL_REG register - * hp_system_reg read/write control register + * HP_SYSREG read/write control register */ #define TEE_HP_SYSTEM_REG_CTRL_REG (DR_REG_TEE_BASE + 0x104) /** TEE_READ_TEE_HP_SYSTEM_REG : R/W; bitpos: [0]; default: 1; @@ -2750,7 +2583,7 @@ extern "C" { #define TEE_WRITE_REE2_HP_SYSTEM_REG_S 7 /** TEE_PCR_REG_CTRL_REG register - * pcr_reg read/write control register + * PCR read/write control register */ #define TEE_PCR_REG_CTRL_REG (DR_REG_TEE_BASE + 0x108) /** TEE_READ_TEE_PCR_REG : R/W; bitpos: [0]; default: 1; @@ -2827,7 +2660,7 @@ extern "C" { #define TEE_WRITE_REE2_PCR_REG_S 7 /** TEE_MSPI_CTRL_REG register - * mspi read/write control register + * SPI01 read/write control register */ #define TEE_MSPI_CTRL_REG (DR_REG_TEE_BASE + 0x10c) /** TEE_READ_TEE_MSPI : R/W; bitpos: [0]; default: 1; @@ -2904,7 +2737,7 @@ extern "C" { #define TEE_WRITE_REE2_MSPI_S 7 /** TEE_HP_APM_CTRL_REG register - * hp_apm read/write control register + * HP_APM and LP_APM0 read/write control register */ #define TEE_HP_APM_CTRL_REG (DR_REG_TEE_BASE + 0x110) /** TEE_READ_TEE_HP_APM : R/W; bitpos: [0]; default: 1; @@ -2981,7 +2814,7 @@ extern "C" { #define TEE_WRITE_REE2_HP_APM_S 7 /** TEE_CPU_APM_CTRL_REG register - * cpu_apm read/write control register + * CPU_APM_REG read/write control register */ #define TEE_CPU_APM_CTRL_REG (DR_REG_TEE_BASE + 0x114) /** TEE_READ_TEE_CPU_APM : R/W; bitpos: [0]; default: 1; @@ -3058,7 +2891,7 @@ extern "C" { #define TEE_WRITE_REE2_CPU_APM_S 7 /** TEE_TEE_CTRL_REG register - * tee read/write control register + * TEE read/write control register */ #define TEE_TEE_CTRL_REG (DR_REG_TEE_BASE + 0x118) /** TEE_READ_TEE_TEE : R/W; bitpos: [0]; default: 1; @@ -3135,7 +2968,8 @@ extern "C" { #define TEE_WRITE_REE2_TEE_S 7 /** TEE_CRYPT_CTRL_REG register - * crypt read/write control register + * CRYPT read/write control register, including security peripherals from AES to ECDSA + * address range */ #define TEE_CRYPT_CTRL_REG (DR_REG_TEE_BASE + 0x11c) /** TEE_READ_TEE_CRYPT : R/W; bitpos: [0]; default: 1; @@ -3212,7 +3046,7 @@ extern "C" { #define TEE_WRITE_REE2_CRYPT_S 7 /** TEE_TRACE_CTRL_REG register - * trace read/write control register + * TRACE read/write control register */ #define TEE_TRACE_CTRL_REG (DR_REG_TEE_BASE + 0x120) /** TEE_READ_TEE_TRACE : R/W; bitpos: [0]; default: 1; @@ -3289,7 +3123,7 @@ extern "C" { #define TEE_WRITE_REE2_TRACE_S 7 /** TEE_CPU_BUS_MONITOR_CTRL_REG register - * cpu_bus_monitor read/write control register + * BUS_MONITOR read/write control register */ #define TEE_CPU_BUS_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0x128) /** TEE_READ_TEE_CPU_BUS_MONITOR : R/W; bitpos: [0]; default: 1; @@ -3366,7 +3200,7 @@ extern "C" { #define TEE_WRITE_REE2_CPU_BUS_MONITOR_S 7 /** TEE_INTPRI_REG_CTRL_REG register - * intpri_reg read/write control register + * INTPRI_REG read/write control register */ #define TEE_INTPRI_REG_CTRL_REG (DR_REG_TEE_BASE + 0x12c) /** TEE_READ_TEE_INTPRI_REG : R/W; bitpos: [0]; default: 1; @@ -3442,239 +3276,85 @@ extern "C" { #define TEE_WRITE_REE2_INTPRI_REG_V 0x00000001U #define TEE_WRITE_REE2_INTPRI_REG_S 7 -/** TEE_CACHE_CFG_CTRL_REG register - * cache_cfg read/write control register +/** TEE_TWAI1_CTRL_REG register + * TWAI1 read/write control register */ -#define TEE_CACHE_CFG_CTRL_REG (DR_REG_TEE_BASE + 0x130) -/** TEE_READ_TEE_CACHE_CFG : R/W; bitpos: [0]; default: 1; - * Configures cache_cfg registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_CACHE_CFG (BIT(0)) -#define TEE_READ_TEE_CACHE_CFG_M (TEE_READ_TEE_CACHE_CFG_V << TEE_READ_TEE_CACHE_CFG_S) -#define TEE_READ_TEE_CACHE_CFG_V 0x00000001U -#define TEE_READ_TEE_CACHE_CFG_S 0 -/** TEE_READ_REE0_CACHE_CFG : R/W; bitpos: [1]; default: 0; - * Configures cache_cfg registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_CACHE_CFG (BIT(1)) -#define TEE_READ_REE0_CACHE_CFG_M (TEE_READ_REE0_CACHE_CFG_V << TEE_READ_REE0_CACHE_CFG_S) -#define TEE_READ_REE0_CACHE_CFG_V 0x00000001U -#define TEE_READ_REE0_CACHE_CFG_S 1 -/** TEE_READ_REE1_CACHE_CFG : R/W; bitpos: [2]; default: 0; - * Configures cache_cfg registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_CACHE_CFG (BIT(2)) -#define TEE_READ_REE1_CACHE_CFG_M (TEE_READ_REE1_CACHE_CFG_V << TEE_READ_REE1_CACHE_CFG_S) -#define TEE_READ_REE1_CACHE_CFG_V 0x00000001U -#define TEE_READ_REE1_CACHE_CFG_S 2 -/** TEE_READ_REE2_CACHE_CFG : R/W; bitpos: [3]; default: 0; - * Configures cache_cfg registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_CACHE_CFG (BIT(3)) -#define TEE_READ_REE2_CACHE_CFG_M (TEE_READ_REE2_CACHE_CFG_V << TEE_READ_REE2_CACHE_CFG_S) -#define TEE_READ_REE2_CACHE_CFG_V 0x00000001U -#define TEE_READ_REE2_CACHE_CFG_S 3 -/** TEE_WRITE_TEE_CACHE_CFG : R/W; bitpos: [4]; default: 1; - * Configures cache_cfg registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_CACHE_CFG (BIT(4)) -#define TEE_WRITE_TEE_CACHE_CFG_M (TEE_WRITE_TEE_CACHE_CFG_V << TEE_WRITE_TEE_CACHE_CFG_S) -#define TEE_WRITE_TEE_CACHE_CFG_V 0x00000001U -#define TEE_WRITE_TEE_CACHE_CFG_S 4 -/** TEE_WRITE_REE0_CACHE_CFG : R/W; bitpos: [5]; default: 0; - * Configures cache_cfg registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_CACHE_CFG (BIT(5)) -#define TEE_WRITE_REE0_CACHE_CFG_M (TEE_WRITE_REE0_CACHE_CFG_V << TEE_WRITE_REE0_CACHE_CFG_S) -#define TEE_WRITE_REE0_CACHE_CFG_V 0x00000001U -#define TEE_WRITE_REE0_CACHE_CFG_S 5 -/** TEE_WRITE_REE1_CACHE_CFG : R/W; bitpos: [6]; default: 0; - * Configures cache_cfg registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_CACHE_CFG (BIT(6)) -#define TEE_WRITE_REE1_CACHE_CFG_M (TEE_WRITE_REE1_CACHE_CFG_V << TEE_WRITE_REE1_CACHE_CFG_S) -#define TEE_WRITE_REE1_CACHE_CFG_V 0x00000001U -#define TEE_WRITE_REE1_CACHE_CFG_S 6 -/** TEE_WRITE_REE2_CACHE_CFG : R/W; bitpos: [7]; default: 0; - * Configures cache_cfg registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_CACHE_CFG (BIT(7)) -#define TEE_WRITE_REE2_CACHE_CFG_M (TEE_WRITE_REE2_CACHE_CFG_V << TEE_WRITE_REE2_CACHE_CFG_S) -#define TEE_WRITE_REE2_CACHE_CFG_V 0x00000001U -#define TEE_WRITE_REE2_CACHE_CFG_S 7 - -/** TEE_MODEM_CTRL_REG register - * modem read/write control register - */ -#define TEE_MODEM_CTRL_REG (DR_REG_TEE_BASE + 0x134) -/** TEE_READ_TEE_MODEM : R/W; bitpos: [0]; default: 1; - * Configures modem registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_MODEM (BIT(0)) -#define TEE_READ_TEE_MODEM_M (TEE_READ_TEE_MODEM_V << TEE_READ_TEE_MODEM_S) -#define TEE_READ_TEE_MODEM_V 0x00000001U -#define TEE_READ_TEE_MODEM_S 0 -/** TEE_READ_REE0_MODEM : R/W; bitpos: [1]; default: 0; - * Configures modem registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_MODEM (BIT(1)) -#define TEE_READ_REE0_MODEM_M (TEE_READ_REE0_MODEM_V << TEE_READ_REE0_MODEM_S) -#define TEE_READ_REE0_MODEM_V 0x00000001U -#define TEE_READ_REE0_MODEM_S 1 -/** TEE_READ_REE1_MODEM : R/W; bitpos: [2]; default: 0; - * Configures modem registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_MODEM (BIT(2)) -#define TEE_READ_REE1_MODEM_M (TEE_READ_REE1_MODEM_V << TEE_READ_REE1_MODEM_S) -#define TEE_READ_REE1_MODEM_V 0x00000001U -#define TEE_READ_REE1_MODEM_S 2 -/** TEE_READ_REE2_MODEM : R/W; bitpos: [3]; default: 0; - * Configures modem registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_MODEM (BIT(3)) -#define TEE_READ_REE2_MODEM_M (TEE_READ_REE2_MODEM_V << TEE_READ_REE2_MODEM_S) -#define TEE_READ_REE2_MODEM_V 0x00000001U -#define TEE_READ_REE2_MODEM_S 3 -/** TEE_WRITE_TEE_MODEM : R/W; bitpos: [4]; default: 1; - * Configures modem registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_MODEM (BIT(4)) -#define TEE_WRITE_TEE_MODEM_M (TEE_WRITE_TEE_MODEM_V << TEE_WRITE_TEE_MODEM_S) -#define TEE_WRITE_TEE_MODEM_V 0x00000001U -#define TEE_WRITE_TEE_MODEM_S 4 -/** TEE_WRITE_REE0_MODEM : R/W; bitpos: [5]; default: 0; - * Configures modem registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_MODEM (BIT(5)) -#define TEE_WRITE_REE0_MODEM_M (TEE_WRITE_REE0_MODEM_V << TEE_WRITE_REE0_MODEM_S) -#define TEE_WRITE_REE0_MODEM_V 0x00000001U -#define TEE_WRITE_REE0_MODEM_S 5 -/** TEE_WRITE_REE1_MODEM : R/W; bitpos: [6]; default: 0; - * Configures modem registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_MODEM (BIT(6)) -#define TEE_WRITE_REE1_MODEM_M (TEE_WRITE_REE1_MODEM_V << TEE_WRITE_REE1_MODEM_S) -#define TEE_WRITE_REE1_MODEM_V 0x00000001U -#define TEE_WRITE_REE1_MODEM_S 6 -/** TEE_WRITE_REE2_MODEM : R/W; bitpos: [7]; default: 0; - * Configures modem registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_MODEM (BIT(7)) -#define TEE_WRITE_REE2_MODEM_M (TEE_WRITE_REE2_MODEM_V << TEE_WRITE_REE2_MODEM_S) -#define TEE_WRITE_REE2_MODEM_V 0x00000001U -#define TEE_WRITE_REE2_MODEM_S 7 - -/** TEE_CAN1_CTRL_REG register - * can1 read/write control register - */ -#define TEE_CAN1_CTRL_REG (DR_REG_TEE_BASE + 0x138) -/** TEE_READ_TEE_CAN1 : R/W; bitpos: [0]; default: 1; +#define TEE_TWAI1_CTRL_REG (DR_REG_TEE_BASE + 0x138) +/** TEE_READ_TEE_TWAI1 : R/W; bitpos: [0]; default: 1; * Configures can1 registers read permission in tee mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_TEE_CAN1 (BIT(0)) -#define TEE_READ_TEE_CAN1_M (TEE_READ_TEE_CAN1_V << TEE_READ_TEE_CAN1_S) -#define TEE_READ_TEE_CAN1_V 0x00000001U -#define TEE_READ_TEE_CAN1_S 0 -/** TEE_READ_REE0_CAN1 : R/W; bitpos: [1]; default: 0; +#define TEE_READ_TEE_TWAI1 (BIT(0)) +#define TEE_READ_TEE_TWAI1_M (TEE_READ_TEE_TWAI1_V << TEE_READ_TEE_TWAI1_S) +#define TEE_READ_TEE_TWAI1_V 0x00000001U +#define TEE_READ_TEE_TWAI1_S 0 +/** TEE_READ_REE0_TWAI1 : R/W; bitpos: [1]; default: 0; * Configures can1 registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE0_CAN1 (BIT(1)) -#define TEE_READ_REE0_CAN1_M (TEE_READ_REE0_CAN1_V << TEE_READ_REE0_CAN1_S) -#define TEE_READ_REE0_CAN1_V 0x00000001U -#define TEE_READ_REE0_CAN1_S 1 -/** TEE_READ_REE1_CAN1 : R/W; bitpos: [2]; default: 0; +#define TEE_READ_REE0_TWAI1 (BIT(1)) +#define TEE_READ_REE0_TWAI1_M (TEE_READ_REE0_TWAI1_V << TEE_READ_REE0_TWAI1_S) +#define TEE_READ_REE0_TWAI1_V 0x00000001U +#define TEE_READ_REE0_TWAI1_S 1 +/** TEE_READ_REE1_TWAI1 : R/W; bitpos: [2]; default: 0; * Configures can1 registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE1_CAN1 (BIT(2)) -#define TEE_READ_REE1_CAN1_M (TEE_READ_REE1_CAN1_V << TEE_READ_REE1_CAN1_S) -#define TEE_READ_REE1_CAN1_V 0x00000001U -#define TEE_READ_REE1_CAN1_S 2 -/** TEE_READ_REE2_CAN1 : R/W; bitpos: [3]; default: 0; +#define TEE_READ_REE1_TWAI1 (BIT(2)) +#define TEE_READ_REE1_TWAI1_M (TEE_READ_REE1_TWAI1_V << TEE_READ_REE1_TWAI1_S) +#define TEE_READ_REE1_TWAI1_V 0x00000001U +#define TEE_READ_REE1_TWAI1_S 2 +/** TEE_READ_REE2_TWAI1 : R/W; bitpos: [3]; default: 0; * Configures can1 registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE2_CAN1 (BIT(3)) -#define TEE_READ_REE2_CAN1_M (TEE_READ_REE2_CAN1_V << TEE_READ_REE2_CAN1_S) -#define TEE_READ_REE2_CAN1_V 0x00000001U -#define TEE_READ_REE2_CAN1_S 3 -/** TEE_WRITE_TEE_CAN1 : R/W; bitpos: [4]; default: 1; +#define TEE_READ_REE2_TWAI1 (BIT(3)) +#define TEE_READ_REE2_TWAI1_M (TEE_READ_REE2_TWAI1_V << TEE_READ_REE2_TWAI1_S) +#define TEE_READ_REE2_TWAI1_V 0x00000001U +#define TEE_READ_REE2_TWAI1_S 3 +/** TEE_WRITE_TEE_TWAI1 : R/W; bitpos: [4]; default: 1; * Configures can1 registers write permission in tee mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_TEE_CAN1 (BIT(4)) -#define TEE_WRITE_TEE_CAN1_M (TEE_WRITE_TEE_CAN1_V << TEE_WRITE_TEE_CAN1_S) -#define TEE_WRITE_TEE_CAN1_V 0x00000001U -#define TEE_WRITE_TEE_CAN1_S 4 -/** TEE_WRITE_REE0_CAN1 : R/W; bitpos: [5]; default: 0; +#define TEE_WRITE_TEE_TWAI1 (BIT(4)) +#define TEE_WRITE_TEE_TWAI1_M (TEE_WRITE_TEE_TWAI1_V << TEE_WRITE_TEE_TWAI1_S) +#define TEE_WRITE_TEE_TWAI1_V 0x00000001U +#define TEE_WRITE_TEE_TWAI1_S 4 +/** TEE_WRITE_REE0_TWAI1 : R/W; bitpos: [5]; default: 0; * Configures can1 registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE0_CAN1 (BIT(5)) -#define TEE_WRITE_REE0_CAN1_M (TEE_WRITE_REE0_CAN1_V << TEE_WRITE_REE0_CAN1_S) -#define TEE_WRITE_REE0_CAN1_V 0x00000001U -#define TEE_WRITE_REE0_CAN1_S 5 -/** TEE_WRITE_REE1_CAN1 : R/W; bitpos: [6]; default: 0; +#define TEE_WRITE_REE0_TWAI1 (BIT(5)) +#define TEE_WRITE_REE0_TWAI1_M (TEE_WRITE_REE0_TWAI1_V << TEE_WRITE_REE0_TWAI1_S) +#define TEE_WRITE_REE0_TWAI1_V 0x00000001U +#define TEE_WRITE_REE0_TWAI1_S 5 +/** TEE_WRITE_REE1_TWAI1 : R/W; bitpos: [6]; default: 0; * Configures can1 registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE1_CAN1 (BIT(6)) -#define TEE_WRITE_REE1_CAN1_M (TEE_WRITE_REE1_CAN1_V << TEE_WRITE_REE1_CAN1_S) -#define TEE_WRITE_REE1_CAN1_V 0x00000001U -#define TEE_WRITE_REE1_CAN1_S 6 -/** TEE_WRITE_REE2_CAN1 : R/W; bitpos: [7]; default: 0; +#define TEE_WRITE_REE1_TWAI1 (BIT(6)) +#define TEE_WRITE_REE1_TWAI1_M (TEE_WRITE_REE1_TWAI1_V << TEE_WRITE_REE1_TWAI1_S) +#define TEE_WRITE_REE1_TWAI1_V 0x00000001U +#define TEE_WRITE_REE1_TWAI1_S 6 +/** TEE_WRITE_REE2_TWAI1 : R/W; bitpos: [7]; default: 0; * Configures can1 registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE2_CAN1 (BIT(7)) -#define TEE_WRITE_REE2_CAN1_M (TEE_WRITE_REE2_CAN1_V << TEE_WRITE_REE2_CAN1_S) -#define TEE_WRITE_REE2_CAN1_V 0x00000001U -#define TEE_WRITE_REE2_CAN1_S 7 +#define TEE_WRITE_REE2_TWAI1 (BIT(7)) +#define TEE_WRITE_REE2_TWAI1_M (TEE_WRITE_REE2_TWAI1_V << TEE_WRITE_REE2_TWAI1_S) +#define TEE_WRITE_REE2_TWAI1_V 0x00000001U +#define TEE_WRITE_REE2_TWAI1_S 7 /** TEE_SPI2_CTRL_REG register - * spi2 read/write control register + * SPI2 read/write control register */ #define TEE_SPI2_CTRL_REG (DR_REG_TEE_BASE + 0x13c) /** TEE_READ_TEE_SPI2 : R/W; bitpos: [0]; default: 1; @@ -3751,7 +3431,7 @@ extern "C" { #define TEE_WRITE_REE2_SPI2_S 7 /** TEE_BS_CTRL_REG register - * bs read/write control register + * BITSCRAMBLER read/write control register */ #define TEE_BS_CTRL_REG (DR_REG_TEE_BASE + 0x140) /** TEE_READ_TEE_BS : R/W; bitpos: [0]; default: 1; @@ -3827,399 +3507,14 @@ extern "C" { #define TEE_WRITE_REE2_BS_V 0x00000001U #define TEE_WRITE_REE2_BS_S 7 -/** TEE_KM_CTRL_REG register - * km read/write control register - */ -#define TEE_KM_CTRL_REG (DR_REG_TEE_BASE + 0x144) -/** TEE_READ_TEE_KM : R/W; bitpos: [0]; default: 1; - * Configures km registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_KM (BIT(0)) -#define TEE_READ_TEE_KM_M (TEE_READ_TEE_KM_V << TEE_READ_TEE_KM_S) -#define TEE_READ_TEE_KM_V 0x00000001U -#define TEE_READ_TEE_KM_S 0 -/** TEE_READ_REE0_KM : R/W; bitpos: [1]; default: 0; - * Configures km registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_KM (BIT(1)) -#define TEE_READ_REE0_KM_M (TEE_READ_REE0_KM_V << TEE_READ_REE0_KM_S) -#define TEE_READ_REE0_KM_V 0x00000001U -#define TEE_READ_REE0_KM_S 1 -/** TEE_READ_REE1_KM : R/W; bitpos: [2]; default: 0; - * Configures km registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_KM (BIT(2)) -#define TEE_READ_REE1_KM_M (TEE_READ_REE1_KM_V << TEE_READ_REE1_KM_S) -#define TEE_READ_REE1_KM_V 0x00000001U -#define TEE_READ_REE1_KM_S 2 -/** TEE_READ_REE2_KM : R/W; bitpos: [3]; default: 0; - * Configures km registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_KM (BIT(3)) -#define TEE_READ_REE2_KM_M (TEE_READ_REE2_KM_V << TEE_READ_REE2_KM_S) -#define TEE_READ_REE2_KM_V 0x00000001U -#define TEE_READ_REE2_KM_S 3 -/** TEE_WRITE_TEE_KM : R/W; bitpos: [4]; default: 1; - * Configures km registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_KM (BIT(4)) -#define TEE_WRITE_TEE_KM_M (TEE_WRITE_TEE_KM_V << TEE_WRITE_TEE_KM_S) -#define TEE_WRITE_TEE_KM_V 0x00000001U -#define TEE_WRITE_TEE_KM_S 4 -/** TEE_WRITE_REE0_KM : R/W; bitpos: [5]; default: 0; - * Configures km registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_KM (BIT(5)) -#define TEE_WRITE_REE0_KM_M (TEE_WRITE_REE0_KM_V << TEE_WRITE_REE0_KM_S) -#define TEE_WRITE_REE0_KM_V 0x00000001U -#define TEE_WRITE_REE0_KM_S 5 -/** TEE_WRITE_REE1_KM : R/W; bitpos: [6]; default: 0; - * Configures km registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_KM (BIT(6)) -#define TEE_WRITE_REE1_KM_M (TEE_WRITE_REE1_KM_V << TEE_WRITE_REE1_KM_S) -#define TEE_WRITE_REE1_KM_V 0x00000001U -#define TEE_WRITE_REE1_KM_S 6 -/** TEE_WRITE_REE2_KM : R/W; bitpos: [7]; default: 0; - * Configures km registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_KM (BIT(7)) -#define TEE_WRITE_REE2_KM_M (TEE_WRITE_REE2_KM_V << TEE_WRITE_REE2_KM_S) -#define TEE_WRITE_REE2_KM_V 0x00000001U -#define TEE_WRITE_REE2_KM_S 7 - -/** TEE_MODEM_PWR_CTRL_REG register - * modem_pwr read/write control register - */ -#define TEE_MODEM_PWR_CTRL_REG (DR_REG_TEE_BASE + 0x148) -/** TEE_READ_TEE_MODEM_PWR : R/W; bitpos: [0]; default: 1; - * Configures modem_pwr registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_MODEM_PWR (BIT(0)) -#define TEE_READ_TEE_MODEM_PWR_M (TEE_READ_TEE_MODEM_PWR_V << TEE_READ_TEE_MODEM_PWR_S) -#define TEE_READ_TEE_MODEM_PWR_V 0x00000001U -#define TEE_READ_TEE_MODEM_PWR_S 0 -/** TEE_READ_REE0_MODEM_PWR : R/W; bitpos: [1]; default: 0; - * Configures modem_pwr registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_MODEM_PWR (BIT(1)) -#define TEE_READ_REE0_MODEM_PWR_M (TEE_READ_REE0_MODEM_PWR_V << TEE_READ_REE0_MODEM_PWR_S) -#define TEE_READ_REE0_MODEM_PWR_V 0x00000001U -#define TEE_READ_REE0_MODEM_PWR_S 1 -/** TEE_READ_REE1_MODEM_PWR : R/W; bitpos: [2]; default: 0; - * Configures modem_pwr registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_MODEM_PWR (BIT(2)) -#define TEE_READ_REE1_MODEM_PWR_M (TEE_READ_REE1_MODEM_PWR_V << TEE_READ_REE1_MODEM_PWR_S) -#define TEE_READ_REE1_MODEM_PWR_V 0x00000001U -#define TEE_READ_REE1_MODEM_PWR_S 2 -/** TEE_READ_REE2_MODEM_PWR : R/W; bitpos: [3]; default: 0; - * Configures modem_pwr registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_MODEM_PWR (BIT(3)) -#define TEE_READ_REE2_MODEM_PWR_M (TEE_READ_REE2_MODEM_PWR_V << TEE_READ_REE2_MODEM_PWR_S) -#define TEE_READ_REE2_MODEM_PWR_V 0x00000001U -#define TEE_READ_REE2_MODEM_PWR_S 3 -/** TEE_WRITE_TEE_MODEM_PWR : R/W; bitpos: [4]; default: 1; - * Configures modem_pwr registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_MODEM_PWR (BIT(4)) -#define TEE_WRITE_TEE_MODEM_PWR_M (TEE_WRITE_TEE_MODEM_PWR_V << TEE_WRITE_TEE_MODEM_PWR_S) -#define TEE_WRITE_TEE_MODEM_PWR_V 0x00000001U -#define TEE_WRITE_TEE_MODEM_PWR_S 4 -/** TEE_WRITE_REE0_MODEM_PWR : R/W; bitpos: [5]; default: 0; - * Configures modem_pwr registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_MODEM_PWR (BIT(5)) -#define TEE_WRITE_REE0_MODEM_PWR_M (TEE_WRITE_REE0_MODEM_PWR_V << TEE_WRITE_REE0_MODEM_PWR_S) -#define TEE_WRITE_REE0_MODEM_PWR_V 0x00000001U -#define TEE_WRITE_REE0_MODEM_PWR_S 5 -/** TEE_WRITE_REE1_MODEM_PWR : R/W; bitpos: [6]; default: 0; - * Configures modem_pwr registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_MODEM_PWR (BIT(6)) -#define TEE_WRITE_REE1_MODEM_PWR_M (TEE_WRITE_REE1_MODEM_PWR_V << TEE_WRITE_REE1_MODEM_PWR_S) -#define TEE_WRITE_REE1_MODEM_PWR_V 0x00000001U -#define TEE_WRITE_REE1_MODEM_PWR_S 6 -/** TEE_WRITE_REE2_MODEM_PWR : R/W; bitpos: [7]; default: 0; - * Configures modem_pwr registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_MODEM_PWR (BIT(7)) -#define TEE_WRITE_REE2_MODEM_PWR_M (TEE_WRITE_REE2_MODEM_PWR_V << TEE_WRITE_REE2_MODEM_PWR_S) -#define TEE_WRITE_REE2_MODEM_PWR_V 0x00000001U -#define TEE_WRITE_REE2_MODEM_PWR_S 7 - -/** TEE_HINF_CTRL_REG register - * hinf read/write control register - */ -#define TEE_HINF_CTRL_REG (DR_REG_TEE_BASE + 0x14c) -/** TEE_READ_TEE_HINF : R/W; bitpos: [0]; default: 1; - * Configures hinf registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_HINF (BIT(0)) -#define TEE_READ_TEE_HINF_M (TEE_READ_TEE_HINF_V << TEE_READ_TEE_HINF_S) -#define TEE_READ_TEE_HINF_V 0x00000001U -#define TEE_READ_TEE_HINF_S 0 -/** TEE_READ_REE0_HINF : R/W; bitpos: [1]; default: 0; - * Configures hinf registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_HINF (BIT(1)) -#define TEE_READ_REE0_HINF_M (TEE_READ_REE0_HINF_V << TEE_READ_REE0_HINF_S) -#define TEE_READ_REE0_HINF_V 0x00000001U -#define TEE_READ_REE0_HINF_S 1 -/** TEE_READ_REE1_HINF : R/W; bitpos: [2]; default: 0; - * Configures hinf registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_HINF (BIT(2)) -#define TEE_READ_REE1_HINF_M (TEE_READ_REE1_HINF_V << TEE_READ_REE1_HINF_S) -#define TEE_READ_REE1_HINF_V 0x00000001U -#define TEE_READ_REE1_HINF_S 2 -/** TEE_READ_REE2_HINF : R/W; bitpos: [3]; default: 0; - * Configures hinf registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_HINF (BIT(3)) -#define TEE_READ_REE2_HINF_M (TEE_READ_REE2_HINF_V << TEE_READ_REE2_HINF_S) -#define TEE_READ_REE2_HINF_V 0x00000001U -#define TEE_READ_REE2_HINF_S 3 -/** TEE_WRITE_TEE_HINF : R/W; bitpos: [4]; default: 1; - * Configures hinf registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_HINF (BIT(4)) -#define TEE_WRITE_TEE_HINF_M (TEE_WRITE_TEE_HINF_V << TEE_WRITE_TEE_HINF_S) -#define TEE_WRITE_TEE_HINF_V 0x00000001U -#define TEE_WRITE_TEE_HINF_S 4 -/** TEE_WRITE_REE0_HINF : R/W; bitpos: [5]; default: 0; - * Configures hinf registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_HINF (BIT(5)) -#define TEE_WRITE_REE0_HINF_M (TEE_WRITE_REE0_HINF_V << TEE_WRITE_REE0_HINF_S) -#define TEE_WRITE_REE0_HINF_V 0x00000001U -#define TEE_WRITE_REE0_HINF_S 5 -/** TEE_WRITE_REE1_HINF : R/W; bitpos: [6]; default: 0; - * Configures hinf registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_HINF (BIT(6)) -#define TEE_WRITE_REE1_HINF_M (TEE_WRITE_REE1_HINF_V << TEE_WRITE_REE1_HINF_S) -#define TEE_WRITE_REE1_HINF_V 0x00000001U -#define TEE_WRITE_REE1_HINF_S 6 -/** TEE_WRITE_REE2_HINF : R/W; bitpos: [7]; default: 0; - * Configures hinf registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_HINF (BIT(7)) -#define TEE_WRITE_REE2_HINF_M (TEE_WRITE_REE2_HINF_V << TEE_WRITE_REE2_HINF_S) -#define TEE_WRITE_REE2_HINF_V 0x00000001U -#define TEE_WRITE_REE2_HINF_S 7 - -/** TEE_SLC_CTRL_REG register - * slc read/write control register - */ -#define TEE_SLC_CTRL_REG (DR_REG_TEE_BASE + 0x150) -/** TEE_READ_TEE_SLC : R/W; bitpos: [0]; default: 1; - * Configures slc registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_SLC (BIT(0)) -#define TEE_READ_TEE_SLC_M (TEE_READ_TEE_SLC_V << TEE_READ_TEE_SLC_S) -#define TEE_READ_TEE_SLC_V 0x00000001U -#define TEE_READ_TEE_SLC_S 0 -/** TEE_READ_REE0_SLC : R/W; bitpos: [1]; default: 0; - * Configures slc registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_SLC (BIT(1)) -#define TEE_READ_REE0_SLC_M (TEE_READ_REE0_SLC_V << TEE_READ_REE0_SLC_S) -#define TEE_READ_REE0_SLC_V 0x00000001U -#define TEE_READ_REE0_SLC_S 1 -/** TEE_READ_REE1_SLC : R/W; bitpos: [2]; default: 0; - * Configures slc registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_SLC (BIT(2)) -#define TEE_READ_REE1_SLC_M (TEE_READ_REE1_SLC_V << TEE_READ_REE1_SLC_S) -#define TEE_READ_REE1_SLC_V 0x00000001U -#define TEE_READ_REE1_SLC_S 2 -/** TEE_READ_REE2_SLC : R/W; bitpos: [3]; default: 0; - * Configures slc registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_SLC (BIT(3)) -#define TEE_READ_REE2_SLC_M (TEE_READ_REE2_SLC_V << TEE_READ_REE2_SLC_S) -#define TEE_READ_REE2_SLC_V 0x00000001U -#define TEE_READ_REE2_SLC_S 3 -/** TEE_WRITE_TEE_SLC : R/W; bitpos: [4]; default: 1; - * Configures slc registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_SLC (BIT(4)) -#define TEE_WRITE_TEE_SLC_M (TEE_WRITE_TEE_SLC_V << TEE_WRITE_TEE_SLC_S) -#define TEE_WRITE_TEE_SLC_V 0x00000001U -#define TEE_WRITE_TEE_SLC_S 4 -/** TEE_WRITE_REE0_SLC : R/W; bitpos: [5]; default: 0; - * Configures slc registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_SLC (BIT(5)) -#define TEE_WRITE_REE0_SLC_M (TEE_WRITE_REE0_SLC_V << TEE_WRITE_REE0_SLC_S) -#define TEE_WRITE_REE0_SLC_V 0x00000001U -#define TEE_WRITE_REE0_SLC_S 5 -/** TEE_WRITE_REE1_SLC : R/W; bitpos: [6]; default: 0; - * Configures slc registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_SLC (BIT(6)) -#define TEE_WRITE_REE1_SLC_M (TEE_WRITE_REE1_SLC_V << TEE_WRITE_REE1_SLC_S) -#define TEE_WRITE_REE1_SLC_V 0x00000001U -#define TEE_WRITE_REE1_SLC_S 6 -/** TEE_WRITE_REE2_SLC : R/W; bitpos: [7]; default: 0; - * Configures slc registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_SLC (BIT(7)) -#define TEE_WRITE_REE2_SLC_M (TEE_WRITE_REE2_SLC_V << TEE_WRITE_REE2_SLC_S) -#define TEE_WRITE_REE2_SLC_V 0x00000001U -#define TEE_WRITE_REE2_SLC_S 7 - -/** TEE_SLC_HOST_CTRL_REG register - * slc_host read/write control register - */ -#define TEE_SLC_HOST_CTRL_REG (DR_REG_TEE_BASE + 0x158) -/** TEE_READ_TEE_SLC_HOST : R/W; bitpos: [0]; default: 1; - * Configures slc_host registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_SLC_HOST (BIT(0)) -#define TEE_READ_TEE_SLC_HOST_M (TEE_READ_TEE_SLC_HOST_V << TEE_READ_TEE_SLC_HOST_S) -#define TEE_READ_TEE_SLC_HOST_V 0x00000001U -#define TEE_READ_TEE_SLC_HOST_S 0 -/** TEE_READ_REE0_SLC_HOST : R/W; bitpos: [1]; default: 0; - * Configures slc_host registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_SLC_HOST (BIT(1)) -#define TEE_READ_REE0_SLC_HOST_M (TEE_READ_REE0_SLC_HOST_V << TEE_READ_REE0_SLC_HOST_S) -#define TEE_READ_REE0_SLC_HOST_V 0x00000001U -#define TEE_READ_REE0_SLC_HOST_S 1 -/** TEE_READ_REE1_SLC_HOST : R/W; bitpos: [2]; default: 0; - * Configures slc_host registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_SLC_HOST (BIT(2)) -#define TEE_READ_REE1_SLC_HOST_M (TEE_READ_REE1_SLC_HOST_V << TEE_READ_REE1_SLC_HOST_S) -#define TEE_READ_REE1_SLC_HOST_V 0x00000001U -#define TEE_READ_REE1_SLC_HOST_S 2 -/** TEE_READ_REE2_SLC_HOST : R/W; bitpos: [3]; default: 0; - * Configures slc_host registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_SLC_HOST (BIT(3)) -#define TEE_READ_REE2_SLC_HOST_M (TEE_READ_REE2_SLC_HOST_V << TEE_READ_REE2_SLC_HOST_S) -#define TEE_READ_REE2_SLC_HOST_V 0x00000001U -#define TEE_READ_REE2_SLC_HOST_S 3 -/** TEE_WRITE_TEE_SLC_HOST : R/W; bitpos: [4]; default: 1; - * Configures slc_host registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_SLC_HOST (BIT(4)) -#define TEE_WRITE_TEE_SLC_HOST_M (TEE_WRITE_TEE_SLC_HOST_V << TEE_WRITE_TEE_SLC_HOST_S) -#define TEE_WRITE_TEE_SLC_HOST_V 0x00000001U -#define TEE_WRITE_TEE_SLC_HOST_S 4 -/** TEE_WRITE_REE0_SLC_HOST : R/W; bitpos: [5]; default: 0; - * Configures slc_host registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_SLC_HOST (BIT(5)) -#define TEE_WRITE_REE0_SLC_HOST_M (TEE_WRITE_REE0_SLC_HOST_V << TEE_WRITE_REE0_SLC_HOST_S) -#define TEE_WRITE_REE0_SLC_HOST_V 0x00000001U -#define TEE_WRITE_REE0_SLC_HOST_S 5 -/** TEE_WRITE_REE1_SLC_HOST : R/W; bitpos: [6]; default: 0; - * Configures slc_host registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_SLC_HOST (BIT(6)) -#define TEE_WRITE_REE1_SLC_HOST_M (TEE_WRITE_REE1_SLC_HOST_V << TEE_WRITE_REE1_SLC_HOST_S) -#define TEE_WRITE_REE1_SLC_HOST_V 0x00000001U -#define TEE_WRITE_REE1_SLC_HOST_S 6 -/** TEE_WRITE_REE2_SLC_HOST : R/W; bitpos: [7]; default: 0; - * Configures slc_host registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_SLC_HOST (BIT(7)) -#define TEE_WRITE_REE2_SLC_HOST_M (TEE_WRITE_REE2_SLC_HOST_V << TEE_WRITE_REE2_SLC_HOST_S) -#define TEE_WRITE_REE2_SLC_HOST_V 0x00000001U -#define TEE_WRITE_REE2_SLC_HOST_S 7 - /** TEE_BUS_ERR_CONF_REG register - * Clock gating register + * Error message return configuration register */ #define TEE_BUS_ERR_CONF_REG (DR_REG_TEE_BASE + 0xff0) /** TEE_BUS_ERR_RESP_EN : R/W; bitpos: [0]; default: 0; - * Configures whether return error response to cpu when access blocked - * 0: disable error response - * 1: enable error response + * Configures whether to return error message to CPU when access is blocked. + * 0: Disable + * 1: Enable */ #define TEE_BUS_ERR_RESP_EN (BIT(0)) #define TEE_BUS_ERR_RESP_EN_M (TEE_BUS_ERR_RESP_EN_V << TEE_BUS_ERR_RESP_EN_S) @@ -4232,8 +3527,8 @@ extern "C" { #define TEE_CLOCK_GATE_REG (DR_REG_TEE_BASE + 0xff8) /** TEE_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ #define TEE_CLK_EN (BIT(0)) #define TEE_CLK_EN_M (TEE_CLK_EN_V << TEE_CLK_EN_S) @@ -4245,7 +3540,7 @@ extern "C" { */ #define TEE_DATE_REG (DR_REG_TEE_BASE + 0xffc) /** TEE_DATE : R/W; bitpos: [27:0]; default: 37773824; - * Version control register + * Version control register. */ #define TEE_DATE 0x0FFFFFFFU #define TEE_DATE_M (TEE_DATE_V << TEE_DATE_S) diff --git a/components/soc/esp32c5/register/soc/tee_struct.h b/components/soc/esp32c5/register/soc/tee_struct.h index 13f9c99d53..23e99d2768 100644 --- a/components/soc/esp32c5/register/soc/tee_struct.h +++ b/components/soc/esp32c5/register/soc/tee_struct.h @@ -10,22 +10,24 @@ extern "C" { #endif -/** Group: Tee mode control register */ +/** Group: Configuration Registers */ /** Type of mn_mode_ctrl register - * TEE mode control register + * Security mode configuration register */ typedef union { struct { /** mn_mode : R/W; bitpos: [1:0]; default: 0; - * Configures Mn security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master n. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ uint32_t mn_mode:2; /** mn_lock : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_Mn_MODE. + * 0: Do not lock + * 1: Lock */ uint32_t mn_lock:1; uint32_t reserved_3:29; @@ -34,9 +36,9 @@ typedef union { } tee_mn_mode_ctrl_reg_t; -/** Group: read write control register */ +/** Group: Peripheral Read/Write Control Registers */ /** Type of uart0_ctrl register - * uart0 read/write control register + * UART0 read/write control register */ typedef union { struct { @@ -94,7 +96,7 @@ typedef union { } tee_uart0_ctrl_reg_t; /** Type of uart1_ctrl register - * uart1 read/write control register + * UART1 read/write control register */ typedef union { struct { @@ -152,7 +154,7 @@ typedef union { } tee_uart1_ctrl_reg_t; /** Type of uhci0_ctrl register - * uhci0 read/write control register + * UHCI read/write control register */ typedef union { struct { @@ -210,7 +212,7 @@ typedef union { } tee_uhci0_ctrl_reg_t; /** Type of i2c_ext0_ctrl register - * i2c_ext0 read/write control register + * I2C read/write control register */ typedef union { struct { @@ -268,7 +270,7 @@ typedef union { } tee_i2c_ext0_ctrl_reg_t; /** Type of i2s_ctrl register - * i2s read/write control register + * I2S read/write control register */ typedef union { struct { @@ -326,7 +328,7 @@ typedef union { } tee_i2s_ctrl_reg_t; /** Type of parl_io_ctrl register - * parl_io read/write control register + * PARL_IO read/write control register */ typedef union { struct { @@ -384,7 +386,7 @@ typedef union { } tee_parl_io_ctrl_reg_t; /** Type of pwm_ctrl register - * pwm read/write control register + * MCPWM read/write control register */ typedef union { struct { @@ -442,7 +444,7 @@ typedef union { } tee_pwm_ctrl_reg_t; /** Type of ledc_ctrl register - * ledc read/write control register + * LEDC read/write control register */ typedef union { struct { @@ -499,124 +501,124 @@ typedef union { uint32_t val; } tee_ledc_ctrl_reg_t; -/** Type of can0_ctrl register - * can read/write control register +/** Type of twai0_ctrl register + * TWAI0 read/write control register */ typedef union { struct { - /** read_tee_can0 : R/W; bitpos: [0]; default: 1; + /** read_tee_twai0 : R/W; bitpos: [0]; default: 1; * Configures can0 registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t read_tee_can0:1; - /** read_ree0_can0 : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_twai0:1; + /** read_ree0_twai0 : R/W; bitpos: [1]; default: 0; * Configures can0 registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree0_can0:1; - /** read_ree1_can0 : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_twai0:1; + /** read_ree1_twai0 : R/W; bitpos: [2]; default: 0; * Configures can0 registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree1_can0:1; - /** read_ree2_can0 : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_twai0:1; + /** read_ree2_twai0 : R/W; bitpos: [3]; default: 0; * Configures can0 registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree2_can0:1; - /** write_tee_can0 : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_twai0:1; + /** write_tee_twai0 : R/W; bitpos: [4]; default: 1; * Configures can0 registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t write_tee_can0:1; - /** write_ree0_can0 : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_twai0:1; + /** write_ree0_twai0 : R/W; bitpos: [5]; default: 0; * Configures can0 registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree0_can0:1; - /** write_ree1_can0 : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_twai0:1; + /** write_ree1_twai0 : R/W; bitpos: [6]; default: 0; * Configures can0 registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree1_can0:1; - /** write_ree2_can0 : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_twai0:1; + /** write_ree2_twai0 : R/W; bitpos: [7]; default: 0; * Configures can0 registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree2_can0:1; + uint32_t write_ree2_twai0:1; uint32_t reserved_8:24; }; uint32_t val; -} tee_can0_ctrl_reg_t; +} tee_twai0_ctrl_reg_t; -/** Type of usb_device_ctrl register - * usb_device read/write control register +/** Type of usb_serial_jtag_ctrl register + * USB_SERIAL_JTAG read/write control register */ typedef union { struct { - /** read_tee_usb_device : R/W; bitpos: [0]; default: 1; + /** read_tee_usb_serial_jtag : R/W; bitpos: [0]; default: 1; * Configures usb_device registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t read_tee_usb_device:1; - /** read_ree0_usb_device : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_usb_serial_jtag:1; + /** read_ree0_usb_serial_jtag : R/W; bitpos: [1]; default: 0; * Configures usb_device registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree0_usb_device:1; - /** read_ree1_usb_device : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_usb_serial_jtag:1; + /** read_ree1_usb_serial_jtag : R/W; bitpos: [2]; default: 0; * Configures usb_device registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree1_usb_device:1; - /** read_ree2_usb_device : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_usb_serial_jtag:1; + /** read_ree2_usb_serial_jtag : R/W; bitpos: [3]; default: 0; * Configures usb_device registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree2_usb_device:1; - /** write_tee_usb_device : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_usb_serial_jtag:1; + /** write_tee_usb_serial_jtag : R/W; bitpos: [4]; default: 1; * Configures usb_device registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t write_tee_usb_device:1; - /** write_ree0_usb_device : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_usb_serial_jtag:1; + /** write_ree0_usb_serial_jtag : R/W; bitpos: [5]; default: 0; * Configures usb_device registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree0_usb_device:1; - /** write_ree1_usb_device : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_usb_serial_jtag:1; + /** write_ree1_usb_serial_jtag : R/W; bitpos: [6]; default: 0; * Configures usb_device registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree1_usb_device:1; - /** write_ree2_usb_device : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_usb_serial_jtag:1; + /** write_ree2_usb_serial_jtag : R/W; bitpos: [7]; default: 0; * Configures usb_device registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree2_usb_device:1; + uint32_t write_ree2_usb_serial_jtag:1; uint32_t reserved_8:24; }; uint32_t val; -} tee_usb_device_ctrl_reg_t; +} tee_usb_serial_jtag_ctrl_reg_t; /** Type of rmt_ctrl register - * rmt read/write control register + * RMT read/write control register */ typedef union { struct { @@ -674,7 +676,7 @@ typedef union { } tee_rmt_ctrl_reg_t; /** Type of gdma_ctrl register - * gdma read/write control register + * GDMA read/write control register */ typedef union { struct { @@ -731,66 +733,8 @@ typedef union { uint32_t val; } tee_gdma_ctrl_reg_t; -/** Type of regdma_ctrl register - * regdma read/write control register - */ -typedef union { - struct { - /** read_tee_regdma : R/W; bitpos: [0]; default: 1; - * Configures regdma registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_regdma:1; - /** read_ree0_regdma : R/W; bitpos: [1]; default: 0; - * Configures regdma registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_regdma:1; - /** read_ree1_regdma : R/W; bitpos: [2]; default: 0; - * Configures regdma registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_regdma:1; - /** read_ree2_regdma : R/W; bitpos: [3]; default: 0; - * Configures regdma registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_regdma:1; - /** write_tee_regdma : R/W; bitpos: [4]; default: 1; - * Configures regdma registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_regdma:1; - /** write_ree0_regdma : R/W; bitpos: [5]; default: 0; - * Configures regdma registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_regdma:1; - /** write_ree1_regdma : R/W; bitpos: [6]; default: 0; - * Configures regdma registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_regdma:1; - /** write_ree2_regdma : R/W; bitpos: [7]; default: 0; - * Configures regdma registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_regdma:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_regdma_ctrl_reg_t; - /** Type of etm_ctrl register - * etm read/write control register + * SOC_ETM read/write control register */ typedef union { struct { @@ -848,7 +792,7 @@ typedef union { } tee_etm_ctrl_reg_t; /** Type of intmtx_ctrl register - * intmtx read/write control register + * INTMTX read/write control register */ typedef union { struct { @@ -906,7 +850,7 @@ typedef union { } tee_intmtx_ctrl_reg_t; /** Type of apb_adc_ctrl register - * apb_adc read/write control register + * SAR ADC read/write control register */ typedef union { struct { @@ -964,7 +908,7 @@ typedef union { } tee_apb_adc_ctrl_reg_t; /** Type of timergroup0_ctrl register - * timergroup0 read/write control register + * TIMG0 read/write control register */ typedef union { struct { @@ -1022,7 +966,7 @@ typedef union { } tee_timergroup0_ctrl_reg_t; /** Type of timergroup1_ctrl register - * timergroup1 read/write control register + * TIMG1 read/write control register */ typedef union { struct { @@ -1080,7 +1024,7 @@ typedef union { } tee_timergroup1_ctrl_reg_t; /** Type of systimer_ctrl register - * systimer read/write control register + * SYSTIMER read/write control register */ typedef union { struct { @@ -1137,124 +1081,8 @@ typedef union { uint32_t val; } tee_systimer_ctrl_reg_t; -/** Type of misc_ctrl register - * misc read/write control register - */ -typedef union { - struct { - /** read_tee_misc : R/W; bitpos: [0]; default: 1; - * Configures misc registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_misc:1; - /** read_ree0_misc : R/W; bitpos: [1]; default: 0; - * Configures misc registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_misc:1; - /** read_ree1_misc : R/W; bitpos: [2]; default: 0; - * Configures misc registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_misc:1; - /** read_ree2_misc : R/W; bitpos: [3]; default: 0; - * Configures misc registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_misc:1; - /** write_tee_misc : R/W; bitpos: [4]; default: 1; - * Configures misc registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_misc:1; - /** write_ree0_misc : R/W; bitpos: [5]; default: 0; - * Configures misc registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_misc:1; - /** write_ree1_misc : R/W; bitpos: [6]; default: 0; - * Configures misc registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_misc:1; - /** write_ree2_misc : R/W; bitpos: [7]; default: 0; - * Configures misc registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_misc:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_misc_ctrl_reg_t; - -/** Type of pvt_monitor_ctrl register - * pvt_monitor read/write control register - */ -typedef union { - struct { - /** read_tee_pvt_monitor : R/W; bitpos: [0]; default: 1; - * Configures pvt_monitor registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_pvt_monitor:1; - /** read_ree0_pvt_monitor : R/W; bitpos: [1]; default: 0; - * Configures pvt_monitor registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_pvt_monitor:1; - /** read_ree1_pvt_monitor : R/W; bitpos: [2]; default: 0; - * Configures pvt_monitor registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_pvt_monitor:1; - /** read_ree2_pvt_monitor : R/W; bitpos: [3]; default: 0; - * Configures pvt_monitor registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_pvt_monitor:1; - /** write_tee_pvt_monitor : R/W; bitpos: [4]; default: 1; - * Configures pvt_monitor registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_pvt_monitor:1; - /** write_ree0_pvt_monitor : R/W; bitpos: [5]; default: 0; - * Configures pvt_monitor registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_pvt_monitor:1; - /** write_ree1_pvt_monitor : R/W; bitpos: [6]; default: 0; - * Configures pvt_monitor registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_pvt_monitor:1; - /** write_ree2_pvt_monitor : R/W; bitpos: [7]; default: 0; - * Configures pvt_monitor registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_pvt_monitor:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_pvt_monitor_ctrl_reg_t; - /** Type of pcnt_ctrl register - * pcnt read/write control register + * PCNT read/write control register */ typedef union { struct { @@ -1312,7 +1140,7 @@ typedef union { } tee_pcnt_ctrl_reg_t; /** Type of iomux_ctrl register - * iomux read/write control register + * IO MUX read/write control register */ typedef union { struct { @@ -1370,7 +1198,7 @@ typedef union { } tee_iomux_ctrl_reg_t; /** Type of psram_mem_monitor_ctrl register - * psram_mem_monitor read/write control register + * PSRAM_MEM_MONITOR read/write control register */ typedef union { struct { @@ -1428,7 +1256,7 @@ typedef union { } tee_psram_mem_monitor_ctrl_reg_t; /** Type of mem_acs_monitor_ctrl register - * mem_acs_monitor read/write control register + * TCM_MEM_MONITOR read/write control register */ typedef union { struct { @@ -1486,7 +1314,7 @@ typedef union { } tee_mem_acs_monitor_ctrl_reg_t; /** Type of hp_system_reg_ctrl register - * hp_system_reg read/write control register + * HP_SYSREG read/write control register */ typedef union { struct { @@ -1544,7 +1372,7 @@ typedef union { } tee_hp_system_reg_ctrl_reg_t; /** Type of pcr_reg_ctrl register - * pcr_reg read/write control register + * PCR read/write control register */ typedef union { struct { @@ -1602,7 +1430,7 @@ typedef union { } tee_pcr_reg_ctrl_reg_t; /** Type of mspi_ctrl register - * mspi read/write control register + * SPI01 read/write control register */ typedef union { struct { @@ -1660,7 +1488,7 @@ typedef union { } tee_mspi_ctrl_reg_t; /** Type of hp_apm_ctrl register - * hp_apm read/write control register + * HP_APM and LP_APM0 read/write control register */ typedef union { struct { @@ -1718,7 +1546,7 @@ typedef union { } tee_hp_apm_ctrl_reg_t; /** Type of cpu_apm_ctrl register - * cpu_apm read/write control register + * CPU_APM_REG read/write control register */ typedef union { struct { @@ -1776,7 +1604,7 @@ typedef union { } tee_cpu_apm_ctrl_reg_t; /** Type of tee_ctrl register - * tee read/write control register + * TEE read/write control register */ typedef union { struct { @@ -1834,7 +1662,8 @@ typedef union { } tee_tee_ctrl_reg_t; /** Type of crypt_ctrl register - * crypt read/write control register + * CRYPT read/write control register, including security peripherals from AES to ECDSA + * address range */ typedef union { struct { @@ -1892,7 +1721,7 @@ typedef union { } tee_crypt_ctrl_reg_t; /** Type of trace_ctrl register - * trace read/write control register + * TRACE read/write control register */ typedef union { struct { @@ -1950,7 +1779,7 @@ typedef union { } tee_trace_ctrl_reg_t; /** Type of cpu_bus_monitor_ctrl register - * cpu_bus_monitor read/write control register + * BUS_MONITOR read/write control register */ typedef union { struct { @@ -2008,7 +1837,7 @@ typedef union { } tee_cpu_bus_monitor_ctrl_reg_t; /** Type of intpri_reg_ctrl register - * intpri_reg read/write control register + * INTPRI_REG read/write control register */ typedef union { struct { @@ -2065,182 +1894,66 @@ typedef union { uint32_t val; } tee_intpri_reg_ctrl_reg_t; -/** Type of cache_cfg_ctrl register - * cache_cfg read/write control register +/** Type of twai1_ctrl register + * TWAI1 read/write control register */ typedef union { struct { - /** read_tee_cache_cfg : R/W; bitpos: [0]; default: 1; - * Configures cache_cfg registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_cache_cfg:1; - /** read_ree0_cache_cfg : R/W; bitpos: [1]; default: 0; - * Configures cache_cfg registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_cache_cfg:1; - /** read_ree1_cache_cfg : R/W; bitpos: [2]; default: 0; - * Configures cache_cfg registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_cache_cfg:1; - /** read_ree2_cache_cfg : R/W; bitpos: [3]; default: 0; - * Configures cache_cfg registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_cache_cfg:1; - /** write_tee_cache_cfg : R/W; bitpos: [4]; default: 1; - * Configures cache_cfg registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_cache_cfg:1; - /** write_ree0_cache_cfg : R/W; bitpos: [5]; default: 0; - * Configures cache_cfg registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_cache_cfg:1; - /** write_ree1_cache_cfg : R/W; bitpos: [6]; default: 0; - * Configures cache_cfg registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_cache_cfg:1; - /** write_ree2_cache_cfg : R/W; bitpos: [7]; default: 0; - * Configures cache_cfg registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_cache_cfg:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_cache_cfg_ctrl_reg_t; - -/** Type of modem_ctrl register - * modem read/write control register - */ -typedef union { - struct { - /** read_tee_modem : R/W; bitpos: [0]; default: 1; - * Configures modem registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_modem:1; - /** read_ree0_modem : R/W; bitpos: [1]; default: 0; - * Configures modem registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_modem:1; - /** read_ree1_modem : R/W; bitpos: [2]; default: 0; - * Configures modem registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_modem:1; - /** read_ree2_modem : R/W; bitpos: [3]; default: 0; - * Configures modem registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_modem:1; - /** write_tee_modem : R/W; bitpos: [4]; default: 1; - * Configures modem registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_modem:1; - /** write_ree0_modem : R/W; bitpos: [5]; default: 0; - * Configures modem registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_modem:1; - /** write_ree1_modem : R/W; bitpos: [6]; default: 0; - * Configures modem registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_modem:1; - /** write_ree2_modem : R/W; bitpos: [7]; default: 0; - * Configures modem registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_modem:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_modem_ctrl_reg_t; - -/** Type of can1_ctrl register - * can1 read/write control register - */ -typedef union { - struct { - /** read_tee_can1 : R/W; bitpos: [0]; default: 1; + /** read_tee_twai1 : R/W; bitpos: [0]; default: 1; * Configures can1 registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t read_tee_can1:1; - /** read_ree0_can1 : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_twai1:1; + /** read_ree0_twai1 : R/W; bitpos: [1]; default: 0; * Configures can1 registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree0_can1:1; - /** read_ree1_can1 : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_twai1:1; + /** read_ree1_twai1 : R/W; bitpos: [2]; default: 0; * Configures can1 registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree1_can1:1; - /** read_ree2_can1 : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_twai1:1; + /** read_ree2_twai1 : R/W; bitpos: [3]; default: 0; * Configures can1 registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree2_can1:1; - /** write_tee_can1 : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_twai1:1; + /** write_tee_twai1 : R/W; bitpos: [4]; default: 1; * Configures can1 registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t write_tee_can1:1; - /** write_ree0_can1 : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_twai1:1; + /** write_ree0_twai1 : R/W; bitpos: [5]; default: 0; * Configures can1 registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree0_can1:1; - /** write_ree1_can1 : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_twai1:1; + /** write_ree1_twai1 : R/W; bitpos: [6]; default: 0; * Configures can1 registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree1_can1:1; - /** write_ree2_can1 : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_twai1:1; + /** write_ree2_twai1 : R/W; bitpos: [7]; default: 0; * Configures can1 registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree2_can1:1; + uint32_t write_ree2_twai1:1; uint32_t reserved_8:24; }; uint32_t val; -} tee_can1_ctrl_reg_t; +} tee_twai1_ctrl_reg_t; /** Type of spi2_ctrl register - * spi2 read/write control register + * SPI2 read/write control register */ typedef union { struct { @@ -2298,7 +2011,7 @@ typedef union { } tee_spi2_ctrl_reg_t; /** Type of bs_ctrl register - * bs read/write control register + * BITSCRAMBLER read/write control register */ typedef union { struct { @@ -2355,307 +2068,15 @@ typedef union { uint32_t val; } tee_bs_ctrl_reg_t; -/** Type of km_ctrl register - * km read/write control register - */ -typedef union { - struct { - /** read_tee_km : R/W; bitpos: [0]; default: 1; - * Configures km registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_km:1; - /** read_ree0_km : R/W; bitpos: [1]; default: 0; - * Configures km registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_km:1; - /** read_ree1_km : R/W; bitpos: [2]; default: 0; - * Configures km registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_km:1; - /** read_ree2_km : R/W; bitpos: [3]; default: 0; - * Configures km registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_km:1; - /** write_tee_km : R/W; bitpos: [4]; default: 1; - * Configures km registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_km:1; - /** write_ree0_km : R/W; bitpos: [5]; default: 0; - * Configures km registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_km:1; - /** write_ree1_km : R/W; bitpos: [6]; default: 0; - * Configures km registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_km:1; - /** write_ree2_km : R/W; bitpos: [7]; default: 0; - * Configures km registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_km:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_km_ctrl_reg_t; - -/** Type of modem_pwr_ctrl register - * modem_pwr read/write control register - */ -typedef union { - struct { - /** read_tee_modem_pwr : R/W; bitpos: [0]; default: 1; - * Configures modem_pwr registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_modem_pwr:1; - /** read_ree0_modem_pwr : R/W; bitpos: [1]; default: 0; - * Configures modem_pwr registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_modem_pwr:1; - /** read_ree1_modem_pwr : R/W; bitpos: [2]; default: 0; - * Configures modem_pwr registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_modem_pwr:1; - /** read_ree2_modem_pwr : R/W; bitpos: [3]; default: 0; - * Configures modem_pwr registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_modem_pwr:1; - /** write_tee_modem_pwr : R/W; bitpos: [4]; default: 1; - * Configures modem_pwr registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_modem_pwr:1; - /** write_ree0_modem_pwr : R/W; bitpos: [5]; default: 0; - * Configures modem_pwr registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_modem_pwr:1; - /** write_ree1_modem_pwr : R/W; bitpos: [6]; default: 0; - * Configures modem_pwr registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_modem_pwr:1; - /** write_ree2_modem_pwr : R/W; bitpos: [7]; default: 0; - * Configures modem_pwr registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_modem_pwr:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_modem_pwr_ctrl_reg_t; - -/** Type of hinf_ctrl register - * hinf read/write control register - */ -typedef union { - struct { - /** read_tee_hinf : R/W; bitpos: [0]; default: 1; - * Configures hinf registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_hinf:1; - /** read_ree0_hinf : R/W; bitpos: [1]; default: 0; - * Configures hinf registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_hinf:1; - /** read_ree1_hinf : R/W; bitpos: [2]; default: 0; - * Configures hinf registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_hinf:1; - /** read_ree2_hinf : R/W; bitpos: [3]; default: 0; - * Configures hinf registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_hinf:1; - /** write_tee_hinf : R/W; bitpos: [4]; default: 1; - * Configures hinf registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_hinf:1; - /** write_ree0_hinf : R/W; bitpos: [5]; default: 0; - * Configures hinf registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_hinf:1; - /** write_ree1_hinf : R/W; bitpos: [6]; default: 0; - * Configures hinf registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_hinf:1; - /** write_ree2_hinf : R/W; bitpos: [7]; default: 0; - * Configures hinf registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_hinf:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_hinf_ctrl_reg_t; - -/** Type of slc_ctrl register - * slc read/write control register - */ -typedef union { - struct { - /** read_tee_slc : R/W; bitpos: [0]; default: 1; - * Configures slc registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_slc:1; - /** read_ree0_slc : R/W; bitpos: [1]; default: 0; - * Configures slc registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_slc:1; - /** read_ree1_slc : R/W; bitpos: [2]; default: 0; - * Configures slc registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_slc:1; - /** read_ree2_slc : R/W; bitpos: [3]; default: 0; - * Configures slc registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_slc:1; - /** write_tee_slc : R/W; bitpos: [4]; default: 1; - * Configures slc registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_slc:1; - /** write_ree0_slc : R/W; bitpos: [5]; default: 0; - * Configures slc registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_slc:1; - /** write_ree1_slc : R/W; bitpos: [6]; default: 0; - * Configures slc registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_slc:1; - /** write_ree2_slc : R/W; bitpos: [7]; default: 0; - * Configures slc registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_slc:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_slc_ctrl_reg_t; - -/** Type of slc_host_ctrl register - * slc_host read/write control register - */ -typedef union { - struct { - /** read_tee_slc_host : R/W; bitpos: [0]; default: 1; - * Configures slc_host registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_slc_host:1; - /** read_ree0_slc_host : R/W; bitpos: [1]; default: 0; - * Configures slc_host registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_slc_host:1; - /** read_ree1_slc_host : R/W; bitpos: [2]; default: 0; - * Configures slc_host registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_slc_host:1; - /** read_ree2_slc_host : R/W; bitpos: [3]; default: 0; - * Configures slc_host registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_slc_host:1; - /** write_tee_slc_host : R/W; bitpos: [4]; default: 1; - * Configures slc_host registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_slc_host:1; - /** write_ree0_slc_host : R/W; bitpos: [5]; default: 0; - * Configures slc_host registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_slc_host:1; - /** write_ree1_slc_host : R/W; bitpos: [6]; default: 0; - * Configures slc_host registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_slc_host:1; - /** write_ree2_slc_host : R/W; bitpos: [7]; default: 0; - * Configures slc_host registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_slc_host:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_slc_host_ctrl_reg_t; - - -/** Group: config register */ /** Type of bus_err_conf register - * Clock gating register + * Error message return configuration register */ typedef union { struct { /** bus_err_resp_en : R/W; bitpos: [0]; default: 0; - * Configures whether return error response to cpu when access blocked - * 0: disable error response - * 1: enable error response + * Configures whether to return error message to CPU when access is blocked. + * 0: Disable + * 1: Enable */ uint32_t bus_err_resp_en:1; uint32_t reserved_1:31; @@ -2672,8 +2093,8 @@ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -2682,14 +2103,14 @@ typedef union { } tee_clock_gate_reg_t; -/** Group: Version control register */ +/** Group: Version Control Registers */ /** Type of date register * Version control register */ typedef union { struct { /** date : R/W; bitpos: [27:0]; default: 37773824; - * Version control register + * Version control register. */ uint32_t date:28; uint32_t reserved_28:4; @@ -2711,11 +2132,11 @@ typedef struct { volatile tee_pwm_ctrl_reg_t pwm_ctrl; uint32_t reserved_0a8; volatile tee_ledc_ctrl_reg_t ledc_ctrl; - volatile tee_can0_ctrl_reg_t can0_ctrl; - volatile tee_usb_device_ctrl_reg_t usb_device_ctrl; + volatile tee_twai0_ctrl_reg_t twai0_ctrl; + volatile tee_usb_serial_jtag_ctrl_reg_t usb_serial_jtag_ctrl; volatile tee_rmt_ctrl_reg_t rmt_ctrl; volatile tee_gdma_ctrl_reg_t gdma_ctrl; - volatile tee_regdma_ctrl_reg_t regdma_ctrl; + uint32_t reserved_0c0; volatile tee_etm_ctrl_reg_t etm_ctrl; volatile tee_intmtx_ctrl_reg_t intmtx_ctrl; uint32_t reserved_0cc; @@ -2723,9 +2144,7 @@ typedef struct { volatile tee_timergroup0_ctrl_reg_t timergroup0_ctrl; volatile tee_timergroup1_ctrl_reg_t timergroup1_ctrl; volatile tee_systimer_ctrl_reg_t systimer_ctrl; - volatile tee_misc_ctrl_reg_t misc_ctrl; - uint32_t reserved_0e4[3]; - volatile tee_pvt_monitor_ctrl_reg_t pvt_monitor_ctrl; + uint32_t reserved_0e0[5]; volatile tee_pcnt_ctrl_reg_t pcnt_ctrl; volatile tee_iomux_ctrl_reg_t iomux_ctrl; volatile tee_psram_mem_monitor_ctrl_reg_t psram_mem_monitor_ctrl; @@ -2741,18 +2160,11 @@ typedef struct { uint32_t reserved_124; volatile tee_cpu_bus_monitor_ctrl_reg_t cpu_bus_monitor_ctrl; volatile tee_intpri_reg_ctrl_reg_t intpri_reg_ctrl; - volatile tee_cache_cfg_ctrl_reg_t cache_cfg_ctrl; - volatile tee_modem_ctrl_reg_t modem_ctrl; - volatile tee_can1_ctrl_reg_t can1_ctrl; + uint32_t reserved_130[2]; + volatile tee_twai1_ctrl_reg_t twai1_ctrl; volatile tee_spi2_ctrl_reg_t spi2_ctrl; volatile tee_bs_ctrl_reg_t bs_ctrl; - volatile tee_km_ctrl_reg_t km_ctrl; - volatile tee_modem_pwr_ctrl_reg_t modem_pwr_ctrl; - volatile tee_hinf_ctrl_reg_t hinf_ctrl; - volatile tee_slc_ctrl_reg_t slc_ctrl; - uint32_t reserved_154; - volatile tee_slc_host_ctrl_reg_t slc_host_ctrl; - uint32_t reserved_15c[933]; + uint32_t reserved_144[939]; volatile tee_bus_err_conf_reg_t bus_err_conf; uint32_t reserved_ff4; volatile tee_clock_gate_reg_t clock_gate;