From f71044c87758114170f725c2da24cef27f3b194d Mon Sep 17 00:00:00 2001 From: morris Date: Tue, 23 Jan 2024 12:35:10 +0800 Subject: [PATCH 1/3] feat(fast_gpio): support CPU controlled fast GPIO driver on esp32p4 --- .../test_apps/gpio_extensions/README.md | 4 +- .../main/test_dedicated_gpio.c | 18 ++++-- .../gpio_extensions/pytest_gpio_extensions.py | 1 + .../esp32p4/include/hal/dedic_gpio_cpu_ll.h | 57 ++++++++++++++++++ components/soc/esp32p4/dedic_gpio_periph.c | 58 +++++++++++++++++++ .../esp32p4/include/soc/Kconfig.soc_caps.in | 4 ++ components/soc/esp32p4/include/soc/soc_caps.h | 2 +- docs/docs_not_updated/esp32p4.txt | 1 - .../api-reference/peripherals/dedic_gpio.rst | 14 ++--- .../api-reference/peripherals/dedic_gpio.rst | 14 ++--- .../dedicated_gpio/soft_i2c/README.md | 4 +- .../dedicated_gpio/soft_spi/README.md | 4 +- .../dedicated_gpio/soft_uart/README.md | 4 +- 13 files changed, 156 insertions(+), 29 deletions(-) create mode 100644 components/hal/esp32p4/include/hal/dedic_gpio_cpu_ll.h create mode 100644 components/soc/esp32p4/dedic_gpio_periph.c diff --git a/components/esp_driver_gpio/test_apps/gpio_extensions/README.md b/components/esp_driver_gpio/test_apps/gpio_extensions/README.md index d2553ff6db..4fc69c16b6 100644 --- a/components/esp_driver_gpio/test_apps/gpio_extensions/README.md +++ b/components/esp_driver_gpio/test_apps/gpio_extensions/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c index a83ae94f99..f0a4ba6576 100644 --- a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c +++ b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -146,7 +146,11 @@ TEST_CASE("Dedicated_GPIO_run_on_multiple_CPU_cores", "[dedic_gpio]") TaskHandle_t task_handle[SOC_CPU_CORES_NUM]; for (int i = 0; i < SOC_CPU_CORES_NUM; i++) { +#if CONFIG_IDF_TARGET_ESP32P4 + int start_gpio = i * TEST_GPIO_GROUP_SIZE + 20; +#else int start_gpio = i * TEST_GPIO_GROUP_SIZE; +#endif test_dedic_task_context_t isr_ctx = { .sem = sem, .gpios = {start_gpio, start_gpio + 1, start_gpio + 2, start_gpio + 3} @@ -181,7 +185,11 @@ TEST_CASE("Dedicated_GPIO_interrupt_and_callback", "[dedic_gpio]") SemaphoreHandle_t sem = xSemaphoreCreateBinary(); // configure GPIO +#if CONFIG_IDF_TARGET_ESP32P4 + const int bundle_gpios[] = {20, 21}; +#else const int bundle_gpios[] = {0, 1}; +#endif gpio_config_t io_conf = { .mode = GPIO_MODE_INPUT_OUTPUT, }; @@ -200,12 +208,12 @@ TEST_CASE("Dedicated_GPIO_interrupt_and_callback", "[dedic_gpio]") }; TEST_ESP_OK(dedic_gpio_new_bundle(&bundle_config, &bundle)); - // enable interrupt on GPIO1 - TEST_ESP_OK(gpio_set_intr_type(1, GPIO_INTR_POSEDGE)); + // enable interrupt + TEST_ESP_OK(gpio_set_intr_type(bundle_gpios[1], GPIO_INTR_POSEDGE)); // install gpio isr service TEST_ESP_OK(gpio_install_isr_service(0)); // hook isr handler for specific gpio pin - TEST_ESP_OK(gpio_isr_handler_add(1, test_dedic_gpio_isr_callback, sem)); + TEST_ESP_OK(gpio_isr_handler_add(bundle_gpios[1], test_dedic_gpio_isr_callback, sem)); // trigger a posedge on GPIO1 dedic_gpio_bundle_write(bundle, BIT(1), 0x00); @@ -214,7 +222,7 @@ TEST_CASE("Dedicated_GPIO_interrupt_and_callback", "[dedic_gpio]") TEST_ASSERT_EQUAL(pdTRUE, xSemaphoreTake(sem, pdMS_TO_TICKS(1000))); // remove isr handler for gpio number - TEST_ESP_OK(gpio_isr_handler_remove(1)); + TEST_ESP_OK(gpio_isr_handler_remove(bundle_gpios[1])); // uninstall GPIO interrupt service gpio_uninstall_isr_service(); diff --git a/components/esp_driver_gpio/test_apps/gpio_extensions/pytest_gpio_extensions.py b/components/esp_driver_gpio/test_apps/gpio_extensions/pytest_gpio_extensions.py index a51ae5e89d..edda8257a7 100644 --- a/components/esp_driver_gpio/test_apps/gpio_extensions/pytest_gpio_extensions.py +++ b/components/esp_driver_gpio/test_apps/gpio_extensions/pytest_gpio_extensions.py @@ -28,6 +28,7 @@ def test_gpio_filter(dut: IdfDut) -> None: @pytest.mark.esp32h2 @pytest.mark.esp32s2 @pytest.mark.esp32s3 +@pytest.mark.esp32p4 @pytest.mark.generic @pytest.mark.parametrize('config', CONFIGS, indirect=True) def test_dedic_gpio(dut: IdfDut) -> None: diff --git a/components/hal/esp32p4/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32p4/include/hal/dedic_gpio_cpu_ll.h new file mode 100644 index 0000000000..8277b8ed0f --- /dev/null +++ b/components/hal/esp32p4/include/hal/dedic_gpio_cpu_ll.h @@ -0,0 +1,57 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "riscv/csr.h" + +/*fast gpio*/ +#define CSR_GPIO_OEN_USER 0x803 +#define CSR_GPIO_IN_USER 0x804 +#define CSR_GPIO_OUT_USER 0x805 + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((always_inline)) +static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) +{ + // the OEN register is active low + RV_CLEAR_CSR(CSR_GPIO_OEN_USER, mask); +} + +__attribute__((always_inline)) +static inline void dedic_gpio_cpu_ll_write_all(uint32_t value) +{ + RV_WRITE_CSR(CSR_GPIO_OUT_USER, value); +} + +__attribute__((always_inline)) +static inline uint32_t dedic_gpio_cpu_ll_read_in(void) +{ + uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER); + return value; +} + +__attribute__((always_inline)) +static inline uint32_t dedic_gpio_cpu_ll_read_out(void) +{ + uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER); + return value; +} + +__attribute__((always_inline)) +static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value) +{ + RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value); + RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value)); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/dedic_gpio_periph.c b/components/soc/esp32p4/dedic_gpio_periph.c new file mode 100644 index 0000000000..c105ab07a1 --- /dev/null +++ b/components/soc/esp32p4/dedic_gpio_periph.c @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/gpio_sig_map.h" +#include "soc/dedic_gpio_periph.h" + +const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = { + .irq = -1, + .cores = { + [0] = { + .in_sig_per_channel = { + [0] = CORE_GPIO_IN_PAD_IN0_IDX, + [1] = CORE_GPIO_IN_PAD_IN1_IDX, + [2] = CORE_GPIO_IN_PAD_IN2_IDX, + [3] = CORE_GPIO_IN_PAD_IN3_IDX, + [4] = CORE_GPIO_IN_PAD_IN4_IDX, + [5] = CORE_GPIO_IN_PAD_IN5_IDX, + [6] = CORE_GPIO_IN_PAD_IN6_IDX, + [7] = CORE_GPIO_IN_PAD_IN7_IDX, + }, + .out_sig_per_channel = { + [0] = CORE_GPIO_OUT_PAD_OUT0_IDX, + [1] = CORE_GPIO_OUT_PAD_OUT1_IDX, + [2] = CORE_GPIO_OUT_PAD_OUT2_IDX, + [3] = CORE_GPIO_OUT_PAD_OUT3_IDX, + [4] = CORE_GPIO_OUT_PAD_OUT4_IDX, + [5] = CORE_GPIO_OUT_PAD_OUT5_IDX, + [6] = CORE_GPIO_OUT_PAD_OUT6_IDX, + [7] = CORE_GPIO_OUT_PAD_OUT7_IDX, + } + }, + [1] = { + .in_sig_per_channel = { + [0] = CORE_GPIO_IN_PAD_IN8_IDX, + [1] = CORE_GPIO_IN_PAD_IN9_IDX, + [2] = CORE_GPIO_IN_PAD_IN10_IDX, + [3] = CORE_GPIO_IN_PAD_IN11_IDX, + [4] = CORE_GPIO_IN_PAD_IN12_IDX, + [5] = CORE_GPIO_IN_PAD_IN13_IDX, + [6] = CORE_GPIO_IN_PAD_IN14_IDX, + [7] = CORE_GPIO_IN_PAD_IN15_IDX, + }, + .out_sig_per_channel = { + [0] = CORE_GPIO_OUT_PAD_OUT8_IDX, + [1] = CORE_GPIO_OUT_PAD_OUT9_IDX, + [2] = CORE_GPIO_OUT_PAD_OUT10_IDX, + [3] = CORE_GPIO_OUT_PAD_OUT11_IDX, + [4] = CORE_GPIO_OUT_PAD_OUT12_IDX, + [5] = CORE_GPIO_OUT_PAD_OUT13_IDX, + [6] = CORE_GPIO_OUT_PAD_OUT14_IDX, + [7] = CORE_GPIO_OUT_PAD_OUT15_IDX, + } + }, + }, +}; diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 06f6053582..a710dd2c2d 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -7,6 +7,10 @@ config SOC_ANA_CMPR_SUPPORTED bool default y +config SOC_DEDICATED_GPIO_SUPPORTED + bool + default y + config SOC_UART_SUPPORTED bool default y diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 1f79bbc93f..4d670d1207 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -19,7 +19,7 @@ /*-------------------------- COMMON CAPS ---------------------------------------*/ // #define SOC_ADC_SUPPORTED 1 //TODO: IDF-6496 #define SOC_ANA_CMPR_SUPPORTED 1 -// #define SOC_DEDICATED_GPIO_SUPPORTED 1 //TODO: IDF-7552 +#define SOC_DEDICATED_GPIO_SUPPORTED 1 #define SOC_UART_SUPPORTED 1 #define SOC_GDMA_SUPPORTED 1 #define SOC_AHB_GDMA_SUPPORTED 1 diff --git a/docs/docs_not_updated/esp32p4.txt b/docs/docs_not_updated/esp32p4.txt index a5931aab8d..45744c43f4 100644 --- a/docs/docs_not_updated/esp32p4.txt +++ b/docs/docs_not_updated/esp32p4.txt @@ -77,7 +77,6 @@ api-reference/peripherals/touch_pad.rst api-reference/peripherals/adc_calibration.rst api-reference/peripherals/parlio.rst api-reference/peripherals/i2c.rst -api-reference/peripherals/dedic_gpio.rst api-reference/peripherals/sd_pullup_requirements.rst api-reference/peripherals/index.rst api-reference/network/esp_openthread.rst diff --git a/docs/en/api-reference/peripherals/dedic_gpio.rst b/docs/en/api-reference/peripherals/dedic_gpio.rst index 477bd66a7e..a568c98289 100644 --- a/docs/en/api-reference/peripherals/dedic_gpio.rst +++ b/docs/en/api-reference/peripherals/dedic_gpio.rst @@ -112,9 +112,7 @@ For advanced users, they can always manipulate the GPIOs by writing assembly cod For details of supported dedicated GPIO instructions, please refer to **{IDF_TARGET_NAME} Technical Reference Manual** > **Processor Instruction Extensions (PIE) (to be added later)** [`PDF <{IDF_TARGET_TRM_EN_URL}#pie>`__]. -.. only:: esp32c2 or esp32c3 or esp32c6 or esp32h2 - - Code examples for manipulating dedicated GPIOs from assembly are provided in the :example:`peripherals/dedicated_gpio` directory of ESP-IDF examples. These examples show how to emulate a UART, an I2C and an SPI bus in assembly thanks to dedicated GPIOs. +.. only:: not (esp32s2 or esp32s3) For details of supported dedicated GPIO instructions, please refer to **{IDF_TARGET_NAME} Technical Reference Manual** > **ESP-RISC-V CPU** [`PDF <{IDF_TARGET_TRM_EN_URL}#riscvcpu>`__]. @@ -152,12 +150,14 @@ Some of the dedicated CPU instructions are also wrapped inside ``hal/dedic_gpio_ // wait for done semaphore xSemaphoreTake(sem, portMAX_DELAY); -.. only:: SOC_DEDIC_GPIO_HAS_INTERRUPT - Application Example - ------------------- +Application Example +------------------- - Matrix keyboard example based on dedicated GPIO: :example:`peripherals/gpio/matrix_keyboard`. +.. list:: + + * Emulate UART/I2C/SPI peripherals in assembly with dedicate CPU instructions designed for manipulating the GPIOs: :example:`peripherals/dedicated_gpio`. + :SOC_DEDIC_GPIO_HAS_INTERRUPT: * Matrix keyboard example based on dedicated GPIO: :example:`peripherals/gpio/matrix_keyboard`. API Reference diff --git a/docs/zh_CN/api-reference/peripherals/dedic_gpio.rst b/docs/zh_CN/api-reference/peripherals/dedic_gpio.rst index 9b49e55d10..f55d2de56b 100644 --- a/docs/zh_CN/api-reference/peripherals/dedic_gpio.rst +++ b/docs/zh_CN/api-reference/peripherals/dedic_gpio.rst @@ -112,9 +112,7 @@ GPIO 捆绑包操作 有关支持的专用 GPIO 指令的详细信息，请参考 **{IDF_TARGET_NAME} 技术参考手册** > **处理器指令拓展 (PIE)（稍后发布）** [`PDF <{IDF_TARGET_TRM_CN_URL}#pie>`__]. -.. only:: esp32c2 or esp32c3 or esp32c6 or esp32h2 - - 通过汇编操作专用 GPIO 的示例代码存放在 ESP-IDF 示例项目的 :example:`peripherals/dedicated_gpio` 目录下。示例演示了如何通过汇编操作专用 GPIO 来模拟 UART、I2C 和 SPI 总线。 +.. only:: not (esp32s2 or esp32s3) 有关支持的专用 GPIO 指令的详细信息，请参考 **{IDF_TARGET_NAME} 技术参考手册** > **ESP-RISC-V CPU** [`PDF <{IDF_TARGET_TRM_CN_URL}#riscvcpu>`__]。 @@ -152,12 +150,14 @@ GPIO 捆绑包操作 // 等待完成信号量 xSemaphoreTake(sem, portMAX_DELAY); -.. only:: SOC_DEDIC_GPIO_HAS_INTERRUPT - 应用示例 - ------------------- +应用示例 +------------------- - 基于专用 GPIO 的矩阵键盘示例：:example:`peripherals/gpio/matrix_keyboard`. +.. list:: + + * 通过汇编代码使用专用的 CPU 指令来操作 GPIO 以模拟 UART/I2C/SPI 外设 :example:`peripherals/dedicated_gpio`. + :SOC_DEDIC_GPIO_HAS_INTERRUPT: * 基于专用 GPIO 驱动的矩阵键盘：:example:`peripherals/gpio/matrix_keyboard`. API 参考 diff --git a/examples/peripherals/dedicated_gpio/soft_i2c/README.md b/examples/peripherals/dedicated_gpio/soft_i2c/README.md index ef4866a055..d9b5a6697d 100644 --- a/examples/peripherals/dedicated_gpio/soft_i2c/README.md +++ b/examples/peripherals/dedicated_gpio/soft_i2c/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | # Example: Software I2C Master via Dedicated/Fast GPIOs diff --git a/examples/peripherals/dedicated_gpio/soft_spi/README.md b/examples/peripherals/dedicated_gpio/soft_spi/README.md index f7ec02a977..beb35c9142 100644 --- a/examples/peripherals/dedicated_gpio/soft_spi/README.md +++ b/examples/peripherals/dedicated_gpio/soft_spi/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | -| ----------------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | # Example: SPI software emulation using dedicated/fast GPIOs diff --git a/examples/peripherals/dedicated_gpio/soft_uart/README.md b/examples/peripherals/dedicated_gpio/soft_uart/README.md index e4cfb18910..9d4481ff64 100644 --- a/examples/peripherals/dedicated_gpio/soft_uart/README.md +++ b/examples/peripherals/dedicated_gpio/soft_uart/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | # Example: UART software emulation using dedicated/fast GPIOs From ddece8f7e9a4cc782046d7577e3e7249aa49f520 Mon Sep 17 00:00:00 2001 From: morris Date: Fri, 22 Mar 2024 11:29:34 +0800 Subject: [PATCH 2/3] feat(glitch_filter): support GPIO glitch filter on esp32p4 --- .../gpio_extensions/main/test_gpio_filter.c | 10 +++- .../gpio_extensions/pytest_gpio_extensions.py | 2 +- .../include/hal/gpio_glitch_filter_ll.h | 60 +++++++++++++++++++ .../esp32p4/include/soc/Kconfig.soc_caps.in | 8 +++ .../soc/esp32p4/include/soc/clk_tree_defs.h | 17 +++++- components/soc/esp32p4/include/soc/soc_caps.h | 4 +- 6 files changed, 94 insertions(+), 7 deletions(-) create mode 100644 components/hal/esp32p4/include/hal/gpio_glitch_filter_ll.h diff --git a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_gpio_filter.c b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_gpio_filter.c index a55c626d7d..6826cd15db 100644 --- a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_gpio_filter.c +++ b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_gpio_filter.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,6 +14,12 @@ #include "driver/dedic_gpio.h" #include "soc/soc_caps.h" +#if CONFIG_IDF_TARGET_ESP32P4 +#define TEST_FILTER_GPIO 20 +#else +#define TEST_FILTER_GPIO 2 +#endif + #if SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER TEST_CASE("GPIO pin glitch filter life cycle", "[gpio_filter]") @@ -108,7 +114,7 @@ NOINLINE_ATTR IRAM_ATTR static void test_gpio_simulate_glitch_pulse(void) TEST_CASE("GPIO flex glitch filter enable/disable", "[gpio_filter]") { - const gpio_num_t test_gpio = 2; + const gpio_num_t test_gpio = TEST_FILTER_GPIO; printf("initialize GPIO for input and out\r\n"); gpio_config_t gpio_cfg = { diff --git a/components/esp_driver_gpio/test_apps/gpio_extensions/pytest_gpio_extensions.py b/components/esp_driver_gpio/test_apps/gpio_extensions/pytest_gpio_extensions.py index edda8257a7..fa4bf41bab 100644 --- a/components/esp_driver_gpio/test_apps/gpio_extensions/pytest_gpio_extensions.py +++ b/components/esp_driver_gpio/test_apps/gpio_extensions/pytest_gpio_extensions.py @@ -1,6 +1,5 @@ # SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 - import pytest from pytest_embedded_idf import IdfDut @@ -16,6 +15,7 @@ CONFIGS = [ @pytest.mark.esp32h2 @pytest.mark.esp32s2 @pytest.mark.esp32s3 +@pytest.mark.esp32p4 @pytest.mark.generic @pytest.mark.parametrize('config', CONFIGS, indirect=True) def test_gpio_filter(dut: IdfDut) -> None: diff --git a/components/hal/esp32p4/include/hal/gpio_glitch_filter_ll.h b/components/hal/esp32p4/include/hal/gpio_glitch_filter_ll.h new file mode 100644 index 0000000000..8799ec6d3f --- /dev/null +++ b/components/hal/esp32p4/include/hal/gpio_glitch_filter_ll.h @@ -0,0 +1,60 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "hal/assert.h" +#include "soc/gpio_ext_struct.h" + +#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW 64 + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable GPIO glitch filter + * + * @param hw Glitch filter register base address + * @param filter_idx Glitch filter index + * @param enable True to enable, false to disable + */ +static inline void gpio_ll_glitch_filter_enable(gpio_glitch_filter_dev_t *hw, uint32_t filter_idx, bool enable) +{ + hw->glitch_filter_chn[filter_idx].filter_chn_en = enable; +} + +/** + * @brief Set the input GPIO for the glitch filter + * + * @param hw Glitch filter register base address + * @param filter_idx Glitch filter index + * @param gpio_num GPIO number + */ +static inline void gpio_ll_glitch_filter_set_gpio(gpio_glitch_filter_dev_t *hw, uint32_t filter_idx, uint32_t gpio_num) +{ + hw->glitch_filter_chn[filter_idx].filter_chn_input_io_num = gpio_num; +} + +/** + * @brief Set the coefficient of the glitch filter window + * + * @param hw Glitch filter register base address + * @param filter_idx Glitch filter index + * @param window_width Window width, in IOMUX clock ticks + * @param window_threshold Window threshold, in IOMUX clock ticks + */ +static inline void gpio_ll_glitch_filter_set_window_coeff(gpio_glitch_filter_dev_t *hw, uint32_t filter_idx, uint32_t window_width, uint32_t window_thres) +{ + HAL_ASSERT(window_thres <= window_width); + hw->glitch_filter_chn[filter_idx].filter_chn_window_width = window_width - 1; + hw->glitch_filter_chn[filter_idx].filter_chn_window_thres = window_thres - 1; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index a710dd2c2d..5fbdac97ad 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -467,6 +467,14 @@ config SOC_GPIO_PIN_COUNT int default 55 +config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER + bool + default y + +config SOC_GPIO_FLEX_GLITCH_FILTER_NUM + int + default 8 + config SOC_GPIO_SUPPORT_PIN_HYS_FILTER bool default y diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h index 3157a0ace3..26fb9a0f82 100644 --- a/components/soc/esp32p4/include/soc/clk_tree_defs.h +++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h @@ -249,8 +249,6 @@ typedef enum { RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock default choice is PLL_F80M */ } soc_periph_rmt_clk_src_legacy_t; -//////////////////////////////////////////////////Temp Sensor/////////////////////////////////////////////////////////// - ///////////////////////////////////////////////////UART///////////////////////////////////////////////////////////////// /** @@ -509,6 +507,21 @@ typedef enum { //////////////////////////////////////////////////GPIO Glitch Filter//////////////////////////////////////////////////// +/** + * @brief Array initializer for all supported clock sources of Glitch Filter + */ +#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL} + +/** + * @brief Glitch filter clock source + */ + +typedef enum { + GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ + GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ + GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ +} soc_periph_glitch_filter_clk_src_t; + ///////////////////////////////////////////////////Analog Comparator//////////////////////////////////////////////////// /** diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 4d670d1207..10693883a5 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -200,8 +200,8 @@ // ESP32-P4 has 1 GPIO peripheral #define SOC_GPIO_PORT 1U #define SOC_GPIO_PIN_COUNT 55 -// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 //TODO: IDF-7481 -// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 //TODO: IDF-7481 +#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 +#define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1 // GPIO peripheral has the ETM extension From 529b6bf97cfac32900fc11350b3d0a84f6eb3000 Mon Sep 17 00:00:00 2001 From: morris Date: Fri, 22 Mar 2024 11:10:23 +0800 Subject: [PATCH 3/3] fix(ana_cmpr): fix wrong set up in the etm test case --- .../test_apps/.build-test-rules.yml | 4 -- .../test_apps/etm/main/test_ana_cmpr_etm.c | 46 +++++++++++-------- .../test_apps/etm/pytest_etm.py | 2 +- 3 files changed, 27 insertions(+), 25 deletions(-) diff --git a/components/esp_hw_support/test_apps/.build-test-rules.yml b/components/esp_hw_support/test_apps/.build-test-rules.yml index 388ffb17e2..d4b8ac8265 100644 --- a/components/esp_hw_support/test_apps/.build-test-rules.yml +++ b/components/esp_hw_support/test_apps/.build-test-rules.yml @@ -25,10 +25,6 @@ components/esp_hw_support/test_apps/esp_hw_support_unity_tests: components/esp_hw_support/test_apps/etm: disable: - if: SOC_ETM_SUPPORTED != 1 - disable_test: - - if: IDF_TARGET == "esp32p4" - temporary: true - reason: test not pass, should be re-enable # TODO: IDF-8974 depends_components: - esp_driver_gptimer - esp_driver_gpio diff --git a/components/esp_hw_support/test_apps/etm/main/test_ana_cmpr_etm.c b/components/esp_hw_support/test_apps/etm/main/test_ana_cmpr_etm.c index 3486628628..53d1fbde88 100644 --- a/components/esp_hw_support/test_apps/etm/main/test_ana_cmpr_etm.c +++ b/components/esp_hw_support/test_apps/etm/main/test_ana_cmpr_etm.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -19,7 +19,7 @@ #define TEST_ANA_CMPR_UNIT 0 #define TEST_TIME_US 5000 -static gptimer_handle_t s_test_ana_cmpr_gptimer_init(void) +static gptimer_handle_t test_ana_cmpr_gptimer_init(void) { gptimer_handle_t gptimer = NULL; gptimer_config_t timer_config = { @@ -33,13 +33,13 @@ static gptimer_handle_t s_test_ana_cmpr_gptimer_init(void) return gptimer; } -static void s_test_ana_cmpr_gptimer_deinit(gptimer_handle_t gptimer) +static void test_ana_cmpr_gptimer_deinit(gptimer_handle_t gptimer) { TEST_ESP_OK(gptimer_disable(gptimer)); TEST_ESP_OK(gptimer_del_timer(gptimer)); } -static ana_cmpr_handle_t s_test_ana_cmpr_init(void) +static ana_cmpr_handle_t test_ana_cmpr_init(void) { ana_cmpr_handle_t cmpr = NULL; @@ -65,13 +65,13 @@ static ana_cmpr_handle_t s_test_ana_cmpr_init(void) return cmpr; } -static void s_test_ana_cmpr_deinit(ana_cmpr_handle_t cmpr) +static void test_ana_cmpr_deinit(ana_cmpr_handle_t cmpr) { TEST_ESP_OK(ana_cmpr_disable(cmpr)); TEST_ESP_OK(ana_cmpr_del_unit(cmpr)); } -static int s_test_ana_cmpr_src_gpio_init(void) +static int test_ana_cmpr_src_gpio_init(void) { int gpio_num = -1; TEST_ESP_OK(ana_cmpr_get_gpio(TEST_ANA_CMPR_UNIT, ANA_CMPR_SOURCE_CHAN, &gpio_num)); @@ -96,7 +96,7 @@ typedef struct { esp_etm_channel_handle_t etm_neg_handle; } test_ana_cmpr_etm_handles_t; -static test_ana_cmpr_etm_handles_t s_test_ana_cmpr_init_etm(ana_cmpr_handle_t cmpr, gptimer_handle_t gptimer) +static test_ana_cmpr_etm_handles_t test_ana_cmpr_init_etm(ana_cmpr_handle_t cmpr, gptimer_handle_t gptimer) { test_ana_cmpr_etm_handles_t etm_handles = {}; @@ -105,7 +105,7 @@ static test_ana_cmpr_etm_handles_t s_test_ana_cmpr_init_etm(ana_cmpr_handle_t cm .event_type = ANA_CMPR_EVENT_POS_CROSS, }; TEST_ESP_OK(ana_cmpr_new_etm_event(cmpr, &evt_cfg, &etm_handles.cmpr_pos_evt)); - evt_cfg.event_type = GPIO_ETM_EVENT_EDGE_NEG; + evt_cfg.event_type = ANA_CMPR_EVENT_NEG_CROSS; TEST_ESP_OK(ana_cmpr_new_etm_event(cmpr, &evt_cfg, &etm_handles.cmpr_neg_evt)); /* Allocate the GPTimer tasks */ @@ -121,8 +121,8 @@ static test_ana_cmpr_etm_handles_t s_test_ana_cmpr_init_etm(ana_cmpr_handle_t cm TEST_ESP_OK(esp_etm_new_channel(&etm_cfg, &etm_handles.etm_pos_handle)); TEST_ESP_OK(esp_etm_new_channel(&etm_cfg, &etm_handles.etm_neg_handle)); /* Bind the events and tasks */ - TEST_ESP_OK(esp_etm_channel_connect(etm_handles.etm_pos_handle, etm_handles.cmpr_pos_evt, etm_handles.gptimer_start_task)); - TEST_ESP_OK(esp_etm_channel_connect(etm_handles.etm_neg_handle, etm_handles.cmpr_neg_evt, etm_handles.gptimer_stop_task)); + TEST_ESP_OK(esp_etm_channel_connect(etm_handles.etm_neg_handle, etm_handles.cmpr_neg_evt, etm_handles.gptimer_start_task)); + TEST_ESP_OK(esp_etm_channel_connect(etm_handles.etm_pos_handle, etm_handles.cmpr_pos_evt, etm_handles.gptimer_stop_task)); /* Enable the ETM channels */ TEST_ESP_OK(esp_etm_channel_enable(etm_handles.etm_pos_handle)); TEST_ESP_OK(esp_etm_channel_enable(etm_handles.etm_neg_handle)); @@ -130,10 +130,10 @@ static test_ana_cmpr_etm_handles_t s_test_ana_cmpr_init_etm(ana_cmpr_handle_t cm return etm_handles; } -static void s_test_ana_cmpr_deinit_etm(test_ana_cmpr_etm_handles_t handles) +static void test_ana_cmpr_deinit_etm(test_ana_cmpr_etm_handles_t handles) { TEST_ESP_OK(esp_etm_channel_disable(handles.etm_pos_handle)); - TEST_ESP_OK(esp_etm_channel_disable(handles.etm_pos_handle)); + TEST_ESP_OK(esp_etm_channel_disable(handles.etm_neg_handle)); TEST_ESP_OK(esp_etm_del_task(handles.gptimer_start_task)); TEST_ESP_OK(esp_etm_del_task(handles.gptimer_stop_task)); @@ -147,21 +147,27 @@ static void s_test_ana_cmpr_deinit_etm(test_ana_cmpr_etm_handles_t handles) TEST_CASE("analog_comparator_etm_event", "[etm]") { - gptimer_handle_t gptimer = s_test_ana_cmpr_gptimer_init(); - ana_cmpr_handle_t cmpr = s_test_ana_cmpr_init(); - int src_gpio = s_test_ana_cmpr_src_gpio_init(); - test_ana_cmpr_etm_handles_t handles = s_test_ana_cmpr_init_etm(cmpr, gptimer); + gptimer_handle_t gptimer = test_ana_cmpr_gptimer_init(); + ana_cmpr_handle_t cmpr = test_ana_cmpr_init(); + int src_gpio = test_ana_cmpr_src_gpio_init(); + test_ana_cmpr_etm_handles_t handles = test_ana_cmpr_init_etm(cmpr, gptimer); + // triggers a negative pulse, whose duration is ~TEST_TIME_US gpio_set_level(src_gpio, 0); esp_rom_delay_us(TEST_TIME_US); gpio_set_level(src_gpio, 1); uint64_t cnt_us = 0; TEST_ESP_OK(gptimer_get_raw_count(gptimer, &cnt_us)); + printf("Count: %" PRIu64 "\n", cnt_us); + // gptimer timer should stopped + uint64_t cnt_us_again = 0; + TEST_ESP_OK(gptimer_get_raw_count(gptimer, &cnt_us_again)); + TEST_ASSERT(cnt_us_again == cnt_us); - s_test_ana_cmpr_deinit_etm(handles); - s_test_ana_cmpr_deinit(cmpr); - s_test_ana_cmpr_gptimer_deinit(gptimer); + test_ana_cmpr_deinit_etm(handles); + test_ana_cmpr_deinit(cmpr); + test_ana_cmpr_gptimer_deinit(gptimer); - TEST_ASSERT_UINT64_WITHIN(TEST_TIME_US * 0.1, 5000, cnt_us); + TEST_ASSERT_UINT_WITHIN(TEST_TIME_US * 0.1, TEST_TIME_US, cnt_us); } diff --git a/components/esp_hw_support/test_apps/etm/pytest_etm.py b/components/esp_hw_support/test_apps/etm/pytest_etm.py index 381282579f..c209342a4c 100644 --- a/components/esp_hw_support/test_apps/etm/pytest_etm.py +++ b/components/esp_hw_support/test_apps/etm/pytest_etm.py @@ -1,12 +1,12 @@ # SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 - import pytest from pytest_embedded import Dut @pytest.mark.esp32c6 @pytest.mark.esp32h2 +@pytest.mark.esp32p4 @pytest.mark.generic @pytest.mark.parametrize( 'config',