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rtcio: support rtcio on c6

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This commit is contained in:
laokaiyao
2022-12-13 17:27:04 +08:00
parent cfef24863f
commit 7a002ab7a6
22 changed files with 594 additions and 107 deletions
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16
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
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@@ -323,6 +323,18 @@ config SOC_GPIO_SUPPORT_SLP_SWITCH
bool
default y
config SOC_RTCIO_PIN_COUNT
int
default 8
config SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
bool
default y
config SOC_RTCIO_HOLD_SUPPORTED
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
@@ -587,10 +599,6 @@ config SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM
int
default 108
config SOC_RTCIO_PIN_COUNT
int
default 0
config SOC_RSA_MAX_BIT_LEN
int
default 3072

32
components/soc/esp32c6/include/soc/rtc_io_channel.h Normal file
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@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
//RTC GPIO channels
#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 0
#define RTCIO_GPIO1_CHANNEL 1 //RTCIO_CHANNEL_1
#define RTCIO_CHANNEL_1_GPIO_NUM 1
#define RTCIO_GPIO2_CHANNEL 2 //RTCIO_CHANNEL_2
#define RTCIO_CHANNEL_2_GPIO_NUM 2
#define RTCIO_GPIO3_CHANNEL 3 //RTCIO_CHANNEL_3
#define RTCIO_CHANNEL_3_GPIO_NUM 3
#define RTCIO_GPIO4_CHANNEL 4 //RTCIO_CHANNEL_4
#define RTCIO_CHANNEL_4_GPIO_NUM 4
#define RTCIO_GPIO5_CHANNEL 5 //RTCIO_CHANNEL_5
#define RTCIO_CHANNEL_5_GPIO_NUM 5
#define RTCIO_GPIO6_CHANNEL 6 //RTCIO_CHANNEL_6
#define RTCIO_CHANNEL_6_GPIO_NUM 6
#define RTCIO_GPIO7_CHANNEL 7 //RTCIO_CHANNEL_7
#define RTCIO_CHANNEL_7_GPIO_NUM 7

8
components/soc/esp32c6/include/soc/rtc_io_reg.h Normal file
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@@ -0,0 +1,8 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/lp_io_reg.h"

19
components/soc/esp32c6/include/soc/rtc_io_struct.h Normal file
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@@ -0,0 +1,19 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/lp_io_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef lp_io_dev_t rtc_io_dev_t;
#define RTCIO LP_IO
#ifdef __cplusplus
}
#endif

14
components/soc/esp32c6/include/soc/soc_caps.h
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@@ -178,11 +178,10 @@
#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
/*-------------------------- RTCIO CAPS --------------------------------------*/
// TODO: IDF-6027
// #define SOC_RTCIO_PIN_COUNT 8
// #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
// #define SOC_RTCIO_HOLD_SUPPORTED 1 (does not have force_hold_all feature, but has deep_sleep_hold_all feature)
// #define SOC_RTCIO_WAKE_SUPPORTED 1
#define SOC_RTCIO_PIN_COUNT 8
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
#define SOC_RTCIO_HOLD_SUPPORTED 1
// #define SOC_RTCIO_WAKE_SUPPORTED 1 // TODO: IDF-5645
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
@@ -280,11 +279,6 @@
#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))
/*-------------------------- RTCIO CAPS --------------------------------------*/
/* No dedicated RTCIO subsystem on ESP32-C6. RTC functions are still supported
* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
#define SOC_RTCIO_PIN_COUNT (0U)
// TODO: IDF-5359 (Copy from esp32c3, need check)
/*--------------------------- RSA CAPS ---------------------------------------*/
#define SOC_RSA_MAX_BIT_LEN (3072)