diff --git a/components/esp_system/port/soc/esp32h4/cache_err_int.c b/components/esp_system/port/soc/esp32h4/cache_err_int.c
index 73bef0431f..b99d9ff146 100644
--- a/components/esp_system/port/soc/esp32h4/cache_err_int.c
+++ b/components/esp_system/port/soc/esp32h4/cache_err_int.c
@@ -19,8 +19,6 @@
 #include "hal/cache_ll.h"
 #include "esp_private/cache_err_int.h"
 
-// TODO: [ESP32H4] IDF-12288 inherited from verification branch, need check
-
 static const char *TAG = "CACHE_ERR";
 
 const char cache_error_msg[] = "Cache access error";
@@ -64,6 +62,13 @@ void esp_cache_err_int_init(void)
     esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
 
     ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
+    /**
+     * Here we
+     * 1. enable the cache fail tracer to take cache error interrupt into effect.
+     * 2. clear potential cache error interrupt raw bits
+     * 3. enable cache error interrupt en bits
+     */
+    cache_ll_l1_enable_fail_tracer(0, true);
     /* On the hardware side, start by clearing all the bits responsible for cache access error */
     cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
     /* Then enable cache access error interrupts. */
diff --git a/components/hal/esp32h4/include/hal/cache_ll.h b/components/hal/esp32h4/include/hal/cache_ll.h
index d4d7706c84..9d40b2b5e0 100644
--- a/components/hal/esp32h4/include/hal/cache_ll.h
+++ b/components/hal/esp32h4/include/hal/cache_ll.h
@@ -10,6 +10,7 @@
 
 #include <stdbool.h>
 #include "soc/cache_reg.h"
+#include "soc/cache_struct.h"
 #include "soc/ext_mem_defs.h"
 #include "hal/cache_types.h"
 #include "hal/assert.h"
@@ -813,42 +814,53 @@ static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32
     return valid;
 }
 
+/**
+ * Enable the Cache fail tracer
+ *
+ * @param cache_id    cache ID
+ * @param en          enable / disable
+ */
+static inline void cache_ll_l1_enable_fail_tracer(uint32_t cache_id, bool en)
+{
+    CACHE.trace_ena.l1_cache_trace_ena = en;
+}
+
 /*------------------------------------------------------------------------------
  * Interrupt
  *----------------------------------------------------------------------------*/
 /**
  * @brief Enable Cache access error interrupt
  *
- * @param cache_id    Cache ID, not used on C3. For compabitlity
+ * @param cache_id    Cache ID
  * @param mask        Interrupt mask
  */
 static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
 {
-    SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG, mask);
+    CACHE.l1_cache_acs_fail_int_ena.val |= mask;
 }
 
 /**
  * @brief Clear Cache access error interrupt status
  *
- * @param cache_id    Cache ID, not used on C3. For compabitlity
+ * @param cache_id    Cache ID
  * @param mask        Interrupt mask
  */
 static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
 {
-    SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG, mask);
+    CACHE.l1_cache_acs_fail_int_clr.val = mask;
 }
 
 /**
  * @brief Get Cache access error interrupt status
  *
- * @param cache_id    Cache ID, not used on C3. For compabitlity
+ * @param cache_id    Cache ID
  * @param mask        Interrupt mask
  *
  * @return            Status mask
  */
 static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
 {
-    return GET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG, mask);
+    return CACHE.l1_cache_acs_fail_int_st.val & mask;
 }
 
 #ifdef __cplusplus