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hal: Fix max value for clkdiv_pre in ESP32-S3 SPI master clock config

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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
This commit is contained in:
Gustavo Henrique Nihei
2022-05-23 10:12:05 -03:00
parent 064148212b
commit 7a9daa3cd3
1 changed files with 2 additions and 2 deletions
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4
components/hal/esp32s3/include/hal/spi_ll.h
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@ -676,8 +676,8 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_
if (pre <= 0) { if (pre <= 0) {
pre = 1; pre = 1;
} }
if (pre > 8192) { if (pre > 16) {
pre = 8192; pre = 16;
} }
errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz);
if (bestn == -1 || errval <= besterr) { if (bestn == -1 || errval <= besterr) {