From 7c0b1dc98c84437e7e3c6f52ed08183eee418415 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Thu, 17 Oct 2024 12:23:49 +0800 Subject: [PATCH] fix(clk): rtc_clk_cpu_freq_set_xtal will always disable CPU's PLL Align C6/H2/C5/C61 rtc_clk_cpu_freq_set_xtal behavior to other chips For PMU supported chips, powering down CPU PLL in sleep will be done by PMU, not sleep code --- .../esp_hw_support/include/esp_private/rtc_clk.h | 15 +++++---------- .../esp_hw_support/port/esp32c5/include/soc/rtc.h | 5 +++-- components/esp_hw_support/port/esp32c5/rtc_clk.c | 6 ++---- .../esp_hw_support/port/esp32c6/include/soc/rtc.h | 5 +++-- components/esp_hw_support/port/esp32c6/rtc_clk.c | 6 ++---- .../port/esp32c61/include/soc/rtc.h | 5 +++-- components/esp_hw_support/port/esp32c61/rtc_clk.c | 6 ++---- .../esp_hw_support/port/esp32h2/include/soc/rtc.h | 5 +++-- components/esp_hw_support/port/esp32h2/rtc_clk.c | 6 ++---- .../esp_hw_support/port/esp32p4/include/soc/rtc.h | 4 ++-- components/esp_hw_support/port/esp32p4/rtc_clk.c | 1 + components/esp_hw_support/sleep_modes.c | 9 +++++++++ 12 files changed, 37 insertions(+), 36 deletions(-) diff --git a/components/esp_hw_support/include/esp_private/rtc_clk.h b/components/esp_hw_support/include/esp_private/rtc_clk.h index 52610fa0d1..4480780217 100644 --- a/components/esp_hw_support/include/esp_private/rtc_clk.h +++ b/components/esp_hw_support/include/esp_private/rtc_clk.h @@ -18,11 +18,12 @@ extern "C" { * @brief Switch CPU clock source to XTAL, and let cpu frequency equal to main XTAL frequency. * * This function does not disable CPU's source PLL. If the PLL requires to be disabled to save power, please call - * `rtc_clk_cpu_freq_set_xtal` instead. It does one extra check (if necessary) to see whether can disable the - * corresponding PLL after switching the CPU clock source to XTAL. + * `rtc_clk_cpu_freq_set_xtal` instead. It will always disable the corresponding PLL after switching the CPU clock + * source to XTAL (except for S2). * - * Currently, this function should only be called in `esp_restart_noos` and `esp_restart_noos_dig` to switch the CPU - * clock source back to XTAL (by default) before reset. + * Currently, this function is only called in `esp_restart_noos` and `esp_restart_noos_dig` to switch the CPU + * clock source back to XTAL (by default) before reset, and in `esp_sleep_start` to switch CPU clock source to XTAL + * before entering sleep for PMU supported chips. */ void rtc_clk_cpu_set_to_default_config(void); @@ -32,12 +33,6 @@ void rtc_clk_cpu_set_to_default_config(void); * Currently, this function is only used for tracking whether USB Serial/JTAG is using the 48MHz PHY clock * * Note: Calling this function only helps to not disable the BBPLL clock in `rtc_clk_cpu_freq_set_config`. - * For light and deep sleep, whether to disable the BBPLL in the internal call to `rtc_clk_cpu_freq_set_xtal` - * varies for targets. - * On ESP32C3/S3, USB CDC device can not function properly during sleep due to the lack of APB clock. Therefore. - * `rtc_clk_cpu_freq_set_xtal` will always disable BBPLL, no matter whether BBPLL has any consumer. - * On ESP32C6/H2, USB CDC device can maintain the minimum connection with the host during sleep, so - * `rtc_clk_cpu_freq_set_xtal` will check for BBPLL consumers, and keep BBPLL if USB Serial/JTAG is in use. */ void rtc_clk_bbpll_add_consumer(void); diff --git a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h index 92a2c4f5c2..a11d201f20 100644 --- a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h @@ -307,8 +307,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. * Assumes that XTAL frequency has been determined — don't call in startup code. * - * @note On ESP32C5, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be - * turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL. + * @note This function always disables BBPLL after switching the CPU clock source to XTAL for power saving purpose. + * If this is unwanted, please use rtc_clk_cpu_freq_set_config. It helps to check whether USB Serial JTAG is in use, + * if so, then BBPLL will not be turned off. */ void rtc_clk_cpu_freq_set_xtal(void); diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk.c b/components/esp_hw_support/port/esp32c5/rtc_clk.c index e3d1052c4b..23a3941c9d 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c5/rtc_clk.c @@ -383,10 +383,7 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) void rtc_clk_cpu_freq_set_xtal(void) { rtc_clk_cpu_set_to_default_config(); - // We don't turn off the bbpll if some consumers depend on bbpll - if (!s_bbpll_digi_consumers_ref_count) { - rtc_clk_bbpll_disable(); - } + rtc_clk_bbpll_disable(); } void rtc_clk_cpu_set_to_default_config(void) @@ -394,6 +391,7 @@ void rtc_clk_cpu_set_to_default_config(void) int freq_mhz = (int)rtc_clk_xtal_freq_get(); rtc_clk_cpu_freq_to_xtal(freq_mhz, 1); + s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep } void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz) diff --git a/components/esp_hw_support/port/esp32c6/include/soc/rtc.h b/components/esp_hw_support/port/esp32c6/include/soc/rtc.h index 8d508d5df3..3880b325e5 100644 --- a/components/esp_hw_support/port/esp32c6/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c6/include/soc/rtc.h @@ -338,8 +338,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. * Assumes that XTAL frequency has been determined — don't call in startup code. * - * @note On ESP32C6, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be - * turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL. + * @note This function always disables BBPLL after switching the CPU clock source to XTAL for power saving purpose. + * If this is unwanted, please use rtc_clk_cpu_freq_set_config. It helps to check whether USB Serial JTAG is in use, + * if so, then BBPLL will not be turned off. */ void rtc_clk_cpu_freq_set_xtal(void); diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk.c b/components/esp_hw_support/port/esp32c6/rtc_clk.c index 521e2fd03f..c36c48d859 100644 --- a/components/esp_hw_support/port/esp32c6/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c6/rtc_clk.c @@ -333,10 +333,7 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) void rtc_clk_cpu_freq_set_xtal(void) { rtc_clk_cpu_set_to_default_config(); - // We don't turn off the bbpll if some consumers depend on bbpll - if (!s_bbpll_digi_consumers_ref_count) { - rtc_clk_bbpll_disable(); - } + rtc_clk_bbpll_disable(); } void rtc_clk_cpu_set_to_default_config(void) @@ -344,6 +341,7 @@ void rtc_clk_cpu_set_to_default_config(void) int freq_mhz = (int)rtc_clk_xtal_freq_get(); rtc_clk_cpu_freq_to_xtal(freq_mhz, 1); + s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep } void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz) diff --git a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h index 12c15bc101..b041327339 100644 --- a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h @@ -307,8 +307,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. * Assumes that XTAL frequency has been determined — don't call in startup code. * - * @note On ESP32C61, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be - * turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL. + * @note This function always disables BBPLL after switching the CPU clock source to XTAL for power saving purpose. + * If this is unwanted, please use rtc_clk_cpu_freq_set_config. It helps to check whether USB Serial JTAG is in use, + * if so, then BBPLL will not be turned off. */ void rtc_clk_cpu_freq_set_xtal(void); diff --git a/components/esp_hw_support/port/esp32c61/rtc_clk.c b/components/esp_hw_support/port/esp32c61/rtc_clk.c index e46cdbe1c4..5c32d17358 100644 --- a/components/esp_hw_support/port/esp32c61/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c61/rtc_clk.c @@ -327,10 +327,7 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) void rtc_clk_cpu_freq_set_xtal(void) { rtc_clk_cpu_set_to_default_config(); - // We don't turn off the bbpll if some consumers depend on bbpll - if (!s_bbpll_digi_consumers_ref_count) { - rtc_clk_bbpll_disable(); - } + rtc_clk_bbpll_disable(); } void rtc_clk_cpu_set_to_default_config(void) @@ -338,6 +335,7 @@ void rtc_clk_cpu_set_to_default_config(void) int freq_mhz = (int)rtc_clk_xtal_freq_get(); rtc_clk_cpu_freq_to_xtal(freq_mhz, 1); + s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep } void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz) diff --git a/components/esp_hw_support/port/esp32h2/include/soc/rtc.h b/components/esp_hw_support/port/esp32h2/include/soc/rtc.h index dfd1f96f01..fa820b48d8 100644 --- a/components/esp_hw_support/port/esp32h2/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32h2/include/soc/rtc.h @@ -354,8 +354,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. * Assumes that XTAL frequency has been determined — don't call in startup code. * - * @note On ESP32H2, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be - * turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL. + * @note This function always disables BBPLL after switching the CPU clock source to XTAL for power saving purpose. + * If this is unwanted, please use rtc_clk_cpu_freq_set_config. It helps to check whether USB Serial JTAG is in use, + * if so, then BBPLL will not be turned off. */ void rtc_clk_cpu_freq_set_xtal(void); diff --git a/components/esp_hw_support/port/esp32h2/rtc_clk.c b/components/esp_hw_support/port/esp32h2/rtc_clk.c index 0c6664fdce..7a8a82ef59 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_clk.c +++ b/components/esp_hw_support/port/esp32h2/rtc_clk.c @@ -393,10 +393,7 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) void rtc_clk_cpu_freq_set_xtal(void) { rtc_clk_cpu_set_to_default_config(); - // We don't turn off the bbpll if some consumers only depends on bbpll - if (!s_bbpll_digi_consumers_ref_count) { - rtc_clk_bbpll_disable(); - } + rtc_clk_bbpll_disable(); } void rtc_clk_cpu_set_to_default_config(void) @@ -404,6 +401,7 @@ void rtc_clk_cpu_set_to_default_config(void) int freq_mhz = (int)rtc_clk_xtal_freq_get(); rtc_clk_cpu_freq_to_xtal(freq_mhz, 1); + s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep } soc_xtal_freq_t rtc_clk_xtal_freq_get(void) diff --git a/components/esp_hw_support/port/esp32p4/include/soc/rtc.h b/components/esp_hw_support/port/esp32p4/include/soc/rtc.h index 183f8a79fe..43acaa253f 100644 --- a/components/esp_hw_support/port/esp32p4/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32p4/include/soc/rtc.h @@ -350,8 +350,8 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. * Assumes that XTAL frequency has been determined — don't call in startup code. * - * @note On ESP32C6, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be - * turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL. + * @note On ESP32P4, this function always disables CPLL after switching the CPU clock source to XTAL, + * since there is no peripheral relies on CPLL clock (except Flash/PSRAM if their clock source selects CPLL). */ void rtc_clk_cpu_freq_set_xtal(void); diff --git a/components/esp_hw_support/port/esp32p4/rtc_clk.c b/components/esp_hw_support/port/esp32p4/rtc_clk.c index aa3bfd9675..f9e19ce08c 100644 --- a/components/esp_hw_support/port/esp32p4/rtc_clk.c +++ b/components/esp_hw_support/port/esp32p4/rtc_clk.c @@ -426,6 +426,7 @@ void rtc_clk_cpu_set_to_default_config(void) int freq_mhz = (int)rtc_clk_xtal_freq_get(); rtc_clk_cpu_freq_to_xtal(freq_mhz, 1, true); + s_cur_cpll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep } soc_xtal_freq_t rtc_clk_xtal_freq_get(void) diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 0f36b970c4..9c60ea1f04 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -810,7 +810,16 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m // Save current frequency and switch to XTAL rtc_cpu_freq_config_t cpu_freq_config; rtc_clk_cpu_freq_get_config(&cpu_freq_config); +#if SOC_PMU_SUPPORTED + // For PMU supported chips, CPU's PLL power can be turned off by PMU, so no need to disable the PLL at here. + // Leaving PLL on at this stage also helps USJ keep connection and retention operation (if they rely on this PLL). + rtc_clk_cpu_set_to_default_config(); +#else + // For earlier chips, there is no PMU module that can turn off the CPU's PLL, so it has to be disabled at here to save the power consumption. + // Though ESP32C3/S3 has USB CDC device, it can not function properly during sleep due to the lack of APB clock (before C6, USJ relies on APB clock to work). + // Therefore, we will always disable CPU's PLL (i.e. BBPLL). rtc_clk_cpu_freq_set_xtal(); +#endif #if SOC_PM_SUPPORT_EXT0_WAKEUP // Configure pins for external wakeup