diff --git a/components/esp32c3/ld/esp32c3.peripherals.ld b/components/esp32c3/ld/esp32c3.peripherals.ld index 61164a12cd..cd93401198 100644 --- a/components/esp32c3/ld/esp32c3.peripherals.ld +++ b/components/esp32c3/ld/esp32c3.peripherals.ld @@ -20,6 +20,7 @@ PROVIDE ( SLC = 0x60018000 ); PROVIDE ( LEDC = 0x60019000 ); PROVIDE ( TIMERG0 = 0x6001F000 ); PROVIDE ( TIMERG1 = 0x60020000 ); +PROVIDE ( SYSTIMER = 0x60023000 ); PROVIDE ( GPSPI2 = 0x60024000 ); PROVIDE ( GPSPI3 = 0x60025000 ); PROVIDE ( SYSCON = 0x60026000 ); diff --git a/components/esp32s2/ld/esp32s2.peripherals.ld b/components/esp32s2/ld/esp32s2.peripherals.ld index 512d840f8e..48aa0414ca 100644 --- a/components/esp32s2/ld/esp32s2.peripherals.ld +++ b/components/esp32s2/ld/esp32s2.peripherals.ld @@ -20,6 +20,7 @@ PROVIDE ( LEDC = 0x3f419000 ); PROVIDE ( CP_DMA = 0x3f4c3000 ); PROVIDE ( TIMERG0 = 0x3f41F000 ); PROVIDE ( TIMERG1 = 0x3f420000 ); +PROVIDE ( SYSTIMER = 0x3f423000 ); PROVIDE ( GPSPI2 = 0x3f424000 ); PROVIDE ( GPSPI3 = 0x3f425000 ); PROVIDE ( SYSCON = 0x3f426000 ); diff --git a/components/esp32s3/ld/esp32s3.peripherals.ld b/components/esp32s3/ld/esp32s3.peripherals.ld index 55772f958e..fd04255209 100644 --- a/components/esp32s3/ld/esp32s3.peripherals.ld +++ b/components/esp32s3/ld/esp32s3.peripherals.ld @@ -23,7 +23,7 @@ PROVIDE ( MCPWM1 = 0x6002C000 ); PROVIDE ( MCP = 0x600c3000 ); PROVIDE ( TIMERG0 = 0x6001F000 ); PROVIDE ( TIMERG1 = 0x60020000 ); -PROVIDE ( SYS_TIMER = 0x60023000 ); +PROVIDE ( SYSTIMER = 0x60023000 ); PROVIDE ( GPSPI2 = 0x60024000 ); PROVIDE ( GPSPI3 = 0x60025000 ); PROVIDE ( SYSCON = 0x60026000 ); diff --git a/components/hal/include/hal/systimer_types.h b/components/hal/include/hal/systimer_types.h index cf88a00f24..2af2f60f30 100644 --- a/components/hal/include/hal/systimer_types.h +++ b/components/hal/include/hal/systimer_types.h @@ -14,13 +14,13 @@ #pragma once +#include +#include "soc/soc_caps.h" + #ifdef __cplusplus extern "C" { #endif -#include -#include "soc/soc_caps.h" - /* * @brief The structure of the counter value in systimer * @@ -39,27 +39,6 @@ typedef struct { _Static_assert(sizeof(systimer_counter_value_t) == 8, "systimer_counter_value_t should occupy 8 bytes in memory"); /** @endcond */ -/** - * @brief systimer counter ID - * - */ -typedef enum { - SYSTIMER_COUNTER_0, /*!< systimer counter 0 */ -#if SOC_SYSTIMER_COUNTER_NUM > 1 - SYSTIMER_COUNTER_1, /*!< systimer counter 1 */ -#endif -} systimer_counter_id_t; - -/** - * @brief systimer alarm ID - * - */ -typedef enum { - SYSTIMER_ALARM_0, /*!< systimer alarm 0 */ - SYSTIMER_ALARM_1, /*!< systimer alarm 1 */ - SYSTIMER_ALARM_2, /*!< systimer alarm 2 */ -} systimer_alarm_id_t; - /** * @brief systimer alarm mode * diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index e17ef9870e..a6769b990f 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -58,7 +58,7 @@ #define DR_REG_BB_BASE 0x6001D000 #define DR_REG_TIMERGROUP0_BASE 0x6001F000 #define DR_REG_TIMERGROUP1_BASE 0x60020000 -#define DR_REG_SYS_TIMER_BASE 0x60023000 +#define DR_REG_SYSTIMER_BASE 0x60023000 #define DR_REG_SPI2_BASE 0x60024000 #define DR_REG_SYSCON_BASE 0x60026000 #define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */ diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index f36268f498..c886a8dd5a 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -16,7 +16,6 @@ #include "i2c_caps.h" #include "mpu_caps.h" #include "sigmadelta_caps.h" -#include "systimer_caps.h" #include "uart_caps.h" #include "brownout_caps.h" #include "gdma_caps.h" @@ -62,6 +61,15 @@ #define SOC_SHA_SUPPORT_SHA224 (1) #define SOC_SHA_SUPPORT_SHA256 (1) +/*-------------------------- SYSTIMER CAPS ----------------------------------*/ +#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units +#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part +#define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed +#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt +#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current) + /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ #define SOC_TIMER_GROUPS (2) #define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1) diff --git a/components/soc/esp32c3/include/soc/systimer_caps.h b/components/soc/esp32c3/include/soc/systimer_caps.h deleted file mode 100644 index feda097f45..0000000000 --- a/components/soc/esp32c3/include/soc/systimer_caps.h +++ /dev/null @@ -1,24 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units -#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units - -#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part -#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part - -#define SOC_SYSTIMER_FIXED_TICKS_US (16) // If defined, number of ticks per microsecond is fixed -#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt diff --git a/components/soc/esp32c3/include/soc/systimer_reg.h b/components/soc/esp32c3/include/soc/systimer_reg.h index cb6ebe6a43..4e9f64fffa 100644 --- a/components/soc/esp32c3/include/soc/systimer_reg.h +++ b/components/soc/esp32c3/include/soc/systimer_reg.h @@ -1,424 +1,567 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_SYS_TIMER_REG_H_ -#define _SOC_SYS_TIMER_REG_H_ - +/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -#define SYS_TIMER_SYSTIMER_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0000) -/* SYS_TIMER_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: register file clk gating*/ -#define SYS_TIMER_CLK_EN (BIT(31)) -#define SYS_TIMER_CLK_EN_M (BIT(31)) -#define SYS_TIMER_CLK_EN_V 0x1 -#define SYS_TIMER_CLK_EN_S 31 -/* SYS_TIMER_TIMER_UNIT0_WORK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: timer unit0 work enable*/ -#define SYS_TIMER_TIMER_UNIT0_WORK_EN (BIT(30)) -#define SYS_TIMER_TIMER_UNIT0_WORK_EN_M (BIT(30)) -#define SYS_TIMER_TIMER_UNIT0_WORK_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_WORK_EN_S 30 -/* SYS_TIMER_TIMER_UNIT1_WORK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: timer unit1 work enable*/ -#define SYS_TIMER_TIMER_UNIT1_WORK_EN (BIT(29)) -#define SYS_TIMER_TIMER_UNIT1_WORK_EN_M (BIT(29)) -#define SYS_TIMER_TIMER_UNIT1_WORK_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_WORK_EN_S 29 -/* SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: If timer unit0 is stalled when core0 stalled*/ -#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) -#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_M (BIT(28)) -#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 -/* SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: If timer unit0 is stalled when core1 stalled*/ -#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) -#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_M (BIT(27)) -#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 -/* SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W ;bitpos:[26] ;default: 1'b1 ; */ -/*description: If timer unit1 is stalled when core0 stalled*/ -#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) -#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_M (BIT(26)) -#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 -/* SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */ -/*description: If timer unit1 is stalled when core1 stalled*/ -#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) -#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_M (BIT(25)) -#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 -/* SYS_TIMER_TARGET0_WORK_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: target0 work enable*/ -#define SYS_TIMER_TARGET0_WORK_EN (BIT(24)) -#define SYS_TIMER_TARGET0_WORK_EN_M (BIT(24)) -#define SYS_TIMER_TARGET0_WORK_EN_V 0x1 -#define SYS_TIMER_TARGET0_WORK_EN_S 24 -/* SYS_TIMER_TARGET1_WORK_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: target1 work enable*/ -#define SYS_TIMER_TARGET1_WORK_EN (BIT(23)) -#define SYS_TIMER_TARGET1_WORK_EN_M (BIT(23)) -#define SYS_TIMER_TARGET1_WORK_EN_V 0x1 -#define SYS_TIMER_TARGET1_WORK_EN_S 23 -/* SYS_TIMER_TARGET2_WORK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: target2 work enable*/ -#define SYS_TIMER_TARGET2_WORK_EN (BIT(22)) -#define SYS_TIMER_TARGET2_WORK_EN_M (BIT(22)) -#define SYS_TIMER_TARGET2_WORK_EN_V 0x1 -#define SYS_TIMER_TARGET2_WORK_EN_S 22 -/* SYS_TIMER_SYSTIMER_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: systimer clock force on*/ -#define SYS_TIMER_SYSTIMER_CLK_FO (BIT(0)) -#define SYS_TIMER_SYSTIMER_CLK_FO_M (BIT(0)) -#define SYS_TIMER_SYSTIMER_CLK_FO_V 0x1 -#define SYS_TIMER_SYSTIMER_CLK_FO_S 0 -#define SYS_TIMER_SYSTIMER_UNIT0_OP_REG (DR_REG_SYS_TIMER_BASE + 0x0004) -/* SYS_TIMER_TIMER_UNIT0_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */ -/*description: update timer_unit0*/ -#define SYS_TIMER_TIMER_UNIT0_UPDATE (BIT(30)) -#define SYS_TIMER_TIMER_UNIT0_UPDATE_M (BIT(30)) -#define SYS_TIMER_TIMER_UNIT0_UPDATE_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_UPDATE_S 30 -/* SYS_TIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) -#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_M (BIT(29)) -#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_S 29 +/** SYSTIMER_CONF_REG register + * SYSTIMER_CONF. + */ +#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0) +/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0; + * systimer clock force on + */ +#define SYSTIMER_SYSTIMER_CLK_FO (BIT(0)) +#define SYSTIMER_SYSTIMER_CLK_FO_M (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S) +#define SYSTIMER_SYSTIMER_CLK_FO_V 0x00000001 +#define SYSTIMER_SYSTIMER_CLK_FO_S 0 +/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ +#define SYSTIMER_TARGET2_WORK_EN (BIT(22)) +#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S) +#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001 +#define SYSTIMER_TARGET2_WORK_EN_S 22 +/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ +#define SYSTIMER_TARGET1_WORK_EN (BIT(23)) +#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S) +#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001 +#define SYSTIMER_TARGET1_WORK_EN_S 23 +/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ +#define SYSTIMER_TARGET0_WORK_EN (BIT(24)) +#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S) +#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001 +#define SYSTIMER_TARGET0_WORK_EN_S 24 +/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 +/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 +/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 +/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 +/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ +#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29 +/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ +#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30 +/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ +#define SYSTIMER_CLK_EN (BIT(31)) +#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S) +#define SYSTIMER_CLK_EN_V 0x00000001 +#define SYSTIMER_CLK_EN_S 31 -#define SYS_TIMER_SYSTIMER_UNIT1_OP_REG (DR_REG_SYS_TIMER_BASE + 0x0008) -/* SYS_TIMER_TIMER_UNIT1_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */ -/*description: update timer unit1*/ -#define SYS_TIMER_TIMER_UNIT1_UPDATE (BIT(30)) -#define SYS_TIMER_TIMER_UNIT1_UPDATE_M (BIT(30)) -#define SYS_TIMER_TIMER_UNIT1_UPDATE_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_UPDATE_S 30 -/* SYS_TIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */ -/*description: timer value is sync and valid*/ -#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) -#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_M (BIT(29)) -#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_S 29 +/** SYSTIMER_UNIT0_OP_REG register + * SYSTIMER_UNIT0_OP. + */ +#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4) +/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * reg_timer_unit0_value_valid + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0; + * update timer_unit0 + */ +#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S) +#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30 -#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x000C) -/* SYS_TIMER_TIMER_UNIT0_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer unit0 load high 32 bit*/ -#define SYS_TIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF -#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT0_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_HI_S)) -#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_S 0 +/** SYSTIMER_UNIT1_OP_REG register + * SYSTIMER_UNIT1_OP. + */ +#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8) +/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0; + * update timer unit1 + */ +#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S) +#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30 -#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0010) -/* SYS_TIMER_TIMER_UNIT0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer unit0 load low 32 bit*/ -#define SYS_TIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT0_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_LO_S)) -#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_S 0 +/** SYSTIMER_UNIT0_LOAD_HI_REG register + * SYSTIMER_UNIT0_LOAD_HI. + */ +#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc) +/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit0 load high 32 bit + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0 -#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0014) -/* SYS_TIMER_TIMER_UNIT1_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer unit1 load high 32 bit*/ -#define SYS_TIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF -#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT1_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_HI_S)) -#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_S 0 +/** SYSTIMER_UNIT0_LOAD_LO_REG register + * SYSTIMER_UNIT0_LOAD_LO. + */ +#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10) +/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit0 load low 32 bit + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0 -#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0018) -/* SYS_TIMER_TIMER_UNIT1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer unit1 load low 32 bit*/ -#define SYS_TIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT1_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_LO_S)) -#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_S 0 +/** SYSTIMER_UNIT1_LOAD_HI_REG register + * SYSTIMER_UNIT1_LOAD_HI. + */ +#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14) +/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit1 load high 32 bit + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0 -#define SYS_TIMER_SYSTIMER_TARGET0_HI_REG (DR_REG_SYS_TIMER_BASE + 0x001C) -/* SYS_TIMER_TIMER_TARGET0_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer taget0 high 32 bit*/ -#define SYS_TIMER_TIMER_TARGET0_HI 0x000FFFFF -#define SYS_TIMER_TIMER_TARGET0_HI_M ((SYS_TIMER_TIMER_TARGET0_HI_V)<<(SYS_TIMER_TIMER_TARGET0_HI_S)) -#define SYS_TIMER_TIMER_TARGET0_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_TARGET0_HI_S 0 +/** SYSTIMER_UNIT1_LOAD_LO_REG register + * SYSTIMER_UNIT1_LOAD_LO. + */ +#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18) +/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit1 load low 32 bit + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0 -#define SYS_TIMER_SYSTIMER_TARGET0_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0020) -/* SYS_TIMER_TIMER_TARGET0_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer taget0 low 32 bit*/ -#define SYS_TIMER_TIMER_TARGET0_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET0_LO_M ((SYS_TIMER_TIMER_TARGET0_LO_V)<<(SYS_TIMER_TIMER_TARGET0_LO_S)) -#define SYS_TIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET0_LO_S 0 +/** SYSTIMER_TARGET0_HI_REG register + * SYSTIMER_TARGET0_HI. + */ +#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c) +/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget0 high 32 bit + */ +#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFF +#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S) +#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_TARGET0_HI_S 0 -#define SYS_TIMER_SYSTIMER_TARGET1_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0024) -/* SYS_TIMER_TIMER_TARGET1_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer taget1 high 32 bit*/ -#define SYS_TIMER_TIMER_TARGET1_HI 0x000FFFFF -#define SYS_TIMER_TIMER_TARGET1_HI_M ((SYS_TIMER_TIMER_TARGET1_HI_V)<<(SYS_TIMER_TIMER_TARGET1_HI_S)) -#define SYS_TIMER_TIMER_TARGET1_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_TARGET1_HI_S 0 +/** SYSTIMER_TARGET0_LO_REG register + * SYSTIMER_TARGET0_LO. + */ +#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20) +/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget0 low 32 bit + */ +#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S) +#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET0_LO_S 0 -#define SYS_TIMER_SYSTIMER_TARGET1_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0028) -/* SYS_TIMER_TIMER_TARGET1_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer taget1 low 32 bit*/ -#define SYS_TIMER_TIMER_TARGET1_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET1_LO_M ((SYS_TIMER_TIMER_TARGET1_LO_V)<<(SYS_TIMER_TIMER_TARGET1_LO_S)) -#define SYS_TIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET1_LO_S 0 +/** SYSTIMER_TARGET1_HI_REG register + * SYSTIMER_TARGET1_HI. + */ +#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24) +/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget1 high 32 bit + */ +#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFF +#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S) +#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_TARGET1_HI_S 0 -#define SYS_TIMER_SYSTIMER_TARGET2_HI_REG (DR_REG_SYS_TIMER_BASE + 0x002C) -/* SYS_TIMER_TIMER_TARGET2_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer taget2 high 32 bit*/ -#define SYS_TIMER_TIMER_TARGET2_HI 0x000FFFFF -#define SYS_TIMER_TIMER_TARGET2_HI_M ((SYS_TIMER_TIMER_TARGET2_HI_V)<<(SYS_TIMER_TIMER_TARGET2_HI_S)) -#define SYS_TIMER_TIMER_TARGET2_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_TARGET2_HI_S 0 +/** SYSTIMER_TARGET1_LO_REG register + * SYSTIMER_TARGET1_LO. + */ +#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28) +/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget1 low 32 bit + */ +#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S) +#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET1_LO_S 0 -#define SYS_TIMER_SYSTIMER_TARGET2_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0030) -/* SYS_TIMER_TIMER_TARGET2_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer taget2 low 32 bit*/ -#define SYS_TIMER_TIMER_TARGET2_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET2_LO_M ((SYS_TIMER_TIMER_TARGET2_LO_V)<<(SYS_TIMER_TIMER_TARGET2_LO_S)) -#define SYS_TIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET2_LO_S 0 +/** SYSTIMER_TARGET2_HI_REG register + * SYSTIMER_TARGET2_HI. + */ +#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c) +/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget2 high 32 bit + */ +#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFF +#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S) +#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_TARGET2_HI_S 0 -#define SYS_TIMER_SYSTIMER_TARGET0_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0034) -/* SYS_TIMER_TARGET0_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: select which unit to compare*/ -#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) -#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_M (BIT(31)) -#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_V 0x1 -#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_S 31 -/* SYS_TIMER_TARGET0_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set target0 to period mode*/ -#define SYS_TIMER_TARGET0_PERIOD_MODE (BIT(30)) -#define SYS_TIMER_TARGET0_PERIOD_MODE_M (BIT(30)) -#define SYS_TIMER_TARGET0_PERIOD_MODE_V 0x1 -#define SYS_TIMER_TARGET0_PERIOD_MODE_S 30 -/* SYS_TIMER_TARGET0_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: target0 period*/ -#define SYS_TIMER_TARGET0_PERIOD 0x03FFFFFF -#define SYS_TIMER_TARGET0_PERIOD_M ((SYS_TIMER_TARGET0_PERIOD_V)<<(SYS_TIMER_TARGET0_PERIOD_S)) -#define SYS_TIMER_TARGET0_PERIOD_V 0x3FFFFFF -#define SYS_TIMER_TARGET0_PERIOD_S 0 +/** SYSTIMER_TARGET2_LO_REG register + * SYSTIMER_TARGET2_LO. + */ +#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30) +/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget2 low 32 bit + */ +#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S) +#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET2_LO_S 0 -#define SYS_TIMER_SYSTIMER_TARGET1_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0038) -/* SYS_TIMER_TARGET1_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: select which unit to compare*/ -#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) -#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_M (BIT(31)) -#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_V 0x1 -#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_S 31 -/* SYS_TIMER_TARGET1_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set target1 to period mode*/ -#define SYS_TIMER_TARGET1_PERIOD_MODE (BIT(30)) -#define SYS_TIMER_TARGET1_PERIOD_MODE_M (BIT(30)) -#define SYS_TIMER_TARGET1_PERIOD_MODE_V 0x1 -#define SYS_TIMER_TARGET1_PERIOD_MODE_S 30 -/* SYS_TIMER_TARGET1_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: target1 period*/ -#define SYS_TIMER_TARGET1_PERIOD 0x03FFFFFF -#define SYS_TIMER_TARGET1_PERIOD_M ((SYS_TIMER_TARGET1_PERIOD_V)<<(SYS_TIMER_TARGET1_PERIOD_S)) -#define SYS_TIMER_TARGET1_PERIOD_V 0x3FFFFFF -#define SYS_TIMER_TARGET1_PERIOD_S 0 +/** SYSTIMER_TARGET0_CONF_REG register + * SYSTIMER_TARGET0_CONF. + */ +#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34) +/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target0 period + */ +#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFF +#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S) +#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFF +#define SYSTIMER_TARGET0_PERIOD_S 0 +/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target0 to period mode + */ +#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S) +#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001 +#define SYSTIMER_TARGET0_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001 +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31 -#define SYS_TIMER_SYSTIMER_TARGET2_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x003C) -/* SYS_TIMER_TARGET2_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: select which unit to compare*/ -#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) -#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_M (BIT(31)) -#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_V 0x1 -#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_S 31 -/* SYS_TIMER_TARGET2_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set target2 to period mode*/ -#define SYS_TIMER_TARGET2_PERIOD_MODE (BIT(30)) -#define SYS_TIMER_TARGET2_PERIOD_MODE_M (BIT(30)) -#define SYS_TIMER_TARGET2_PERIOD_MODE_V 0x1 -#define SYS_TIMER_TARGET2_PERIOD_MODE_S 30 -/* SYS_TIMER_TARGET2_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: target2 period*/ -#define SYS_TIMER_TARGET2_PERIOD 0x03FFFFFF -#define SYS_TIMER_TARGET2_PERIOD_M ((SYS_TIMER_TARGET2_PERIOD_V)<<(SYS_TIMER_TARGET2_PERIOD_S)) -#define SYS_TIMER_TARGET2_PERIOD_V 0x3FFFFFF -#define SYS_TIMER_TARGET2_PERIOD_S 0 +/** SYSTIMER_TARGET1_CONF_REG register + * SYSTIMER_TARGET1_CONF. + */ +#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38) +/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target1 period + */ +#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFF +#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S) +#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFF +#define SYSTIMER_TARGET1_PERIOD_S 0 +/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target1 to period mode + */ +#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S) +#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001 +#define SYSTIMER_TARGET1_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001 +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31 -#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0040) -/* SYS_TIMER_TIMER_UNIT0_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer read value high 32bit*/ -#define SYS_TIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF -#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT0_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_HI_S)) -#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_S 0 +/** SYSTIMER_TARGET2_CONF_REG register + * SYSTIMER_TARGET2_CONF. + */ +#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c) +/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target2 period + */ +#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFF +#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S) +#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFF +#define SYSTIMER_TARGET2_PERIOD_S 0 +/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target2 to period mode + */ +#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S) +#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001 +#define SYSTIMER_TARGET2_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001 +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31 -#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0044) -/* SYS_TIMER_TIMER_UNIT0_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer read value low 32bit*/ -#define SYS_TIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT0_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_LO_S)) -#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_S 0 +/** SYSTIMER_UNIT0_VALUE_HI_REG register + * SYSTIMER_UNIT0_VALUE_HI. + */ +#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40) +/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 32bit + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0 -#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0048) -/* SYS_TIMER_TIMER_UNIT1_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer read value high 32bit*/ -#define SYS_TIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF -#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT1_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_HI_S)) -#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_S 0 +/** SYSTIMER_UNIT0_VALUE_LO_REG register + * SYSTIMER_UNIT0_VALUE_LO. + */ +#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44) +/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bit + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0 -#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x004C) -/* SYS_TIMER_TIMER_UNIT1_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer read value low 32bit*/ -#define SYS_TIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT1_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_LO_S)) -#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_S 0 +/** SYSTIMER_UNIT1_VALUE_HI_REG register + * SYSTIMER_UNIT1_VALUE_HI. + */ +#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48) +/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 32bit + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0 -#define SYS_TIMER_SYSTIMER_COMP0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0050) -/* SYS_TIMER_TIMER_COMP0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer comp0 load value*/ -#define SYS_TIMER_TIMER_COMP0_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_COMP0_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_COMP0_LOAD_V 0x1 -#define SYS_TIMER_TIMER_COMP0_LOAD_S 0 +/** SYSTIMER_UNIT1_VALUE_LO_REG register + * SYSTIMER_UNIT1_VALUE_LO. + */ +#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c) +/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bit + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0 -#define SYS_TIMER_SYSTIMER_COMP1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0054) -/* SYS_TIMER_TIMER_COMP1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer comp1 load value*/ -#define SYS_TIMER_TIMER_COMP1_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_COMP1_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_COMP1_LOAD_V 0x1 -#define SYS_TIMER_TIMER_COMP1_LOAD_S 0 +/** SYSTIMER_COMP0_LOAD_REG register + * SYSTIMER_COMP0_LOAD. + */ +#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50) +/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0; + * timer comp0 load value + */ +#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S) +#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_COMP0_LOAD_S 0 -#define SYS_TIMER_SYSTIMER_COMP2_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0058) -/* SYS_TIMER_TIMER_COMP2_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer comp2 load value*/ -#define SYS_TIMER_TIMER_COMP2_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_COMP2_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_COMP2_LOAD_V 0x1 -#define SYS_TIMER_TIMER_COMP2_LOAD_S 0 +/** SYSTIMER_COMP1_LOAD_REG register + * SYSTIMER_COMP1_LOAD. + */ +#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54) +/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0; + * timer comp1 load value + */ +#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S) +#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_COMP1_LOAD_S 0 -#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x005C) -/* SYS_TIMER_TIMER_UNIT0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer unit0 load value*/ -#define SYS_TIMER_TIMER_UNIT0_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_UNIT0_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_UNIT0_LOAD_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_LOAD_S 0 +/** SYSTIMER_COMP2_LOAD_REG register + * SYSTIMER_COMP2_LOAD. + */ +#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58) +/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0; + * timer comp2 load value + */ +#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S) +#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_COMP2_LOAD_S 0 -#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0060) -/* SYS_TIMER_TIMER_UNIT1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer unit1 load value*/ -#define SYS_TIMER_TIMER_UNIT1_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_UNIT1_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_UNIT1_LOAD_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_LOAD_S 0 +/** SYSTIMER_UNIT0_LOAD_REG register + * SYSTIMER_UNIT0_LOAD. + */ +#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c) +/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0; + * timer unit0 load value + */ +#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_LOAD_S 0 -#define SYS_TIMER_SYSTIMER_INT_ENA_REG (DR_REG_SYS_TIMER_BASE + 0x0064) -/* SYS_TIMER_TARGET2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: interupt2 enable*/ -#define SYS_TIMER_TARGET2_INT_ENA (BIT(2)) -#define SYS_TIMER_TARGET2_INT_ENA_M (BIT(2)) -#define SYS_TIMER_TARGET2_INT_ENA_V 0x1 -#define SYS_TIMER_TARGET2_INT_ENA_S 2 -/* SYS_TIMER_TARGET1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: interupt1 enable*/ -#define SYS_TIMER_TARGET1_INT_ENA (BIT(1)) -#define SYS_TIMER_TARGET1_INT_ENA_M (BIT(1)) -#define SYS_TIMER_TARGET1_INT_ENA_V 0x1 -#define SYS_TIMER_TARGET1_INT_ENA_S 1 -/* SYS_TIMER_TARGET0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: interupt0 enable*/ -#define SYS_TIMER_TARGET0_INT_ENA (BIT(0)) -#define SYS_TIMER_TARGET0_INT_ENA_M (BIT(0)) -#define SYS_TIMER_TARGET0_INT_ENA_V 0x1 -#define SYS_TIMER_TARGET0_INT_ENA_S 0 +/** SYSTIMER_UNIT1_LOAD_REG register + * SYSTIMER_UNIT1_LOAD. + */ +#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60) +/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0; + * timer unit1 load value + */ +#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_LOAD_S 0 -#define SYS_TIMER_SYSTIMER_INT_RAW_REG (DR_REG_SYS_TIMER_BASE + 0x0068) -/* SYS_TIMER_TARGET2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: interupt2 raw*/ -#define SYS_TIMER_TARGET2_INT_RAW (BIT(2)) -#define SYS_TIMER_TARGET2_INT_RAW_M (BIT(2)) -#define SYS_TIMER_TARGET2_INT_RAW_V 0x1 -#define SYS_TIMER_TARGET2_INT_RAW_S 2 -/* SYS_TIMER_TARGET1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: interupt1 raw*/ -#define SYS_TIMER_TARGET1_INT_RAW (BIT(1)) -#define SYS_TIMER_TARGET1_INT_RAW_M (BIT(1)) -#define SYS_TIMER_TARGET1_INT_RAW_V 0x1 -#define SYS_TIMER_TARGET1_INT_RAW_S 1 -/* SYS_TIMER_TARGET0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: interupt0 raw*/ -#define SYS_TIMER_TARGET0_INT_RAW (BIT(0)) -#define SYS_TIMER_TARGET0_INT_RAW_M (BIT(0)) -#define SYS_TIMER_TARGET0_INT_RAW_V 0x1 -#define SYS_TIMER_TARGET0_INT_RAW_S 0 +/** SYSTIMER_INT_ENA_REG register + * SYSTIMER_INT_ENA. + */ +#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64) +/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ +#define SYSTIMER_TARGET0_INT_ENA (BIT(0)) +#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S) +#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001 +#define SYSTIMER_TARGET0_INT_ENA_S 0 +/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ +#define SYSTIMER_TARGET1_INT_ENA (BIT(1)) +#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S) +#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001 +#define SYSTIMER_TARGET1_INT_ENA_S 1 +/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ +#define SYSTIMER_TARGET2_INT_ENA (BIT(2)) +#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S) +#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001 +#define SYSTIMER_TARGET2_INT_ENA_S 2 -#define SYS_TIMER_SYSTIMER_INT_CLR_REG (DR_REG_SYS_TIMER_BASE + 0x006c) -/* SYS_TIMER_TARGET2_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: interupt2 clear*/ -#define SYS_TIMER_TARGET2_INT_CLR (BIT(2)) -#define SYS_TIMER_TARGET2_INT_CLR_M (BIT(2)) -#define SYS_TIMER_TARGET2_INT_CLR_V 0x1 -#define SYS_TIMER_TARGET2_INT_CLR_S 2 -/* SYS_TIMER_TARGET1_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: interupt1 clear*/ -#define SYS_TIMER_TARGET1_INT_CLR (BIT(1)) -#define SYS_TIMER_TARGET1_INT_CLR_M (BIT(1)) -#define SYS_TIMER_TARGET1_INT_CLR_V 0x1 -#define SYS_TIMER_TARGET1_INT_CLR_S 1 -/* SYS_TIMER_TARGET0_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: interupt0 clear*/ -#define SYS_TIMER_TARGET0_INT_CLR (BIT(0)) -#define SYS_TIMER_TARGET0_INT_CLR_M (BIT(0)) -#define SYS_TIMER_TARGET0_INT_CLR_V 0x1 -#define SYS_TIMER_TARGET0_INT_CLR_S 0 +/** SYSTIMER_INT_RAW_REG register + * SYSTIMER_INT_RAW. + */ +#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68) +/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ +#define SYSTIMER_TARGET0_INT_RAW (BIT(0)) +#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S) +#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001 +#define SYSTIMER_TARGET0_INT_RAW_S 0 +/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ +#define SYSTIMER_TARGET1_INT_RAW (BIT(1)) +#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S) +#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001 +#define SYSTIMER_TARGET1_INT_RAW_S 1 +/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ +#define SYSTIMER_TARGET2_INT_RAW (BIT(2)) +#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S) +#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001 +#define SYSTIMER_TARGET2_INT_RAW_S 2 -#define SYS_TIMER_SYSTIMER_INT_ST_REG (DR_REG_SYS_TIMER_BASE + 0x0070) -/* SYS_TIMER_TARGET2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SYS_TIMER_TARGET2_INT_ST (BIT(2)) -#define SYS_TIMER_TARGET2_INT_ST_M (BIT(2)) -#define SYS_TIMER_TARGET2_INT_ST_V 0x1 -#define SYS_TIMER_TARGET2_INT_ST_S 2 -/* SYS_TIMER_TARGET1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYS_TIMER_TARGET1_INT_ST (BIT(1)) -#define SYS_TIMER_TARGET1_INT_ST_M (BIT(1)) -#define SYS_TIMER_TARGET1_INT_ST_V 0x1 -#define SYS_TIMER_TARGET1_INT_ST_S 1 -/* SYS_TIMER_TARGET0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYS_TIMER_TARGET0_INT_ST (BIT(0)) -#define SYS_TIMER_TARGET0_INT_ST_M (BIT(0)) -#define SYS_TIMER_TARGET0_INT_ST_V 0x1 -#define SYS_TIMER_TARGET0_INT_ST_S 0 +/** SYSTIMER_INT_CLR_REG register + * SYSTIMER_INT_CLR. + */ +#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c) +/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ +#define SYSTIMER_TARGET0_INT_CLR (BIT(0)) +#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S) +#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001 +#define SYSTIMER_TARGET0_INT_CLR_S 0 +/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ +#define SYSTIMER_TARGET1_INT_CLR (BIT(1)) +#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S) +#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001 +#define SYSTIMER_TARGET1_INT_CLR_S 1 +/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ +#define SYSTIMER_TARGET2_INT_CLR (BIT(2)) +#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S) +#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001 +#define SYSTIMER_TARGET2_INT_CLR_S 2 -#define SYS_TIMER_SYSTIMER_DATE_REG (DR_REG_SYS_TIMER_BASE + 0x00fc) -/* SYS_TIMER_DATE : R/W ;bitpos:[31:0] ;default: 28'h2006171 ; */ -/*description: */ -#define SYS_TIMER_DATE 0xFFFFFFFF -#define SYS_TIMER_DATE_M ((SYS_TIMER_DATE_V)<<(SYS_TIMER_DATE_S)) -#define SYS_TIMER_DATE_V 0xFFFFFFFF -#define SYS_TIMER_DATE_S 0 +/** SYSTIMER_INT_ST_REG register + * SYSTIMER_INT_ST. + */ +#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70) +/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0; + * reg_target0_int_st + */ +#define SYSTIMER_TARGET0_INT_ST (BIT(0)) +#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S) +#define SYSTIMER_TARGET0_INT_ST_V 0x00000001 +#define SYSTIMER_TARGET0_INT_ST_S 0 +/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0; + * reg_target1_int_st + */ +#define SYSTIMER_TARGET1_INT_ST (BIT(1)) +#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S) +#define SYSTIMER_TARGET1_INT_ST_V 0x00000001 +#define SYSTIMER_TARGET1_INT_ST_S 1 +/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0; + * reg_target2_int_st + */ +#define SYSTIMER_TARGET2_INT_ST (BIT(2)) +#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S) +#define SYSTIMER_TARGET2_INT_ST_V 0x00000001 +#define SYSTIMER_TARGET2_INT_ST_S 2 + +/** SYSTIMER_DATE_REG register + * SYSTIMER_DATE. + */ +#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc) +/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 33579377; + * reg_date + */ +#define SYSTIMER_DATE 0xFFFFFFFF +#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S) +#define SYSTIMER_DATE_V 0xFFFFFFFF +#define SYSTIMER_DATE_S 0 #ifdef __cplusplus } #endif - - - -#endif /*_SOC_SYS_TIMER_REG_H_ */ diff --git a/components/soc/esp32c3/include/soc/systimer_struct.h b/components/soc/esp32c3/include/soc/systimer_struct.h index b029eca80b..af41b1f3e2 100644 --- a/components/soc/esp32c3/include/soc/systimer_struct.h +++ b/components/soc/esp32c3/include/soc/systimer_struct.h @@ -1,251 +1,370 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_SYS_TIMER_STRUCT_H_ -#define _SOC_SYS_TIMER_STRUCT_H_ +/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include #ifdef __cplusplus extern "C" { #endif -typedef volatile struct { +/** Configuration Register */ +/** Type of conf register + * SYSTIMER_CONF. + */ +typedef union { + struct { + /** systimer_clk_fo : R/W; bitpos: [0]; default: 0; + * systimer clock force on + */ + uint32_t systimer_clk_fo: 1; + uint32_t reserved_1: 21; + /** target2_work_en : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ + uint32_t target2_work_en: 1; + /** target1_work_en : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ + uint32_t target1_work_en: 1; + /** target0_work_en : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ + uint32_t target0_work_en: 1; + /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ + uint32_t timer_unit1_core1_stall_en: 1; + /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ + uint32_t timer_unit1_core0_stall_en: 1; + /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ + uint32_t timer_unit0_core1_stall_en: 1; + /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ + uint32_t timer_unit0_core0_stall_en: 1; + /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ + uint32_t timer_unit1_work_en: 1; + /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ + uint32_t timer_unit0_work_en: 1; + /** clk_en : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ + uint32_t clk_en: 1; + }; + uint32_t val; +} systimer_conf_reg_t; + +/** Type of unit_op register + * SYSTIMER_UNIT_OP. + */ +typedef union { + struct { + uint32_t reserved_0: 29; + /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0; + * reg_timer_unit0_value_valid + */ + uint32_t timer_unit_value_valid: 1; + /** timer_unit_update : WT; bitpos: [30]; default: 0; + * update timer_unit0 + */ + uint32_t timer_unit_update: 1; + }; + uint32_t val; +} systimer_unit_op_reg_t; + +/** Type of unit_load register + * SYSTIMER_UNIT_LOAD + */ +typedef struct { union { struct { - uint32_t systimer_clk_fo: 1; /*systimer clock force on*/ - uint32_t reserved1: 21; - uint32_t target2_work_en: 1; /*target2 work enable*/ - uint32_t target1_work_en: 1; /*target1 work enable*/ - uint32_t target0_work_en: 1; /*target0 work enable*/ - uint32_t timer_unit1_core1_stall_en: 1; /*If timer unit1 is stalled when core1 stalled*/ - uint32_t timer_unit1_core0_stall_en: 1; /*If timer unit1 is stalled when core0 stalled*/ - uint32_t timer_unit0_core1_stall_en: 1; /*If timer unit0 is stalled when core1 stalled*/ - uint32_t timer_unit0_core0_stall_en: 1; /*If timer unit0 is stalled when core0 stalled*/ - uint32_t timer_unit1_work_en: 1; /*timer unit1 work enable*/ - uint32_t timer_unit0_work_en: 1; /*timer unit0 work enable*/ - uint32_t clk_en: 1; /*register file clk gating*/ + /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0; + * timer unit load high 32 bit + */ + uint32_t timer_unit_load_hi: 20; }; uint32_t val; - } systimer_conf; + } hi; union { struct { - uint32_t reserved0: 29; - uint32_t timer_unit0_value_valid: 1; - uint32_t timer_unit0_update: 1; /*update timer_unit0*/ - uint32_t reserved31: 1; + /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0; + * timer unit load low 32 bit + */ + uint32_t timer_unit_load_lo: 32; }; uint32_t val; - } systimer_unit0_op; + } lo; +} systimer_unit_load_val_reg_t; + +/** Type of target register + * SYSTIMER_TARGET. + */ +typedef struct { union { struct { - uint32_t reserved0: 29; - uint32_t timer_unit1_value_valid: 1; /*timer value is sync and valid*/ - uint32_t timer_unit1_update: 1; /*update timer unit1*/ - uint32_t reserved31: 1; + /** timer_target_hi : R/W; bitpos: [19:0]; default: 0; + * timer target high 32 bit + */ + uint32_t timer_target_hi: 20; }; uint32_t val; - } systimer_unit1_op; + } hi; union { struct { - uint32_t timer_unit0_load_hi:20; /*timer unit0 load high 32 bit*/ - uint32_t reserved20: 12; + /** timer_target_lo : R/W; bitpos: [31:0]; default: 0; + * timer target low 32 bit + */ + uint32_t timer_target_lo: 32; }; uint32_t val; - } systimer_unit0_load_hi; - uint32_t systimer_unit0_load_lo; /**/ + } lo; +} systimer_target_val_reg_t; + +/** Type of target_conf register + * SYSTIMER_TARGET_CONF. + */ +typedef union { + struct { + /** target_period : R/W; bitpos: [25:0]; default: 0; + * target period + */ + uint32_t target_period: 26; + uint32_t reserved_26: 4; + /** target_period_mode : R/W; bitpos: [30]; default: 0; + * Set target to period mode + */ + uint32_t target_period_mode: 1; + /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ + uint32_t target_timer_unit_sel: 1; + }; + uint32_t val; +} systimer_target_conf_reg_t; + +/** Type of unit_value_hi register + * SYSTIMER_UNIT_VALUE_HI. + */ +typedef struct { union { struct { - uint32_t timer_unit1_load_hi:20; /*timer unit1 load high 32 bit*/ - uint32_t reserved20: 12; + /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bit + */ + uint32_t timer_unit_value_hi: 20; }; uint32_t val; - } systimer_unit1_load_hi; - uint32_t systimer_unit1_load_lo; /**/ + } hi; union { struct { - uint32_t timer_target0_hi:20; /*timer taget0 high 32 bit*/ - uint32_t reserved20: 12; + /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bit + */ + uint32_t timer_unit_value_lo: 32; }; uint32_t val; - } systimer_target0_hi; - uint32_t systimer_target0_lo; /**/ - union { - struct { - uint32_t timer_target1_hi:20; /*timer taget1 high 32 bit*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } systimer_target1_hi; - uint32_t systimer_target1_lo; /**/ - union { - struct { - uint32_t timer_target2_hi:20; /*timer taget2 high 32 bit*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } systimer_target2_hi; - uint32_t systimer_target2_lo; /**/ - union { - struct { - uint32_t target0_period: 26; /*target0 period*/ - uint32_t reserved26: 4; - uint32_t target0_period_mode: 1; /*Set target0 to period mode*/ - uint32_t target0_timer_unit_sel: 1; /*select which unit to compare*/ - }; - uint32_t val; - } systimer_target0_conf; - union { - struct { - uint32_t target1_period: 26; /*target1 period*/ - uint32_t reserved26: 4; - uint32_t target1_period_mode: 1; /*Set target1 to period mode*/ - uint32_t target1_timer_unit_sel: 1; /*select which unit to compare*/ - }; - uint32_t val; - } systimer_target1_conf; - union { - struct { - uint32_t target2_period: 26; /*target2 period*/ - uint32_t reserved26: 4; - uint32_t target2_period_mode: 1; /*Set target2 to period mode*/ - uint32_t target2_timer_unit_sel: 1; /*select which unit to compare*/ - }; - uint32_t val; - } systimer_target2_conf; - union { - struct { - uint32_t timer_unit0_value_hi:20; /*timer read value high 32bit*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } systimer_unit0_value_hi; - uint32_t systimer_unit0_value_lo; /**/ - union { - struct { - uint32_t timer_unit1_value_hi:20; /*timer read value high 32bit*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } systimer_unit1_value_hi; - uint32_t systimer_unit1_value_lo; /**/ - union { - struct { - uint32_t timer_comp0_load: 1; /*timer comp0 load value*/ - uint32_t reserved1: 31; - }; - uint32_t val; - } systimer_comp0_load; - union { - struct { - uint32_t timer_comp1_load: 1; /*timer comp1 load value*/ - uint32_t reserved1: 31; - }; - uint32_t val; - } systimer_comp1_load; - union { - struct { - uint32_t timer_comp2_load: 1; /*timer comp2 load value*/ - uint32_t reserved1: 31; - }; - uint32_t val; - } systimer_comp2_load; - union { - struct { - uint32_t timer_unit0_load: 1; /*timer unit0 load value*/ - uint32_t reserved1: 31; - }; - uint32_t val; - } systimer_unit0_load; - union { - struct { - uint32_t timer_unit1_load: 1; /*timer unit1 load value*/ - uint32_t reserved1: 31; - }; - uint32_t val; - } systimer_unit1_load; - union { - struct { - uint32_t target0: 1; /*interupt0 enable*/ - uint32_t target1: 1; /*interupt1 enable*/ - uint32_t target2: 1; /*interupt2 enable*/ - uint32_t reserved3: 29; - }; - uint32_t val; - } systimer_int_ena; - union { - struct { - uint32_t target0: 1; /*interupt0 raw*/ - uint32_t target1: 1; /*interupt1 raw*/ - uint32_t target2: 1; /*interupt2 raw*/ - uint32_t reserved3: 29; - }; - uint32_t val; - } systimer_int_raw; - union { - struct { - uint32_t target0: 1; /*interupt0 clear*/ - uint32_t target1: 1; /*interupt1 clear*/ - uint32_t target2: 1; /*interupt2 clear*/ - uint32_t reserved3: 29; - }; - uint32_t val; - } systimer_int_clr; - union { - struct { - uint32_t target0: 1; - uint32_t target1: 1; - uint32_t target2: 1; - uint32_t reserved3: 29; - }; - uint32_t val; - } systimer_int_st; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t systimer_date; /**/ -} sys_timer_dev_t; -extern sys_timer_dev_t SYS_TIMER; + } lo; +} systimer_unit_value_reg_t; + +/** Type of comp_load register + * SYSTIMER_COMP_LOAD. + */ +typedef union { + struct { + /** timer_comp_load : WT; bitpos: [0]; default: 0; + * timer comp load value + */ + uint32_t timer_comp_load: 1; + }; + uint32_t val; +} systimer_comp_load_reg_t; + +/** Type of unit_load register + * SYSTIMER_UNIT_LOAD. + */ +typedef union { + struct { + /** timer_unit_load : WT; bitpos: [0]; default: 0; + * timer unit load value + */ + uint32_t timer_unit_load: 1; + }; + uint32_t val; +} systimer_unit_load_reg_t; + +/** Interrupt Register */ +/** Type of int_ena register + * SYSTIMER_INT_ENA. + */ +typedef union { + struct { + /** target0_int_ena : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ + uint32_t target0_int_ena: 1; + /** target1_int_ena : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ + uint32_t target1_int_ena: 1; + /** target2_int_ena : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ + uint32_t target2_int_ena: 1; + }; + uint32_t val; +} systimer_int_ena_reg_t; + +/** Type of int_raw register + * SYSTIMER_INT_RAW. + */ +typedef union { + struct { + /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ + uint32_t target0_int_raw: 1; + /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ + uint32_t target1_int_raw: 1; + /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ + uint32_t target2_int_raw: 1; + }; + uint32_t val; +} systimer_int_raw_reg_t; + +/** Type of int_clr register + * SYSTIMER_INT_CLR. + */ +typedef union { + struct { + /** target0_int_clr : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ + uint32_t target0_int_clr: 1; + /** target1_int_clr : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ + uint32_t target1_int_clr: 1; + /** target2_int_clr : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ + uint32_t target2_int_clr: 1; + }; + uint32_t val; +} systimer_int_clr_reg_t; + +/** Type of int_st register + * SYSTIMER_INT_ST. + */ +typedef union { + struct { + /** target0_int_st : RO; bitpos: [0]; default: 0; + * reg_target0_int_st + */ + uint32_t target0_int_st: 1; + /** target1_int_st : RO; bitpos: [1]; default: 0; + * reg_target1_int_st + */ + uint32_t target1_int_st: 1; + /** target2_int_st : RO; bitpos: [2]; default: 0; + * reg_target2_int_st + */ + uint32_t target2_int_st: 1; + }; + uint32_t val; +} systimer_int_st_reg_t; + + +/** Version Register */ +/** Type of date register + * SYSTIMER_DATE. + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 33579377; + * reg_date + */ + uint32_t date: 32; + }; + uint32_t val; +} systimer_date_reg_t; + + +typedef struct { + volatile systimer_conf_reg_t conf; + volatile systimer_unit_op_reg_t unit_op[2]; + volatile systimer_unit_load_val_reg_t unit_load_val[2]; + volatile systimer_target_val_reg_t target_val[3]; + volatile systimer_target_conf_reg_t target_conf[3]; + volatile systimer_unit_value_reg_t unit_val[2]; + volatile systimer_comp_load_reg_t comp_load[3]; + volatile systimer_unit_load_reg_t unit_load[2]; + volatile systimer_int_ena_reg_t int_ena; + volatile systimer_int_raw_reg_t int_raw; + volatile systimer_int_clr_reg_t int_clr; + volatile systimer_int_st_reg_t int_st; + uint32_t reserved_074; + uint32_t reserved_078; + uint32_t reserved_07c; + uint32_t reserved_080; + uint32_t reserved_084; + uint32_t reserved_088; + uint32_t reserved_08c; + uint32_t reserved_090; + uint32_t reserved_094; + uint32_t reserved_098; + uint32_t reserved_09c; + uint32_t reserved_0a0; + uint32_t reserved_0a4; + uint32_t reserved_0a8; + uint32_t reserved_0ac; + uint32_t reserved_0b0; + uint32_t reserved_0b4; + uint32_t reserved_0b8; + uint32_t reserved_0bc; + uint32_t reserved_0c0; + uint32_t reserved_0c4; + uint32_t reserved_0c8; + uint32_t reserved_0cc; + uint32_t reserved_0d0; + uint32_t reserved_0d4; + uint32_t reserved_0d8; + uint32_t reserved_0dc; + uint32_t reserved_0e0; + uint32_t reserved_0e4; + uint32_t reserved_0e8; + uint32_t reserved_0ec; + uint32_t reserved_0f0; + uint32_t reserved_0f4; + uint32_t reserved_0f8; + volatile systimer_date_reg_t date; +} systimer_dev_t; + +extern systimer_dev_t SYSTIMER; + #ifdef __cplusplus } #endif - -#endif /* _SOC_SYS_TIMER_STRUCT_H_ */ diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index 5d16add7a8..355994d420 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -210,10 +210,9 @@ #define SOC_MEMSPI_IS_INDEPENDENT 1 -/*-------------------------- SYS TIMER CAPS ----------------------------------*/ -#define SOC_SYSTIMER_COUNTER_NUM (1) // Number of counter units -#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units - +/*-------------------------- SYSTIMER CAPS ----------------------------------*/ +#define SOC_SYSTIMER_COUNTER_NUM (1) // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units #define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part #define SOC_SYSTIMER_BIT_WIDTH_HI (32) // Bit width of systimer high part diff --git a/components/soc/esp32s2/include/soc/systimer_reg.h b/components/soc/esp32s2/include/soc/systimer_reg.h index 5debf1148a..ede37127c4 100644 --- a/components/soc/esp32s2/include/soc/systimer_reg.h +++ b/components/soc/esp32s2/include/soc/systimer_reg.h @@ -1,16 +1,17 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ #pragma once #include @@ -38,7 +39,6 @@ extern "C" { #define SYSTIMER_CLK_EN_V 0x00000001 #define SYSTIMER_CLK_EN_S 31 - /** SYSTIMER_LOAD_REG register * load value to system timer */ @@ -51,12 +51,11 @@ extern "C" { #define SYSTIMER_TIMER_LOAD_V 0x00000001 #define SYSTIMER_TIMER_LOAD_S 31 - /** SYSTIMER_LOAD_HI_REG register * High 32-bit load to system timer */ #define SYSTIMER_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x8) -/** SYSTIMER_TIMER_LOAD_HI : R/W; bitpos: [32:0]; default: 0; +/** SYSTIMER_TIMER_LOAD_HI : R/W; bitpos: [31:0]; default: 0; * High 32-bit load to system timer */ #define SYSTIMER_TIMER_LOAD_HI 0xFFFFFFFF @@ -64,12 +63,11 @@ extern "C" { #define SYSTIMER_TIMER_LOAD_HI_V 0xFFFFFFFF #define SYSTIMER_TIMER_LOAD_HI_S 0 - /** SYSTIMER_LOAD_LO_REG register * Low 32-bit load to system timer */ #define SYSTIMER_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0xc) -/** SYSTIMER_TIMER_LOAD_LO : R/W; bitpos: [32:0]; default: 0; +/** SYSTIMER_TIMER_LOAD_LO : R/W; bitpos: [31:0]; default: 0; * Low 32-bit load to system timer */ #define SYSTIMER_TIMER_LOAD_LO 0xFFFFFFFF @@ -77,19 +75,18 @@ extern "C" { #define SYSTIMER_TIMER_LOAD_LO_V 0xFFFFFFFF #define SYSTIMER_TIMER_LOAD_LO_S 0 - /** SYSTIMER_STEP_REG register * system timer accumulation step */ #define SYSTIMER_STEP_REG (DR_REG_SYSTIMER_BASE + 0x10) -/** SYSTIMER_TIMER_XTAL_STEP : R/W; bitpos: [10:0]; default: 80; +/** SYSTIMER_TIMER_XTAL_STEP : R/W; bitpos: [9:0]; default: 80; * system timer accumulation step when using XTAL */ #define SYSTIMER_TIMER_XTAL_STEP 0x000003FF #define SYSTIMER_TIMER_XTAL_STEP_M (SYSTIMER_TIMER_XTAL_STEP_V << SYSTIMER_TIMER_XTAL_STEP_S) #define SYSTIMER_TIMER_XTAL_STEP_V 0x000003FF #define SYSTIMER_TIMER_XTAL_STEP_S 0 -/** SYSTIMER_TIMER_PLL_STEP : R/W; bitpos: [20:10]; default: 1; +/** SYSTIMER_TIMER_PLL_STEP : R/W; bitpos: [19:10]; default: 1; * system timer accumulation step when using PLL */ #define SYSTIMER_TIMER_PLL_STEP 0x000003FF @@ -97,12 +94,11 @@ extern "C" { #define SYSTIMER_TIMER_PLL_STEP_V 0x000003FF #define SYSTIMER_TIMER_PLL_STEP_S 10 - /** SYSTIMER_TARGET0_HI_REG register * System timer target0 high 32-bit */ #define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x14) -/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [32:0]; default: 0; +/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [31:0]; default: 0; * System timer target0 high 32-bit */ #define SYSTIMER_TIMER_TARGET0_HI 0xFFFFFFFF @@ -110,12 +106,11 @@ extern "C" { #define SYSTIMER_TIMER_TARGET0_HI_V 0xFFFFFFFF #define SYSTIMER_TIMER_TARGET0_HI_S 0 - /** SYSTIMER_TARGET0_LO_REG register * System timer target0 low 32-bit */ #define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x18) -/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [32:0]; default: 0; +/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0; * System timer target0 low 32-bit */ #define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFF @@ -123,12 +118,11 @@ extern "C" { #define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF #define SYSTIMER_TIMER_TARGET0_LO_S 0 - /** SYSTIMER_TARGET1_HI_REG register * System timer target1 high 32-bit */ #define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c) -/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [32:0]; default: 0; +/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [31:0]; default: 0; * System timer target1 high 32-bit */ #define SYSTIMER_TIMER_TARGET1_HI 0xFFFFFFFF @@ -136,12 +130,11 @@ extern "C" { #define SYSTIMER_TIMER_TARGET1_HI_V 0xFFFFFFFF #define SYSTIMER_TIMER_TARGET1_HI_S 0 - /** SYSTIMER_TARGET1_LO_REG register * System timer target1 low 32-bit */ #define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x20) -/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [32:0]; default: 0; +/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0; * System timer target1 low 32-bit */ #define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFF @@ -149,12 +142,11 @@ extern "C" { #define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF #define SYSTIMER_TIMER_TARGET1_LO_S 0 - /** SYSTIMER_TARGET2_HI_REG register * System timer target2 high 32-bit */ #define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x24) -/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [32:0]; default: 0; +/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [31:0]; default: 0; * System timer target2 high 32-bit */ #define SYSTIMER_TIMER_TARGET2_HI 0xFFFFFFFF @@ -162,12 +154,11 @@ extern "C" { #define SYSTIMER_TIMER_TARGET2_HI_V 0xFFFFFFFF #define SYSTIMER_TIMER_TARGET2_HI_S 0 - /** SYSTIMER_TARGET2_LO_REG register * System timer target2 low 32-bit */ #define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x28) -/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [32:0]; default: 0; +/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0; * System timer target2 low 32-bit */ #define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFF @@ -175,12 +166,11 @@ extern "C" { #define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF #define SYSTIMER_TIMER_TARGET2_LO_S 0 - /** SYSTIMER_TARGET0_CONF_REG register * Configure system timer target0 work mode */ #define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x2c) -/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [30:0]; default: 0; +/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [29:0]; default: 0; * System timer target0 alarm period */ #define SYSTIMER_TARGET0_PERIOD 0x3FFFFFFF @@ -202,12 +192,11 @@ extern "C" { #define SYSTIMER_TARGET0_WORK_EN_V 0x00000001 #define SYSTIMER_TARGET0_WORK_EN_S 31 - /** SYSTIMER_TARGET1_CONF_REG register * Configure system timer target1 work mode */ #define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x30) -/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [30:0]; default: 0; +/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [29:0]; default: 0; * System timer target1 alarm period */ #define SYSTIMER_TARGET1_PERIOD 0x3FFFFFFF @@ -229,12 +218,11 @@ extern "C" { #define SYSTIMER_TARGET1_WORK_EN_V 0x00000001 #define SYSTIMER_TARGET1_WORK_EN_S 31 - /** SYSTIMER_TARGET2_CONF_REG register * Configure system timer target2 work mode */ #define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34) -/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [30:0]; default: 0; +/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [29:0]; default: 0; * System timer target2 alarm period */ #define SYSTIMER_TARGET2_PERIOD 0x3FFFFFFF @@ -256,7 +244,6 @@ extern "C" { #define SYSTIMER_TARGET2_WORK_EN_V 0x00000001 #define SYSTIMER_TARGET2_WORK_EN_S 31 - /** SYSTIMER_UPDATE_REG register * Read out system timer value */ @@ -276,12 +263,11 @@ extern "C" { #define SYSTIMER_TIMER_UPDATE_V 0x00000001 #define SYSTIMER_TIMER_UPDATE_S 31 - /** SYSTIMER_VALUE_HI_REG register * system timer high 32-bit */ #define SYSTIMER_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x3c) -/** SYSTIMER_TIMER_VALUE_HI : RO; bitpos: [32:0]; default: 0; +/** SYSTIMER_TIMER_VALUE_HI : RO; bitpos: [31:0]; default: 0; * system timer high 32-bit */ #define SYSTIMER_TIMER_VALUE_HI 0xFFFFFFFF @@ -289,12 +275,11 @@ extern "C" { #define SYSTIMER_TIMER_VALUE_HI_V 0xFFFFFFFF #define SYSTIMER_TIMER_VALUE_HI_S 0 - /** SYSTIMER_VALUE_LO_REG register * system timer low 32-bit */ #define SYSTIMER_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x40) -/** SYSTIMER_TIMER_VALUE_LO : RO; bitpos: [32:0]; default: 0; +/** SYSTIMER_TIMER_VALUE_LO : RO; bitpos: [31:0]; default: 0; * system timer low 32-bit */ #define SYSTIMER_TIMER_VALUE_LO 0xFFFFFFFF @@ -302,93 +287,89 @@ extern "C" { #define SYSTIMER_TIMER_VALUE_LO_V 0xFFFFFFFF #define SYSTIMER_TIMER_VALUE_LO_S 0 - /** SYSTIMER_INT_ENA_REG register * system timer interrupt enable */ #define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x44) -/** SYSTIMER_INT0_ENA : R/W; bitpos: [0]; default: 0; +/** SYSTIMER_SYSTIMER_INT0_ENA : R/W; bitpos: [0]; default: 0; * system timer target0 interrupt enable */ -#define SYSTIMER_INT0_ENA (BIT(0)) -#define SYSTIMER_INT0_ENA_M (SYSTIMER_INT0_ENA_V << SYSTIMER_INT0_ENA_S) -#define SYSTIMER_INT0_ENA_V 0x00000001 -#define SYSTIMER_INT0_ENA_S 0 -/** SYSTIMER_INT1_ENA : R/W; bitpos: [1]; default: 0; +#define SYSTIMER_SYSTIMER_INT0_ENA (BIT(0)) +#define SYSTIMER_SYSTIMER_INT0_ENA_M (SYSTIMER_SYSTIMER_INT0_ENA_V << SYSTIMER_SYSTIMER_INT0_ENA_S) +#define SYSTIMER_SYSTIMER_INT0_ENA_V 0x00000001 +#define SYSTIMER_SYSTIMER_INT0_ENA_S 0 +/** SYSTIMER_SYSTIMER_INT1_ENA : R/W; bitpos: [1]; default: 0; * system timer target1 interrupt enable */ -#define SYSTIMER_INT1_ENA (BIT(1)) -#define SYSTIMER_INT1_ENA_M (SYSTIMER_INT1_ENA_V << SYSTIMER_INT1_ENA_S) -#define SYSTIMER_INT1_ENA_V 0x00000001 -#define SYSTIMER_INT1_ENA_S 1 -/** SYSTIMER_INT2_ENA : R/W; bitpos: [2]; default: 0; +#define SYSTIMER_SYSTIMER_INT1_ENA (BIT(1)) +#define SYSTIMER_SYSTIMER_INT1_ENA_M (SYSTIMER_SYSTIMER_INT1_ENA_V << SYSTIMER_SYSTIMER_INT1_ENA_S) +#define SYSTIMER_SYSTIMER_INT1_ENA_V 0x00000001 +#define SYSTIMER_SYSTIMER_INT1_ENA_S 1 +/** SYSTIMER_SYSTIMER_INT2_ENA : R/W; bitpos: [2]; default: 0; * system timer target2 interrupt enable */ -#define SYSTIMER_INT2_ENA (BIT(2)) -#define SYSTIMER_INT2_ENA_M (SYSTIMER_INT2_ENA_V << SYSTIMER_INT2_ENA_S) -#define SYSTIMER_INT2_ENA_V 0x00000001 -#define SYSTIMER_INT2_ENA_S 2 - +#define SYSTIMER_SYSTIMER_INT2_ENA (BIT(2)) +#define SYSTIMER_SYSTIMER_INT2_ENA_M (SYSTIMER_SYSTIMER_INT2_ENA_V << SYSTIMER_SYSTIMER_INT2_ENA_S) +#define SYSTIMER_SYSTIMER_INT2_ENA_V 0x00000001 +#define SYSTIMER_SYSTIMER_INT2_ENA_S 2 /** SYSTIMER_INT_RAW_REG register * system timer interrupt raw */ #define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x48) -/** SYSTIMER_INT0_RAW : RO; bitpos: [0]; default: 0; +/** SYSTIMER_SYSTIMER_INT0_RAW : RO; bitpos: [0]; default: 0; * system timer target0 interrupt raw */ -#define SYSTIMER_INT0_RAW (BIT(0)) -#define SYSTIMER_INT0_RAW_M (SYSTIMER_INT0_RAW_V << SYSTIMER_INT0_RAW_S) -#define SYSTIMER_INT0_RAW_V 0x00000001 -#define SYSTIMER_INT0_RAW_S 0 -/** SYSTIMER_INT1_RAW : RO; bitpos: [1]; default: 0; +#define SYSTIMER_SYSTIMER_INT0_RAW (BIT(0)) +#define SYSTIMER_SYSTIMER_INT0_RAW_M (SYSTIMER_SYSTIMER_INT0_RAW_V << SYSTIMER_SYSTIMER_INT0_RAW_S) +#define SYSTIMER_SYSTIMER_INT0_RAW_V 0x00000001 +#define SYSTIMER_SYSTIMER_INT0_RAW_S 0 +/** SYSTIMER_SYSTIMER_INT1_RAW : RO; bitpos: [1]; default: 0; * system timer target1 interrupt raw */ -#define SYSTIMER_INT1_RAW (BIT(1)) -#define SYSTIMER_INT1_RAW_M (SYSTIMER_INT1_RAW_V << SYSTIMER_INT1_RAW_S) -#define SYSTIMER_INT1_RAW_V 0x00000001 -#define SYSTIMER_INT1_RAW_S 1 -/** SYSTIMER_INT2_RAW : RO; bitpos: [2]; default: 0; +#define SYSTIMER_SYSTIMER_INT1_RAW (BIT(1)) +#define SYSTIMER_SYSTIMER_INT1_RAW_M (SYSTIMER_SYSTIMER_INT1_RAW_V << SYSTIMER_SYSTIMER_INT1_RAW_S) +#define SYSTIMER_SYSTIMER_INT1_RAW_V 0x00000001 +#define SYSTIMER_SYSTIMER_INT1_RAW_S 1 +/** SYSTIMER_SYSTIMER_INT2_RAW : RO; bitpos: [2]; default: 0; * system timer target2 interrupt raw */ -#define SYSTIMER_INT2_RAW (BIT(2)) -#define SYSTIMER_INT2_RAW_M (SYSTIMER_INT2_RAW_V << SYSTIMER_INT2_RAW_S) -#define SYSTIMER_INT2_RAW_V 0x00000001 -#define SYSTIMER_INT2_RAW_S 2 - +#define SYSTIMER_SYSTIMER_INT2_RAW (BIT(2)) +#define SYSTIMER_SYSTIMER_INT2_RAW_M (SYSTIMER_SYSTIMER_INT2_RAW_V << SYSTIMER_SYSTIMER_INT2_RAW_S) +#define SYSTIMER_SYSTIMER_INT2_RAW_V 0x00000001 +#define SYSTIMER_SYSTIMER_INT2_RAW_S 2 /** SYSTIMER_INT_CLR_REG register * system timer interrupt clear */ #define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x4c) -/** SYSTIMER_INT0_CLR : WO; bitpos: [0]; default: 0; +/** SYSTIMER_SYSTIMER_INT0_CLR : WO; bitpos: [0]; default: 0; * system timer target0 interrupt clear */ -#define SYSTIMER_INT0_CLR (BIT(0)) -#define SYSTIMER_INT0_CLR_M (SYSTIMER_INT0_CLR_V << SYSTIMER_INT0_CLR_S) -#define SYSTIMER_INT0_CLR_V 0x00000001 -#define SYSTIMER_INT0_CLR_S 0 -/** SYSTIMER_INT1_CLR : WO; bitpos: [1]; default: 0; +#define SYSTIMER_SYSTIMER_INT0_CLR (BIT(0)) +#define SYSTIMER_SYSTIMER_INT0_CLR_M (SYSTIMER_SYSTIMER_INT0_CLR_V << SYSTIMER_SYSTIMER_INT0_CLR_S) +#define SYSTIMER_SYSTIMER_INT0_CLR_V 0x00000001 +#define SYSTIMER_SYSTIMER_INT0_CLR_S 0 +/** SYSTIMER_SYSTIMER_INT1_CLR : WO; bitpos: [1]; default: 0; * system timer target1 interrupt clear */ -#define SYSTIMER_INT1_CLR (BIT(1)) -#define SYSTIMER_INT1_CLR_M (SYSTIMER_INT1_CLR_V << SYSTIMER_INT1_CLR_S) -#define SYSTIMER_INT1_CLR_V 0x00000001 -#define SYSTIMER_INT1_CLR_S 1 -/** SYSTIMER_INT2_CLR : WO; bitpos: [2]; default: 0; +#define SYSTIMER_SYSTIMER_INT1_CLR (BIT(1)) +#define SYSTIMER_SYSTIMER_INT1_CLR_M (SYSTIMER_SYSTIMER_INT1_CLR_V << SYSTIMER_SYSTIMER_INT1_CLR_S) +#define SYSTIMER_SYSTIMER_INT1_CLR_V 0x00000001 +#define SYSTIMER_SYSTIMER_INT1_CLR_S 1 +/** SYSTIMER_SYSTIMER_INT2_CLR : WO; bitpos: [2]; default: 0; * system timer target2 interrupt clear */ -#define SYSTIMER_INT2_CLR (BIT(2)) -#define SYSTIMER_INT2_CLR_M (SYSTIMER_INT2_CLR_V << SYSTIMER_INT2_CLR_S) -#define SYSTIMER_INT2_CLR_V 0x00000001 -#define SYSTIMER_INT2_CLR_S 2 - +#define SYSTIMER_SYSTIMER_INT2_CLR (BIT(2)) +#define SYSTIMER_SYSTIMER_INT2_CLR_M (SYSTIMER_SYSTIMER_INT2_CLR_V << SYSTIMER_SYSTIMER_INT2_CLR_S) +#define SYSTIMER_SYSTIMER_INT2_CLR_V 0x00000001 +#define SYSTIMER_SYSTIMER_INT2_CLR_S 2 /** SYSTIMER_DATE_REG register * system timer register version */ #define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc) -/** SYSTIMER_DATE : R/W; bitpos: [32:0]; default: 25194848; +/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 25194848; * system timer register version */ #define SYSTIMER_DATE 0xFFFFFFFF @@ -396,7 +377,6 @@ extern "C" { #define SYSTIMER_DATE_V 0xFFFFFFFF #define SYSTIMER_DATE_S 0 - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s2/include/soc/systimer_struct.h b/components/soc/esp32s2/include/soc/systimer_struct.h new file mode 100644 index 0000000000..48b1d79276 --- /dev/null +++ b/components/soc/esp32s2/include/soc/systimer_struct.h @@ -0,0 +1,330 @@ +/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** SYSTEM TIMER REGISTER */ +/** Type of conf register + * Configure system timer clock + */ +typedef union { + struct { + /** clk_fo : R/W; bitpos: [0]; default: 0; + * system timer force clock enable + */ + uint32_t clk_fo: 1; + uint32_t reserved_1: 30; + /** clk_en : R/W; bitpos: [31]; default: 0; + * register clock enable + */ + uint32_t clk_en: 1; + }; + uint32_t val; +} systimer_conf_reg_t; + +/** Type of load register + * load value to system timer + */ +typedef union { + struct { + uint32_t reserved_0: 31; + /** timer_load : WO; bitpos: [31]; default: 0; + * load value to system timer + */ + uint32_t timer_load: 1; + }; + uint32_t val; +} systimer_load_reg_t; + +/** Type of load_hi register + * High 32-bit load to system timer + */ +typedef union { + struct { + /** timer_load_hi : R/W; bitpos: [31:0]; default: 0; + * High 32-bit load to system timer + */ + uint32_t timer_load_hi: 32; + }; + uint32_t val; +} systimer_load_hi_reg_t; + +/** Type of load_lo register + * Low 32-bit load to system timer + */ +typedef union { + struct { + /** timer_load_lo : R/W; bitpos: [31:0]; default: 0; + * Low 32-bit load to system timer + */ + uint32_t timer_load_lo: 32; + }; + uint32_t val; +} systimer_load_lo_reg_t; + +/** Type of step register + * system timer accumulation step + */ +typedef union { + struct { + /** timer_xtal_step : R/W; bitpos: [9:0]; default: 80; + * system timer accumulation step when using XTAL + */ + uint32_t timer_xtal_step: 10; + /** timer_pll_step : R/W; bitpos: [19:10]; default: 1; + * system timer accumulation step when using PLL + */ + uint32_t timer_pll_step: 10; + }; + uint32_t val; +} systimer_step_reg_t; + +/** Type of target_val register + * System timer target value + */ +typedef struct { + union { + struct { + /** timer_target_hi : R/W; bitpos: [31:0]; default: 0; + * System timer target0 high 32-bit + */ + uint32_t timer_target_hi: 32; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_target_lo : R/W; bitpos: [31:0]; default: 0; + * System timer target0 low 32-bit + */ + uint32_t timer_target_lo: 32; + }; + uint32_t val; + } lo; +} systimer_target_val_reg_t; + +/** Type of target_conf register + * Configure system timer target work mode + */ +typedef union { + struct { + /** target_period : R/W; bitpos: [29:0]; default: 0; + * System timer target alarm period + */ + uint32_t target_period: 30; + /** target_period_mode : R/W; bitpos: [30]; default: 0; + * Whether system timer target work in period mode + */ + uint32_t target_period_mode: 1; + /** target_work_en : R/W; bitpos: [31]; default: 0; + * system timer target work enable + */ + uint32_t target_work_en: 1; + }; + uint32_t val; +} systimer_target_conf_reg_t; + +/** Type of update register + * Read out system timer value + */ +typedef union { + struct { + uint32_t reserved_0: 30; + /** timer_value_valid : RO; bitpos: [30]; default: 0; + * If it is valid to read out timer value from register + */ + uint32_t timer_value_valid: 1; + /** timer_update : WO; bitpos: [31]; default: 0; + * Update system timer value to register + */ + uint32_t timer_update: 1; + }; + uint32_t val; +} systimer_update_reg_t; + +/** Type of value_hi register + * system timer high 32-bit + */ +typedef union { + struct { + /** timer_value_hi : RO; bitpos: [31:0]; default: 0; + * system timer high 32-bit + */ + uint32_t timer_value_hi: 32; + }; + uint32_t val; +} systimer_value_hi_reg_t; + +/** Type of value_lo register + * system timer low 32-bit + */ +typedef union { + struct { + /** timer_value_lo : RO; bitpos: [31:0]; default: 0; + * system timer low 32-bit + */ + uint32_t timer_value_lo: 32; + }; + uint32_t val; +} systimer_value_lo_reg_t; + +/** Type of int_ena register + * system timer interrupt enable + */ +typedef union { + struct { + /** systimer_int0_ena : R/W; bitpos: [0]; default: 0; + * system timer target0 interrupt enable + */ + uint32_t systimer_int0_ena: 1; + /** systimer_int1_ena : R/W; bitpos: [1]; default: 0; + * system timer target1 interrupt enable + */ + uint32_t systimer_int1_ena: 1; + /** systimer_int2_ena : R/W; bitpos: [2]; default: 0; + * system timer target2 interrupt enable + */ + uint32_t systimer_int2_ena: 1; + }; + uint32_t val; +} systimer_int_ena_reg_t; + +/** Type of int_raw register + * system timer interrupt raw + */ +typedef union { + struct { + /** systimer_int0_raw : RO; bitpos: [0]; default: 0; + * system timer target0 interrupt raw + */ + uint32_t systimer_int0_raw: 1; + /** systimer_int1_raw : RO; bitpos: [1]; default: 0; + * system timer target1 interrupt raw + */ + uint32_t systimer_int1_raw: 1; + /** systimer_int2_raw : RO; bitpos: [2]; default: 0; + * system timer target2 interrupt raw + */ + uint32_t systimer_int2_raw: 1; + }; + uint32_t val; +} systimer_int_raw_reg_t; + +/** Type of int_clr register + * system timer interrupt clear + */ +typedef union { + struct { + /** systimer_int0_clr : WO; bitpos: [0]; default: 0; + * system timer target0 interrupt clear + */ + uint32_t systimer_int0_clr: 1; + /** systimer_int1_clr : WO; bitpos: [1]; default: 0; + * system timer target1 interrupt clear + */ + uint32_t systimer_int1_clr: 1; + /** systimer_int2_clr : WO; bitpos: [2]; default: 0; + * system timer target2 interrupt clear + */ + uint32_t systimer_int2_clr: 1; + }; + uint32_t val; +} systimer_int_clr_reg_t; + + +/** DATE */ +/** Type of date register + * system timer register version + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 25194848; + * system timer register version + */ + uint32_t date: 32; + }; + uint32_t val; +} systimer_date_reg_t; + + +typedef struct { + volatile systimer_conf_reg_t conf; + volatile systimer_load_reg_t load; + volatile systimer_load_hi_reg_t load_hi; + volatile systimer_load_lo_reg_t load_lo; + volatile systimer_step_reg_t step; + volatile systimer_target_val_reg_t target_val[3]; + volatile systimer_target_conf_reg_t target_conf[3]; + volatile systimer_update_reg_t update; + volatile systimer_value_hi_reg_t value_hi; + volatile systimer_value_lo_reg_t value_lo; + volatile systimer_int_ena_reg_t int_ena; + volatile systimer_int_raw_reg_t int_raw; + volatile systimer_int_clr_reg_t int_clr; + uint32_t reserved_050; + uint32_t reserved_054; + uint32_t reserved_058; + uint32_t reserved_05c; + uint32_t reserved_060; + uint32_t reserved_064; + uint32_t reserved_068; + uint32_t reserved_06c; + uint32_t reserved_070; + uint32_t reserved_074; + uint32_t reserved_078; + uint32_t reserved_07c; + uint32_t reserved_080; + uint32_t reserved_084; + uint32_t reserved_088; + uint32_t reserved_08c; + uint32_t reserved_090; + uint32_t reserved_094; + uint32_t reserved_098; + uint32_t reserved_09c; + uint32_t reserved_0a0; + uint32_t reserved_0a4; + uint32_t reserved_0a8; + uint32_t reserved_0ac; + uint32_t reserved_0b0; + uint32_t reserved_0b4; + uint32_t reserved_0b8; + uint32_t reserved_0bc; + uint32_t reserved_0c0; + uint32_t reserved_0c4; + uint32_t reserved_0c8; + uint32_t reserved_0cc; + uint32_t reserved_0d0; + uint32_t reserved_0d4; + uint32_t reserved_0d8; + uint32_t reserved_0dc; + uint32_t reserved_0e0; + uint32_t reserved_0e4; + uint32_t reserved_0e8; + uint32_t reserved_0ec; + uint32_t reserved_0f0; + uint32_t reserved_0f4; + uint32_t reserved_0f8; + volatile systimer_date_reg_t date; +} systimer_dev_t; + +extern systimer_dev_t SYSTIMER; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index 2583b13130..27568c92d2 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -77,7 +77,7 @@ #define DR_REG_TIMERGROUP0_BASE 0x6001F000 #define DR_REG_TIMERGROUP1_BASE 0x60020000 #define DR_REG_RTC_SLOWMEM_BASE 0x60021000 -#define DR_REG_SYS_TIMER_BASE 0x60023000 +#define DR_REG_SYSTIMER_BASE 0x60023000 #define DR_REG_SPI2_BASE 0x60024000 #define DR_REG_SPI3_BASE 0x60025000 #define DR_REG_SYSCON_BASE 0x60026000 diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index ba177fa275..659b51505a 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -103,7 +103,13 @@ #define SOC_SPIRAM_SUPPORTED 1 /*-------------------------- SYS TIMER CAPS ----------------------------------*/ -#include "systimer_caps.h" +#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units +#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part +#define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed +#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level +#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current) /*-------------------------- TIMER GROUP CAPS --------------------------------*/ #define SOC_TIMER_GROUPS (2) diff --git a/components/soc/esp32s3/include/soc/sys_timer_reg.h b/components/soc/esp32s3/include/soc/sys_timer_reg.h deleted file mode 100644 index 55c1802312..0000000000 --- a/components/soc/esp32s3/include/soc/sys_timer_reg.h +++ /dev/null @@ -1,474 +0,0 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_SYS_TIMER_REG_H_ -#define _SOC_SYS_TIMER_REG_H_ - - -#ifdef __cplusplus -extern "C" { -#endif -#include "soc.h" - -#define SYS_TIMER_SYSTIMER_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0) -/* SYS_TIMER_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: register file clk gating.*/ -#define SYS_TIMER_CLK_EN (BIT(31)) -#define SYS_TIMER_CLK_EN_M (BIT(31)) -#define SYS_TIMER_CLK_EN_V 0x1 -#define SYS_TIMER_CLK_EN_S 31 -/* SYS_TIMER_TIMER_UNIT0_WORK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: timer unit0 work enable.*/ -#define SYS_TIMER_TIMER_UNIT0_WORK_EN (BIT(30)) -#define SYS_TIMER_TIMER_UNIT0_WORK_EN_M (BIT(30)) -#define SYS_TIMER_TIMER_UNIT0_WORK_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_WORK_EN_S 30 -/* SYS_TIMER_TIMER_UNIT1_WORK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: timer unit1 work enable.*/ -#define SYS_TIMER_TIMER_UNIT1_WORK_EN (BIT(29)) -#define SYS_TIMER_TIMER_UNIT1_WORK_EN_M (BIT(29)) -#define SYS_TIMER_TIMER_UNIT1_WORK_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_WORK_EN_S 29 -/* SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: If timer unit0 is stalled when core0 stalled.*/ -#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) -#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_M (BIT(28)) -#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 -/* SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: If timer unit0 is stalled when core1 stalled.*/ -#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) -#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_M (BIT(27)) -#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 -/* SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W ;bitpos:[26] ;default: 1'b1 ; */ -/*description: If timer unit1 is stalled when core0 stalled.*/ -#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) -#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_M (BIT(26)) -#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 -/* SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */ -/*description: If timer unit1 is stalled when core1 stalled.*/ -#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) -#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_M (BIT(25)) -#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 -/* SYS_TIMER_TARGET0_WORK_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: target0 work enable.*/ -#define SYS_TIMER_TARGET0_WORK_EN (BIT(24)) -#define SYS_TIMER_TARGET0_WORK_EN_M (BIT(24)) -#define SYS_TIMER_TARGET0_WORK_EN_V 0x1 -#define SYS_TIMER_TARGET0_WORK_EN_S 24 -/* SYS_TIMER_TARGET1_WORK_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: target1 work enable.*/ -#define SYS_TIMER_TARGET1_WORK_EN (BIT(23)) -#define SYS_TIMER_TARGET1_WORK_EN_M (BIT(23)) -#define SYS_TIMER_TARGET1_WORK_EN_V 0x1 -#define SYS_TIMER_TARGET1_WORK_EN_S 23 -/* SYS_TIMER_TARGET2_WORK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: target2 work enable.*/ -#define SYS_TIMER_TARGET2_WORK_EN (BIT(22)) -#define SYS_TIMER_TARGET2_WORK_EN_M (BIT(22)) -#define SYS_TIMER_TARGET2_WORK_EN_V 0x1 -#define SYS_TIMER_TARGET2_WORK_EN_S 22 -/* SYS_TIMER_SYSTIMER_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: systimer clock force on.*/ -#define SYS_TIMER_SYSTIMER_CLK_FO (BIT(0)) -#define SYS_TIMER_SYSTIMER_CLK_FO_M (BIT(0)) -#define SYS_TIMER_SYSTIMER_CLK_FO_V 0x1 -#define SYS_TIMER_SYSTIMER_CLK_FO_S 0 - -#define SYS_TIMER_SYSTIMER_UNIT0_OP_REG (DR_REG_SYS_TIMER_BASE + 0x4) -/* SYS_TIMER_TIMER_UNIT0_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */ -/*description: update timer_unit0.*/ -#define SYS_TIMER_TIMER_UNIT0_UPDATE (BIT(30)) -#define SYS_TIMER_TIMER_UNIT0_UPDATE_M (BIT(30)) -#define SYS_TIMER_TIMER_UNIT0_UPDATE_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_UPDATE_S 30 -/* SYS_TIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) -#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_M (BIT(29)) -#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_S 29 - -#define SYS_TIMER_SYSTIMER_UNIT1_OP_REG (DR_REG_SYS_TIMER_BASE + 0x8) -/* SYS_TIMER_TIMER_UNIT1_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */ -/*description: update timer unit1.*/ -#define SYS_TIMER_TIMER_UNIT1_UPDATE (BIT(30)) -#define SYS_TIMER_TIMER_UNIT1_UPDATE_M (BIT(30)) -#define SYS_TIMER_TIMER_UNIT1_UPDATE_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_UPDATE_S 30 -/* SYS_TIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */ -/*description: timer value is sync and valid.*/ -#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) -#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_M (BIT(29)) -#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_S 29 - -#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0xC) -/* SYS_TIMER_TIMER_UNIT0_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer unit0 load high 32 bit.*/ -#define SYS_TIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF -#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT0_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_HI_S)) -#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_S 0 - -#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x10) -/* SYS_TIMER_TIMER_UNIT0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer unit0 load low 32 bit.*/ -#define SYS_TIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT0_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_LO_S)) -#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_S 0 - -#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x14) -/* SYS_TIMER_TIMER_UNIT1_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer unit1 load high 32 bit.*/ -#define SYS_TIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF -#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT1_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_HI_S)) -#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_S 0 - -#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x18) -/* SYS_TIMER_TIMER_UNIT1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer unit1 load low 32 bit.*/ -#define SYS_TIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT1_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_LO_S)) -#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_S 0 - -#define SYS_TIMER_SYSTIMER_TARGET0_HI_REG (DR_REG_SYS_TIMER_BASE + 0x1C) -/* SYS_TIMER_TIMER_TARGET0_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer taget0 high 32 bit.*/ -#define SYS_TIMER_TIMER_TARGET0_HI 0x000FFFFF -#define SYS_TIMER_TIMER_TARGET0_HI_M ((SYS_TIMER_TIMER_TARGET0_HI_V)<<(SYS_TIMER_TIMER_TARGET0_HI_S)) -#define SYS_TIMER_TIMER_TARGET0_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_TARGET0_HI_S 0 - -#define SYS_TIMER_SYSTIMER_TARGET0_LO_REG (DR_REG_SYS_TIMER_BASE + 0x20) -/* SYS_TIMER_TIMER_TARGET0_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer taget0 low 32 bit.*/ -#define SYS_TIMER_TIMER_TARGET0_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET0_LO_M ((SYS_TIMER_TIMER_TARGET0_LO_V)<<(SYS_TIMER_TIMER_TARGET0_LO_S)) -#define SYS_TIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET0_LO_S 0 - -#define SYS_TIMER_SYSTIMER_TARGET1_HI_REG (DR_REG_SYS_TIMER_BASE + 0x24) -/* SYS_TIMER_TIMER_TARGET1_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer taget1 high 32 bit.*/ -#define SYS_TIMER_TIMER_TARGET1_HI 0x000FFFFF -#define SYS_TIMER_TIMER_TARGET1_HI_M ((SYS_TIMER_TIMER_TARGET1_HI_V)<<(SYS_TIMER_TIMER_TARGET1_HI_S)) -#define SYS_TIMER_TIMER_TARGET1_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_TARGET1_HI_S 0 - -#define SYS_TIMER_SYSTIMER_TARGET1_LO_REG (DR_REG_SYS_TIMER_BASE + 0x28) -/* SYS_TIMER_TIMER_TARGET1_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer taget1 low 32 bit.*/ -#define SYS_TIMER_TIMER_TARGET1_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET1_LO_M ((SYS_TIMER_TIMER_TARGET1_LO_V)<<(SYS_TIMER_TIMER_TARGET1_LO_S)) -#define SYS_TIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET1_LO_S 0 - -#define SYS_TIMER_SYSTIMER_TARGET2_HI_REG (DR_REG_SYS_TIMER_BASE + 0x2C) -/* SYS_TIMER_TIMER_TARGET2_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer taget2 high 32 bit.*/ -#define SYS_TIMER_TIMER_TARGET2_HI 0x000FFFFF -#define SYS_TIMER_TIMER_TARGET2_HI_M ((SYS_TIMER_TIMER_TARGET2_HI_V)<<(SYS_TIMER_TIMER_TARGET2_HI_S)) -#define SYS_TIMER_TIMER_TARGET2_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_TARGET2_HI_S 0 - -#define SYS_TIMER_SYSTIMER_TARGET2_LO_REG (DR_REG_SYS_TIMER_BASE + 0x30) -/* SYS_TIMER_TIMER_TARGET2_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer taget2 low 32 bit.*/ -#define SYS_TIMER_TIMER_TARGET2_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET2_LO_M ((SYS_TIMER_TIMER_TARGET2_LO_V)<<(SYS_TIMER_TIMER_TARGET2_LO_S)) -#define SYS_TIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET2_LO_S 0 - -#define SYS_TIMER_SYSTIMER_TARGET0_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x34) -/* SYS_TIMER_TARGET0_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: select which unit to compare.*/ -#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) -#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_M (BIT(31)) -#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_V 0x1 -#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_S 31 -/* SYS_TIMER_TARGET0_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set target0 to period mode.*/ -#define SYS_TIMER_TARGET0_PERIOD_MODE (BIT(30)) -#define SYS_TIMER_TARGET0_PERIOD_MODE_M (BIT(30)) -#define SYS_TIMER_TARGET0_PERIOD_MODE_V 0x1 -#define SYS_TIMER_TARGET0_PERIOD_MODE_S 30 -/* SYS_TIMER_TARGET0_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: target0 period.*/ -#define SYS_TIMER_TARGET0_PERIOD 0x03FFFFFF -#define SYS_TIMER_TARGET0_PERIOD_M ((SYS_TIMER_TARGET0_PERIOD_V)<<(SYS_TIMER_TARGET0_PERIOD_S)) -#define SYS_TIMER_TARGET0_PERIOD_V 0x3FFFFFF -#define SYS_TIMER_TARGET0_PERIOD_S 0 - -#define SYS_TIMER_SYSTIMER_TARGET1_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x38) -/* SYS_TIMER_TARGET1_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: select which unit to compare.*/ -#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) -#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_M (BIT(31)) -#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_V 0x1 -#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_S 31 -/* SYS_TIMER_TARGET1_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set target1 to period mode.*/ -#define SYS_TIMER_TARGET1_PERIOD_MODE (BIT(30)) -#define SYS_TIMER_TARGET1_PERIOD_MODE_M (BIT(30)) -#define SYS_TIMER_TARGET1_PERIOD_MODE_V 0x1 -#define SYS_TIMER_TARGET1_PERIOD_MODE_S 30 -/* SYS_TIMER_TARGET1_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: target1 period.*/ -#define SYS_TIMER_TARGET1_PERIOD 0x03FFFFFF -#define SYS_TIMER_TARGET1_PERIOD_M ((SYS_TIMER_TARGET1_PERIOD_V)<<(SYS_TIMER_TARGET1_PERIOD_S)) -#define SYS_TIMER_TARGET1_PERIOD_V 0x3FFFFFF -#define SYS_TIMER_TARGET1_PERIOD_S 0 - -#define SYS_TIMER_SYSTIMER_TARGET2_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x3C) -/* SYS_TIMER_TARGET2_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: select which unit to compare.*/ -#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) -#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_M (BIT(31)) -#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_V 0x1 -#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_S 31 -/* SYS_TIMER_TARGET2_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set target2 to period mode.*/ -#define SYS_TIMER_TARGET2_PERIOD_MODE (BIT(30)) -#define SYS_TIMER_TARGET2_PERIOD_MODE_M (BIT(30)) -#define SYS_TIMER_TARGET2_PERIOD_MODE_V 0x1 -#define SYS_TIMER_TARGET2_PERIOD_MODE_S 30 -/* SYS_TIMER_TARGET2_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: target2 period.*/ -#define SYS_TIMER_TARGET2_PERIOD 0x03FFFFFF -#define SYS_TIMER_TARGET2_PERIOD_M ((SYS_TIMER_TARGET2_PERIOD_V)<<(SYS_TIMER_TARGET2_PERIOD_S)) -#define SYS_TIMER_TARGET2_PERIOD_V 0x3FFFFFF -#define SYS_TIMER_TARGET2_PERIOD_S 0 - -#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x40) -/* SYS_TIMER_TIMER_UNIT0_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer read value high 32bit.*/ -#define SYS_TIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF -#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT0_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_HI_S)) -#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_S 0 - -#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x44) -/* SYS_TIMER_TIMER_UNIT0_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer read value low 32bit.*/ -#define SYS_TIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT0_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_LO_S)) -#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_S 0 - -#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x48) -/* SYS_TIMER_TIMER_UNIT1_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer read value high 32bit.*/ -#define SYS_TIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF -#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT1_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_HI_S)) -#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_S 0 - -#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x4C) -/* SYS_TIMER_TIMER_UNIT1_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer read value low 32bit.*/ -#define SYS_TIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT1_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_LO_S)) -#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_S 0 - -#define SYS_TIMER_SYSTIMER_COMP0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x50) -/* SYS_TIMER_TIMER_COMP0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer comp0 load value.*/ -#define SYS_TIMER_TIMER_COMP0_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_COMP0_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_COMP0_LOAD_V 0x1 -#define SYS_TIMER_TIMER_COMP0_LOAD_S 0 - -#define SYS_TIMER_SYSTIMER_COMP1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x54) -/* SYS_TIMER_TIMER_COMP1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer comp1 load value.*/ -#define SYS_TIMER_TIMER_COMP1_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_COMP1_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_COMP1_LOAD_V 0x1 -#define SYS_TIMER_TIMER_COMP1_LOAD_S 0 - -#define SYS_TIMER_SYSTIMER_COMP2_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x58) -/* SYS_TIMER_TIMER_COMP2_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer comp2 load value.*/ -#define SYS_TIMER_TIMER_COMP2_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_COMP2_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_COMP2_LOAD_V 0x1 -#define SYS_TIMER_TIMER_COMP2_LOAD_S 0 - -#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x5C) -/* SYS_TIMER_TIMER_UNIT0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer unit0 load value.*/ -#define SYS_TIMER_TIMER_UNIT0_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_UNIT0_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_UNIT0_LOAD_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_LOAD_S 0 - -#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x60) -/* SYS_TIMER_TIMER_UNIT1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer unit1 load value.*/ -#define SYS_TIMER_TIMER_UNIT1_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_UNIT1_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_UNIT1_LOAD_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_LOAD_S 0 - -#define SYS_TIMER_SYSTIMER_INT_ENA_REG (DR_REG_SYS_TIMER_BASE + 0x64) -/* SYS_TIMER_TARGET2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: interupt2 enable.*/ -#define SYS_TIMER_TARGET2_INT_ENA (BIT(2)) -#define SYS_TIMER_TARGET2_INT_ENA_M (BIT(2)) -#define SYS_TIMER_TARGET2_INT_ENA_V 0x1 -#define SYS_TIMER_TARGET2_INT_ENA_S 2 -/* SYS_TIMER_TARGET1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: interupt1 enable.*/ -#define SYS_TIMER_TARGET1_INT_ENA (BIT(1)) -#define SYS_TIMER_TARGET1_INT_ENA_M (BIT(1)) -#define SYS_TIMER_TARGET1_INT_ENA_V 0x1 -#define SYS_TIMER_TARGET1_INT_ENA_S 1 -/* SYS_TIMER_TARGET0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: interupt0 enable.*/ -#define SYS_TIMER_TARGET0_INT_ENA (BIT(0)) -#define SYS_TIMER_TARGET0_INT_ENA_M (BIT(0)) -#define SYS_TIMER_TARGET0_INT_ENA_V 0x1 -#define SYS_TIMER_TARGET0_INT_ENA_S 0 - -#define SYS_TIMER_SYSTIMER_INT_RAW_REG (DR_REG_SYS_TIMER_BASE + 0x68) -/* SYS_TIMER_TARGET2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: interupt2 raw.*/ -#define SYS_TIMER_TARGET2_INT_RAW (BIT(2)) -#define SYS_TIMER_TARGET2_INT_RAW_M (BIT(2)) -#define SYS_TIMER_TARGET2_INT_RAW_V 0x1 -#define SYS_TIMER_TARGET2_INT_RAW_S 2 -/* SYS_TIMER_TARGET1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: interupt1 raw.*/ -#define SYS_TIMER_TARGET1_INT_RAW (BIT(1)) -#define SYS_TIMER_TARGET1_INT_RAW_M (BIT(1)) -#define SYS_TIMER_TARGET1_INT_RAW_V 0x1 -#define SYS_TIMER_TARGET1_INT_RAW_S 1 -/* SYS_TIMER_TARGET0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: interupt0 raw.*/ -#define SYS_TIMER_TARGET0_INT_RAW (BIT(0)) -#define SYS_TIMER_TARGET0_INT_RAW_M (BIT(0)) -#define SYS_TIMER_TARGET0_INT_RAW_V 0x1 -#define SYS_TIMER_TARGET0_INT_RAW_S 0 - -#define SYS_TIMER_SYSTIMER_INT_CLR_REG (DR_REG_SYS_TIMER_BASE + 0x6C) -/* SYS_TIMER_TARGET2_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: interupt2 clear.*/ -#define SYS_TIMER_TARGET2_INT_CLR (BIT(2)) -#define SYS_TIMER_TARGET2_INT_CLR_M (BIT(2)) -#define SYS_TIMER_TARGET2_INT_CLR_V 0x1 -#define SYS_TIMER_TARGET2_INT_CLR_S 2 -/* SYS_TIMER_TARGET1_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: interupt1 clear.*/ -#define SYS_TIMER_TARGET1_INT_CLR (BIT(1)) -#define SYS_TIMER_TARGET1_INT_CLR_M (BIT(1)) -#define SYS_TIMER_TARGET1_INT_CLR_V 0x1 -#define SYS_TIMER_TARGET1_INT_CLR_S 1 -/* SYS_TIMER_TARGET0_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: interupt0 clear.*/ -#define SYS_TIMER_TARGET0_INT_CLR (BIT(0)) -#define SYS_TIMER_TARGET0_INT_CLR_M (BIT(0)) -#define SYS_TIMER_TARGET0_INT_CLR_V 0x1 -#define SYS_TIMER_TARGET0_INT_CLR_S 0 - -#define SYS_TIMER_SYSTIMER_INT_ST_REG (DR_REG_SYS_TIMER_BASE + 0x70) -/* SYS_TIMER_TARGET2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_TIMER_TARGET2_INT_ST (BIT(2)) -#define SYS_TIMER_TARGET2_INT_ST_M (BIT(2)) -#define SYS_TIMER_TARGET2_INT_ST_V 0x1 -#define SYS_TIMER_TARGET2_INT_ST_S 2 -/* SYS_TIMER_TARGET1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_TIMER_TARGET1_INT_ST (BIT(1)) -#define SYS_TIMER_TARGET1_INT_ST_M (BIT(1)) -#define SYS_TIMER_TARGET1_INT_ST_V 0x1 -#define SYS_TIMER_TARGET1_INT_ST_S 1 -/* SYS_TIMER_TARGET0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_TIMER_TARGET0_INT_ST (BIT(0)) -#define SYS_TIMER_TARGET0_INT_ST_M (BIT(0)) -#define SYS_TIMER_TARGET0_INT_ST_V 0x1 -#define SYS_TIMER_TARGET0_INT_ST_S 0 - -#define SYS_TIMER_SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYS_TIMER_BASE + 0x74) -/* SYS_TIMER_TARGET0_LO_RO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: .*/ -#define SYS_TIMER_TARGET0_LO_RO 0xFFFFFFFF -#define SYS_TIMER_TARGET0_LO_RO_M ((SYS_TIMER_TARGET0_LO_RO_V)<<(SYS_TIMER_TARGET0_LO_RO_S)) -#define SYS_TIMER_TARGET0_LO_RO_V 0xFFFFFFFF -#define SYS_TIMER_TARGET0_LO_RO_S 0 - -#define SYS_TIMER_SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYS_TIMER_BASE + 0x78) -/* SYS_TIMER_TARGET0_HI_RO : RO ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: .*/ -#define SYS_TIMER_TARGET0_HI_RO 0x000FFFFF -#define SYS_TIMER_TARGET0_HI_RO_M ((SYS_TIMER_TARGET0_HI_RO_V)<<(SYS_TIMER_TARGET0_HI_RO_S)) -#define SYS_TIMER_TARGET0_HI_RO_V 0xFFFFF -#define SYS_TIMER_TARGET0_HI_RO_S 0 - -#define SYS_TIMER_SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYS_TIMER_BASE + 0x7C) -/* SYS_TIMER_TARGET1_LO_RO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: .*/ -#define SYS_TIMER_TARGET1_LO_RO 0xFFFFFFFF -#define SYS_TIMER_TARGET1_LO_RO_M ((SYS_TIMER_TARGET1_LO_RO_V)<<(SYS_TIMER_TARGET1_LO_RO_S)) -#define SYS_TIMER_TARGET1_LO_RO_V 0xFFFFFFFF -#define SYS_TIMER_TARGET1_LO_RO_S 0 - -#define SYS_TIMER_SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYS_TIMER_BASE + 0x80) -/* SYS_TIMER_TARGET1_HI_RO : RO ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: .*/ -#define SYS_TIMER_TARGET1_HI_RO 0x000FFFFF -#define SYS_TIMER_TARGET1_HI_RO_M ((SYS_TIMER_TARGET1_HI_RO_V)<<(SYS_TIMER_TARGET1_HI_RO_S)) -#define SYS_TIMER_TARGET1_HI_RO_V 0xFFFFF -#define SYS_TIMER_TARGET1_HI_RO_S 0 - -#define SYS_TIMER_SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYS_TIMER_BASE + 0x84) -/* SYS_TIMER_TARGET2_LO_RO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: .*/ -#define SYS_TIMER_TARGET2_LO_RO 0xFFFFFFFF -#define SYS_TIMER_TARGET2_LO_RO_M ((SYS_TIMER_TARGET2_LO_RO_V)<<(SYS_TIMER_TARGET2_LO_RO_S)) -#define SYS_TIMER_TARGET2_LO_RO_V 0xFFFFFFFF -#define SYS_TIMER_TARGET2_LO_RO_S 0 - -#define SYS_TIMER_SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYS_TIMER_BASE + 0x88) -/* SYS_TIMER_TARGET2_HI_RO : RO ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: .*/ -#define SYS_TIMER_TARGET2_HI_RO 0x000FFFFF -#define SYS_TIMER_TARGET2_HI_RO_M ((SYS_TIMER_TARGET2_HI_RO_V)<<(SYS_TIMER_TARGET2_HI_RO_S)) -#define SYS_TIMER_TARGET2_HI_RO_V 0xFFFFF -#define SYS_TIMER_TARGET2_HI_RO_S 0 - -#define SYS_TIMER_SYSTIMER_DATE_REG (DR_REG_SYS_TIMER_BASE + 0xFC) -/* SYS_TIMER_DATE : R/W ;bitpos:[31:0] ;default: 28'h2012251 ; */ -/*description: .*/ -#define SYS_TIMER_DATE 0xFFFFFFFF -#define SYS_TIMER_DATE_M ((SYS_TIMER_DATE_V)<<(SYS_TIMER_DATE_S)) -#define SYS_TIMER_DATE_V 0xFFFFFFFF -#define SYS_TIMER_DATE_S 0 - - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_SYS_TIMER_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/sys_timer_struct.h b/components/soc/esp32s3/include/soc/sys_timer_struct.h deleted file mode 100644 index 1641f7e44c..0000000000 --- a/components/soc/esp32s3/include/soc/sys_timer_struct.h +++ /dev/null @@ -1,271 +0,0 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_SYS_TIMER_STRUCT_H_ -#define _SOC_SYS_TIMER_STRUCT_H_ -#ifdef __cplusplus -extern "C" { -#endif - -#include - -typedef volatile struct { - union { - struct { - uint32_t systimer_clk_fo : 1; /*systimer clock force on*/ - uint32_t reserved1 : 21; - uint32_t target2_work_en : 1; /*target2 work enable*/ - uint32_t target1_work_en : 1; /*target1 work enable*/ - uint32_t target0_work_en : 1; /*target0 work enable*/ - uint32_t timer_unit1_core1_stall_en : 1; /*If timer unit1 is stalled when core1 stalled*/ - uint32_t timer_unit1_core0_stall_en : 1; /*If timer unit1 is stalled when core0 stalled*/ - uint32_t timer_unit0_core1_stall_en : 1; /*If timer unit0 is stalled when core1 stalled*/ - uint32_t timer_unit0_core0_stall_en : 1; /*If timer unit0 is stalled when core0 stalled*/ - uint32_t timer_unit1_work_en : 1; /*timer unit1 work enable*/ - uint32_t timer_unit0_work_en : 1; /*timer unit0 work enable*/ - uint32_t clk_en : 1; /*register file clk gating*/ - }; - uint32_t val; - } systimer_conf; - union { - struct { - uint32_t reserved0 : 29; - uint32_t timer_unit0_value_valid : 1; - uint32_t timer_unit0_update : 1; /*update timer_unit0*/ - uint32_t reserved31 : 1; - }; - uint32_t val; - } systimer_unit0_op; - union { - struct { - uint32_t reserved0 : 29; - uint32_t timer_unit1_value_valid : 1; /*timer value is sync and valid*/ - uint32_t timer_unit1_update : 1; /*update timer unit1*/ - uint32_t reserved31 : 1; - }; - uint32_t val; - } systimer_unit1_op; - union { - struct { - uint32_t timer_unit0_load_hi : 20; /*timer unit0 load high 32 bit*/ - uint32_t reserved20 : 12; - }; - uint32_t val; - } systimer_unit0_load_hi; - uint32_t systimer_unit0_load_lo; - union { - struct { - uint32_t timer_unit1_load_hi : 20; /*timer unit1 load high 32 bit*/ - uint32_t reserved20 : 12; - }; - uint32_t val; - } systimer_unit1_load_hi; - uint32_t systimer_unit1_load_lo; - union { - struct { - uint32_t timer_target0_hi : 20; /*timer taget0 high 32 bit*/ - uint32_t reserved20 : 12; - }; - uint32_t val; - } systimer_target0_hi; - uint32_t systimer_target0_lo; - union { - struct { - uint32_t timer_target1_hi : 20; /*timer taget1 high 32 bit*/ - uint32_t reserved20 : 12; - }; - uint32_t val; - } systimer_target1_hi; - uint32_t systimer_target1_lo; - union { - struct { - uint32_t timer_target2_hi : 20; /*timer taget2 high 32 bit*/ - uint32_t reserved20 : 12; - }; - uint32_t val; - } systimer_target2_hi; - uint32_t systimer_target2_lo; - union { - struct { - uint32_t target0_period : 26; /*target0 period*/ - uint32_t reserved26 : 4; - uint32_t target0_period_mode : 1; /*Set target0 to period mode*/ - uint32_t target0_timer_unit_sel : 1; /*select which unit to compare*/ - }; - uint32_t val; - } systimer_target0_conf; - union { - struct { - uint32_t target1_period : 26; /*target1 period*/ - uint32_t reserved26 : 4; - uint32_t target1_period_mode : 1; /*Set target1 to period mode*/ - uint32_t target1_timer_unit_sel : 1; /*select which unit to compare*/ - }; - uint32_t val; - } systimer_target1_conf; - union { - struct { - uint32_t target2_period : 26; /*target2 period*/ - uint32_t reserved26 : 4; - uint32_t target2_period_mode : 1; /*Set target2 to period mode*/ - uint32_t target2_timer_unit_sel : 1; /*select which unit to compare*/ - }; - uint32_t val; - } systimer_target2_conf; - union { - struct { - uint32_t timer_unit0_value_hi : 20; /*timer read value high 32bit*/ - uint32_t reserved20 : 12; - }; - uint32_t val; - } systimer_unit0_value_hi; - uint32_t systimer_unit0_value_lo; - union { - struct { - uint32_t timer_unit1_value_hi : 20; /*timer read value high 32bit*/ - uint32_t reserved20 : 12; - }; - uint32_t val; - } systimer_unit1_value_hi; - uint32_t systimer_unit1_value_lo; - union { - struct { - uint32_t timer_comp0_load : 1; /*timer comp0 load value*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } systimer_comp0_load; - union { - struct { - uint32_t timer_comp1_load : 1; /*timer comp1 load value*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } systimer_comp1_load; - union { - struct { - uint32_t timer_comp2_load : 1; /*timer comp2 load value*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } systimer_comp2_load; - union { - struct { - uint32_t timer_unit0_load : 1; /*timer unit0 load value*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } systimer_unit0_load; - union { - struct { - uint32_t timer_unit1_load : 1; /*timer unit1 load value*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } systimer_unit1_load; - union { - struct { - uint32_t target0 : 1; /*interupt0 enable*/ - uint32_t target1 : 1; /*interupt1 enable*/ - uint32_t target2 : 1; /*interupt2 enable*/ - uint32_t reserved3 : 29; - }; - uint32_t val; - } systimer_int_ena; - union { - struct { - uint32_t target0 : 1; /*interupt0 raw*/ - uint32_t target1 : 1; /*interupt1 raw*/ - uint32_t target2 : 1; /*interupt2 raw*/ - uint32_t reserved3 : 29; - }; - uint32_t val; - } systimer_int_raw; - union { - struct { - uint32_t target0 : 1; /*interupt0 clear*/ - uint32_t target1 : 1; /*interupt1 clear*/ - uint32_t target2 : 1; /*interupt2 clear*/ - uint32_t reserved3 : 29; - }; - uint32_t val; - } systimer_int_clr; - union { - struct { - uint32_t target0 : 1; - uint32_t target1 : 1; - uint32_t target2 : 1; - uint32_t reserved3 : 29; - }; - uint32_t val; - } systimer_int_st; - uint32_t systimer_real_target0_lo; - union { - struct { - uint32_t target0_hi_ro : 20; - uint32_t reserved20 : 12; - }; - uint32_t val; - } systimer_real_target0_hi; - uint32_t systimer_real_target1_lo; - union { - struct { - uint32_t target1_hi_ro : 20; - uint32_t reserved20 : 12; - }; - uint32_t val; - } systimer_real_target1_hi; - uint32_t systimer_real_target2_lo; - union { - struct { - uint32_t target2_hi_ro : 20; - uint32_t reserved20 : 12; - }; - uint32_t val; - } systimer_real_target2_hi; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t systimer_date; -} sys_timer_dev_t; -extern sys_timer_dev_t SYS_TIMER; -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_SYS_TIMER_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/systimer_caps.h b/components/soc/esp32s3/include/soc/systimer_caps.h deleted file mode 100644 index 37683122ba..0000000000 --- a/components/soc/esp32s3/include/soc/systimer_caps.h +++ /dev/null @@ -1,22 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units -#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units - -#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part -#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part -#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt diff --git a/components/soc/esp32s3/include/soc/systimer_reg.h b/components/soc/esp32s3/include/soc/systimer_reg.h new file mode 100644 index 0000000000..869012065b --- /dev/null +++ b/components/soc/esp32s3/include/soc/systimer_reg.h @@ -0,0 +1,639 @@ +/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SYSTIMER_CONF_REG register + * Configure system timer clock + */ +#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0) +/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0; + * systimer clock force on + */ +#define SYSTIMER_SYSTIMER_CLK_FO (BIT(0)) +#define SYSTIMER_SYSTIMER_CLK_FO_M (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S) +#define SYSTIMER_SYSTIMER_CLK_FO_V 0x00000001 +#define SYSTIMER_SYSTIMER_CLK_FO_S 0 +/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ +#define SYSTIMER_TARGET2_WORK_EN (BIT(22)) +#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S) +#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001 +#define SYSTIMER_TARGET2_WORK_EN_S 22 +/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ +#define SYSTIMER_TARGET1_WORK_EN (BIT(23)) +#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S) +#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001 +#define SYSTIMER_TARGET1_WORK_EN_S 23 +/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ +#define SYSTIMER_TARGET0_WORK_EN (BIT(24)) +#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S) +#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001 +#define SYSTIMER_TARGET0_WORK_EN_S 24 +/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 +/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 +/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 +/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 +/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ +#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29 +/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ +#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30 +/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ +#define SYSTIMER_CLK_EN (BIT(31)) +#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S) +#define SYSTIMER_CLK_EN_V 0x00000001 +#define SYSTIMER_CLK_EN_S 31 + +/** SYSTIMER_UNIT0_OP_REG register + * system timer unit0 value update register + */ +#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4) +/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0; + * update timer_unit0 + */ +#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S) +#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30 + +/** SYSTIMER_UNIT1_OP_REG register + * system timer unit1 value update register + */ +#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8) +/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0; + * update timer unit1 + */ +#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S) +#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30 + +/** SYSTIMER_UNIT0_LOAD_HI_REG register + * system timer unit0 value high load register + */ +#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc) +/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit0 load high 20 bits + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0 + +/** SYSTIMER_UNIT0_LOAD_LO_REG register + * system timer unit0 value low load register + */ +#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10) +/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit0 load low 32 bits + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0 + +/** SYSTIMER_UNIT1_LOAD_HI_REG register + * system timer unit1 value high load register + */ +#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14) +/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit1 load high 20 bits + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0 + +/** SYSTIMER_UNIT1_LOAD_LO_REG register + * system timer unit1 value low load register + */ +#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18) +/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit1 load low 32 bits + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0 + +/** SYSTIMER_TARGET0_HI_REG register + * system timer comp0 value high register + */ +#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c) +/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget0 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFF +#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S) +#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_TARGET0_HI_S 0 + +/** SYSTIMER_TARGET0_LO_REG register + * system timer comp0 value low register + */ +#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20) +/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget0 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S) +#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET0_LO_S 0 + +/** SYSTIMER_TARGET1_HI_REG register + * system timer comp1 value high register + */ +#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24) +/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget1 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFF +#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S) +#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_TARGET1_HI_S 0 + +/** SYSTIMER_TARGET1_LO_REG register + * system timer comp1 value low register + */ +#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28) +/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget1 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S) +#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET1_LO_S 0 + +/** SYSTIMER_TARGET2_HI_REG register + * system timer comp2 value high register + */ +#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c) +/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget2 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFF +#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S) +#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_TARGET2_HI_S 0 + +/** SYSTIMER_TARGET2_LO_REG register + * system timer comp2 value low register + */ +#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30) +/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget2 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S) +#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET2_LO_S 0 + +/** SYSTIMER_TARGET0_CONF_REG register + * system timer comp0 target mode register + */ +#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34) +/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target0 period + */ +#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFF +#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S) +#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFF +#define SYSTIMER_TARGET0_PERIOD_S 0 +/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target0 to period mode + */ +#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S) +#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001 +#define SYSTIMER_TARGET0_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001 +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_TARGET1_CONF_REG register + * system timer comp1 target mode register + */ +#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38) +/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target1 period + */ +#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFF +#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S) +#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFF +#define SYSTIMER_TARGET1_PERIOD_S 0 +/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target1 to period mode + */ +#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S) +#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001 +#define SYSTIMER_TARGET1_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001 +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_TARGET2_CONF_REG register + * system timer comp2 target mode register + */ +#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c) +/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target2 period + */ +#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFF +#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S) +#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFF +#define SYSTIMER_TARGET2_PERIOD_S 0 +/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target2 to period mode + */ +#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S) +#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001 +#define SYSTIMER_TARGET2_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001 +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_UNIT0_VALUE_HI_REG register + * system timer unit0 value high register + */ +#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40) +/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bits + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0 + +/** SYSTIMER_UNIT0_VALUE_LO_REG register + * system timer unit0 value low register + */ +#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44) +/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bits + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0 + +/** SYSTIMER_UNIT1_VALUE_HI_REG register + * system timer unit1 value high register + */ +#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48) +/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bits + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0 + +/** SYSTIMER_UNIT1_VALUE_LO_REG register + * system timer unit1 value low register + */ +#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c) +/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bits + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0 + +/** SYSTIMER_COMP0_LOAD_REG register + * system timer comp0 conf sync register + */ +#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50) +/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0; + * timer comp0 sync enable signal + */ +#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S) +#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_COMP0_LOAD_S 0 + +/** SYSTIMER_COMP1_LOAD_REG register + * system timer comp1 conf sync register + */ +#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54) +/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0; + * timer comp1 sync enable signal + */ +#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S) +#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_COMP1_LOAD_S 0 + +/** SYSTIMER_COMP2_LOAD_REG register + * system timer comp2 conf sync register + */ +#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58) +/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0; + * timer comp2 sync enable signal + */ +#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S) +#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_COMP2_LOAD_S 0 + +/** SYSTIMER_UNIT0_LOAD_REG register + * system timer unit0 conf sync register + */ +#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c) +/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0; + * timer unit0 sync enable signal + */ +#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_LOAD_S 0 + +/** SYSTIMER_UNIT1_LOAD_REG register + * system timer unit1 conf sync register + */ +#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60) +/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0; + * timer unit1 sync enable signal + */ +#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_LOAD_S 0 + +/** SYSTIMER_INT_ENA_REG register + * systimer interrupt enable register + */ +#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64) +/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ +#define SYSTIMER_TARGET0_INT_ENA (BIT(0)) +#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S) +#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001 +#define SYSTIMER_TARGET0_INT_ENA_S 0 +/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ +#define SYSTIMER_TARGET1_INT_ENA (BIT(1)) +#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S) +#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001 +#define SYSTIMER_TARGET1_INT_ENA_S 1 +/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ +#define SYSTIMER_TARGET2_INT_ENA (BIT(2)) +#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S) +#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001 +#define SYSTIMER_TARGET2_INT_ENA_S 2 + +/** SYSTIMER_INT_RAW_REG register + * systimer interrupt raw register + */ +#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68) +/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ +#define SYSTIMER_TARGET0_INT_RAW (BIT(0)) +#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S) +#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001 +#define SYSTIMER_TARGET0_INT_RAW_S 0 +/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ +#define SYSTIMER_TARGET1_INT_RAW (BIT(1)) +#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S) +#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001 +#define SYSTIMER_TARGET1_INT_RAW_S 1 +/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ +#define SYSTIMER_TARGET2_INT_RAW (BIT(2)) +#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S) +#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001 +#define SYSTIMER_TARGET2_INT_RAW_S 2 + +/** SYSTIMER_INT_CLR_REG register + * systimer interrupt clear register + */ +#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c) +/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ +#define SYSTIMER_TARGET0_INT_CLR (BIT(0)) +#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S) +#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001 +#define SYSTIMER_TARGET0_INT_CLR_S 0 +/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ +#define SYSTIMER_TARGET1_INT_CLR (BIT(1)) +#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S) +#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001 +#define SYSTIMER_TARGET1_INT_CLR_S 1 +/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ +#define SYSTIMER_TARGET2_INT_CLR (BIT(2)) +#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S) +#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001 +#define SYSTIMER_TARGET2_INT_CLR_S 2 + +/** SYSTIMER_INT_ST_REG register + * systimer interrupt status register + */ +#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70) +/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0; + * interupt0 status + */ +#define SYSTIMER_TARGET0_INT_ST (BIT(0)) +#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S) +#define SYSTIMER_TARGET0_INT_ST_V 0x00000001 +#define SYSTIMER_TARGET0_INT_ST_S 0 +/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0; + * interupt1 status + */ +#define SYSTIMER_TARGET1_INT_ST (BIT(1)) +#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S) +#define SYSTIMER_TARGET1_INT_ST_V 0x00000001 +#define SYSTIMER_TARGET1_INT_ST_S 1 +/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0; + * interupt2 status + */ +#define SYSTIMER_TARGET2_INT_ST (BIT(2)) +#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S) +#define SYSTIMER_TARGET2_INT_ST_V 0x00000001 +#define SYSTIMER_TARGET2_INT_ST_S 2 + +/** SYSTIMER_REAL_TARGET0_LO_REG register + * system timer comp0 actual target value low register + */ +#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74) +/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET0_LO_RO 0xFFFFFFFF +#define SYSTIMER_TARGET0_LO_RO_M (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S) +#define SYSTIMER_TARGET0_LO_RO_V 0xFFFFFFFF +#define SYSTIMER_TARGET0_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET0_HI_REG register + * system timer comp0 actual target value high register + */ +#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78) +/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET0_HI_RO 0x000FFFFF +#define SYSTIMER_TARGET0_HI_RO_M (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S) +#define SYSTIMER_TARGET0_HI_RO_V 0x000FFFFF +#define SYSTIMER_TARGET0_HI_RO_S 0 + +/** SYSTIMER_REAL_TARGET1_LO_REG register + * system timer comp1 actual target value low register + */ +#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c) +/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET1_LO_RO 0xFFFFFFFF +#define SYSTIMER_TARGET1_LO_RO_M (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S) +#define SYSTIMER_TARGET1_LO_RO_V 0xFFFFFFFF +#define SYSTIMER_TARGET1_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET1_HI_REG register + * system timer comp1 actual target value high register + */ +#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80) +/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET1_HI_RO 0x000FFFFF +#define SYSTIMER_TARGET1_HI_RO_M (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S) +#define SYSTIMER_TARGET1_HI_RO_V 0x000FFFFF +#define SYSTIMER_TARGET1_HI_RO_S 0 + +/** SYSTIMER_REAL_TARGET2_LO_REG register + * system timer comp2 actual target value low register + */ +#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84) +/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET2_LO_RO 0xFFFFFFFF +#define SYSTIMER_TARGET2_LO_RO_M (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S) +#define SYSTIMER_TARGET2_LO_RO_V 0xFFFFFFFF +#define SYSTIMER_TARGET2_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET2_HI_REG register + * system timer comp2 actual target value high register + */ +#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88) +/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET2_HI_RO 0x000FFFFF +#define SYSTIMER_TARGET2_HI_RO_M (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S) +#define SYSTIMER_TARGET2_HI_RO_V 0x000FFFFF +#define SYSTIMER_TARGET2_HI_RO_S 0 + +/** SYSTIMER_DATE_REG register + * system timer version control register + */ +#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc) +/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 33628753; + * systimer register version + */ +#define SYSTIMER_DATE 0xFFFFFFFF +#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S) +#define SYSTIMER_DATE_V 0xFFFFFFFF +#define SYSTIMER_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s3/include/soc/systimer_struct.h b/components/soc/esp32s3/include/soc/systimer_struct.h new file mode 100644 index 0000000000..30d3f7e7d5 --- /dev/null +++ b/components/soc/esp32s3/include/soc/systimer_struct.h @@ -0,0 +1,397 @@ +/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** SYSTEM TIMER CLK CONTROL REGISTER */ +/** Type of conf register + * Configure system timer clock + */ +typedef union { + struct { + /** systimer_clk_fo : R/W; bitpos: [0]; default: 0; + * systimer clock force on + */ + uint32_t systimer_clk_fo: 1; + uint32_t reserved_1: 21; + /** target2_work_en : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ + uint32_t target2_work_en: 1; + /** target1_work_en : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ + uint32_t target1_work_en: 1; + /** target0_work_en : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ + uint32_t target0_work_en: 1; + /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ + uint32_t timer_unit1_core1_stall_en: 1; + /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ + uint32_t timer_unit1_core0_stall_en: 1; + /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ + uint32_t timer_unit0_core1_stall_en: 1; + /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ + uint32_t timer_unit0_core0_stall_en: 1; + /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ + uint32_t timer_unit1_work_en: 1; + /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ + uint32_t timer_unit0_work_en: 1; + /** clk_en : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ + uint32_t clk_en: 1; + }; + uint32_t val; +} systimer_conf_reg_t; + + +/** Type of unit_op register + * SYSTIMER_UNIT_OP. + */ +typedef union { + struct { + uint32_t reserved_0: 29; + /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0; + * reg_timer_unit0_value_valid + */ + uint32_t timer_unit_value_valid: 1; + /** timer_unit_update : WT; bitpos: [30]; default: 0; + * update timer_unit0 + */ + uint32_t timer_unit_update: 1; + }; + uint32_t val; +} systimer_unit_op_reg_t; + +/** Type of unit_load register + * SYSTIMER_UNIT_LOAD + */ +typedef struct { + union { + struct { + /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0; + * timer unit load high 32 bit + */ + uint32_t timer_unit_load_hi: 20; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0; + * timer unit load low 32 bit + */ + uint32_t timer_unit_load_lo: 32; + }; + uint32_t val; + } lo; +} systimer_unit_load_val_reg_t; + + +/** Type of target register + * SYSTIMER_TARGET. + */ +typedef struct { + union { + struct { + /** timer_target_hi : R/W; bitpos: [19:0]; default: 0; + * timer target high 32 bit + */ + uint32_t timer_target_hi: 20; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_target_lo : R/W; bitpos: [31:0]; default: 0; + * timer target low 32 bit + */ + uint32_t timer_target_lo: 32; + }; + uint32_t val; + } lo; +} systimer_target_val_reg_t; + + +/** Type of target_conf register + * SYSTIMER_TARGET_CONF. + */ +typedef union { + struct { + /** target_period : R/W; bitpos: [25:0]; default: 0; + * target period + */ + uint32_t target_period: 26; + uint32_t reserved_26: 4; + /** target_period_mode : R/W; bitpos: [30]; default: 0; + * Set target to period mode + */ + uint32_t target_period_mode: 1; + /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ + uint32_t target_timer_unit_sel: 1; + }; + uint32_t val; +} systimer_target_conf_reg_t; + + +/** Type of unit_value_hi register + * SYSTIMER_UNIT_VALUE_HI. + */ +typedef struct { + union { + struct { + /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bit + */ + uint32_t timer_unit_value_hi: 20; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bit + */ + uint32_t timer_unit_value_lo: 32; + }; + uint32_t val; + } lo; +} systimer_unit_value_reg_t; + + +/** Type of comp_load register + * SYSTIMER_COMP_LOAD. + */ +typedef union { + struct { + /** timer_comp_load : WT; bitpos: [0]; default: 0; + * timer comp load value + */ + uint32_t timer_comp_load: 1; + }; + uint32_t val; +} systimer_comp_load_reg_t; + + +/** Type of unit_load register + * SYSTIMER_UNIT_LOAD. + */ +typedef union { + struct { + /** timer_unit_load : WT; bitpos: [0]; default: 0; + * timer unit load value + */ + uint32_t timer_unit_load: 1; + }; + uint32_t val; +} systimer_unit_load_reg_t; + + +/** SYSTEM TIMER INTERRUPT REGISTER */ +/** Type of int_ena register + * systimer interrupt enable register + */ +typedef union { + struct { + /** target0_int_ena : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ + uint32_t target0_int_ena: 1; + /** target1_int_ena : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ + uint32_t target1_int_ena: 1; + /** target2_int_ena : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ + uint32_t target2_int_ena: 1; + }; + uint32_t val; +} systimer_int_ena_reg_t; + +/** Type of int_raw register + * systimer interrupt raw register + */ +typedef union { + struct { + /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ + uint32_t target0_int_raw: 1; + /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ + uint32_t target1_int_raw: 1; + /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ + uint32_t target2_int_raw: 1; + }; + uint32_t val; +} systimer_int_raw_reg_t; + +/** Type of int_clr register + * systimer interrupt clear register + */ +typedef union { + struct { + /** target0_int_clr : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ + uint32_t target0_int_clr: 1; + /** target1_int_clr : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ + uint32_t target1_int_clr: 1; + /** target2_int_clr : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ + uint32_t target2_int_clr: 1; + }; + uint32_t val; +} systimer_int_clr_reg_t; + +/** Type of int_st register + * systimer interrupt status register + */ +typedef union { + struct { + /** target0_int_st : RO; bitpos: [0]; default: 0; + * interupt0 status + */ + uint32_t target0_int_st: 1; + /** target1_int_st : RO; bitpos: [1]; default: 0; + * interupt1 status + */ + uint32_t target1_int_st: 1; + /** target2_int_st : RO; bitpos: [2]; default: 0; + * interupt2 status + */ + uint32_t target2_int_st: 1; + }; + uint32_t val; +} systimer_int_st_reg_t; + + +/** SYSTEM TIMER COMP STATUS REGISTER + * systimer comp actual target value low register + */ +typedef struct { + union { + struct { + /** target_lo_ro : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ + uint32_t target_lo_ro: 32; + }; + uint32_t val; + } lo; + union { + struct { + /** target_hi_ro : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ + uint32_t target_hi_ro: 20; + }; + uint32_t val; + } hi; +} systimer_real_target_val_reg_t; + + +/** VERSION REGISTER */ +/** Type of date register + * system timer version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 33628753; + * systimer register version + */ + uint32_t date: 32; + }; + uint32_t val; +} systimer_date_reg_t; + + +typedef struct { + volatile systimer_conf_reg_t conf; + volatile systimer_unit_op_reg_t unit_op[2]; + volatile systimer_unit_load_val_reg_t unit_load_val[2]; + volatile systimer_target_val_reg_t target_val[3]; + volatile systimer_target_conf_reg_t target_conf[3]; + volatile systimer_unit_value_reg_t unit_val[2]; + volatile systimer_comp_load_reg_t comp_load[3]; + volatile systimer_unit_load_reg_t unit_load[2]; + volatile systimer_int_ena_reg_t int_ena; + volatile systimer_int_raw_reg_t int_raw; + volatile systimer_int_clr_reg_t int_clr; + volatile systimer_int_st_reg_t int_st; + volatile systimer_real_target_val_reg_t real_target_val[3]; + uint32_t reserved_08c; + uint32_t reserved_090; + uint32_t reserved_094; + uint32_t reserved_098; + uint32_t reserved_09c; + uint32_t reserved_0a0; + uint32_t reserved_0a4; + uint32_t reserved_0a8; + uint32_t reserved_0ac; + uint32_t reserved_0b0; + uint32_t reserved_0b4; + uint32_t reserved_0b8; + uint32_t reserved_0bc; + uint32_t reserved_0c0; + uint32_t reserved_0c4; + uint32_t reserved_0c8; + uint32_t reserved_0cc; + uint32_t reserved_0d0; + uint32_t reserved_0d4; + uint32_t reserved_0d8; + uint32_t reserved_0dc; + uint32_t reserved_0e0; + uint32_t reserved_0e4; + uint32_t reserved_0e8; + uint32_t reserved_0ec; + uint32_t reserved_0f0; + uint32_t reserved_0f4; + uint32_t reserved_0f8; + volatile systimer_date_reg_t date; +} systimer_dev_t; + +extern systimer_dev_t SYSTIMER; + +#ifdef __cplusplus +} +#endif