From 10aef84983246c195b02d80de159b8180393e8cb Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Fri, 23 May 2025 14:23:45 +0800 Subject: [PATCH 1/3] change(etm): update etm soc headers of h21 --- .../soc/esp32h21/register/soc/soc_etm_reg.h | 2740 ++++++++-------- .../esp32h21/register/soc/soc_etm_struct.h | 2764 +++++------------ 2 files changed, 2320 insertions(+), 3184 deletions(-) diff --git a/components/soc/esp32h21/register/soc/soc_etm_reg.h b/components/soc/esp32h21/register/soc/soc_etm_reg.h index 4ad78c27ce..4d3c8d564f 100644 --- a/components/soc/esp32h21/register/soc/soc_etm_reg.h +++ b/components/soc/esp32h21/register/soc/soc_etm_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,1091 +12,1391 @@ extern "C" { #endif /** SOC_ETM_CH_ENA_AD0_REG register - * channel enable register + * Channel enable status register */ -#define SOC_ETM_CH_ENA_AD0_REG (DR_REG_SOC_BASE + 0x0) -/** SOC_ETM_CH_ENA0 : R/WTC/WTS; bitpos: [0]; default: 0; - * ch0 enable +#define SOC_ETM_CH_ENA_AD0_REG (DR_REG_SOC_ETM_BASE + 0x0) +/** SOC_ETM_CH_ENABLED0 : R/WTC/SS; bitpos: [0]; default: 0; + * Represents channel0 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA0 (BIT(0)) -#define SOC_ETM_CH_ENA0_M (SOC_ETM_CH_ENA0_V << SOC_ETM_CH_ENA0_S) -#define SOC_ETM_CH_ENA0_V 0x00000001U -#define SOC_ETM_CH_ENA0_S 0 -/** SOC_ETM_CH_ENA1 : R/WTC/WTS; bitpos: [1]; default: 0; - * ch1 enable +#define SOC_ETM_CH_ENABLED0 (BIT(0)) +#define SOC_ETM_CH_ENABLED0_M (SOC_ETM_CH_ENABLED0_V << SOC_ETM_CH_ENABLED0_S) +#define SOC_ETM_CH_ENABLED0_V 0x00000001U +#define SOC_ETM_CH_ENABLED0_S 0 +/** SOC_ETM_CH_ENABLED1 : R/WTC/SS; bitpos: [1]; default: 0; + * Represents channel1 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA1 (BIT(1)) -#define SOC_ETM_CH_ENA1_M (SOC_ETM_CH_ENA1_V << SOC_ETM_CH_ENA1_S) -#define SOC_ETM_CH_ENA1_V 0x00000001U -#define SOC_ETM_CH_ENA1_S 1 -/** SOC_ETM_CH_ENA2 : R/WTC/WTS; bitpos: [2]; default: 0; - * ch2 enable +#define SOC_ETM_CH_ENABLED1 (BIT(1)) +#define SOC_ETM_CH_ENABLED1_M (SOC_ETM_CH_ENABLED1_V << SOC_ETM_CH_ENABLED1_S) +#define SOC_ETM_CH_ENABLED1_V 0x00000001U +#define SOC_ETM_CH_ENABLED1_S 1 +/** SOC_ETM_CH_ENABLED2 : R/WTC/SS; bitpos: [2]; default: 0; + * Represents channel2 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA2 (BIT(2)) -#define SOC_ETM_CH_ENA2_M (SOC_ETM_CH_ENA2_V << SOC_ETM_CH_ENA2_S) -#define SOC_ETM_CH_ENA2_V 0x00000001U -#define SOC_ETM_CH_ENA2_S 2 -/** SOC_ETM_CH_ENA3 : R/WTC/WTS; bitpos: [3]; default: 0; - * ch3 enable +#define SOC_ETM_CH_ENABLED2 (BIT(2)) +#define SOC_ETM_CH_ENABLED2_M (SOC_ETM_CH_ENABLED2_V << SOC_ETM_CH_ENABLED2_S) +#define SOC_ETM_CH_ENABLED2_V 0x00000001U +#define SOC_ETM_CH_ENABLED2_S 2 +/** SOC_ETM_CH_ENABLED3 : R/WTC/SS; bitpos: [3]; default: 0; + * Represents channel3 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA3 (BIT(3)) -#define SOC_ETM_CH_ENA3_M (SOC_ETM_CH_ENA3_V << SOC_ETM_CH_ENA3_S) -#define SOC_ETM_CH_ENA3_V 0x00000001U -#define SOC_ETM_CH_ENA3_S 3 -/** SOC_ETM_CH_ENA4 : R/WTC/WTS; bitpos: [4]; default: 0; - * ch4 enable +#define SOC_ETM_CH_ENABLED3 (BIT(3)) +#define SOC_ETM_CH_ENABLED3_M (SOC_ETM_CH_ENABLED3_V << SOC_ETM_CH_ENABLED3_S) +#define SOC_ETM_CH_ENABLED3_V 0x00000001U +#define SOC_ETM_CH_ENABLED3_S 3 +/** SOC_ETM_CH_ENABLED4 : R/WTC/SS; bitpos: [4]; default: 0; + * Represents channel4 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA4 (BIT(4)) -#define SOC_ETM_CH_ENA4_M (SOC_ETM_CH_ENA4_V << SOC_ETM_CH_ENA4_S) -#define SOC_ETM_CH_ENA4_V 0x00000001U -#define SOC_ETM_CH_ENA4_S 4 -/** SOC_ETM_CH_ENA5 : R/WTC/WTS; bitpos: [5]; default: 0; - * ch5 enable +#define SOC_ETM_CH_ENABLED4 (BIT(4)) +#define SOC_ETM_CH_ENABLED4_M (SOC_ETM_CH_ENABLED4_V << SOC_ETM_CH_ENABLED4_S) +#define SOC_ETM_CH_ENABLED4_V 0x00000001U +#define SOC_ETM_CH_ENABLED4_S 4 +/** SOC_ETM_CH_ENABLED5 : R/WTC/SS; bitpos: [5]; default: 0; + * Represents channel5 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA5 (BIT(5)) -#define SOC_ETM_CH_ENA5_M (SOC_ETM_CH_ENA5_V << SOC_ETM_CH_ENA5_S) -#define SOC_ETM_CH_ENA5_V 0x00000001U -#define SOC_ETM_CH_ENA5_S 5 -/** SOC_ETM_CH_ENA6 : R/WTC/WTS; bitpos: [6]; default: 0; - * ch6 enable +#define SOC_ETM_CH_ENABLED5 (BIT(5)) +#define SOC_ETM_CH_ENABLED5_M (SOC_ETM_CH_ENABLED5_V << SOC_ETM_CH_ENABLED5_S) +#define SOC_ETM_CH_ENABLED5_V 0x00000001U +#define SOC_ETM_CH_ENABLED5_S 5 +/** SOC_ETM_CH_ENABLED6 : R/WTC/SS; bitpos: [6]; default: 0; + * Represents channel6 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA6 (BIT(6)) -#define SOC_ETM_CH_ENA6_M (SOC_ETM_CH_ENA6_V << SOC_ETM_CH_ENA6_S) -#define SOC_ETM_CH_ENA6_V 0x00000001U -#define SOC_ETM_CH_ENA6_S 6 -/** SOC_ETM_CH_ENA7 : R/WTC/WTS; bitpos: [7]; default: 0; - * ch7 enable +#define SOC_ETM_CH_ENABLED6 (BIT(6)) +#define SOC_ETM_CH_ENABLED6_M (SOC_ETM_CH_ENABLED6_V << SOC_ETM_CH_ENABLED6_S) +#define SOC_ETM_CH_ENABLED6_V 0x00000001U +#define SOC_ETM_CH_ENABLED6_S 6 +/** SOC_ETM_CH_ENABLED7 : R/WTC/SS; bitpos: [7]; default: 0; + * Represents channel7 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA7 (BIT(7)) -#define SOC_ETM_CH_ENA7_M (SOC_ETM_CH_ENA7_V << SOC_ETM_CH_ENA7_S) -#define SOC_ETM_CH_ENA7_V 0x00000001U -#define SOC_ETM_CH_ENA7_S 7 -/** SOC_ETM_CH_ENA8 : R/WTC/WTS; bitpos: [8]; default: 0; - * ch8 enable +#define SOC_ETM_CH_ENABLED7 (BIT(7)) +#define SOC_ETM_CH_ENABLED7_M (SOC_ETM_CH_ENABLED7_V << SOC_ETM_CH_ENABLED7_S) +#define SOC_ETM_CH_ENABLED7_V 0x00000001U +#define SOC_ETM_CH_ENABLED7_S 7 +/** SOC_ETM_CH_ENABLED8 : R/WTC/SS; bitpos: [8]; default: 0; + * Represents channel8 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA8 (BIT(8)) -#define SOC_ETM_CH_ENA8_M (SOC_ETM_CH_ENA8_V << SOC_ETM_CH_ENA8_S) -#define SOC_ETM_CH_ENA8_V 0x00000001U -#define SOC_ETM_CH_ENA8_S 8 -/** SOC_ETM_CH_ENA9 : R/WTC/WTS; bitpos: [9]; default: 0; - * ch9 enable +#define SOC_ETM_CH_ENABLED8 (BIT(8)) +#define SOC_ETM_CH_ENABLED8_M (SOC_ETM_CH_ENABLED8_V << SOC_ETM_CH_ENABLED8_S) +#define SOC_ETM_CH_ENABLED8_V 0x00000001U +#define SOC_ETM_CH_ENABLED8_S 8 +/** SOC_ETM_CH_ENABLED9 : R/WTC/SS; bitpos: [9]; default: 0; + * Represents channel9 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA9 (BIT(9)) -#define SOC_ETM_CH_ENA9_M (SOC_ETM_CH_ENA9_V << SOC_ETM_CH_ENA9_S) -#define SOC_ETM_CH_ENA9_V 0x00000001U -#define SOC_ETM_CH_ENA9_S 9 -/** SOC_ETM_CH_ENA10 : R/WTC/WTS; bitpos: [10]; default: 0; - * ch10 enable +#define SOC_ETM_CH_ENABLED9 (BIT(9)) +#define SOC_ETM_CH_ENABLED9_M (SOC_ETM_CH_ENABLED9_V << SOC_ETM_CH_ENABLED9_S) +#define SOC_ETM_CH_ENABLED9_V 0x00000001U +#define SOC_ETM_CH_ENABLED9_S 9 +/** SOC_ETM_CH_ENABLED10 : R/WTC/SS; bitpos: [10]; default: 0; + * Represents channel10 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA10 (BIT(10)) -#define SOC_ETM_CH_ENA10_M (SOC_ETM_CH_ENA10_V << SOC_ETM_CH_ENA10_S) -#define SOC_ETM_CH_ENA10_V 0x00000001U -#define SOC_ETM_CH_ENA10_S 10 -/** SOC_ETM_CH_ENA11 : R/WTC/WTS; bitpos: [11]; default: 0; - * ch11 enable +#define SOC_ETM_CH_ENABLED10 (BIT(10)) +#define SOC_ETM_CH_ENABLED10_M (SOC_ETM_CH_ENABLED10_V << SOC_ETM_CH_ENABLED10_S) +#define SOC_ETM_CH_ENABLED10_V 0x00000001U +#define SOC_ETM_CH_ENABLED10_S 10 +/** SOC_ETM_CH_ENABLED11 : R/WTC/SS; bitpos: [11]; default: 0; + * Represents channel11 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA11 (BIT(11)) -#define SOC_ETM_CH_ENA11_M (SOC_ETM_CH_ENA11_V << SOC_ETM_CH_ENA11_S) -#define SOC_ETM_CH_ENA11_V 0x00000001U -#define SOC_ETM_CH_ENA11_S 11 -/** SOC_ETM_CH_ENA12 : R/WTC/WTS; bitpos: [12]; default: 0; - * ch12 enable +#define SOC_ETM_CH_ENABLED11 (BIT(11)) +#define SOC_ETM_CH_ENABLED11_M (SOC_ETM_CH_ENABLED11_V << SOC_ETM_CH_ENABLED11_S) +#define SOC_ETM_CH_ENABLED11_V 0x00000001U +#define SOC_ETM_CH_ENABLED11_S 11 +/** SOC_ETM_CH_ENABLED12 : R/WTC/SS; bitpos: [12]; default: 0; + * Represents channel12 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA12 (BIT(12)) -#define SOC_ETM_CH_ENA12_M (SOC_ETM_CH_ENA12_V << SOC_ETM_CH_ENA12_S) -#define SOC_ETM_CH_ENA12_V 0x00000001U -#define SOC_ETM_CH_ENA12_S 12 -/** SOC_ETM_CH_ENA13 : R/WTC/WTS; bitpos: [13]; default: 0; - * ch13 enable +#define SOC_ETM_CH_ENABLED12 (BIT(12)) +#define SOC_ETM_CH_ENABLED12_M (SOC_ETM_CH_ENABLED12_V << SOC_ETM_CH_ENABLED12_S) +#define SOC_ETM_CH_ENABLED12_V 0x00000001U +#define SOC_ETM_CH_ENABLED12_S 12 +/** SOC_ETM_CH_ENABLED13 : R/WTC/SS; bitpos: [13]; default: 0; + * Represents channel13 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA13 (BIT(13)) -#define SOC_ETM_CH_ENA13_M (SOC_ETM_CH_ENA13_V << SOC_ETM_CH_ENA13_S) -#define SOC_ETM_CH_ENA13_V 0x00000001U -#define SOC_ETM_CH_ENA13_S 13 -/** SOC_ETM_CH_ENA14 : R/WTC/WTS; bitpos: [14]; default: 0; - * ch14 enable +#define SOC_ETM_CH_ENABLED13 (BIT(13)) +#define SOC_ETM_CH_ENABLED13_M (SOC_ETM_CH_ENABLED13_V << SOC_ETM_CH_ENABLED13_S) +#define SOC_ETM_CH_ENABLED13_V 0x00000001U +#define SOC_ETM_CH_ENABLED13_S 13 +/** SOC_ETM_CH_ENABLED14 : R/WTC/SS; bitpos: [14]; default: 0; + * Represents channel14 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA14 (BIT(14)) -#define SOC_ETM_CH_ENA14_M (SOC_ETM_CH_ENA14_V << SOC_ETM_CH_ENA14_S) -#define SOC_ETM_CH_ENA14_V 0x00000001U -#define SOC_ETM_CH_ENA14_S 14 -/** SOC_ETM_CH_ENA15 : R/WTC/WTS; bitpos: [15]; default: 0; - * ch15 enable +#define SOC_ETM_CH_ENABLED14 (BIT(14)) +#define SOC_ETM_CH_ENABLED14_M (SOC_ETM_CH_ENABLED14_V << SOC_ETM_CH_ENABLED14_S) +#define SOC_ETM_CH_ENABLED14_V 0x00000001U +#define SOC_ETM_CH_ENABLED14_S 14 +/** SOC_ETM_CH_ENABLED15 : R/WTC/SS; bitpos: [15]; default: 0; + * Represents channel15 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA15 (BIT(15)) -#define SOC_ETM_CH_ENA15_M (SOC_ETM_CH_ENA15_V << SOC_ETM_CH_ENA15_S) -#define SOC_ETM_CH_ENA15_V 0x00000001U -#define SOC_ETM_CH_ENA15_S 15 -/** SOC_ETM_CH_ENA16 : R/WTC/WTS; bitpos: [16]; default: 0; - * ch16 enable +#define SOC_ETM_CH_ENABLED15 (BIT(15)) +#define SOC_ETM_CH_ENABLED15_M (SOC_ETM_CH_ENABLED15_V << SOC_ETM_CH_ENABLED15_S) +#define SOC_ETM_CH_ENABLED15_V 0x00000001U +#define SOC_ETM_CH_ENABLED15_S 15 +/** SOC_ETM_CH_ENABLED16 : R/WTC/SS; bitpos: [16]; default: 0; + * Represents channel16 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA16 (BIT(16)) -#define SOC_ETM_CH_ENA16_M (SOC_ETM_CH_ENA16_V << SOC_ETM_CH_ENA16_S) -#define SOC_ETM_CH_ENA16_V 0x00000001U -#define SOC_ETM_CH_ENA16_S 16 -/** SOC_ETM_CH_ENA17 : R/WTC/WTS; bitpos: [17]; default: 0; - * ch17 enable +#define SOC_ETM_CH_ENABLED16 (BIT(16)) +#define SOC_ETM_CH_ENABLED16_M (SOC_ETM_CH_ENABLED16_V << SOC_ETM_CH_ENABLED16_S) +#define SOC_ETM_CH_ENABLED16_V 0x00000001U +#define SOC_ETM_CH_ENABLED16_S 16 +/** SOC_ETM_CH_ENABLED17 : R/WTC/SS; bitpos: [17]; default: 0; + * Represents channel17 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA17 (BIT(17)) -#define SOC_ETM_CH_ENA17_M (SOC_ETM_CH_ENA17_V << SOC_ETM_CH_ENA17_S) -#define SOC_ETM_CH_ENA17_V 0x00000001U -#define SOC_ETM_CH_ENA17_S 17 -/** SOC_ETM_CH_ENA18 : R/WTC/WTS; bitpos: [18]; default: 0; - * ch18 enable +#define SOC_ETM_CH_ENABLED17 (BIT(17)) +#define SOC_ETM_CH_ENABLED17_M (SOC_ETM_CH_ENABLED17_V << SOC_ETM_CH_ENABLED17_S) +#define SOC_ETM_CH_ENABLED17_V 0x00000001U +#define SOC_ETM_CH_ENABLED17_S 17 +/** SOC_ETM_CH_ENABLED18 : R/WTC/SS; bitpos: [18]; default: 0; + * Represents channel18 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA18 (BIT(18)) -#define SOC_ETM_CH_ENA18_M (SOC_ETM_CH_ENA18_V << SOC_ETM_CH_ENA18_S) -#define SOC_ETM_CH_ENA18_V 0x00000001U -#define SOC_ETM_CH_ENA18_S 18 -/** SOC_ETM_CH_ENA19 : R/WTC/WTS; bitpos: [19]; default: 0; - * ch19 enable +#define SOC_ETM_CH_ENABLED18 (BIT(18)) +#define SOC_ETM_CH_ENABLED18_M (SOC_ETM_CH_ENABLED18_V << SOC_ETM_CH_ENABLED18_S) +#define SOC_ETM_CH_ENABLED18_V 0x00000001U +#define SOC_ETM_CH_ENABLED18_S 18 +/** SOC_ETM_CH_ENABLED19 : R/WTC/SS; bitpos: [19]; default: 0; + * Represents channel19 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA19 (BIT(19)) -#define SOC_ETM_CH_ENA19_M (SOC_ETM_CH_ENA19_V << SOC_ETM_CH_ENA19_S) -#define SOC_ETM_CH_ENA19_V 0x00000001U -#define SOC_ETM_CH_ENA19_S 19 -/** SOC_ETM_CH_ENA20 : R/WTC/WTS; bitpos: [20]; default: 0; - * ch20 enable +#define SOC_ETM_CH_ENABLED19 (BIT(19)) +#define SOC_ETM_CH_ENABLED19_M (SOC_ETM_CH_ENABLED19_V << SOC_ETM_CH_ENABLED19_S) +#define SOC_ETM_CH_ENABLED19_V 0x00000001U +#define SOC_ETM_CH_ENABLED19_S 19 +/** SOC_ETM_CH_ENABLED20 : R/WTC/SS; bitpos: [20]; default: 0; + * Represents channel20 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA20 (BIT(20)) -#define SOC_ETM_CH_ENA20_M (SOC_ETM_CH_ENA20_V << SOC_ETM_CH_ENA20_S) -#define SOC_ETM_CH_ENA20_V 0x00000001U -#define SOC_ETM_CH_ENA20_S 20 -/** SOC_ETM_CH_ENA21 : R/WTC/WTS; bitpos: [21]; default: 0; - * ch21 enable +#define SOC_ETM_CH_ENABLED20 (BIT(20)) +#define SOC_ETM_CH_ENABLED20_M (SOC_ETM_CH_ENABLED20_V << SOC_ETM_CH_ENABLED20_S) +#define SOC_ETM_CH_ENABLED20_V 0x00000001U +#define SOC_ETM_CH_ENABLED20_S 20 +/** SOC_ETM_CH_ENABLED21 : R/WTC/SS; bitpos: [21]; default: 0; + * Represents channel21 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA21 (BIT(21)) -#define SOC_ETM_CH_ENA21_M (SOC_ETM_CH_ENA21_V << SOC_ETM_CH_ENA21_S) -#define SOC_ETM_CH_ENA21_V 0x00000001U -#define SOC_ETM_CH_ENA21_S 21 -/** SOC_ETM_CH_ENA22 : R/WTC/WTS; bitpos: [22]; default: 0; - * ch22 enable +#define SOC_ETM_CH_ENABLED21 (BIT(21)) +#define SOC_ETM_CH_ENABLED21_M (SOC_ETM_CH_ENABLED21_V << SOC_ETM_CH_ENABLED21_S) +#define SOC_ETM_CH_ENABLED21_V 0x00000001U +#define SOC_ETM_CH_ENABLED21_S 21 +/** SOC_ETM_CH_ENABLED22 : R/WTC/SS; bitpos: [22]; default: 0; + * Represents channel22 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA22 (BIT(22)) -#define SOC_ETM_CH_ENA22_M (SOC_ETM_CH_ENA22_V << SOC_ETM_CH_ENA22_S) -#define SOC_ETM_CH_ENA22_V 0x00000001U -#define SOC_ETM_CH_ENA22_S 22 -/** SOC_ETM_CH_ENA23 : R/WTC/WTS; bitpos: [23]; default: 0; - * ch23 enable +#define SOC_ETM_CH_ENABLED22 (BIT(22)) +#define SOC_ETM_CH_ENABLED22_M (SOC_ETM_CH_ENABLED22_V << SOC_ETM_CH_ENABLED22_S) +#define SOC_ETM_CH_ENABLED22_V 0x00000001U +#define SOC_ETM_CH_ENABLED22_S 22 +/** SOC_ETM_CH_ENABLED23 : R/WTC/SS; bitpos: [23]; default: 0; + * Represents channel23 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA23 (BIT(23)) -#define SOC_ETM_CH_ENA23_M (SOC_ETM_CH_ENA23_V << SOC_ETM_CH_ENA23_S) -#define SOC_ETM_CH_ENA23_V 0x00000001U -#define SOC_ETM_CH_ENA23_S 23 -/** SOC_ETM_CH_ENA24 : R/WTC/WTS; bitpos: [24]; default: 0; - * ch24 enable +#define SOC_ETM_CH_ENABLED23 (BIT(23)) +#define SOC_ETM_CH_ENABLED23_M (SOC_ETM_CH_ENABLED23_V << SOC_ETM_CH_ENABLED23_S) +#define SOC_ETM_CH_ENABLED23_V 0x00000001U +#define SOC_ETM_CH_ENABLED23_S 23 +/** SOC_ETM_CH_ENABLED24 : R/WTC/SS; bitpos: [24]; default: 0; + * Represents channel24 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA24 (BIT(24)) -#define SOC_ETM_CH_ENA24_M (SOC_ETM_CH_ENA24_V << SOC_ETM_CH_ENA24_S) -#define SOC_ETM_CH_ENA24_V 0x00000001U -#define SOC_ETM_CH_ENA24_S 24 -/** SOC_ETM_CH_ENA25 : R/WTC/WTS; bitpos: [25]; default: 0; - * ch25 enable +#define SOC_ETM_CH_ENABLED24 (BIT(24)) +#define SOC_ETM_CH_ENABLED24_M (SOC_ETM_CH_ENABLED24_V << SOC_ETM_CH_ENABLED24_S) +#define SOC_ETM_CH_ENABLED24_V 0x00000001U +#define SOC_ETM_CH_ENABLED24_S 24 +/** SOC_ETM_CH_ENABLED25 : R/WTC/SS; bitpos: [25]; default: 0; + * Represents channel25 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA25 (BIT(25)) -#define SOC_ETM_CH_ENA25_M (SOC_ETM_CH_ENA25_V << SOC_ETM_CH_ENA25_S) -#define SOC_ETM_CH_ENA25_V 0x00000001U -#define SOC_ETM_CH_ENA25_S 25 -/** SOC_ETM_CH_ENA26 : R/WTC/WTS; bitpos: [26]; default: 0; - * ch26 enable +#define SOC_ETM_CH_ENABLED25 (BIT(25)) +#define SOC_ETM_CH_ENABLED25_M (SOC_ETM_CH_ENABLED25_V << SOC_ETM_CH_ENABLED25_S) +#define SOC_ETM_CH_ENABLED25_V 0x00000001U +#define SOC_ETM_CH_ENABLED25_S 25 +/** SOC_ETM_CH_ENABLED26 : R/WTC/SS; bitpos: [26]; default: 0; + * Represents channel26 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA26 (BIT(26)) -#define SOC_ETM_CH_ENA26_M (SOC_ETM_CH_ENA26_V << SOC_ETM_CH_ENA26_S) -#define SOC_ETM_CH_ENA26_V 0x00000001U -#define SOC_ETM_CH_ENA26_S 26 -/** SOC_ETM_CH_ENA27 : R/WTC/WTS; bitpos: [27]; default: 0; - * ch27 enable +#define SOC_ETM_CH_ENABLED26 (BIT(26)) +#define SOC_ETM_CH_ENABLED26_M (SOC_ETM_CH_ENABLED26_V << SOC_ETM_CH_ENABLED26_S) +#define SOC_ETM_CH_ENABLED26_V 0x00000001U +#define SOC_ETM_CH_ENABLED26_S 26 +/** SOC_ETM_CH_ENABLED27 : R/WTC/SS; bitpos: [27]; default: 0; + * Represents channel27 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA27 (BIT(27)) -#define SOC_ETM_CH_ENA27_M (SOC_ETM_CH_ENA27_V << SOC_ETM_CH_ENA27_S) -#define SOC_ETM_CH_ENA27_V 0x00000001U -#define SOC_ETM_CH_ENA27_S 27 -/** SOC_ETM_CH_ENA28 : R/WTC/WTS; bitpos: [28]; default: 0; - * ch28 enable +#define SOC_ETM_CH_ENABLED27 (BIT(27)) +#define SOC_ETM_CH_ENABLED27_M (SOC_ETM_CH_ENABLED27_V << SOC_ETM_CH_ENABLED27_S) +#define SOC_ETM_CH_ENABLED27_V 0x00000001U +#define SOC_ETM_CH_ENABLED27_S 27 +/** SOC_ETM_CH_ENABLED28 : R/WTC/SS; bitpos: [28]; default: 0; + * Represents channel28 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA28 (BIT(28)) -#define SOC_ETM_CH_ENA28_M (SOC_ETM_CH_ENA28_V << SOC_ETM_CH_ENA28_S) -#define SOC_ETM_CH_ENA28_V 0x00000001U -#define SOC_ETM_CH_ENA28_S 28 -/** SOC_ETM_CH_ENA29 : R/WTC/WTS; bitpos: [29]; default: 0; - * ch29 enable +#define SOC_ETM_CH_ENABLED28 (BIT(28)) +#define SOC_ETM_CH_ENABLED28_M (SOC_ETM_CH_ENABLED28_V << SOC_ETM_CH_ENABLED28_S) +#define SOC_ETM_CH_ENABLED28_V 0x00000001U +#define SOC_ETM_CH_ENABLED28_S 28 +/** SOC_ETM_CH_ENABLED29 : R/WTC/SS; bitpos: [29]; default: 0; + * Represents channel29 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA29 (BIT(29)) -#define SOC_ETM_CH_ENA29_M (SOC_ETM_CH_ENA29_V << SOC_ETM_CH_ENA29_S) -#define SOC_ETM_CH_ENA29_V 0x00000001U -#define SOC_ETM_CH_ENA29_S 29 -/** SOC_ETM_CH_ENA30 : R/WTC/WTS; bitpos: [30]; default: 0; - * ch30 enable +#define SOC_ETM_CH_ENABLED29 (BIT(29)) +#define SOC_ETM_CH_ENABLED29_M (SOC_ETM_CH_ENABLED29_V << SOC_ETM_CH_ENABLED29_S) +#define SOC_ETM_CH_ENABLED29_V 0x00000001U +#define SOC_ETM_CH_ENABLED29_S 29 +/** SOC_ETM_CH_ENABLED30 : R/WTC/SS; bitpos: [30]; default: 0; + * Represents channel30 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA30 (BIT(30)) -#define SOC_ETM_CH_ENA30_M (SOC_ETM_CH_ENA30_V << SOC_ETM_CH_ENA30_S) -#define SOC_ETM_CH_ENA30_V 0x00000001U -#define SOC_ETM_CH_ENA30_S 30 -/** SOC_ETM_CH_ENA31 : R/WTC/WTS; bitpos: [31]; default: 0; - * ch31 enable +#define SOC_ETM_CH_ENABLED30 (BIT(30)) +#define SOC_ETM_CH_ENABLED30_M (SOC_ETM_CH_ENABLED30_V << SOC_ETM_CH_ENABLED30_S) +#define SOC_ETM_CH_ENABLED30_V 0x00000001U +#define SOC_ETM_CH_ENABLED30_S 30 +/** SOC_ETM_CH_ENABLED31 : R/WTC/SS; bitpos: [31]; default: 0; + * Represents channel31 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA31 (BIT(31)) -#define SOC_ETM_CH_ENA31_M (SOC_ETM_CH_ENA31_V << SOC_ETM_CH_ENA31_S) -#define SOC_ETM_CH_ENA31_V 0x00000001U -#define SOC_ETM_CH_ENA31_S 31 +#define SOC_ETM_CH_ENABLED31 (BIT(31)) +#define SOC_ETM_CH_ENABLED31_M (SOC_ETM_CH_ENABLED31_V << SOC_ETM_CH_ENABLED31_S) +#define SOC_ETM_CH_ENABLED31_V 0x00000001U +#define SOC_ETM_CH_ENABLED31_S 31 /** SOC_ETM_CH_ENA_AD0_SET_REG register - * channel enable set register + * Channel enable register */ -#define SOC_ETM_CH_ENA_AD0_SET_REG (DR_REG_SOC_BASE + 0x4) -/** SOC_ETM_CH_SET0 : WT; bitpos: [0]; default: 0; - * ch0 set +#define SOC_ETM_CH_ENA_AD0_SET_REG (DR_REG_SOC_ETM_BASE + 0x4) +/** SOC_ETM_CH_ENABLE0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable channel0. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET0 (BIT(0)) -#define SOC_ETM_CH_SET0_M (SOC_ETM_CH_SET0_V << SOC_ETM_CH_SET0_S) -#define SOC_ETM_CH_SET0_V 0x00000001U -#define SOC_ETM_CH_SET0_S 0 -/** SOC_ETM_CH_SET1 : WT; bitpos: [1]; default: 0; - * ch1 set +#define SOC_ETM_CH_ENABLE0 (BIT(0)) +#define SOC_ETM_CH_ENABLE0_M (SOC_ETM_CH_ENABLE0_V << SOC_ETM_CH_ENABLE0_S) +#define SOC_ETM_CH_ENABLE0_V 0x00000001U +#define SOC_ETM_CH_ENABLE0_S 0 +/** SOC_ETM_CH_ENABLE1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable channel1. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET1 (BIT(1)) -#define SOC_ETM_CH_SET1_M (SOC_ETM_CH_SET1_V << SOC_ETM_CH_SET1_S) -#define SOC_ETM_CH_SET1_V 0x00000001U -#define SOC_ETM_CH_SET1_S 1 -/** SOC_ETM_CH_SET2 : WT; bitpos: [2]; default: 0; - * ch2 set +#define SOC_ETM_CH_ENABLE1 (BIT(1)) +#define SOC_ETM_CH_ENABLE1_M (SOC_ETM_CH_ENABLE1_V << SOC_ETM_CH_ENABLE1_S) +#define SOC_ETM_CH_ENABLE1_V 0x00000001U +#define SOC_ETM_CH_ENABLE1_S 1 +/** SOC_ETM_CH_ENABLE2 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable channel2. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET2 (BIT(2)) -#define SOC_ETM_CH_SET2_M (SOC_ETM_CH_SET2_V << SOC_ETM_CH_SET2_S) -#define SOC_ETM_CH_SET2_V 0x00000001U -#define SOC_ETM_CH_SET2_S 2 -/** SOC_ETM_CH_SET3 : WT; bitpos: [3]; default: 0; - * ch3 set +#define SOC_ETM_CH_ENABLE2 (BIT(2)) +#define SOC_ETM_CH_ENABLE2_M (SOC_ETM_CH_ENABLE2_V << SOC_ETM_CH_ENABLE2_S) +#define SOC_ETM_CH_ENABLE2_V 0x00000001U +#define SOC_ETM_CH_ENABLE2_S 2 +/** SOC_ETM_CH_ENABLE3 : WT; bitpos: [3]; default: 0; + * Configures whether or not to enable channel3. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET3 (BIT(3)) -#define SOC_ETM_CH_SET3_M (SOC_ETM_CH_SET3_V << SOC_ETM_CH_SET3_S) -#define SOC_ETM_CH_SET3_V 0x00000001U -#define SOC_ETM_CH_SET3_S 3 -/** SOC_ETM_CH_SET4 : WT; bitpos: [4]; default: 0; - * ch4 set +#define SOC_ETM_CH_ENABLE3 (BIT(3)) +#define SOC_ETM_CH_ENABLE3_M (SOC_ETM_CH_ENABLE3_V << SOC_ETM_CH_ENABLE3_S) +#define SOC_ETM_CH_ENABLE3_V 0x00000001U +#define SOC_ETM_CH_ENABLE3_S 3 +/** SOC_ETM_CH_ENABLE4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to enable channel4. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET4 (BIT(4)) -#define SOC_ETM_CH_SET4_M (SOC_ETM_CH_SET4_V << SOC_ETM_CH_SET4_S) -#define SOC_ETM_CH_SET4_V 0x00000001U -#define SOC_ETM_CH_SET4_S 4 -/** SOC_ETM_CH_SET5 : WT; bitpos: [5]; default: 0; - * ch5 set +#define SOC_ETM_CH_ENABLE4 (BIT(4)) +#define SOC_ETM_CH_ENABLE4_M (SOC_ETM_CH_ENABLE4_V << SOC_ETM_CH_ENABLE4_S) +#define SOC_ETM_CH_ENABLE4_V 0x00000001U +#define SOC_ETM_CH_ENABLE4_S 4 +/** SOC_ETM_CH_ENABLE5 : WT; bitpos: [5]; default: 0; + * Configures whether or not to enable channel5. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET5 (BIT(5)) -#define SOC_ETM_CH_SET5_M (SOC_ETM_CH_SET5_V << SOC_ETM_CH_SET5_S) -#define SOC_ETM_CH_SET5_V 0x00000001U -#define SOC_ETM_CH_SET5_S 5 -/** SOC_ETM_CH_SET6 : WT; bitpos: [6]; default: 0; - * ch6 set +#define SOC_ETM_CH_ENABLE5 (BIT(5)) +#define SOC_ETM_CH_ENABLE5_M (SOC_ETM_CH_ENABLE5_V << SOC_ETM_CH_ENABLE5_S) +#define SOC_ETM_CH_ENABLE5_V 0x00000001U +#define SOC_ETM_CH_ENABLE5_S 5 +/** SOC_ETM_CH_ENABLE6 : WT; bitpos: [6]; default: 0; + * Configures whether or not to enable channel6. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET6 (BIT(6)) -#define SOC_ETM_CH_SET6_M (SOC_ETM_CH_SET6_V << SOC_ETM_CH_SET6_S) -#define SOC_ETM_CH_SET6_V 0x00000001U -#define SOC_ETM_CH_SET6_S 6 -/** SOC_ETM_CH_SET7 : WT; bitpos: [7]; default: 0; - * ch7 set +#define SOC_ETM_CH_ENABLE6 (BIT(6)) +#define SOC_ETM_CH_ENABLE6_M (SOC_ETM_CH_ENABLE6_V << SOC_ETM_CH_ENABLE6_S) +#define SOC_ETM_CH_ENABLE6_V 0x00000001U +#define SOC_ETM_CH_ENABLE6_S 6 +/** SOC_ETM_CH_ENABLE7 : WT; bitpos: [7]; default: 0; + * Configures whether or not to enable channel7. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET7 (BIT(7)) -#define SOC_ETM_CH_SET7_M (SOC_ETM_CH_SET7_V << SOC_ETM_CH_SET7_S) -#define SOC_ETM_CH_SET7_V 0x00000001U -#define SOC_ETM_CH_SET7_S 7 -/** SOC_ETM_CH_SET8 : WT; bitpos: [8]; default: 0; - * ch8 set +#define SOC_ETM_CH_ENABLE7 (BIT(7)) +#define SOC_ETM_CH_ENABLE7_M (SOC_ETM_CH_ENABLE7_V << SOC_ETM_CH_ENABLE7_S) +#define SOC_ETM_CH_ENABLE7_V 0x00000001U +#define SOC_ETM_CH_ENABLE7_S 7 +/** SOC_ETM_CH_ENABLE8 : WT; bitpos: [8]; default: 0; + * Configures whether or not to enable channel8. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET8 (BIT(8)) -#define SOC_ETM_CH_SET8_M (SOC_ETM_CH_SET8_V << SOC_ETM_CH_SET8_S) -#define SOC_ETM_CH_SET8_V 0x00000001U -#define SOC_ETM_CH_SET8_S 8 -/** SOC_ETM_CH_SET9 : WT; bitpos: [9]; default: 0; - * ch9 set +#define SOC_ETM_CH_ENABLE8 (BIT(8)) +#define SOC_ETM_CH_ENABLE8_M (SOC_ETM_CH_ENABLE8_V << SOC_ETM_CH_ENABLE8_S) +#define SOC_ETM_CH_ENABLE8_V 0x00000001U +#define SOC_ETM_CH_ENABLE8_S 8 +/** SOC_ETM_CH_ENABLE9 : WT; bitpos: [9]; default: 0; + * Configures whether or not to enable channel9. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET9 (BIT(9)) -#define SOC_ETM_CH_SET9_M (SOC_ETM_CH_SET9_V << SOC_ETM_CH_SET9_S) -#define SOC_ETM_CH_SET9_V 0x00000001U -#define SOC_ETM_CH_SET9_S 9 -/** SOC_ETM_CH_SET10 : WT; bitpos: [10]; default: 0; - * ch10 set +#define SOC_ETM_CH_ENABLE9 (BIT(9)) +#define SOC_ETM_CH_ENABLE9_M (SOC_ETM_CH_ENABLE9_V << SOC_ETM_CH_ENABLE9_S) +#define SOC_ETM_CH_ENABLE9_V 0x00000001U +#define SOC_ETM_CH_ENABLE9_S 9 +/** SOC_ETM_CH_ENABLE10 : WT; bitpos: [10]; default: 0; + * Configures whether or not to enable channel10. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET10 (BIT(10)) -#define SOC_ETM_CH_SET10_M (SOC_ETM_CH_SET10_V << SOC_ETM_CH_SET10_S) -#define SOC_ETM_CH_SET10_V 0x00000001U -#define SOC_ETM_CH_SET10_S 10 -/** SOC_ETM_CH_SET11 : WT; bitpos: [11]; default: 0; - * ch11 set +#define SOC_ETM_CH_ENABLE10 (BIT(10)) +#define SOC_ETM_CH_ENABLE10_M (SOC_ETM_CH_ENABLE10_V << SOC_ETM_CH_ENABLE10_S) +#define SOC_ETM_CH_ENABLE10_V 0x00000001U +#define SOC_ETM_CH_ENABLE10_S 10 +/** SOC_ETM_CH_ENABLE11 : WT; bitpos: [11]; default: 0; + * Configures whether or not to enable channel11. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET11 (BIT(11)) -#define SOC_ETM_CH_SET11_M (SOC_ETM_CH_SET11_V << SOC_ETM_CH_SET11_S) -#define SOC_ETM_CH_SET11_V 0x00000001U -#define SOC_ETM_CH_SET11_S 11 -/** SOC_ETM_CH_SET12 : WT; bitpos: [12]; default: 0; - * ch12 set +#define SOC_ETM_CH_ENABLE11 (BIT(11)) +#define SOC_ETM_CH_ENABLE11_M (SOC_ETM_CH_ENABLE11_V << SOC_ETM_CH_ENABLE11_S) +#define SOC_ETM_CH_ENABLE11_V 0x00000001U +#define SOC_ETM_CH_ENABLE11_S 11 +/** SOC_ETM_CH_ENABLE12 : WT; bitpos: [12]; default: 0; + * Configures whether or not to enable channel12. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET12 (BIT(12)) -#define SOC_ETM_CH_SET12_M (SOC_ETM_CH_SET12_V << SOC_ETM_CH_SET12_S) -#define SOC_ETM_CH_SET12_V 0x00000001U -#define SOC_ETM_CH_SET12_S 12 -/** SOC_ETM_CH_SET13 : WT; bitpos: [13]; default: 0; - * ch13 set +#define SOC_ETM_CH_ENABLE12 (BIT(12)) +#define SOC_ETM_CH_ENABLE12_M (SOC_ETM_CH_ENABLE12_V << SOC_ETM_CH_ENABLE12_S) +#define SOC_ETM_CH_ENABLE12_V 0x00000001U +#define SOC_ETM_CH_ENABLE12_S 12 +/** SOC_ETM_CH_ENABLE13 : WT; bitpos: [13]; default: 0; + * Configures whether or not to enable channel13. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET13 (BIT(13)) -#define SOC_ETM_CH_SET13_M (SOC_ETM_CH_SET13_V << SOC_ETM_CH_SET13_S) -#define SOC_ETM_CH_SET13_V 0x00000001U -#define SOC_ETM_CH_SET13_S 13 -/** SOC_ETM_CH_SET14 : WT; bitpos: [14]; default: 0; - * ch14 set +#define SOC_ETM_CH_ENABLE13 (BIT(13)) +#define SOC_ETM_CH_ENABLE13_M (SOC_ETM_CH_ENABLE13_V << SOC_ETM_CH_ENABLE13_S) +#define SOC_ETM_CH_ENABLE13_V 0x00000001U +#define SOC_ETM_CH_ENABLE13_S 13 +/** SOC_ETM_CH_ENABLE14 : WT; bitpos: [14]; default: 0; + * Configures whether or not to enable channel14. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET14 (BIT(14)) -#define SOC_ETM_CH_SET14_M (SOC_ETM_CH_SET14_V << SOC_ETM_CH_SET14_S) -#define SOC_ETM_CH_SET14_V 0x00000001U -#define SOC_ETM_CH_SET14_S 14 -/** SOC_ETM_CH_SET15 : WT; bitpos: [15]; default: 0; - * ch15 set +#define SOC_ETM_CH_ENABLE14 (BIT(14)) +#define SOC_ETM_CH_ENABLE14_M (SOC_ETM_CH_ENABLE14_V << SOC_ETM_CH_ENABLE14_S) +#define SOC_ETM_CH_ENABLE14_V 0x00000001U +#define SOC_ETM_CH_ENABLE14_S 14 +/** SOC_ETM_CH_ENABLE15 : WT; bitpos: [15]; default: 0; + * Configures whether or not to enable channel15. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET15 (BIT(15)) -#define SOC_ETM_CH_SET15_M (SOC_ETM_CH_SET15_V << SOC_ETM_CH_SET15_S) -#define SOC_ETM_CH_SET15_V 0x00000001U -#define SOC_ETM_CH_SET15_S 15 -/** SOC_ETM_CH_SET16 : WT; bitpos: [16]; default: 0; - * ch16 set +#define SOC_ETM_CH_ENABLE15 (BIT(15)) +#define SOC_ETM_CH_ENABLE15_M (SOC_ETM_CH_ENABLE15_V << SOC_ETM_CH_ENABLE15_S) +#define SOC_ETM_CH_ENABLE15_V 0x00000001U +#define SOC_ETM_CH_ENABLE15_S 15 +/** SOC_ETM_CH_ENABLE16 : WT; bitpos: [16]; default: 0; + * Configures whether or not to enable channel16. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET16 (BIT(16)) -#define SOC_ETM_CH_SET16_M (SOC_ETM_CH_SET16_V << SOC_ETM_CH_SET16_S) -#define SOC_ETM_CH_SET16_V 0x00000001U -#define SOC_ETM_CH_SET16_S 16 -/** SOC_ETM_CH_SET17 : WT; bitpos: [17]; default: 0; - * ch17 set +#define SOC_ETM_CH_ENABLE16 (BIT(16)) +#define SOC_ETM_CH_ENABLE16_M (SOC_ETM_CH_ENABLE16_V << SOC_ETM_CH_ENABLE16_S) +#define SOC_ETM_CH_ENABLE16_V 0x00000001U +#define SOC_ETM_CH_ENABLE16_S 16 +/** SOC_ETM_CH_ENABLE17 : WT; bitpos: [17]; default: 0; + * Configures whether or not to enable channel17. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET17 (BIT(17)) -#define SOC_ETM_CH_SET17_M (SOC_ETM_CH_SET17_V << SOC_ETM_CH_SET17_S) -#define SOC_ETM_CH_SET17_V 0x00000001U -#define SOC_ETM_CH_SET17_S 17 -/** SOC_ETM_CH_SET18 : WT; bitpos: [18]; default: 0; - * ch18 set +#define SOC_ETM_CH_ENABLE17 (BIT(17)) +#define SOC_ETM_CH_ENABLE17_M (SOC_ETM_CH_ENABLE17_V << SOC_ETM_CH_ENABLE17_S) +#define SOC_ETM_CH_ENABLE17_V 0x00000001U +#define SOC_ETM_CH_ENABLE17_S 17 +/** SOC_ETM_CH_ENABLE18 : WT; bitpos: [18]; default: 0; + * Configures whether or not to enable channel18. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET18 (BIT(18)) -#define SOC_ETM_CH_SET18_M (SOC_ETM_CH_SET18_V << SOC_ETM_CH_SET18_S) -#define SOC_ETM_CH_SET18_V 0x00000001U -#define SOC_ETM_CH_SET18_S 18 -/** SOC_ETM_CH_SET19 : WT; bitpos: [19]; default: 0; - * ch19 set +#define SOC_ETM_CH_ENABLE18 (BIT(18)) +#define SOC_ETM_CH_ENABLE18_M (SOC_ETM_CH_ENABLE18_V << SOC_ETM_CH_ENABLE18_S) +#define SOC_ETM_CH_ENABLE18_V 0x00000001U +#define SOC_ETM_CH_ENABLE18_S 18 +/** SOC_ETM_CH_ENABLE19 : WT; bitpos: [19]; default: 0; + * Configures whether or not to enable channel19. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET19 (BIT(19)) -#define SOC_ETM_CH_SET19_M (SOC_ETM_CH_SET19_V << SOC_ETM_CH_SET19_S) -#define SOC_ETM_CH_SET19_V 0x00000001U -#define SOC_ETM_CH_SET19_S 19 -/** SOC_ETM_CH_SET20 : WT; bitpos: [20]; default: 0; - * ch20 set +#define SOC_ETM_CH_ENABLE19 (BIT(19)) +#define SOC_ETM_CH_ENABLE19_M (SOC_ETM_CH_ENABLE19_V << SOC_ETM_CH_ENABLE19_S) +#define SOC_ETM_CH_ENABLE19_V 0x00000001U +#define SOC_ETM_CH_ENABLE19_S 19 +/** SOC_ETM_CH_ENABLE20 : WT; bitpos: [20]; default: 0; + * Configures whether or not to enable channel20. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET20 (BIT(20)) -#define SOC_ETM_CH_SET20_M (SOC_ETM_CH_SET20_V << SOC_ETM_CH_SET20_S) -#define SOC_ETM_CH_SET20_V 0x00000001U -#define SOC_ETM_CH_SET20_S 20 -/** SOC_ETM_CH_SET21 : WT; bitpos: [21]; default: 0; - * ch21 set +#define SOC_ETM_CH_ENABLE20 (BIT(20)) +#define SOC_ETM_CH_ENABLE20_M (SOC_ETM_CH_ENABLE20_V << SOC_ETM_CH_ENABLE20_S) +#define SOC_ETM_CH_ENABLE20_V 0x00000001U +#define SOC_ETM_CH_ENABLE20_S 20 +/** SOC_ETM_CH_ENABLE21 : WT; bitpos: [21]; default: 0; + * Configures whether or not to enable channel21. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET21 (BIT(21)) -#define SOC_ETM_CH_SET21_M (SOC_ETM_CH_SET21_V << SOC_ETM_CH_SET21_S) -#define SOC_ETM_CH_SET21_V 0x00000001U -#define SOC_ETM_CH_SET21_S 21 -/** SOC_ETM_CH_SET22 : WT; bitpos: [22]; default: 0; - * ch22 set +#define SOC_ETM_CH_ENABLE21 (BIT(21)) +#define SOC_ETM_CH_ENABLE21_M (SOC_ETM_CH_ENABLE21_V << SOC_ETM_CH_ENABLE21_S) +#define SOC_ETM_CH_ENABLE21_V 0x00000001U +#define SOC_ETM_CH_ENABLE21_S 21 +/** SOC_ETM_CH_ENABLE22 : WT; bitpos: [22]; default: 0; + * Configures whether or not to enable channel22. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET22 (BIT(22)) -#define SOC_ETM_CH_SET22_M (SOC_ETM_CH_SET22_V << SOC_ETM_CH_SET22_S) -#define SOC_ETM_CH_SET22_V 0x00000001U -#define SOC_ETM_CH_SET22_S 22 -/** SOC_ETM_CH_SET23 : WT; bitpos: [23]; default: 0; - * ch23 set +#define SOC_ETM_CH_ENABLE22 (BIT(22)) +#define SOC_ETM_CH_ENABLE22_M (SOC_ETM_CH_ENABLE22_V << SOC_ETM_CH_ENABLE22_S) +#define SOC_ETM_CH_ENABLE22_V 0x00000001U +#define SOC_ETM_CH_ENABLE22_S 22 +/** SOC_ETM_CH_ENABLE23 : WT; bitpos: [23]; default: 0; + * Configures whether or not to enable channel23. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET23 (BIT(23)) -#define SOC_ETM_CH_SET23_M (SOC_ETM_CH_SET23_V << SOC_ETM_CH_SET23_S) -#define SOC_ETM_CH_SET23_V 0x00000001U -#define SOC_ETM_CH_SET23_S 23 -/** SOC_ETM_CH_SET24 : WT; bitpos: [24]; default: 0; - * ch24 set +#define SOC_ETM_CH_ENABLE23 (BIT(23)) +#define SOC_ETM_CH_ENABLE23_M (SOC_ETM_CH_ENABLE23_V << SOC_ETM_CH_ENABLE23_S) +#define SOC_ETM_CH_ENABLE23_V 0x00000001U +#define SOC_ETM_CH_ENABLE23_S 23 +/** SOC_ETM_CH_ENABLE24 : WT; bitpos: [24]; default: 0; + * Configures whether or not to enable channel24. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET24 (BIT(24)) -#define SOC_ETM_CH_SET24_M (SOC_ETM_CH_SET24_V << SOC_ETM_CH_SET24_S) -#define SOC_ETM_CH_SET24_V 0x00000001U -#define SOC_ETM_CH_SET24_S 24 -/** SOC_ETM_CH_SET25 : WT; bitpos: [25]; default: 0; - * ch25 set +#define SOC_ETM_CH_ENABLE24 (BIT(24)) +#define SOC_ETM_CH_ENABLE24_M (SOC_ETM_CH_ENABLE24_V << SOC_ETM_CH_ENABLE24_S) +#define SOC_ETM_CH_ENABLE24_V 0x00000001U +#define SOC_ETM_CH_ENABLE24_S 24 +/** SOC_ETM_CH_ENABLE25 : WT; bitpos: [25]; default: 0; + * Configures whether or not to enable channel25. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET25 (BIT(25)) -#define SOC_ETM_CH_SET25_M (SOC_ETM_CH_SET25_V << SOC_ETM_CH_SET25_S) -#define SOC_ETM_CH_SET25_V 0x00000001U -#define SOC_ETM_CH_SET25_S 25 -/** SOC_ETM_CH_SET26 : WT; bitpos: [26]; default: 0; - * ch26 set +#define SOC_ETM_CH_ENABLE25 (BIT(25)) +#define SOC_ETM_CH_ENABLE25_M (SOC_ETM_CH_ENABLE25_V << SOC_ETM_CH_ENABLE25_S) +#define SOC_ETM_CH_ENABLE25_V 0x00000001U +#define SOC_ETM_CH_ENABLE25_S 25 +/** SOC_ETM_CH_ENABLE26 : WT; bitpos: [26]; default: 0; + * Configures whether or not to enable channel26. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET26 (BIT(26)) -#define SOC_ETM_CH_SET26_M (SOC_ETM_CH_SET26_V << SOC_ETM_CH_SET26_S) -#define SOC_ETM_CH_SET26_V 0x00000001U -#define SOC_ETM_CH_SET26_S 26 -/** SOC_ETM_CH_SET27 : WT; bitpos: [27]; default: 0; - * ch27 set +#define SOC_ETM_CH_ENABLE26 (BIT(26)) +#define SOC_ETM_CH_ENABLE26_M (SOC_ETM_CH_ENABLE26_V << SOC_ETM_CH_ENABLE26_S) +#define SOC_ETM_CH_ENABLE26_V 0x00000001U +#define SOC_ETM_CH_ENABLE26_S 26 +/** SOC_ETM_CH_ENABLE27 : WT; bitpos: [27]; default: 0; + * Configures whether or not to enable channel27. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET27 (BIT(27)) -#define SOC_ETM_CH_SET27_M (SOC_ETM_CH_SET27_V << SOC_ETM_CH_SET27_S) -#define SOC_ETM_CH_SET27_V 0x00000001U -#define SOC_ETM_CH_SET27_S 27 -/** SOC_ETM_CH_SET28 : WT; bitpos: [28]; default: 0; - * ch28 set +#define SOC_ETM_CH_ENABLE27 (BIT(27)) +#define SOC_ETM_CH_ENABLE27_M (SOC_ETM_CH_ENABLE27_V << SOC_ETM_CH_ENABLE27_S) +#define SOC_ETM_CH_ENABLE27_V 0x00000001U +#define SOC_ETM_CH_ENABLE27_S 27 +/** SOC_ETM_CH_ENABLE28 : WT; bitpos: [28]; default: 0; + * Configures whether or not to enable channel28. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET28 (BIT(28)) -#define SOC_ETM_CH_SET28_M (SOC_ETM_CH_SET28_V << SOC_ETM_CH_SET28_S) -#define SOC_ETM_CH_SET28_V 0x00000001U -#define SOC_ETM_CH_SET28_S 28 -/** SOC_ETM_CH_SET29 : WT; bitpos: [29]; default: 0; - * ch29 set +#define SOC_ETM_CH_ENABLE28 (BIT(28)) +#define SOC_ETM_CH_ENABLE28_M (SOC_ETM_CH_ENABLE28_V << SOC_ETM_CH_ENABLE28_S) +#define SOC_ETM_CH_ENABLE28_V 0x00000001U +#define SOC_ETM_CH_ENABLE28_S 28 +/** SOC_ETM_CH_ENABLE29 : WT; bitpos: [29]; default: 0; + * Configures whether or not to enable channel29. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET29 (BIT(29)) -#define SOC_ETM_CH_SET29_M (SOC_ETM_CH_SET29_V << SOC_ETM_CH_SET29_S) -#define SOC_ETM_CH_SET29_V 0x00000001U -#define SOC_ETM_CH_SET29_S 29 -/** SOC_ETM_CH_SET30 : WT; bitpos: [30]; default: 0; - * ch30 set +#define SOC_ETM_CH_ENABLE29 (BIT(29)) +#define SOC_ETM_CH_ENABLE29_M (SOC_ETM_CH_ENABLE29_V << SOC_ETM_CH_ENABLE29_S) +#define SOC_ETM_CH_ENABLE29_V 0x00000001U +#define SOC_ETM_CH_ENABLE29_S 29 +/** SOC_ETM_CH_ENABLE30 : WT; bitpos: [30]; default: 0; + * Configures whether or not to enable channel30. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET30 (BIT(30)) -#define SOC_ETM_CH_SET30_M (SOC_ETM_CH_SET30_V << SOC_ETM_CH_SET30_S) -#define SOC_ETM_CH_SET30_V 0x00000001U -#define SOC_ETM_CH_SET30_S 30 -/** SOC_ETM_CH_SET31 : WT; bitpos: [31]; default: 0; - * ch31 set +#define SOC_ETM_CH_ENABLE30 (BIT(30)) +#define SOC_ETM_CH_ENABLE30_M (SOC_ETM_CH_ENABLE30_V << SOC_ETM_CH_ENABLE30_S) +#define SOC_ETM_CH_ENABLE30_V 0x00000001U +#define SOC_ETM_CH_ENABLE30_S 30 +/** SOC_ETM_CH_ENABLE31 : WT; bitpos: [31]; default: 0; + * Configures whether or not to enable channel31. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET31 (BIT(31)) -#define SOC_ETM_CH_SET31_M (SOC_ETM_CH_SET31_V << SOC_ETM_CH_SET31_S) -#define SOC_ETM_CH_SET31_V 0x00000001U -#define SOC_ETM_CH_SET31_S 31 +#define SOC_ETM_CH_ENABLE31 (BIT(31)) +#define SOC_ETM_CH_ENABLE31_M (SOC_ETM_CH_ENABLE31_V << SOC_ETM_CH_ENABLE31_S) +#define SOC_ETM_CH_ENABLE31_V 0x00000001U +#define SOC_ETM_CH_ENABLE31_S 31 /** SOC_ETM_CH_ENA_AD0_CLR_REG register - * channel enable clear register + * Channel disable register */ -#define SOC_ETM_CH_ENA_AD0_CLR_REG (DR_REG_SOC_BASE + 0x8) -/** SOC_ETM_CH_CLR0 : WT; bitpos: [0]; default: 0; - * ch0 clear +#define SOC_ETM_CH_ENA_AD0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x8) +/** SOC_ETM_CH_DISABLE0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to disable channel0. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR0 (BIT(0)) -#define SOC_ETM_CH_CLR0_M (SOC_ETM_CH_CLR0_V << SOC_ETM_CH_CLR0_S) -#define SOC_ETM_CH_CLR0_V 0x00000001U -#define SOC_ETM_CH_CLR0_S 0 -/** SOC_ETM_CH_CLR1 : WT; bitpos: [1]; default: 0; - * ch1 clear +#define SOC_ETM_CH_DISABLE0 (BIT(0)) +#define SOC_ETM_CH_DISABLE0_M (SOC_ETM_CH_DISABLE0_V << SOC_ETM_CH_DISABLE0_S) +#define SOC_ETM_CH_DISABLE0_V 0x00000001U +#define SOC_ETM_CH_DISABLE0_S 0 +/** SOC_ETM_CH_DISABLE1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to disable channel1. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR1 (BIT(1)) -#define SOC_ETM_CH_CLR1_M (SOC_ETM_CH_CLR1_V << SOC_ETM_CH_CLR1_S) -#define SOC_ETM_CH_CLR1_V 0x00000001U -#define SOC_ETM_CH_CLR1_S 1 -/** SOC_ETM_CH_CLR2 : WT; bitpos: [2]; default: 0; - * ch2 clear +#define SOC_ETM_CH_DISABLE1 (BIT(1)) +#define SOC_ETM_CH_DISABLE1_M (SOC_ETM_CH_DISABLE1_V << SOC_ETM_CH_DISABLE1_S) +#define SOC_ETM_CH_DISABLE1_V 0x00000001U +#define SOC_ETM_CH_DISABLE1_S 1 +/** SOC_ETM_CH_DISABLE2 : WT; bitpos: [2]; default: 0; + * Configures whether or not to disable channel2. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR2 (BIT(2)) -#define SOC_ETM_CH_CLR2_M (SOC_ETM_CH_CLR2_V << SOC_ETM_CH_CLR2_S) -#define SOC_ETM_CH_CLR2_V 0x00000001U -#define SOC_ETM_CH_CLR2_S 2 -/** SOC_ETM_CH_CLR3 : WT; bitpos: [3]; default: 0; - * ch3 clear +#define SOC_ETM_CH_DISABLE2 (BIT(2)) +#define SOC_ETM_CH_DISABLE2_M (SOC_ETM_CH_DISABLE2_V << SOC_ETM_CH_DISABLE2_S) +#define SOC_ETM_CH_DISABLE2_V 0x00000001U +#define SOC_ETM_CH_DISABLE2_S 2 +/** SOC_ETM_CH_DISABLE3 : WT; bitpos: [3]; default: 0; + * Configures whether or not to disable channel3. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR3 (BIT(3)) -#define SOC_ETM_CH_CLR3_M (SOC_ETM_CH_CLR3_V << SOC_ETM_CH_CLR3_S) -#define SOC_ETM_CH_CLR3_V 0x00000001U -#define SOC_ETM_CH_CLR3_S 3 -/** SOC_ETM_CH_CLR4 : WT; bitpos: [4]; default: 0; - * ch4 clear +#define SOC_ETM_CH_DISABLE3 (BIT(3)) +#define SOC_ETM_CH_DISABLE3_M (SOC_ETM_CH_DISABLE3_V << SOC_ETM_CH_DISABLE3_S) +#define SOC_ETM_CH_DISABLE3_V 0x00000001U +#define SOC_ETM_CH_DISABLE3_S 3 +/** SOC_ETM_CH_DISABLE4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to disable channel4. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR4 (BIT(4)) -#define SOC_ETM_CH_CLR4_M (SOC_ETM_CH_CLR4_V << SOC_ETM_CH_CLR4_S) -#define SOC_ETM_CH_CLR4_V 0x00000001U -#define SOC_ETM_CH_CLR4_S 4 -/** SOC_ETM_CH_CLR5 : WT; bitpos: [5]; default: 0; - * ch5 clear +#define SOC_ETM_CH_DISABLE4 (BIT(4)) +#define SOC_ETM_CH_DISABLE4_M (SOC_ETM_CH_DISABLE4_V << SOC_ETM_CH_DISABLE4_S) +#define SOC_ETM_CH_DISABLE4_V 0x00000001U +#define SOC_ETM_CH_DISABLE4_S 4 +/** SOC_ETM_CH_DISABLE5 : WT; bitpos: [5]; default: 0; + * Configures whether or not to disable channel5. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR5 (BIT(5)) -#define SOC_ETM_CH_CLR5_M (SOC_ETM_CH_CLR5_V << SOC_ETM_CH_CLR5_S) -#define SOC_ETM_CH_CLR5_V 0x00000001U -#define SOC_ETM_CH_CLR5_S 5 -/** SOC_ETM_CH_CLR6 : WT; bitpos: [6]; default: 0; - * ch6 clear +#define SOC_ETM_CH_DISABLE5 (BIT(5)) +#define SOC_ETM_CH_DISABLE5_M (SOC_ETM_CH_DISABLE5_V << SOC_ETM_CH_DISABLE5_S) +#define SOC_ETM_CH_DISABLE5_V 0x00000001U +#define SOC_ETM_CH_DISABLE5_S 5 +/** SOC_ETM_CH_DISABLE6 : WT; bitpos: [6]; default: 0; + * Configures whether or not to disable channel6. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR6 (BIT(6)) -#define SOC_ETM_CH_CLR6_M (SOC_ETM_CH_CLR6_V << SOC_ETM_CH_CLR6_S) -#define SOC_ETM_CH_CLR6_V 0x00000001U -#define SOC_ETM_CH_CLR6_S 6 -/** SOC_ETM_CH_CLR7 : WT; bitpos: [7]; default: 0; - * ch7 clear +#define SOC_ETM_CH_DISABLE6 (BIT(6)) +#define SOC_ETM_CH_DISABLE6_M (SOC_ETM_CH_DISABLE6_V << SOC_ETM_CH_DISABLE6_S) +#define SOC_ETM_CH_DISABLE6_V 0x00000001U +#define SOC_ETM_CH_DISABLE6_S 6 +/** SOC_ETM_CH_DISABLE7 : WT; bitpos: [7]; default: 0; + * Configures whether or not to disable channel7. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR7 (BIT(7)) -#define SOC_ETM_CH_CLR7_M (SOC_ETM_CH_CLR7_V << SOC_ETM_CH_CLR7_S) -#define SOC_ETM_CH_CLR7_V 0x00000001U -#define SOC_ETM_CH_CLR7_S 7 -/** SOC_ETM_CH_CLR8 : WT; bitpos: [8]; default: 0; - * ch8 clear +#define SOC_ETM_CH_DISABLE7 (BIT(7)) +#define SOC_ETM_CH_DISABLE7_M (SOC_ETM_CH_DISABLE7_V << SOC_ETM_CH_DISABLE7_S) +#define SOC_ETM_CH_DISABLE7_V 0x00000001U +#define SOC_ETM_CH_DISABLE7_S 7 +/** SOC_ETM_CH_DISABLE8 : WT; bitpos: [8]; default: 0; + * Configures whether or not to disable channel8. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR8 (BIT(8)) -#define SOC_ETM_CH_CLR8_M (SOC_ETM_CH_CLR8_V << SOC_ETM_CH_CLR8_S) -#define SOC_ETM_CH_CLR8_V 0x00000001U -#define SOC_ETM_CH_CLR8_S 8 -/** SOC_ETM_CH_CLR9 : WT; bitpos: [9]; default: 0; - * ch9 clear +#define SOC_ETM_CH_DISABLE8 (BIT(8)) +#define SOC_ETM_CH_DISABLE8_M (SOC_ETM_CH_DISABLE8_V << SOC_ETM_CH_DISABLE8_S) +#define SOC_ETM_CH_DISABLE8_V 0x00000001U +#define SOC_ETM_CH_DISABLE8_S 8 +/** SOC_ETM_CH_DISABLE9 : WT; bitpos: [9]; default: 0; + * Configures whether or not to disable channel9. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR9 (BIT(9)) -#define SOC_ETM_CH_CLR9_M (SOC_ETM_CH_CLR9_V << SOC_ETM_CH_CLR9_S) -#define SOC_ETM_CH_CLR9_V 0x00000001U -#define SOC_ETM_CH_CLR9_S 9 -/** SOC_ETM_CH_CLR10 : WT; bitpos: [10]; default: 0; - * ch10 clear +#define SOC_ETM_CH_DISABLE9 (BIT(9)) +#define SOC_ETM_CH_DISABLE9_M (SOC_ETM_CH_DISABLE9_V << SOC_ETM_CH_DISABLE9_S) +#define SOC_ETM_CH_DISABLE9_V 0x00000001U +#define SOC_ETM_CH_DISABLE9_S 9 +/** SOC_ETM_CH_DISABLE10 : WT; bitpos: [10]; default: 0; + * Configures whether or not to disable channel10. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR10 (BIT(10)) -#define SOC_ETM_CH_CLR10_M (SOC_ETM_CH_CLR10_V << SOC_ETM_CH_CLR10_S) -#define SOC_ETM_CH_CLR10_V 0x00000001U -#define SOC_ETM_CH_CLR10_S 10 -/** SOC_ETM_CH_CLR11 : WT; bitpos: [11]; default: 0; - * ch11 clear +#define SOC_ETM_CH_DISABLE10 (BIT(10)) +#define SOC_ETM_CH_DISABLE10_M (SOC_ETM_CH_DISABLE10_V << SOC_ETM_CH_DISABLE10_S) +#define SOC_ETM_CH_DISABLE10_V 0x00000001U +#define SOC_ETM_CH_DISABLE10_S 10 +/** SOC_ETM_CH_DISABLE11 : WT; bitpos: [11]; default: 0; + * Configures whether or not to disable channel11. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR11 (BIT(11)) -#define SOC_ETM_CH_CLR11_M (SOC_ETM_CH_CLR11_V << SOC_ETM_CH_CLR11_S) -#define SOC_ETM_CH_CLR11_V 0x00000001U -#define SOC_ETM_CH_CLR11_S 11 -/** SOC_ETM_CH_CLR12 : WT; bitpos: [12]; default: 0; - * ch12 clear +#define SOC_ETM_CH_DISABLE11 (BIT(11)) +#define SOC_ETM_CH_DISABLE11_M (SOC_ETM_CH_DISABLE11_V << SOC_ETM_CH_DISABLE11_S) +#define SOC_ETM_CH_DISABLE11_V 0x00000001U +#define SOC_ETM_CH_DISABLE11_S 11 +/** SOC_ETM_CH_DISABLE12 : WT; bitpos: [12]; default: 0; + * Configures whether or not to disable channel12. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR12 (BIT(12)) -#define SOC_ETM_CH_CLR12_M (SOC_ETM_CH_CLR12_V << SOC_ETM_CH_CLR12_S) -#define SOC_ETM_CH_CLR12_V 0x00000001U -#define SOC_ETM_CH_CLR12_S 12 -/** SOC_ETM_CH_CLR13 : WT; bitpos: [13]; default: 0; - * ch13 clear +#define SOC_ETM_CH_DISABLE12 (BIT(12)) +#define SOC_ETM_CH_DISABLE12_M (SOC_ETM_CH_DISABLE12_V << SOC_ETM_CH_DISABLE12_S) +#define SOC_ETM_CH_DISABLE12_V 0x00000001U +#define SOC_ETM_CH_DISABLE12_S 12 +/** SOC_ETM_CH_DISABLE13 : WT; bitpos: [13]; default: 0; + * Configures whether or not to disable channel13. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR13 (BIT(13)) -#define SOC_ETM_CH_CLR13_M (SOC_ETM_CH_CLR13_V << SOC_ETM_CH_CLR13_S) -#define SOC_ETM_CH_CLR13_V 0x00000001U -#define SOC_ETM_CH_CLR13_S 13 -/** SOC_ETM_CH_CLR14 : WT; bitpos: [14]; default: 0; - * ch14 clear +#define SOC_ETM_CH_DISABLE13 (BIT(13)) +#define SOC_ETM_CH_DISABLE13_M (SOC_ETM_CH_DISABLE13_V << SOC_ETM_CH_DISABLE13_S) +#define SOC_ETM_CH_DISABLE13_V 0x00000001U +#define SOC_ETM_CH_DISABLE13_S 13 +/** SOC_ETM_CH_DISABLE14 : WT; bitpos: [14]; default: 0; + * Configures whether or not to disable channel14. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR14 (BIT(14)) -#define SOC_ETM_CH_CLR14_M (SOC_ETM_CH_CLR14_V << SOC_ETM_CH_CLR14_S) -#define SOC_ETM_CH_CLR14_V 0x00000001U -#define SOC_ETM_CH_CLR14_S 14 -/** SOC_ETM_CH_CLR15 : WT; bitpos: [15]; default: 0; - * ch15 clear +#define SOC_ETM_CH_DISABLE14 (BIT(14)) +#define SOC_ETM_CH_DISABLE14_M (SOC_ETM_CH_DISABLE14_V << SOC_ETM_CH_DISABLE14_S) +#define SOC_ETM_CH_DISABLE14_V 0x00000001U +#define SOC_ETM_CH_DISABLE14_S 14 +/** SOC_ETM_CH_DISABLE15 : WT; bitpos: [15]; default: 0; + * Configures whether or not to disable channel15. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR15 (BIT(15)) -#define SOC_ETM_CH_CLR15_M (SOC_ETM_CH_CLR15_V << SOC_ETM_CH_CLR15_S) -#define SOC_ETM_CH_CLR15_V 0x00000001U -#define SOC_ETM_CH_CLR15_S 15 -/** SOC_ETM_CH_CLR16 : WT; bitpos: [16]; default: 0; - * ch16 clear +#define SOC_ETM_CH_DISABLE15 (BIT(15)) +#define SOC_ETM_CH_DISABLE15_M (SOC_ETM_CH_DISABLE15_V << SOC_ETM_CH_DISABLE15_S) +#define SOC_ETM_CH_DISABLE15_V 0x00000001U +#define SOC_ETM_CH_DISABLE15_S 15 +/** SOC_ETM_CH_DISABLE16 : WT; bitpos: [16]; default: 0; + * Configures whether or not to disable channel16. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR16 (BIT(16)) -#define SOC_ETM_CH_CLR16_M (SOC_ETM_CH_CLR16_V << SOC_ETM_CH_CLR16_S) -#define SOC_ETM_CH_CLR16_V 0x00000001U -#define SOC_ETM_CH_CLR16_S 16 -/** SOC_ETM_CH_CLR17 : WT; bitpos: [17]; default: 0; - * ch17 clear +#define SOC_ETM_CH_DISABLE16 (BIT(16)) +#define SOC_ETM_CH_DISABLE16_M (SOC_ETM_CH_DISABLE16_V << SOC_ETM_CH_DISABLE16_S) +#define SOC_ETM_CH_DISABLE16_V 0x00000001U +#define SOC_ETM_CH_DISABLE16_S 16 +/** SOC_ETM_CH_DISABLE17 : WT; bitpos: [17]; default: 0; + * Configures whether or not to disable channel17. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR17 (BIT(17)) -#define SOC_ETM_CH_CLR17_M (SOC_ETM_CH_CLR17_V << SOC_ETM_CH_CLR17_S) -#define SOC_ETM_CH_CLR17_V 0x00000001U -#define SOC_ETM_CH_CLR17_S 17 -/** SOC_ETM_CH_CLR18 : WT; bitpos: [18]; default: 0; - * ch18 clear +#define SOC_ETM_CH_DISABLE17 (BIT(17)) +#define SOC_ETM_CH_DISABLE17_M (SOC_ETM_CH_DISABLE17_V << SOC_ETM_CH_DISABLE17_S) +#define SOC_ETM_CH_DISABLE17_V 0x00000001U +#define SOC_ETM_CH_DISABLE17_S 17 +/** SOC_ETM_CH_DISABLE18 : WT; bitpos: [18]; default: 0; + * Configures whether or not to disable channel18. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR18 (BIT(18)) -#define SOC_ETM_CH_CLR18_M (SOC_ETM_CH_CLR18_V << SOC_ETM_CH_CLR18_S) -#define SOC_ETM_CH_CLR18_V 0x00000001U -#define SOC_ETM_CH_CLR18_S 18 -/** SOC_ETM_CH_CLR19 : WT; bitpos: [19]; default: 0; - * ch19 clear +#define SOC_ETM_CH_DISABLE18 (BIT(18)) +#define SOC_ETM_CH_DISABLE18_M (SOC_ETM_CH_DISABLE18_V << SOC_ETM_CH_DISABLE18_S) +#define SOC_ETM_CH_DISABLE18_V 0x00000001U +#define SOC_ETM_CH_DISABLE18_S 18 +/** SOC_ETM_CH_DISABLE19 : WT; bitpos: [19]; default: 0; + * Configures whether or not to disable channel19. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR19 (BIT(19)) -#define SOC_ETM_CH_CLR19_M (SOC_ETM_CH_CLR19_V << SOC_ETM_CH_CLR19_S) -#define SOC_ETM_CH_CLR19_V 0x00000001U -#define SOC_ETM_CH_CLR19_S 19 -/** SOC_ETM_CH_CLR20 : WT; bitpos: [20]; default: 0; - * ch20 clear +#define SOC_ETM_CH_DISABLE19 (BIT(19)) +#define SOC_ETM_CH_DISABLE19_M (SOC_ETM_CH_DISABLE19_V << SOC_ETM_CH_DISABLE19_S) +#define SOC_ETM_CH_DISABLE19_V 0x00000001U +#define SOC_ETM_CH_DISABLE19_S 19 +/** SOC_ETM_CH_DISABLE20 : WT; bitpos: [20]; default: 0; + * Configures whether or not to disable channel20. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR20 (BIT(20)) -#define SOC_ETM_CH_CLR20_M (SOC_ETM_CH_CLR20_V << SOC_ETM_CH_CLR20_S) -#define SOC_ETM_CH_CLR20_V 0x00000001U -#define SOC_ETM_CH_CLR20_S 20 -/** SOC_ETM_CH_CLR21 : WT; bitpos: [21]; default: 0; - * ch21 clear +#define SOC_ETM_CH_DISABLE20 (BIT(20)) +#define SOC_ETM_CH_DISABLE20_M (SOC_ETM_CH_DISABLE20_V << SOC_ETM_CH_DISABLE20_S) +#define SOC_ETM_CH_DISABLE20_V 0x00000001U +#define SOC_ETM_CH_DISABLE20_S 20 +/** SOC_ETM_CH_DISABLE21 : WT; bitpos: [21]; default: 0; + * Configures whether or not to disable channel21. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR21 (BIT(21)) -#define SOC_ETM_CH_CLR21_M (SOC_ETM_CH_CLR21_V << SOC_ETM_CH_CLR21_S) -#define SOC_ETM_CH_CLR21_V 0x00000001U -#define SOC_ETM_CH_CLR21_S 21 -/** SOC_ETM_CH_CLR22 : WT; bitpos: [22]; default: 0; - * ch22 clear +#define SOC_ETM_CH_DISABLE21 (BIT(21)) +#define SOC_ETM_CH_DISABLE21_M (SOC_ETM_CH_DISABLE21_V << SOC_ETM_CH_DISABLE21_S) +#define SOC_ETM_CH_DISABLE21_V 0x00000001U +#define SOC_ETM_CH_DISABLE21_S 21 +/** SOC_ETM_CH_DISABLE22 : WT; bitpos: [22]; default: 0; + * Configures whether or not to disable channel22. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR22 (BIT(22)) -#define SOC_ETM_CH_CLR22_M (SOC_ETM_CH_CLR22_V << SOC_ETM_CH_CLR22_S) -#define SOC_ETM_CH_CLR22_V 0x00000001U -#define SOC_ETM_CH_CLR22_S 22 -/** SOC_ETM_CH_CLR23 : WT; bitpos: [23]; default: 0; - * ch23 clear +#define SOC_ETM_CH_DISABLE22 (BIT(22)) +#define SOC_ETM_CH_DISABLE22_M (SOC_ETM_CH_DISABLE22_V << SOC_ETM_CH_DISABLE22_S) +#define SOC_ETM_CH_DISABLE22_V 0x00000001U +#define SOC_ETM_CH_DISABLE22_S 22 +/** SOC_ETM_CH_DISABLE23 : WT; bitpos: [23]; default: 0; + * Configures whether or not to disable channel23. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR23 (BIT(23)) -#define SOC_ETM_CH_CLR23_M (SOC_ETM_CH_CLR23_V << SOC_ETM_CH_CLR23_S) -#define SOC_ETM_CH_CLR23_V 0x00000001U -#define SOC_ETM_CH_CLR23_S 23 -/** SOC_ETM_CH_CLR24 : WT; bitpos: [24]; default: 0; - * ch24 clear +#define SOC_ETM_CH_DISABLE23 (BIT(23)) +#define SOC_ETM_CH_DISABLE23_M (SOC_ETM_CH_DISABLE23_V << SOC_ETM_CH_DISABLE23_S) +#define SOC_ETM_CH_DISABLE23_V 0x00000001U +#define SOC_ETM_CH_DISABLE23_S 23 +/** SOC_ETM_CH_DISABLE24 : WT; bitpos: [24]; default: 0; + * Configures whether or not to disable channel24. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR24 (BIT(24)) -#define SOC_ETM_CH_CLR24_M (SOC_ETM_CH_CLR24_V << SOC_ETM_CH_CLR24_S) -#define SOC_ETM_CH_CLR24_V 0x00000001U -#define SOC_ETM_CH_CLR24_S 24 -/** SOC_ETM_CH_CLR25 : WT; bitpos: [25]; default: 0; - * ch25 clear +#define SOC_ETM_CH_DISABLE24 (BIT(24)) +#define SOC_ETM_CH_DISABLE24_M (SOC_ETM_CH_DISABLE24_V << SOC_ETM_CH_DISABLE24_S) +#define SOC_ETM_CH_DISABLE24_V 0x00000001U +#define SOC_ETM_CH_DISABLE24_S 24 +/** SOC_ETM_CH_DISABLE25 : WT; bitpos: [25]; default: 0; + * Configures whether or not to disable channel25. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR25 (BIT(25)) -#define SOC_ETM_CH_CLR25_M (SOC_ETM_CH_CLR25_V << SOC_ETM_CH_CLR25_S) -#define SOC_ETM_CH_CLR25_V 0x00000001U -#define SOC_ETM_CH_CLR25_S 25 -/** SOC_ETM_CH_CLR26 : WT; bitpos: [26]; default: 0; - * ch26 clear +#define SOC_ETM_CH_DISABLE25 (BIT(25)) +#define SOC_ETM_CH_DISABLE25_M (SOC_ETM_CH_DISABLE25_V << SOC_ETM_CH_DISABLE25_S) +#define SOC_ETM_CH_DISABLE25_V 0x00000001U +#define SOC_ETM_CH_DISABLE25_S 25 +/** SOC_ETM_CH_DISABLE26 : WT; bitpos: [26]; default: 0; + * Configures whether or not to disable channel26. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR26 (BIT(26)) -#define SOC_ETM_CH_CLR26_M (SOC_ETM_CH_CLR26_V << SOC_ETM_CH_CLR26_S) -#define SOC_ETM_CH_CLR26_V 0x00000001U -#define SOC_ETM_CH_CLR26_S 26 -/** SOC_ETM_CH_CLR27 : WT; bitpos: [27]; default: 0; - * ch27 clear +#define SOC_ETM_CH_DISABLE26 (BIT(26)) +#define SOC_ETM_CH_DISABLE26_M (SOC_ETM_CH_DISABLE26_V << SOC_ETM_CH_DISABLE26_S) +#define SOC_ETM_CH_DISABLE26_V 0x00000001U +#define SOC_ETM_CH_DISABLE26_S 26 +/** SOC_ETM_CH_DISABLE27 : WT; bitpos: [27]; default: 0; + * Configures whether or not to disable channel27. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR27 (BIT(27)) -#define SOC_ETM_CH_CLR27_M (SOC_ETM_CH_CLR27_V << SOC_ETM_CH_CLR27_S) -#define SOC_ETM_CH_CLR27_V 0x00000001U -#define SOC_ETM_CH_CLR27_S 27 -/** SOC_ETM_CH_CLR28 : WT; bitpos: [28]; default: 0; - * ch28 clear +#define SOC_ETM_CH_DISABLE27 (BIT(27)) +#define SOC_ETM_CH_DISABLE27_M (SOC_ETM_CH_DISABLE27_V << SOC_ETM_CH_DISABLE27_S) +#define SOC_ETM_CH_DISABLE27_V 0x00000001U +#define SOC_ETM_CH_DISABLE27_S 27 +/** SOC_ETM_CH_DISABLE28 : WT; bitpos: [28]; default: 0; + * Configures whether or not to disable channel28. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR28 (BIT(28)) -#define SOC_ETM_CH_CLR28_M (SOC_ETM_CH_CLR28_V << SOC_ETM_CH_CLR28_S) -#define SOC_ETM_CH_CLR28_V 0x00000001U -#define SOC_ETM_CH_CLR28_S 28 -/** SOC_ETM_CH_CLR29 : WT; bitpos: [29]; default: 0; - * ch29 clear +#define SOC_ETM_CH_DISABLE28 (BIT(28)) +#define SOC_ETM_CH_DISABLE28_M (SOC_ETM_CH_DISABLE28_V << SOC_ETM_CH_DISABLE28_S) +#define SOC_ETM_CH_DISABLE28_V 0x00000001U +#define SOC_ETM_CH_DISABLE28_S 28 +/** SOC_ETM_CH_DISABLE29 : WT; bitpos: [29]; default: 0; + * Configures whether or not to disable channel29. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR29 (BIT(29)) -#define SOC_ETM_CH_CLR29_M (SOC_ETM_CH_CLR29_V << SOC_ETM_CH_CLR29_S) -#define SOC_ETM_CH_CLR29_V 0x00000001U -#define SOC_ETM_CH_CLR29_S 29 -/** SOC_ETM_CH_CLR30 : WT; bitpos: [30]; default: 0; - * ch30 clear +#define SOC_ETM_CH_DISABLE29 (BIT(29)) +#define SOC_ETM_CH_DISABLE29_M (SOC_ETM_CH_DISABLE29_V << SOC_ETM_CH_DISABLE29_S) +#define SOC_ETM_CH_DISABLE29_V 0x00000001U +#define SOC_ETM_CH_DISABLE29_S 29 +/** SOC_ETM_CH_DISABLE30 : WT; bitpos: [30]; default: 0; + * Configures whether or not to disable channel30. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR30 (BIT(30)) -#define SOC_ETM_CH_CLR30_M (SOC_ETM_CH_CLR30_V << SOC_ETM_CH_CLR30_S) -#define SOC_ETM_CH_CLR30_V 0x00000001U -#define SOC_ETM_CH_CLR30_S 30 -/** SOC_ETM_CH_CLR31 : WT; bitpos: [31]; default: 0; - * ch31 clear +#define SOC_ETM_CH_DISABLE30 (BIT(30)) +#define SOC_ETM_CH_DISABLE30_M (SOC_ETM_CH_DISABLE30_V << SOC_ETM_CH_DISABLE30_S) +#define SOC_ETM_CH_DISABLE30_V 0x00000001U +#define SOC_ETM_CH_DISABLE30_S 30 +/** SOC_ETM_CH_DISABLE31 : WT; bitpos: [31]; default: 0; + * Configures whether or not to disable channel31. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR31 (BIT(31)) -#define SOC_ETM_CH_CLR31_M (SOC_ETM_CH_CLR31_V << SOC_ETM_CH_CLR31_S) -#define SOC_ETM_CH_CLR31_V 0x00000001U -#define SOC_ETM_CH_CLR31_S 31 +#define SOC_ETM_CH_DISABLE31 (BIT(31)) +#define SOC_ETM_CH_DISABLE31_M (SOC_ETM_CH_DISABLE31_V << SOC_ETM_CH_DISABLE31_S) +#define SOC_ETM_CH_DISABLE31_V 0x00000001U +#define SOC_ETM_CH_DISABLE31_S 31 /** SOC_ETM_CH_ENA_AD1_REG register - * channel enable register + * Channel enable status register */ -#define SOC_ETM_CH_ENA_AD1_REG (DR_REG_SOC_BASE + 0xc) -/** SOC_ETM_CH_ENA32 : R/WTC/WTS; bitpos: [0]; default: 0; - * ch32 enable +#define SOC_ETM_CH_ENA_AD1_REG (DR_REG_SOC_ETM_BASE + 0xc) +/** SOC_ETM_CH_ENABLED32 : R/WTC/SS; bitpos: [0]; default: 0; + * Represents channel32 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA32 (BIT(0)) -#define SOC_ETM_CH_ENA32_M (SOC_ETM_CH_ENA32_V << SOC_ETM_CH_ENA32_S) -#define SOC_ETM_CH_ENA32_V 0x00000001U -#define SOC_ETM_CH_ENA32_S 0 -/** SOC_ETM_CH_ENA33 : R/WTC/WTS; bitpos: [1]; default: 0; - * ch33 enable +#define SOC_ETM_CH_ENABLED32 (BIT(0)) +#define SOC_ETM_CH_ENABLED32_M (SOC_ETM_CH_ENABLED32_V << SOC_ETM_CH_ENABLED32_S) +#define SOC_ETM_CH_ENABLED32_V 0x00000001U +#define SOC_ETM_CH_ENABLED32_S 0 +/** SOC_ETM_CH_ENABLED33 : R/WTC/SS; bitpos: [1]; default: 0; + * Represents channel33 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA33 (BIT(1)) -#define SOC_ETM_CH_ENA33_M (SOC_ETM_CH_ENA33_V << SOC_ETM_CH_ENA33_S) -#define SOC_ETM_CH_ENA33_V 0x00000001U -#define SOC_ETM_CH_ENA33_S 1 -/** SOC_ETM_CH_ENA34 : R/WTC/WTS; bitpos: [2]; default: 0; - * ch34 enable +#define SOC_ETM_CH_ENABLED33 (BIT(1)) +#define SOC_ETM_CH_ENABLED33_M (SOC_ETM_CH_ENABLED33_V << SOC_ETM_CH_ENABLED33_S) +#define SOC_ETM_CH_ENABLED33_V 0x00000001U +#define SOC_ETM_CH_ENABLED33_S 1 +/** SOC_ETM_CH_ENABLED34 : R/WTC/SS; bitpos: [2]; default: 0; + * Represents channel34 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA34 (BIT(2)) -#define SOC_ETM_CH_ENA34_M (SOC_ETM_CH_ENA34_V << SOC_ETM_CH_ENA34_S) -#define SOC_ETM_CH_ENA34_V 0x00000001U -#define SOC_ETM_CH_ENA34_S 2 -/** SOC_ETM_CH_ENA35 : R/WTC/WTS; bitpos: [3]; default: 0; - * ch35 enable +#define SOC_ETM_CH_ENABLED34 (BIT(2)) +#define SOC_ETM_CH_ENABLED34_M (SOC_ETM_CH_ENABLED34_V << SOC_ETM_CH_ENABLED34_S) +#define SOC_ETM_CH_ENABLED34_V 0x00000001U +#define SOC_ETM_CH_ENABLED34_S 2 +/** SOC_ETM_CH_ENABLED35 : R/WTC/SS; bitpos: [3]; default: 0; + * Represents channel35 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA35 (BIT(3)) -#define SOC_ETM_CH_ENA35_M (SOC_ETM_CH_ENA35_V << SOC_ETM_CH_ENA35_S) -#define SOC_ETM_CH_ENA35_V 0x00000001U -#define SOC_ETM_CH_ENA35_S 3 -/** SOC_ETM_CH_ENA36 : R/WTC/WTS; bitpos: [4]; default: 0; - * ch36 enable +#define SOC_ETM_CH_ENABLED35 (BIT(3)) +#define SOC_ETM_CH_ENABLED35_M (SOC_ETM_CH_ENABLED35_V << SOC_ETM_CH_ENABLED35_S) +#define SOC_ETM_CH_ENABLED35_V 0x00000001U +#define SOC_ETM_CH_ENABLED35_S 3 +/** SOC_ETM_CH_ENABLED36 : R/WTC/SS; bitpos: [4]; default: 0; + * Represents channel36 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA36 (BIT(4)) -#define SOC_ETM_CH_ENA36_M (SOC_ETM_CH_ENA36_V << SOC_ETM_CH_ENA36_S) -#define SOC_ETM_CH_ENA36_V 0x00000001U -#define SOC_ETM_CH_ENA36_S 4 -/** SOC_ETM_CH_ENA37 : R/WTC/WTS; bitpos: [5]; default: 0; - * ch37 enable +#define SOC_ETM_CH_ENABLED36 (BIT(4)) +#define SOC_ETM_CH_ENABLED36_M (SOC_ETM_CH_ENABLED36_V << SOC_ETM_CH_ENABLED36_S) +#define SOC_ETM_CH_ENABLED36_V 0x00000001U +#define SOC_ETM_CH_ENABLED36_S 4 +/** SOC_ETM_CH_ENABLED37 : R/WTC/SS; bitpos: [5]; default: 0; + * Represents channel37 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA37 (BIT(5)) -#define SOC_ETM_CH_ENA37_M (SOC_ETM_CH_ENA37_V << SOC_ETM_CH_ENA37_S) -#define SOC_ETM_CH_ENA37_V 0x00000001U -#define SOC_ETM_CH_ENA37_S 5 -/** SOC_ETM_CH_ENA38 : R/WTC/WTS; bitpos: [6]; default: 0; - * ch38 enable +#define SOC_ETM_CH_ENABLED37 (BIT(5)) +#define SOC_ETM_CH_ENABLED37_M (SOC_ETM_CH_ENABLED37_V << SOC_ETM_CH_ENABLED37_S) +#define SOC_ETM_CH_ENABLED37_V 0x00000001U +#define SOC_ETM_CH_ENABLED37_S 5 +/** SOC_ETM_CH_ENABLED38 : R/WTC/SS; bitpos: [6]; default: 0; + * Represents channel38 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA38 (BIT(6)) -#define SOC_ETM_CH_ENA38_M (SOC_ETM_CH_ENA38_V << SOC_ETM_CH_ENA38_S) -#define SOC_ETM_CH_ENA38_V 0x00000001U -#define SOC_ETM_CH_ENA38_S 6 -/** SOC_ETM_CH_ENA39 : R/WTC/WTS; bitpos: [7]; default: 0; - * ch39 enable +#define SOC_ETM_CH_ENABLED38 (BIT(6)) +#define SOC_ETM_CH_ENABLED38_M (SOC_ETM_CH_ENABLED38_V << SOC_ETM_CH_ENABLED38_S) +#define SOC_ETM_CH_ENABLED38_V 0x00000001U +#define SOC_ETM_CH_ENABLED38_S 6 +/** SOC_ETM_CH_ENABLED39 : R/WTC/SS; bitpos: [7]; default: 0; + * Represents channel39 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA39 (BIT(7)) -#define SOC_ETM_CH_ENA39_M (SOC_ETM_CH_ENA39_V << SOC_ETM_CH_ENA39_S) -#define SOC_ETM_CH_ENA39_V 0x00000001U -#define SOC_ETM_CH_ENA39_S 7 -/** SOC_ETM_CH_ENA40 : R/WTC/WTS; bitpos: [8]; default: 0; - * ch40 enable +#define SOC_ETM_CH_ENABLED39 (BIT(7)) +#define SOC_ETM_CH_ENABLED39_M (SOC_ETM_CH_ENABLED39_V << SOC_ETM_CH_ENABLED39_S) +#define SOC_ETM_CH_ENABLED39_V 0x00000001U +#define SOC_ETM_CH_ENABLED39_S 7 +/** SOC_ETM_CH_ENABLED40 : R/WTC/SS; bitpos: [8]; default: 0; + * Represents channel40 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA40 (BIT(8)) -#define SOC_ETM_CH_ENA40_M (SOC_ETM_CH_ENA40_V << SOC_ETM_CH_ENA40_S) -#define SOC_ETM_CH_ENA40_V 0x00000001U -#define SOC_ETM_CH_ENA40_S 8 -/** SOC_ETM_CH_ENA41 : R/WTC/WTS; bitpos: [9]; default: 0; - * ch41 enable +#define SOC_ETM_CH_ENABLED40 (BIT(8)) +#define SOC_ETM_CH_ENABLED40_M (SOC_ETM_CH_ENABLED40_V << SOC_ETM_CH_ENABLED40_S) +#define SOC_ETM_CH_ENABLED40_V 0x00000001U +#define SOC_ETM_CH_ENABLED40_S 8 +/** SOC_ETM_CH_ENABLED41 : R/WTC/SS; bitpos: [9]; default: 0; + * Represents channel41 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA41 (BIT(9)) -#define SOC_ETM_CH_ENA41_M (SOC_ETM_CH_ENA41_V << SOC_ETM_CH_ENA41_S) -#define SOC_ETM_CH_ENA41_V 0x00000001U -#define SOC_ETM_CH_ENA41_S 9 -/** SOC_ETM_CH_ENA42 : R/WTC/WTS; bitpos: [10]; default: 0; - * ch42 enable +#define SOC_ETM_CH_ENABLED41 (BIT(9)) +#define SOC_ETM_CH_ENABLED41_M (SOC_ETM_CH_ENABLED41_V << SOC_ETM_CH_ENABLED41_S) +#define SOC_ETM_CH_ENABLED41_V 0x00000001U +#define SOC_ETM_CH_ENABLED41_S 9 +/** SOC_ETM_CH_ENABLED42 : R/WTC/SS; bitpos: [10]; default: 0; + * Represents channel42 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA42 (BIT(10)) -#define SOC_ETM_CH_ENA42_M (SOC_ETM_CH_ENA42_V << SOC_ETM_CH_ENA42_S) -#define SOC_ETM_CH_ENA42_V 0x00000001U -#define SOC_ETM_CH_ENA42_S 10 -/** SOC_ETM_CH_ENA43 : R/WTC/WTS; bitpos: [11]; default: 0; - * ch43 enable +#define SOC_ETM_CH_ENABLED42 (BIT(10)) +#define SOC_ETM_CH_ENABLED42_M (SOC_ETM_CH_ENABLED42_V << SOC_ETM_CH_ENABLED42_S) +#define SOC_ETM_CH_ENABLED42_V 0x00000001U +#define SOC_ETM_CH_ENABLED42_S 10 +/** SOC_ETM_CH_ENABLED43 : R/WTC/SS; bitpos: [11]; default: 0; + * Represents channel43 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA43 (BIT(11)) -#define SOC_ETM_CH_ENA43_M (SOC_ETM_CH_ENA43_V << SOC_ETM_CH_ENA43_S) -#define SOC_ETM_CH_ENA43_V 0x00000001U -#define SOC_ETM_CH_ENA43_S 11 -/** SOC_ETM_CH_ENA44 : R/WTC/WTS; bitpos: [12]; default: 0; - * ch44 enable +#define SOC_ETM_CH_ENABLED43 (BIT(11)) +#define SOC_ETM_CH_ENABLED43_M (SOC_ETM_CH_ENABLED43_V << SOC_ETM_CH_ENABLED43_S) +#define SOC_ETM_CH_ENABLED43_V 0x00000001U +#define SOC_ETM_CH_ENABLED43_S 11 +/** SOC_ETM_CH_ENABLED44 : R/WTC/SS; bitpos: [12]; default: 0; + * Represents channel44 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA44 (BIT(12)) -#define SOC_ETM_CH_ENA44_M (SOC_ETM_CH_ENA44_V << SOC_ETM_CH_ENA44_S) -#define SOC_ETM_CH_ENA44_V 0x00000001U -#define SOC_ETM_CH_ENA44_S 12 -/** SOC_ETM_CH_ENA45 : R/WTC/WTS; bitpos: [13]; default: 0; - * ch45 enable +#define SOC_ETM_CH_ENABLED44 (BIT(12)) +#define SOC_ETM_CH_ENABLED44_M (SOC_ETM_CH_ENABLED44_V << SOC_ETM_CH_ENABLED44_S) +#define SOC_ETM_CH_ENABLED44_V 0x00000001U +#define SOC_ETM_CH_ENABLED44_S 12 +/** SOC_ETM_CH_ENABLED45 : R/WTC/SS; bitpos: [13]; default: 0; + * Represents channel45 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA45 (BIT(13)) -#define SOC_ETM_CH_ENA45_M (SOC_ETM_CH_ENA45_V << SOC_ETM_CH_ENA45_S) -#define SOC_ETM_CH_ENA45_V 0x00000001U -#define SOC_ETM_CH_ENA45_S 13 -/** SOC_ETM_CH_ENA46 : R/WTC/WTS; bitpos: [14]; default: 0; - * ch46 enable +#define SOC_ETM_CH_ENABLED45 (BIT(13)) +#define SOC_ETM_CH_ENABLED45_M (SOC_ETM_CH_ENABLED45_V << SOC_ETM_CH_ENABLED45_S) +#define SOC_ETM_CH_ENABLED45_V 0x00000001U +#define SOC_ETM_CH_ENABLED45_S 13 +/** SOC_ETM_CH_ENABLED46 : R/WTC/SS; bitpos: [14]; default: 0; + * Represents channel46 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA46 (BIT(14)) -#define SOC_ETM_CH_ENA46_M (SOC_ETM_CH_ENA46_V << SOC_ETM_CH_ENA46_S) -#define SOC_ETM_CH_ENA46_V 0x00000001U -#define SOC_ETM_CH_ENA46_S 14 -/** SOC_ETM_CH_ENA47 : R/WTC/WTS; bitpos: [15]; default: 0; - * ch47 enable +#define SOC_ETM_CH_ENABLED46 (BIT(14)) +#define SOC_ETM_CH_ENABLED46_M (SOC_ETM_CH_ENABLED46_V << SOC_ETM_CH_ENABLED46_S) +#define SOC_ETM_CH_ENABLED46_V 0x00000001U +#define SOC_ETM_CH_ENABLED46_S 14 +/** SOC_ETM_CH_ENABLED47 : R/WTC/SS; bitpos: [15]; default: 0; + * Represents channel47 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA47 (BIT(15)) -#define SOC_ETM_CH_ENA47_M (SOC_ETM_CH_ENA47_V << SOC_ETM_CH_ENA47_S) -#define SOC_ETM_CH_ENA47_V 0x00000001U -#define SOC_ETM_CH_ENA47_S 15 -/** SOC_ETM_CH_ENA48 : R/WTC/WTS; bitpos: [16]; default: 0; - * ch48 enable +#define SOC_ETM_CH_ENABLED47 (BIT(15)) +#define SOC_ETM_CH_ENABLED47_M (SOC_ETM_CH_ENABLED47_V << SOC_ETM_CH_ENABLED47_S) +#define SOC_ETM_CH_ENABLED47_V 0x00000001U +#define SOC_ETM_CH_ENABLED47_S 15 +/** SOC_ETM_CH_ENABLED48 : R/WTC/SS; bitpos: [16]; default: 0; + * Represents channel48 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA48 (BIT(16)) -#define SOC_ETM_CH_ENA48_M (SOC_ETM_CH_ENA48_V << SOC_ETM_CH_ENA48_S) -#define SOC_ETM_CH_ENA48_V 0x00000001U -#define SOC_ETM_CH_ENA48_S 16 -/** SOC_ETM_CH_ENA49 : R/WTC/WTS; bitpos: [17]; default: 0; - * ch49 enable +#define SOC_ETM_CH_ENABLED48 (BIT(16)) +#define SOC_ETM_CH_ENABLED48_M (SOC_ETM_CH_ENABLED48_V << SOC_ETM_CH_ENABLED48_S) +#define SOC_ETM_CH_ENABLED48_V 0x00000001U +#define SOC_ETM_CH_ENABLED48_S 16 +/** SOC_ETM_CH_ENABLED49 : R/WTC/SS; bitpos: [17]; default: 0; + * Represents channel49 enable status. + * 0: Disable + * 1: Enable */ -#define SOC_ETM_CH_ENA49 (BIT(17)) -#define SOC_ETM_CH_ENA49_M (SOC_ETM_CH_ENA49_V << SOC_ETM_CH_ENA49_S) -#define SOC_ETM_CH_ENA49_V 0x00000001U -#define SOC_ETM_CH_ENA49_S 17 +#define SOC_ETM_CH_ENABLED49 (BIT(17)) +#define SOC_ETM_CH_ENABLED49_M (SOC_ETM_CH_ENABLED49_V << SOC_ETM_CH_ENABLED49_S) +#define SOC_ETM_CH_ENABLED49_V 0x00000001U +#define SOC_ETM_CH_ENABLED49_S 17 /** SOC_ETM_CH_ENA_AD1_SET_REG register - * channel enable set register + * Channel enable register */ -#define SOC_ETM_CH_ENA_AD1_SET_REG (DR_REG_SOC_BASE + 0x10) -/** SOC_ETM_CH_SET32 : WT; bitpos: [0]; default: 0; - * ch32 set +#define SOC_ETM_CH_ENA_AD1_SET_REG (DR_REG_SOC_ETM_BASE + 0x10) +/** SOC_ETM_CH_ENABLE32 : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable channel32. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET32 (BIT(0)) -#define SOC_ETM_CH_SET32_M (SOC_ETM_CH_SET32_V << SOC_ETM_CH_SET32_S) -#define SOC_ETM_CH_SET32_V 0x00000001U -#define SOC_ETM_CH_SET32_S 0 -/** SOC_ETM_CH_SET33 : WT; bitpos: [1]; default: 0; - * ch33 set +#define SOC_ETM_CH_ENABLE32 (BIT(0)) +#define SOC_ETM_CH_ENABLE32_M (SOC_ETM_CH_ENABLE32_V << SOC_ETM_CH_ENABLE32_S) +#define SOC_ETM_CH_ENABLE32_V 0x00000001U +#define SOC_ETM_CH_ENABLE32_S 0 +/** SOC_ETM_CH_ENABLE33 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable channel33. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET33 (BIT(1)) -#define SOC_ETM_CH_SET33_M (SOC_ETM_CH_SET33_V << SOC_ETM_CH_SET33_S) -#define SOC_ETM_CH_SET33_V 0x00000001U -#define SOC_ETM_CH_SET33_S 1 -/** SOC_ETM_CH_SET34 : WT; bitpos: [2]; default: 0; - * ch34 set +#define SOC_ETM_CH_ENABLE33 (BIT(1)) +#define SOC_ETM_CH_ENABLE33_M (SOC_ETM_CH_ENABLE33_V << SOC_ETM_CH_ENABLE33_S) +#define SOC_ETM_CH_ENABLE33_V 0x00000001U +#define SOC_ETM_CH_ENABLE33_S 1 +/** SOC_ETM_CH_ENABLE34 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable channel34. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET34 (BIT(2)) -#define SOC_ETM_CH_SET34_M (SOC_ETM_CH_SET34_V << SOC_ETM_CH_SET34_S) -#define SOC_ETM_CH_SET34_V 0x00000001U -#define SOC_ETM_CH_SET34_S 2 -/** SOC_ETM_CH_SET35 : WT; bitpos: [3]; default: 0; - * ch35 set +#define SOC_ETM_CH_ENABLE34 (BIT(2)) +#define SOC_ETM_CH_ENABLE34_M (SOC_ETM_CH_ENABLE34_V << SOC_ETM_CH_ENABLE34_S) +#define SOC_ETM_CH_ENABLE34_V 0x00000001U +#define SOC_ETM_CH_ENABLE34_S 2 +/** SOC_ETM_CH_ENABLE35 : WT; bitpos: [3]; default: 0; + * Configures whether or not to enable channel35. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET35 (BIT(3)) -#define SOC_ETM_CH_SET35_M (SOC_ETM_CH_SET35_V << SOC_ETM_CH_SET35_S) -#define SOC_ETM_CH_SET35_V 0x00000001U -#define SOC_ETM_CH_SET35_S 3 -/** SOC_ETM_CH_SET36 : WT; bitpos: [4]; default: 0; - * ch36 set +#define SOC_ETM_CH_ENABLE35 (BIT(3)) +#define SOC_ETM_CH_ENABLE35_M (SOC_ETM_CH_ENABLE35_V << SOC_ETM_CH_ENABLE35_S) +#define SOC_ETM_CH_ENABLE35_V 0x00000001U +#define SOC_ETM_CH_ENABLE35_S 3 +/** SOC_ETM_CH_ENABLE36 : WT; bitpos: [4]; default: 0; + * Configures whether or not to enable channel36. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET36 (BIT(4)) -#define SOC_ETM_CH_SET36_M (SOC_ETM_CH_SET36_V << SOC_ETM_CH_SET36_S) -#define SOC_ETM_CH_SET36_V 0x00000001U -#define SOC_ETM_CH_SET36_S 4 -/** SOC_ETM_CH_SET37 : WT; bitpos: [5]; default: 0; - * ch37 set +#define SOC_ETM_CH_ENABLE36 (BIT(4)) +#define SOC_ETM_CH_ENABLE36_M (SOC_ETM_CH_ENABLE36_V << SOC_ETM_CH_ENABLE36_S) +#define SOC_ETM_CH_ENABLE36_V 0x00000001U +#define SOC_ETM_CH_ENABLE36_S 4 +/** SOC_ETM_CH_ENABLE37 : WT; bitpos: [5]; default: 0; + * Configures whether or not to enable channel37. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET37 (BIT(5)) -#define SOC_ETM_CH_SET37_M (SOC_ETM_CH_SET37_V << SOC_ETM_CH_SET37_S) -#define SOC_ETM_CH_SET37_V 0x00000001U -#define SOC_ETM_CH_SET37_S 5 -/** SOC_ETM_CH_SET38 : WT; bitpos: [6]; default: 0; - * ch38 set +#define SOC_ETM_CH_ENABLE37 (BIT(5)) +#define SOC_ETM_CH_ENABLE37_M (SOC_ETM_CH_ENABLE37_V << SOC_ETM_CH_ENABLE37_S) +#define SOC_ETM_CH_ENABLE37_V 0x00000001U +#define SOC_ETM_CH_ENABLE37_S 5 +/** SOC_ETM_CH_ENABLE38 : WT; bitpos: [6]; default: 0; + * Configures whether or not to enable channel38. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET38 (BIT(6)) -#define SOC_ETM_CH_SET38_M (SOC_ETM_CH_SET38_V << SOC_ETM_CH_SET38_S) -#define SOC_ETM_CH_SET38_V 0x00000001U -#define SOC_ETM_CH_SET38_S 6 -/** SOC_ETM_CH_SET39 : WT; bitpos: [7]; default: 0; - * ch39 set +#define SOC_ETM_CH_ENABLE38 (BIT(6)) +#define SOC_ETM_CH_ENABLE38_M (SOC_ETM_CH_ENABLE38_V << SOC_ETM_CH_ENABLE38_S) +#define SOC_ETM_CH_ENABLE38_V 0x00000001U +#define SOC_ETM_CH_ENABLE38_S 6 +/** SOC_ETM_CH_ENABLE39 : WT; bitpos: [7]; default: 0; + * Configures whether or not to enable channel39. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET39 (BIT(7)) -#define SOC_ETM_CH_SET39_M (SOC_ETM_CH_SET39_V << SOC_ETM_CH_SET39_S) -#define SOC_ETM_CH_SET39_V 0x00000001U -#define SOC_ETM_CH_SET39_S 7 -/** SOC_ETM_CH_SET40 : WT; bitpos: [8]; default: 0; - * ch40 set +#define SOC_ETM_CH_ENABLE39 (BIT(7)) +#define SOC_ETM_CH_ENABLE39_M (SOC_ETM_CH_ENABLE39_V << SOC_ETM_CH_ENABLE39_S) +#define SOC_ETM_CH_ENABLE39_V 0x00000001U +#define SOC_ETM_CH_ENABLE39_S 7 +/** SOC_ETM_CH_ENABLE40 : WT; bitpos: [8]; default: 0; + * Configures whether or not to enable channel40. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET40 (BIT(8)) -#define SOC_ETM_CH_SET40_M (SOC_ETM_CH_SET40_V << SOC_ETM_CH_SET40_S) -#define SOC_ETM_CH_SET40_V 0x00000001U -#define SOC_ETM_CH_SET40_S 8 -/** SOC_ETM_CH_SET41 : WT; bitpos: [9]; default: 0; - * ch41 set +#define SOC_ETM_CH_ENABLE40 (BIT(8)) +#define SOC_ETM_CH_ENABLE40_M (SOC_ETM_CH_ENABLE40_V << SOC_ETM_CH_ENABLE40_S) +#define SOC_ETM_CH_ENABLE40_V 0x00000001U +#define SOC_ETM_CH_ENABLE40_S 8 +/** SOC_ETM_CH_ENABLE41 : WT; bitpos: [9]; default: 0; + * Configures whether or not to enable channel41. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET41 (BIT(9)) -#define SOC_ETM_CH_SET41_M (SOC_ETM_CH_SET41_V << SOC_ETM_CH_SET41_S) -#define SOC_ETM_CH_SET41_V 0x00000001U -#define SOC_ETM_CH_SET41_S 9 -/** SOC_ETM_CH_SET42 : WT; bitpos: [10]; default: 0; - * ch42 set +#define SOC_ETM_CH_ENABLE41 (BIT(9)) +#define SOC_ETM_CH_ENABLE41_M (SOC_ETM_CH_ENABLE41_V << SOC_ETM_CH_ENABLE41_S) +#define SOC_ETM_CH_ENABLE41_V 0x00000001U +#define SOC_ETM_CH_ENABLE41_S 9 +/** SOC_ETM_CH_ENABLE42 : WT; bitpos: [10]; default: 0; + * Configures whether or not to enable channel42. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET42 (BIT(10)) -#define SOC_ETM_CH_SET42_M (SOC_ETM_CH_SET42_V << SOC_ETM_CH_SET42_S) -#define SOC_ETM_CH_SET42_V 0x00000001U -#define SOC_ETM_CH_SET42_S 10 -/** SOC_ETM_CH_SET43 : WT; bitpos: [11]; default: 0; - * ch43 set +#define SOC_ETM_CH_ENABLE42 (BIT(10)) +#define SOC_ETM_CH_ENABLE42_M (SOC_ETM_CH_ENABLE42_V << SOC_ETM_CH_ENABLE42_S) +#define SOC_ETM_CH_ENABLE42_V 0x00000001U +#define SOC_ETM_CH_ENABLE42_S 10 +/** SOC_ETM_CH_ENABLE43 : WT; bitpos: [11]; default: 0; + * Configures whether or not to enable channel43. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET43 (BIT(11)) -#define SOC_ETM_CH_SET43_M (SOC_ETM_CH_SET43_V << SOC_ETM_CH_SET43_S) -#define SOC_ETM_CH_SET43_V 0x00000001U -#define SOC_ETM_CH_SET43_S 11 -/** SOC_ETM_CH_SET44 : WT; bitpos: [12]; default: 0; - * ch44 set +#define SOC_ETM_CH_ENABLE43 (BIT(11)) +#define SOC_ETM_CH_ENABLE43_M (SOC_ETM_CH_ENABLE43_V << SOC_ETM_CH_ENABLE43_S) +#define SOC_ETM_CH_ENABLE43_V 0x00000001U +#define SOC_ETM_CH_ENABLE43_S 11 +/** SOC_ETM_CH_ENABLE44 : WT; bitpos: [12]; default: 0; + * Configures whether or not to enable channel44. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET44 (BIT(12)) -#define SOC_ETM_CH_SET44_M (SOC_ETM_CH_SET44_V << SOC_ETM_CH_SET44_S) -#define SOC_ETM_CH_SET44_V 0x00000001U -#define SOC_ETM_CH_SET44_S 12 -/** SOC_ETM_CH_SET45 : WT; bitpos: [13]; default: 0; - * ch45 set +#define SOC_ETM_CH_ENABLE44 (BIT(12)) +#define SOC_ETM_CH_ENABLE44_M (SOC_ETM_CH_ENABLE44_V << SOC_ETM_CH_ENABLE44_S) +#define SOC_ETM_CH_ENABLE44_V 0x00000001U +#define SOC_ETM_CH_ENABLE44_S 12 +/** SOC_ETM_CH_ENABLE45 : WT; bitpos: [13]; default: 0; + * Configures whether or not to enable channel45. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET45 (BIT(13)) -#define SOC_ETM_CH_SET45_M (SOC_ETM_CH_SET45_V << SOC_ETM_CH_SET45_S) -#define SOC_ETM_CH_SET45_V 0x00000001U -#define SOC_ETM_CH_SET45_S 13 -/** SOC_ETM_CH_SET46 : WT; bitpos: [14]; default: 0; - * ch46 set +#define SOC_ETM_CH_ENABLE45 (BIT(13)) +#define SOC_ETM_CH_ENABLE45_M (SOC_ETM_CH_ENABLE45_V << SOC_ETM_CH_ENABLE45_S) +#define SOC_ETM_CH_ENABLE45_V 0x00000001U +#define SOC_ETM_CH_ENABLE45_S 13 +/** SOC_ETM_CH_ENABLE46 : WT; bitpos: [14]; default: 0; + * Configures whether or not to enable channel46. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET46 (BIT(14)) -#define SOC_ETM_CH_SET46_M (SOC_ETM_CH_SET46_V << SOC_ETM_CH_SET46_S) -#define SOC_ETM_CH_SET46_V 0x00000001U -#define SOC_ETM_CH_SET46_S 14 -/** SOC_ETM_CH_SET47 : WT; bitpos: [15]; default: 0; - * ch47 set +#define SOC_ETM_CH_ENABLE46 (BIT(14)) +#define SOC_ETM_CH_ENABLE46_M (SOC_ETM_CH_ENABLE46_V << SOC_ETM_CH_ENABLE46_S) +#define SOC_ETM_CH_ENABLE46_V 0x00000001U +#define SOC_ETM_CH_ENABLE46_S 14 +/** SOC_ETM_CH_ENABLE47 : WT; bitpos: [15]; default: 0; + * Configures whether or not to enable channel47. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET47 (BIT(15)) -#define SOC_ETM_CH_SET47_M (SOC_ETM_CH_SET47_V << SOC_ETM_CH_SET47_S) -#define SOC_ETM_CH_SET47_V 0x00000001U -#define SOC_ETM_CH_SET47_S 15 -/** SOC_ETM_CH_SET48 : WT; bitpos: [16]; default: 0; - * ch48 set +#define SOC_ETM_CH_ENABLE47 (BIT(15)) +#define SOC_ETM_CH_ENABLE47_M (SOC_ETM_CH_ENABLE47_V << SOC_ETM_CH_ENABLE47_S) +#define SOC_ETM_CH_ENABLE47_V 0x00000001U +#define SOC_ETM_CH_ENABLE47_S 15 +/** SOC_ETM_CH_ENABLE48 : WT; bitpos: [16]; default: 0; + * Configures whether or not to enable channel48. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET48 (BIT(16)) -#define SOC_ETM_CH_SET48_M (SOC_ETM_CH_SET48_V << SOC_ETM_CH_SET48_S) -#define SOC_ETM_CH_SET48_V 0x00000001U -#define SOC_ETM_CH_SET48_S 16 -/** SOC_ETM_CH_SET49 : WT; bitpos: [17]; default: 0; - * ch49 set +#define SOC_ETM_CH_ENABLE48 (BIT(16)) +#define SOC_ETM_CH_ENABLE48_M (SOC_ETM_CH_ENABLE48_V << SOC_ETM_CH_ENABLE48_S) +#define SOC_ETM_CH_ENABLE48_V 0x00000001U +#define SOC_ETM_CH_ENABLE48_S 16 +/** SOC_ETM_CH_ENABLE49 : WT; bitpos: [17]; default: 0; + * Configures whether or not to enable channel49. + * 0: Invalid. No effect + * 1: Enable */ -#define SOC_ETM_CH_SET49 (BIT(17)) -#define SOC_ETM_CH_SET49_M (SOC_ETM_CH_SET49_V << SOC_ETM_CH_SET49_S) -#define SOC_ETM_CH_SET49_V 0x00000001U -#define SOC_ETM_CH_SET49_S 17 +#define SOC_ETM_CH_ENABLE49 (BIT(17)) +#define SOC_ETM_CH_ENABLE49_M (SOC_ETM_CH_ENABLE49_V << SOC_ETM_CH_ENABLE49_S) +#define SOC_ETM_CH_ENABLE49_V 0x00000001U +#define SOC_ETM_CH_ENABLE49_S 17 /** SOC_ETM_CH_ENA_AD1_CLR_REG register - * channel enable clear register + * Channel disable register */ -#define SOC_ETM_CH_ENA_AD1_CLR_REG (DR_REG_SOC_BASE + 0x14) -/** SOC_ETM_CH_CLR32 : WT; bitpos: [0]; default: 0; - * ch32 clear +#define SOC_ETM_CH_ENA_AD1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x14) +/** SOC_ETM_CH_DISABLE32 : WT; bitpos: [0]; default: 0; + * Configures whether or not to disable channel32. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR32 (BIT(0)) -#define SOC_ETM_CH_CLR32_M (SOC_ETM_CH_CLR32_V << SOC_ETM_CH_CLR32_S) -#define SOC_ETM_CH_CLR32_V 0x00000001U -#define SOC_ETM_CH_CLR32_S 0 -/** SOC_ETM_CH_CLR33 : WT; bitpos: [1]; default: 0; - * ch33 clear +#define SOC_ETM_CH_DISABLE32 (BIT(0)) +#define SOC_ETM_CH_DISABLE32_M (SOC_ETM_CH_DISABLE32_V << SOC_ETM_CH_DISABLE32_S) +#define SOC_ETM_CH_DISABLE32_V 0x00000001U +#define SOC_ETM_CH_DISABLE32_S 0 +/** SOC_ETM_CH_DISABLE33 : WT; bitpos: [1]; default: 0; + * Configures whether or not to disable channel33. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR33 (BIT(1)) -#define SOC_ETM_CH_CLR33_M (SOC_ETM_CH_CLR33_V << SOC_ETM_CH_CLR33_S) -#define SOC_ETM_CH_CLR33_V 0x00000001U -#define SOC_ETM_CH_CLR33_S 1 -/** SOC_ETM_CH_CLR34 : WT; bitpos: [2]; default: 0; - * ch34 clear +#define SOC_ETM_CH_DISABLE33 (BIT(1)) +#define SOC_ETM_CH_DISABLE33_M (SOC_ETM_CH_DISABLE33_V << SOC_ETM_CH_DISABLE33_S) +#define SOC_ETM_CH_DISABLE33_V 0x00000001U +#define SOC_ETM_CH_DISABLE33_S 1 +/** SOC_ETM_CH_DISABLE34 : WT; bitpos: [2]; default: 0; + * Configures whether or not to disable channel34. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR34 (BIT(2)) -#define SOC_ETM_CH_CLR34_M (SOC_ETM_CH_CLR34_V << SOC_ETM_CH_CLR34_S) -#define SOC_ETM_CH_CLR34_V 0x00000001U -#define SOC_ETM_CH_CLR34_S 2 -/** SOC_ETM_CH_CLR35 : WT; bitpos: [3]; default: 0; - * ch35 clear +#define SOC_ETM_CH_DISABLE34 (BIT(2)) +#define SOC_ETM_CH_DISABLE34_M (SOC_ETM_CH_DISABLE34_V << SOC_ETM_CH_DISABLE34_S) +#define SOC_ETM_CH_DISABLE34_V 0x00000001U +#define SOC_ETM_CH_DISABLE34_S 2 +/** SOC_ETM_CH_DISABLE35 : WT; bitpos: [3]; default: 0; + * Configures whether or not to disable channel35. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR35 (BIT(3)) -#define SOC_ETM_CH_CLR35_M (SOC_ETM_CH_CLR35_V << SOC_ETM_CH_CLR35_S) -#define SOC_ETM_CH_CLR35_V 0x00000001U -#define SOC_ETM_CH_CLR35_S 3 -/** SOC_ETM_CH_CLR36 : WT; bitpos: [4]; default: 0; - * ch36 clear +#define SOC_ETM_CH_DISABLE35 (BIT(3)) +#define SOC_ETM_CH_DISABLE35_M (SOC_ETM_CH_DISABLE35_V << SOC_ETM_CH_DISABLE35_S) +#define SOC_ETM_CH_DISABLE35_V 0x00000001U +#define SOC_ETM_CH_DISABLE35_S 3 +/** SOC_ETM_CH_DISABLE36 : WT; bitpos: [4]; default: 0; + * Configures whether or not to disable channel36. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR36 (BIT(4)) -#define SOC_ETM_CH_CLR36_M (SOC_ETM_CH_CLR36_V << SOC_ETM_CH_CLR36_S) -#define SOC_ETM_CH_CLR36_V 0x00000001U -#define SOC_ETM_CH_CLR36_S 4 -/** SOC_ETM_CH_CLR37 : WT; bitpos: [5]; default: 0; - * ch37 clear +#define SOC_ETM_CH_DISABLE36 (BIT(4)) +#define SOC_ETM_CH_DISABLE36_M (SOC_ETM_CH_DISABLE36_V << SOC_ETM_CH_DISABLE36_S) +#define SOC_ETM_CH_DISABLE36_V 0x00000001U +#define SOC_ETM_CH_DISABLE36_S 4 +/** SOC_ETM_CH_DISABLE37 : WT; bitpos: [5]; default: 0; + * Configures whether or not to disable channel37. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR37 (BIT(5)) -#define SOC_ETM_CH_CLR37_M (SOC_ETM_CH_CLR37_V << SOC_ETM_CH_CLR37_S) -#define SOC_ETM_CH_CLR37_V 0x00000001U -#define SOC_ETM_CH_CLR37_S 5 -/** SOC_ETM_CH_CLR38 : WT; bitpos: [6]; default: 0; - * ch38 clear +#define SOC_ETM_CH_DISABLE37 (BIT(5)) +#define SOC_ETM_CH_DISABLE37_M (SOC_ETM_CH_DISABLE37_V << SOC_ETM_CH_DISABLE37_S) +#define SOC_ETM_CH_DISABLE37_V 0x00000001U +#define SOC_ETM_CH_DISABLE37_S 5 +/** SOC_ETM_CH_DISABLE38 : WT; bitpos: [6]; default: 0; + * Configures whether or not to disable channel38. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR38 (BIT(6)) -#define SOC_ETM_CH_CLR38_M (SOC_ETM_CH_CLR38_V << SOC_ETM_CH_CLR38_S) -#define SOC_ETM_CH_CLR38_V 0x00000001U -#define SOC_ETM_CH_CLR38_S 6 -/** SOC_ETM_CH_CLR39 : WT; bitpos: [7]; default: 0; - * ch39 clear +#define SOC_ETM_CH_DISABLE38 (BIT(6)) +#define SOC_ETM_CH_DISABLE38_M (SOC_ETM_CH_DISABLE38_V << SOC_ETM_CH_DISABLE38_S) +#define SOC_ETM_CH_DISABLE38_V 0x00000001U +#define SOC_ETM_CH_DISABLE38_S 6 +/** SOC_ETM_CH_DISABLE39 : WT; bitpos: [7]; default: 0; + * Configures whether or not to disable channel39. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR39 (BIT(7)) -#define SOC_ETM_CH_CLR39_M (SOC_ETM_CH_CLR39_V << SOC_ETM_CH_CLR39_S) -#define SOC_ETM_CH_CLR39_V 0x00000001U -#define SOC_ETM_CH_CLR39_S 7 -/** SOC_ETM_CH_CLR40 : WT; bitpos: [8]; default: 0; - * ch40 clear +#define SOC_ETM_CH_DISABLE39 (BIT(7)) +#define SOC_ETM_CH_DISABLE39_M (SOC_ETM_CH_DISABLE39_V << SOC_ETM_CH_DISABLE39_S) +#define SOC_ETM_CH_DISABLE39_V 0x00000001U +#define SOC_ETM_CH_DISABLE39_S 7 +/** SOC_ETM_CH_DISABLE40 : WT; bitpos: [8]; default: 0; + * Configures whether or not to disable channel40. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR40 (BIT(8)) -#define SOC_ETM_CH_CLR40_M (SOC_ETM_CH_CLR40_V << SOC_ETM_CH_CLR40_S) -#define SOC_ETM_CH_CLR40_V 0x00000001U -#define SOC_ETM_CH_CLR40_S 8 -/** SOC_ETM_CH_CLR41 : WT; bitpos: [9]; default: 0; - * ch41 clear +#define SOC_ETM_CH_DISABLE40 (BIT(8)) +#define SOC_ETM_CH_DISABLE40_M (SOC_ETM_CH_DISABLE40_V << SOC_ETM_CH_DISABLE40_S) +#define SOC_ETM_CH_DISABLE40_V 0x00000001U +#define SOC_ETM_CH_DISABLE40_S 8 +/** SOC_ETM_CH_DISABLE41 : WT; bitpos: [9]; default: 0; + * Configures whether or not to disable channel41. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR41 (BIT(9)) -#define SOC_ETM_CH_CLR41_M (SOC_ETM_CH_CLR41_V << SOC_ETM_CH_CLR41_S) -#define SOC_ETM_CH_CLR41_V 0x00000001U -#define SOC_ETM_CH_CLR41_S 9 -/** SOC_ETM_CH_CLR42 : WT; bitpos: [10]; default: 0; - * ch42 clear +#define SOC_ETM_CH_DISABLE41 (BIT(9)) +#define SOC_ETM_CH_DISABLE41_M (SOC_ETM_CH_DISABLE41_V << SOC_ETM_CH_DISABLE41_S) +#define SOC_ETM_CH_DISABLE41_V 0x00000001U +#define SOC_ETM_CH_DISABLE41_S 9 +/** SOC_ETM_CH_DISABLE42 : WT; bitpos: [10]; default: 0; + * Configures whether or not to disable channel42. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR42 (BIT(10)) -#define SOC_ETM_CH_CLR42_M (SOC_ETM_CH_CLR42_V << SOC_ETM_CH_CLR42_S) -#define SOC_ETM_CH_CLR42_V 0x00000001U -#define SOC_ETM_CH_CLR42_S 10 -/** SOC_ETM_CH_CLR43 : WT; bitpos: [11]; default: 0; - * ch43 clear +#define SOC_ETM_CH_DISABLE42 (BIT(10)) +#define SOC_ETM_CH_DISABLE42_M (SOC_ETM_CH_DISABLE42_V << SOC_ETM_CH_DISABLE42_S) +#define SOC_ETM_CH_DISABLE42_V 0x00000001U +#define SOC_ETM_CH_DISABLE42_S 10 +/** SOC_ETM_CH_DISABLE43 : WT; bitpos: [11]; default: 0; + * Configures whether or not to disable channel43. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR43 (BIT(11)) -#define SOC_ETM_CH_CLR43_M (SOC_ETM_CH_CLR43_V << SOC_ETM_CH_CLR43_S) -#define SOC_ETM_CH_CLR43_V 0x00000001U -#define SOC_ETM_CH_CLR43_S 11 -/** SOC_ETM_CH_CLR44 : WT; bitpos: [12]; default: 0; - * ch44 clear +#define SOC_ETM_CH_DISABLE43 (BIT(11)) +#define SOC_ETM_CH_DISABLE43_M (SOC_ETM_CH_DISABLE43_V << SOC_ETM_CH_DISABLE43_S) +#define SOC_ETM_CH_DISABLE43_V 0x00000001U +#define SOC_ETM_CH_DISABLE43_S 11 +/** SOC_ETM_CH_DISABLE44 : WT; bitpos: [12]; default: 0; + * Configures whether or not to disable channel44. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR44 (BIT(12)) -#define SOC_ETM_CH_CLR44_M (SOC_ETM_CH_CLR44_V << SOC_ETM_CH_CLR44_S) -#define SOC_ETM_CH_CLR44_V 0x00000001U -#define SOC_ETM_CH_CLR44_S 12 -/** SOC_ETM_CH_CLR45 : WT; bitpos: [13]; default: 0; - * ch45 clear +#define SOC_ETM_CH_DISABLE44 (BIT(12)) +#define SOC_ETM_CH_DISABLE44_M (SOC_ETM_CH_DISABLE44_V << SOC_ETM_CH_DISABLE44_S) +#define SOC_ETM_CH_DISABLE44_V 0x00000001U +#define SOC_ETM_CH_DISABLE44_S 12 +/** SOC_ETM_CH_DISABLE45 : WT; bitpos: [13]; default: 0; + * Configures whether or not to disable channel45. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR45 (BIT(13)) -#define SOC_ETM_CH_CLR45_M (SOC_ETM_CH_CLR45_V << SOC_ETM_CH_CLR45_S) -#define SOC_ETM_CH_CLR45_V 0x00000001U -#define SOC_ETM_CH_CLR45_S 13 -/** SOC_ETM_CH_CLR46 : WT; bitpos: [14]; default: 0; - * ch46 clear +#define SOC_ETM_CH_DISABLE45 (BIT(13)) +#define SOC_ETM_CH_DISABLE45_M (SOC_ETM_CH_DISABLE45_V << SOC_ETM_CH_DISABLE45_S) +#define SOC_ETM_CH_DISABLE45_V 0x00000001U +#define SOC_ETM_CH_DISABLE45_S 13 +/** SOC_ETM_CH_DISABLE46 : WT; bitpos: [14]; default: 0; + * Configures whether or not to disable channel46. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR46 (BIT(14)) -#define SOC_ETM_CH_CLR46_M (SOC_ETM_CH_CLR46_V << SOC_ETM_CH_CLR46_S) -#define SOC_ETM_CH_CLR46_V 0x00000001U -#define SOC_ETM_CH_CLR46_S 14 -/** SOC_ETM_CH_CLR47 : WT; bitpos: [15]; default: 0; - * ch47 clear +#define SOC_ETM_CH_DISABLE46 (BIT(14)) +#define SOC_ETM_CH_DISABLE46_M (SOC_ETM_CH_DISABLE46_V << SOC_ETM_CH_DISABLE46_S) +#define SOC_ETM_CH_DISABLE46_V 0x00000001U +#define SOC_ETM_CH_DISABLE46_S 14 +/** SOC_ETM_CH_DISABLE47 : WT; bitpos: [15]; default: 0; + * Configures whether or not to disable channel47. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR47 (BIT(15)) -#define SOC_ETM_CH_CLR47_M (SOC_ETM_CH_CLR47_V << SOC_ETM_CH_CLR47_S) -#define SOC_ETM_CH_CLR47_V 0x00000001U -#define SOC_ETM_CH_CLR47_S 15 -/** SOC_ETM_CH_CLR48 : WT; bitpos: [16]; default: 0; - * ch48 clear +#define SOC_ETM_CH_DISABLE47 (BIT(15)) +#define SOC_ETM_CH_DISABLE47_M (SOC_ETM_CH_DISABLE47_V << SOC_ETM_CH_DISABLE47_S) +#define SOC_ETM_CH_DISABLE47_V 0x00000001U +#define SOC_ETM_CH_DISABLE47_S 15 +/** SOC_ETM_CH_DISABLE48 : WT; bitpos: [16]; default: 0; + * Configures whether or not to disable channel48. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR48 (BIT(16)) -#define SOC_ETM_CH_CLR48_M (SOC_ETM_CH_CLR48_V << SOC_ETM_CH_CLR48_S) -#define SOC_ETM_CH_CLR48_V 0x00000001U -#define SOC_ETM_CH_CLR48_S 16 -/** SOC_ETM_CH_CLR49 : WT; bitpos: [17]; default: 0; - * ch49 clear +#define SOC_ETM_CH_DISABLE48 (BIT(16)) +#define SOC_ETM_CH_DISABLE48_M (SOC_ETM_CH_DISABLE48_V << SOC_ETM_CH_DISABLE48_S) +#define SOC_ETM_CH_DISABLE48_V 0x00000001U +#define SOC_ETM_CH_DISABLE48_S 16 +/** SOC_ETM_CH_DISABLE49 : WT; bitpos: [17]; default: 0; + * Configures whether or not to disable channel49. + * 0: Invalid. No effect + * 1: Clear */ -#define SOC_ETM_CH_CLR49 (BIT(17)) -#define SOC_ETM_CH_CLR49_M (SOC_ETM_CH_CLR49_V << SOC_ETM_CH_CLR49_S) -#define SOC_ETM_CH_CLR49_V 0x00000001U -#define SOC_ETM_CH_CLR49_S 17 +#define SOC_ETM_CH_DISABLE49 (BIT(17)) +#define SOC_ETM_CH_DISABLE49_M (SOC_ETM_CH_DISABLE49_V << SOC_ETM_CH_DISABLE49_S) +#define SOC_ETM_CH_DISABLE49_V 0x00000001U +#define SOC_ETM_CH_DISABLE49_S 17 /** SOC_ETM_CH0_EVT_ID_REG register - * channel0 event id register + * Channel0 event ID register */ -#define SOC_ETM_CH0_EVT_ID_REG (DR_REG_SOC_BASE + 0x18) +#define SOC_ETM_CH0_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x18) /** SOC_ETM_CH0_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch0_evt_id + * Configures the event ID of channel0. */ #define SOC_ETM_CH0_EVT_ID 0x000000FFU #define SOC_ETM_CH0_EVT_ID_M (SOC_ETM_CH0_EVT_ID_V << SOC_ETM_CH0_EVT_ID_S) @@ -1104,11 +1404,11 @@ extern "C" { #define SOC_ETM_CH0_EVT_ID_S 0 /** SOC_ETM_CH0_TASK_ID_REG register - * channel0 task id register + * Channel0 task ID register */ -#define SOC_ETM_CH0_TASK_ID_REG (DR_REG_SOC_BASE + 0x1c) +#define SOC_ETM_CH0_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1c) /** SOC_ETM_CH0_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch0_task_id + * Configures the task ID of channel0. */ #define SOC_ETM_CH0_TASK_ID 0x000000FFU #define SOC_ETM_CH0_TASK_ID_M (SOC_ETM_CH0_TASK_ID_V << SOC_ETM_CH0_TASK_ID_S) @@ -1116,11 +1416,11 @@ extern "C" { #define SOC_ETM_CH0_TASK_ID_S 0 /** SOC_ETM_CH1_EVT_ID_REG register - * channel1 event id register + * Channel1 event ID register */ -#define SOC_ETM_CH1_EVT_ID_REG (DR_REG_SOC_BASE + 0x20) +#define SOC_ETM_CH1_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x20) /** SOC_ETM_CH1_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch1_evt_id + * Configures the event ID of channel1. */ #define SOC_ETM_CH1_EVT_ID 0x000000FFU #define SOC_ETM_CH1_EVT_ID_M (SOC_ETM_CH1_EVT_ID_V << SOC_ETM_CH1_EVT_ID_S) @@ -1128,11 +1428,11 @@ extern "C" { #define SOC_ETM_CH1_EVT_ID_S 0 /** SOC_ETM_CH1_TASK_ID_REG register - * channel1 task id register + * Channel1 task ID register */ -#define SOC_ETM_CH1_TASK_ID_REG (DR_REG_SOC_BASE + 0x24) +#define SOC_ETM_CH1_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x24) /** SOC_ETM_CH1_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch1_task_id + * Configures the task ID of channel1. */ #define SOC_ETM_CH1_TASK_ID 0x000000FFU #define SOC_ETM_CH1_TASK_ID_M (SOC_ETM_CH1_TASK_ID_V << SOC_ETM_CH1_TASK_ID_S) @@ -1140,11 +1440,11 @@ extern "C" { #define SOC_ETM_CH1_TASK_ID_S 0 /** SOC_ETM_CH2_EVT_ID_REG register - * channel2 event id register + * Channel2 event ID register */ -#define SOC_ETM_CH2_EVT_ID_REG (DR_REG_SOC_BASE + 0x28) +#define SOC_ETM_CH2_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x28) /** SOC_ETM_CH2_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch2_evt_id + * Configures the event ID of channel2. */ #define SOC_ETM_CH2_EVT_ID 0x000000FFU #define SOC_ETM_CH2_EVT_ID_M (SOC_ETM_CH2_EVT_ID_V << SOC_ETM_CH2_EVT_ID_S) @@ -1152,11 +1452,11 @@ extern "C" { #define SOC_ETM_CH2_EVT_ID_S 0 /** SOC_ETM_CH2_TASK_ID_REG register - * channel2 task id register + * Channel2 task ID register */ -#define SOC_ETM_CH2_TASK_ID_REG (DR_REG_SOC_BASE + 0x2c) +#define SOC_ETM_CH2_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x2c) /** SOC_ETM_CH2_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch2_task_id + * Configures the task ID of channel2. */ #define SOC_ETM_CH2_TASK_ID 0x000000FFU #define SOC_ETM_CH2_TASK_ID_M (SOC_ETM_CH2_TASK_ID_V << SOC_ETM_CH2_TASK_ID_S) @@ -1164,11 +1464,11 @@ extern "C" { #define SOC_ETM_CH2_TASK_ID_S 0 /** SOC_ETM_CH3_EVT_ID_REG register - * channel3 event id register + * Channel3 event ID register */ -#define SOC_ETM_CH3_EVT_ID_REG (DR_REG_SOC_BASE + 0x30) +#define SOC_ETM_CH3_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x30) /** SOC_ETM_CH3_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch3_evt_id + * Configures the event ID of channel3. */ #define SOC_ETM_CH3_EVT_ID 0x000000FFU #define SOC_ETM_CH3_EVT_ID_M (SOC_ETM_CH3_EVT_ID_V << SOC_ETM_CH3_EVT_ID_S) @@ -1176,11 +1476,11 @@ extern "C" { #define SOC_ETM_CH3_EVT_ID_S 0 /** SOC_ETM_CH3_TASK_ID_REG register - * channel3 task id register + * Channel3 task ID register */ -#define SOC_ETM_CH3_TASK_ID_REG (DR_REG_SOC_BASE + 0x34) +#define SOC_ETM_CH3_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x34) /** SOC_ETM_CH3_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch3_task_id + * Configures the task ID of channel3. */ #define SOC_ETM_CH3_TASK_ID 0x000000FFU #define SOC_ETM_CH3_TASK_ID_M (SOC_ETM_CH3_TASK_ID_V << SOC_ETM_CH3_TASK_ID_S) @@ -1188,11 +1488,11 @@ extern "C" { #define SOC_ETM_CH3_TASK_ID_S 0 /** SOC_ETM_CH4_EVT_ID_REG register - * channel4 event id register + * Channel4 event ID register */ -#define SOC_ETM_CH4_EVT_ID_REG (DR_REG_SOC_BASE + 0x38) +#define SOC_ETM_CH4_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x38) /** SOC_ETM_CH4_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch4_evt_id + * Configures the event ID of channel4. */ #define SOC_ETM_CH4_EVT_ID 0x000000FFU #define SOC_ETM_CH4_EVT_ID_M (SOC_ETM_CH4_EVT_ID_V << SOC_ETM_CH4_EVT_ID_S) @@ -1200,11 +1500,11 @@ extern "C" { #define SOC_ETM_CH4_EVT_ID_S 0 /** SOC_ETM_CH4_TASK_ID_REG register - * channel4 task id register + * Channel4 task ID register */ -#define SOC_ETM_CH4_TASK_ID_REG (DR_REG_SOC_BASE + 0x3c) +#define SOC_ETM_CH4_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x3c) /** SOC_ETM_CH4_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch4_task_id + * Configures the task ID of channel4. */ #define SOC_ETM_CH4_TASK_ID 0x000000FFU #define SOC_ETM_CH4_TASK_ID_M (SOC_ETM_CH4_TASK_ID_V << SOC_ETM_CH4_TASK_ID_S) @@ -1212,11 +1512,11 @@ extern "C" { #define SOC_ETM_CH4_TASK_ID_S 0 /** SOC_ETM_CH5_EVT_ID_REG register - * channel5 event id register + * Channel5 event ID register */ -#define SOC_ETM_CH5_EVT_ID_REG (DR_REG_SOC_BASE + 0x40) +#define SOC_ETM_CH5_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x40) /** SOC_ETM_CH5_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch5_evt_id + * Configures the event ID of channel5. */ #define SOC_ETM_CH5_EVT_ID 0x000000FFU #define SOC_ETM_CH5_EVT_ID_M (SOC_ETM_CH5_EVT_ID_V << SOC_ETM_CH5_EVT_ID_S) @@ -1224,11 +1524,11 @@ extern "C" { #define SOC_ETM_CH5_EVT_ID_S 0 /** SOC_ETM_CH5_TASK_ID_REG register - * channel5 task id register + * Channel5 task ID register */ -#define SOC_ETM_CH5_TASK_ID_REG (DR_REG_SOC_BASE + 0x44) +#define SOC_ETM_CH5_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x44) /** SOC_ETM_CH5_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch5_task_id + * Configures the task ID of channel5. */ #define SOC_ETM_CH5_TASK_ID 0x000000FFU #define SOC_ETM_CH5_TASK_ID_M (SOC_ETM_CH5_TASK_ID_V << SOC_ETM_CH5_TASK_ID_S) @@ -1236,11 +1536,11 @@ extern "C" { #define SOC_ETM_CH5_TASK_ID_S 0 /** SOC_ETM_CH6_EVT_ID_REG register - * channel6 event id register + * Channel6 event ID register */ -#define SOC_ETM_CH6_EVT_ID_REG (DR_REG_SOC_BASE + 0x48) +#define SOC_ETM_CH6_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x48) /** SOC_ETM_CH6_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch6_evt_id + * Configures the event ID of channel6. */ #define SOC_ETM_CH6_EVT_ID 0x000000FFU #define SOC_ETM_CH6_EVT_ID_M (SOC_ETM_CH6_EVT_ID_V << SOC_ETM_CH6_EVT_ID_S) @@ -1248,11 +1548,11 @@ extern "C" { #define SOC_ETM_CH6_EVT_ID_S 0 /** SOC_ETM_CH6_TASK_ID_REG register - * channel6 task id register + * Channel6 task ID register */ -#define SOC_ETM_CH6_TASK_ID_REG (DR_REG_SOC_BASE + 0x4c) +#define SOC_ETM_CH6_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x4c) /** SOC_ETM_CH6_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch6_task_id + * Configures the task ID of channel6. */ #define SOC_ETM_CH6_TASK_ID 0x000000FFU #define SOC_ETM_CH6_TASK_ID_M (SOC_ETM_CH6_TASK_ID_V << SOC_ETM_CH6_TASK_ID_S) @@ -1260,11 +1560,11 @@ extern "C" { #define SOC_ETM_CH6_TASK_ID_S 0 /** SOC_ETM_CH7_EVT_ID_REG register - * channel7 event id register + * Channel7 event ID register */ -#define SOC_ETM_CH7_EVT_ID_REG (DR_REG_SOC_BASE + 0x50) +#define SOC_ETM_CH7_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x50) /** SOC_ETM_CH7_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch7_evt_id + * Configures the event ID of channel7. */ #define SOC_ETM_CH7_EVT_ID 0x000000FFU #define SOC_ETM_CH7_EVT_ID_M (SOC_ETM_CH7_EVT_ID_V << SOC_ETM_CH7_EVT_ID_S) @@ -1272,11 +1572,11 @@ extern "C" { #define SOC_ETM_CH7_EVT_ID_S 0 /** SOC_ETM_CH7_TASK_ID_REG register - * channel7 task id register + * Channel7 task ID register */ -#define SOC_ETM_CH7_TASK_ID_REG (DR_REG_SOC_BASE + 0x54) +#define SOC_ETM_CH7_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x54) /** SOC_ETM_CH7_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch7_task_id + * Configures the task ID of channel7. */ #define SOC_ETM_CH7_TASK_ID 0x000000FFU #define SOC_ETM_CH7_TASK_ID_M (SOC_ETM_CH7_TASK_ID_V << SOC_ETM_CH7_TASK_ID_S) @@ -1284,11 +1584,11 @@ extern "C" { #define SOC_ETM_CH7_TASK_ID_S 0 /** SOC_ETM_CH8_EVT_ID_REG register - * channel8 event id register + * Channel8 event ID register */ -#define SOC_ETM_CH8_EVT_ID_REG (DR_REG_SOC_BASE + 0x58) +#define SOC_ETM_CH8_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x58) /** SOC_ETM_CH8_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch8_evt_id + * Configures the event ID of channel8. */ #define SOC_ETM_CH8_EVT_ID 0x000000FFU #define SOC_ETM_CH8_EVT_ID_M (SOC_ETM_CH8_EVT_ID_V << SOC_ETM_CH8_EVT_ID_S) @@ -1296,11 +1596,11 @@ extern "C" { #define SOC_ETM_CH8_EVT_ID_S 0 /** SOC_ETM_CH8_TASK_ID_REG register - * channel8 task id register + * Channel8 task ID register */ -#define SOC_ETM_CH8_TASK_ID_REG (DR_REG_SOC_BASE + 0x5c) +#define SOC_ETM_CH8_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x5c) /** SOC_ETM_CH8_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch8_task_id + * Configures the task ID of channel8. */ #define SOC_ETM_CH8_TASK_ID 0x000000FFU #define SOC_ETM_CH8_TASK_ID_M (SOC_ETM_CH8_TASK_ID_V << SOC_ETM_CH8_TASK_ID_S) @@ -1308,11 +1608,11 @@ extern "C" { #define SOC_ETM_CH8_TASK_ID_S 0 /** SOC_ETM_CH9_EVT_ID_REG register - * channel9 event id register + * Channel9 event ID register */ -#define SOC_ETM_CH9_EVT_ID_REG (DR_REG_SOC_BASE + 0x60) +#define SOC_ETM_CH9_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x60) /** SOC_ETM_CH9_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch9_evt_id + * Configures the event ID of channel9. */ #define SOC_ETM_CH9_EVT_ID 0x000000FFU #define SOC_ETM_CH9_EVT_ID_M (SOC_ETM_CH9_EVT_ID_V << SOC_ETM_CH9_EVT_ID_S) @@ -1320,11 +1620,11 @@ extern "C" { #define SOC_ETM_CH9_EVT_ID_S 0 /** SOC_ETM_CH9_TASK_ID_REG register - * channel9 task id register + * Channel9 task ID register */ -#define SOC_ETM_CH9_TASK_ID_REG (DR_REG_SOC_BASE + 0x64) +#define SOC_ETM_CH9_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x64) /** SOC_ETM_CH9_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch9_task_id + * Configures the task ID of channel9. */ #define SOC_ETM_CH9_TASK_ID 0x000000FFU #define SOC_ETM_CH9_TASK_ID_M (SOC_ETM_CH9_TASK_ID_V << SOC_ETM_CH9_TASK_ID_S) @@ -1332,11 +1632,11 @@ extern "C" { #define SOC_ETM_CH9_TASK_ID_S 0 /** SOC_ETM_CH10_EVT_ID_REG register - * channel10 event id register + * Channel10 event ID register */ -#define SOC_ETM_CH10_EVT_ID_REG (DR_REG_SOC_BASE + 0x68) +#define SOC_ETM_CH10_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x68) /** SOC_ETM_CH10_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch10_evt_id + * Configures the event ID of channel10. */ #define SOC_ETM_CH10_EVT_ID 0x000000FFU #define SOC_ETM_CH10_EVT_ID_M (SOC_ETM_CH10_EVT_ID_V << SOC_ETM_CH10_EVT_ID_S) @@ -1344,11 +1644,11 @@ extern "C" { #define SOC_ETM_CH10_EVT_ID_S 0 /** SOC_ETM_CH10_TASK_ID_REG register - * channel10 task id register + * Channel10 task ID register */ -#define SOC_ETM_CH10_TASK_ID_REG (DR_REG_SOC_BASE + 0x6c) +#define SOC_ETM_CH10_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x6c) /** SOC_ETM_CH10_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch10_task_id + * Configures the task ID of channel10. */ #define SOC_ETM_CH10_TASK_ID 0x000000FFU #define SOC_ETM_CH10_TASK_ID_M (SOC_ETM_CH10_TASK_ID_V << SOC_ETM_CH10_TASK_ID_S) @@ -1356,11 +1656,11 @@ extern "C" { #define SOC_ETM_CH10_TASK_ID_S 0 /** SOC_ETM_CH11_EVT_ID_REG register - * channel11 event id register + * Channel11 event ID register */ -#define SOC_ETM_CH11_EVT_ID_REG (DR_REG_SOC_BASE + 0x70) +#define SOC_ETM_CH11_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x70) /** SOC_ETM_CH11_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch11_evt_id + * Configures the event ID of channel11. */ #define SOC_ETM_CH11_EVT_ID 0x000000FFU #define SOC_ETM_CH11_EVT_ID_M (SOC_ETM_CH11_EVT_ID_V << SOC_ETM_CH11_EVT_ID_S) @@ -1368,11 +1668,11 @@ extern "C" { #define SOC_ETM_CH11_EVT_ID_S 0 /** SOC_ETM_CH11_TASK_ID_REG register - * channel11 task id register + * Channel11 task ID register */ -#define SOC_ETM_CH11_TASK_ID_REG (DR_REG_SOC_BASE + 0x74) +#define SOC_ETM_CH11_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x74) /** SOC_ETM_CH11_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch11_task_id + * Configures the task ID of channel11. */ #define SOC_ETM_CH11_TASK_ID 0x000000FFU #define SOC_ETM_CH11_TASK_ID_M (SOC_ETM_CH11_TASK_ID_V << SOC_ETM_CH11_TASK_ID_S) @@ -1380,11 +1680,11 @@ extern "C" { #define SOC_ETM_CH11_TASK_ID_S 0 /** SOC_ETM_CH12_EVT_ID_REG register - * channel12 event id register + * Channel12 event ID register */ -#define SOC_ETM_CH12_EVT_ID_REG (DR_REG_SOC_BASE + 0x78) +#define SOC_ETM_CH12_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x78) /** SOC_ETM_CH12_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch12_evt_id + * Configures the event ID of channel12. */ #define SOC_ETM_CH12_EVT_ID 0x000000FFU #define SOC_ETM_CH12_EVT_ID_M (SOC_ETM_CH12_EVT_ID_V << SOC_ETM_CH12_EVT_ID_S) @@ -1392,11 +1692,11 @@ extern "C" { #define SOC_ETM_CH12_EVT_ID_S 0 /** SOC_ETM_CH12_TASK_ID_REG register - * channel12 task id register + * Channel12 task ID register */ -#define SOC_ETM_CH12_TASK_ID_REG (DR_REG_SOC_BASE + 0x7c) +#define SOC_ETM_CH12_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x7c) /** SOC_ETM_CH12_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch12_task_id + * Configures the task ID of channel12. */ #define SOC_ETM_CH12_TASK_ID 0x000000FFU #define SOC_ETM_CH12_TASK_ID_M (SOC_ETM_CH12_TASK_ID_V << SOC_ETM_CH12_TASK_ID_S) @@ -1404,11 +1704,11 @@ extern "C" { #define SOC_ETM_CH12_TASK_ID_S 0 /** SOC_ETM_CH13_EVT_ID_REG register - * channel13 event id register + * Channel13 event ID register */ -#define SOC_ETM_CH13_EVT_ID_REG (DR_REG_SOC_BASE + 0x80) +#define SOC_ETM_CH13_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x80) /** SOC_ETM_CH13_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch13_evt_id + * Configures the event ID of channel13. */ #define SOC_ETM_CH13_EVT_ID 0x000000FFU #define SOC_ETM_CH13_EVT_ID_M (SOC_ETM_CH13_EVT_ID_V << SOC_ETM_CH13_EVT_ID_S) @@ -1416,11 +1716,11 @@ extern "C" { #define SOC_ETM_CH13_EVT_ID_S 0 /** SOC_ETM_CH13_TASK_ID_REG register - * channel13 task id register + * Channel13 task ID register */ -#define SOC_ETM_CH13_TASK_ID_REG (DR_REG_SOC_BASE + 0x84) +#define SOC_ETM_CH13_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x84) /** SOC_ETM_CH13_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch13_task_id + * Configures the task ID of channel13. */ #define SOC_ETM_CH13_TASK_ID 0x000000FFU #define SOC_ETM_CH13_TASK_ID_M (SOC_ETM_CH13_TASK_ID_V << SOC_ETM_CH13_TASK_ID_S) @@ -1428,11 +1728,11 @@ extern "C" { #define SOC_ETM_CH13_TASK_ID_S 0 /** SOC_ETM_CH14_EVT_ID_REG register - * channel14 event id register + * Channel14 event ID register */ -#define SOC_ETM_CH14_EVT_ID_REG (DR_REG_SOC_BASE + 0x88) +#define SOC_ETM_CH14_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x88) /** SOC_ETM_CH14_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch14_evt_id + * Configures the event ID of channel14. */ #define SOC_ETM_CH14_EVT_ID 0x000000FFU #define SOC_ETM_CH14_EVT_ID_M (SOC_ETM_CH14_EVT_ID_V << SOC_ETM_CH14_EVT_ID_S) @@ -1440,11 +1740,11 @@ extern "C" { #define SOC_ETM_CH14_EVT_ID_S 0 /** SOC_ETM_CH14_TASK_ID_REG register - * channel14 task id register + * Channel14 task ID register */ -#define SOC_ETM_CH14_TASK_ID_REG (DR_REG_SOC_BASE + 0x8c) +#define SOC_ETM_CH14_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x8c) /** SOC_ETM_CH14_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch14_task_id + * Configures the task ID of channel14. */ #define SOC_ETM_CH14_TASK_ID 0x000000FFU #define SOC_ETM_CH14_TASK_ID_M (SOC_ETM_CH14_TASK_ID_V << SOC_ETM_CH14_TASK_ID_S) @@ -1452,11 +1752,11 @@ extern "C" { #define SOC_ETM_CH14_TASK_ID_S 0 /** SOC_ETM_CH15_EVT_ID_REG register - * channel15 event id register + * Channel15 event ID register */ -#define SOC_ETM_CH15_EVT_ID_REG (DR_REG_SOC_BASE + 0x90) +#define SOC_ETM_CH15_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x90) /** SOC_ETM_CH15_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch15_evt_id + * Configures the event ID of channel15. */ #define SOC_ETM_CH15_EVT_ID 0x000000FFU #define SOC_ETM_CH15_EVT_ID_M (SOC_ETM_CH15_EVT_ID_V << SOC_ETM_CH15_EVT_ID_S) @@ -1464,11 +1764,11 @@ extern "C" { #define SOC_ETM_CH15_EVT_ID_S 0 /** SOC_ETM_CH15_TASK_ID_REG register - * channel15 task id register + * Channel15 task ID register */ -#define SOC_ETM_CH15_TASK_ID_REG (DR_REG_SOC_BASE + 0x94) +#define SOC_ETM_CH15_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x94) /** SOC_ETM_CH15_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch15_task_id + * Configures the task ID of channel15. */ #define SOC_ETM_CH15_TASK_ID 0x000000FFU #define SOC_ETM_CH15_TASK_ID_M (SOC_ETM_CH15_TASK_ID_V << SOC_ETM_CH15_TASK_ID_S) @@ -1476,11 +1776,11 @@ extern "C" { #define SOC_ETM_CH15_TASK_ID_S 0 /** SOC_ETM_CH16_EVT_ID_REG register - * channel16 event id register + * Channel16 event ID register */ -#define SOC_ETM_CH16_EVT_ID_REG (DR_REG_SOC_BASE + 0x98) +#define SOC_ETM_CH16_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x98) /** SOC_ETM_CH16_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch16_evt_id + * Configures the event ID of channel16. */ #define SOC_ETM_CH16_EVT_ID 0x000000FFU #define SOC_ETM_CH16_EVT_ID_M (SOC_ETM_CH16_EVT_ID_V << SOC_ETM_CH16_EVT_ID_S) @@ -1488,11 +1788,11 @@ extern "C" { #define SOC_ETM_CH16_EVT_ID_S 0 /** SOC_ETM_CH16_TASK_ID_REG register - * channel16 task id register + * Channel16 task ID register */ -#define SOC_ETM_CH16_TASK_ID_REG (DR_REG_SOC_BASE + 0x9c) +#define SOC_ETM_CH16_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x9c) /** SOC_ETM_CH16_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch16_task_id + * Configures the task ID of channel16. */ #define SOC_ETM_CH16_TASK_ID 0x000000FFU #define SOC_ETM_CH16_TASK_ID_M (SOC_ETM_CH16_TASK_ID_V << SOC_ETM_CH16_TASK_ID_S) @@ -1500,11 +1800,11 @@ extern "C" { #define SOC_ETM_CH16_TASK_ID_S 0 /** SOC_ETM_CH17_EVT_ID_REG register - * channel17 event id register + * Channel17 event ID register */ -#define SOC_ETM_CH17_EVT_ID_REG (DR_REG_SOC_BASE + 0xa0) +#define SOC_ETM_CH17_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa0) /** SOC_ETM_CH17_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch17_evt_id + * Configures the event ID of channel17. */ #define SOC_ETM_CH17_EVT_ID 0x000000FFU #define SOC_ETM_CH17_EVT_ID_M (SOC_ETM_CH17_EVT_ID_V << SOC_ETM_CH17_EVT_ID_S) @@ -1512,11 +1812,11 @@ extern "C" { #define SOC_ETM_CH17_EVT_ID_S 0 /** SOC_ETM_CH17_TASK_ID_REG register - * channel17 task id register + * Channel17 task ID register */ -#define SOC_ETM_CH17_TASK_ID_REG (DR_REG_SOC_BASE + 0xa4) +#define SOC_ETM_CH17_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xa4) /** SOC_ETM_CH17_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch17_task_id + * Configures the task ID of channel17. */ #define SOC_ETM_CH17_TASK_ID 0x000000FFU #define SOC_ETM_CH17_TASK_ID_M (SOC_ETM_CH17_TASK_ID_V << SOC_ETM_CH17_TASK_ID_S) @@ -1524,11 +1824,11 @@ extern "C" { #define SOC_ETM_CH17_TASK_ID_S 0 /** SOC_ETM_CH18_EVT_ID_REG register - * channel18 event id register + * Channel18 event ID register */ -#define SOC_ETM_CH18_EVT_ID_REG (DR_REG_SOC_BASE + 0xa8) +#define SOC_ETM_CH18_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa8) /** SOC_ETM_CH18_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch18_evt_id + * Configures the event ID of channel18. */ #define SOC_ETM_CH18_EVT_ID 0x000000FFU #define SOC_ETM_CH18_EVT_ID_M (SOC_ETM_CH18_EVT_ID_V << SOC_ETM_CH18_EVT_ID_S) @@ -1536,11 +1836,11 @@ extern "C" { #define SOC_ETM_CH18_EVT_ID_S 0 /** SOC_ETM_CH18_TASK_ID_REG register - * channel18 task id register + * Channel18 task ID register */ -#define SOC_ETM_CH18_TASK_ID_REG (DR_REG_SOC_BASE + 0xac) +#define SOC_ETM_CH18_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xac) /** SOC_ETM_CH18_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch18_task_id + * Configures the task ID of channel18. */ #define SOC_ETM_CH18_TASK_ID 0x000000FFU #define SOC_ETM_CH18_TASK_ID_M (SOC_ETM_CH18_TASK_ID_V << SOC_ETM_CH18_TASK_ID_S) @@ -1548,11 +1848,11 @@ extern "C" { #define SOC_ETM_CH18_TASK_ID_S 0 /** SOC_ETM_CH19_EVT_ID_REG register - * channel19 event id register + * Channel19 event ID register */ -#define SOC_ETM_CH19_EVT_ID_REG (DR_REG_SOC_BASE + 0xb0) +#define SOC_ETM_CH19_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb0) /** SOC_ETM_CH19_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch19_evt_id + * Configures the event ID of channel19. */ #define SOC_ETM_CH19_EVT_ID 0x000000FFU #define SOC_ETM_CH19_EVT_ID_M (SOC_ETM_CH19_EVT_ID_V << SOC_ETM_CH19_EVT_ID_S) @@ -1560,11 +1860,11 @@ extern "C" { #define SOC_ETM_CH19_EVT_ID_S 0 /** SOC_ETM_CH19_TASK_ID_REG register - * channel19 task id register + * Channel19 task ID register */ -#define SOC_ETM_CH19_TASK_ID_REG (DR_REG_SOC_BASE + 0xb4) +#define SOC_ETM_CH19_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xb4) /** SOC_ETM_CH19_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch19_task_id + * Configures the task ID of channel19. */ #define SOC_ETM_CH19_TASK_ID 0x000000FFU #define SOC_ETM_CH19_TASK_ID_M (SOC_ETM_CH19_TASK_ID_V << SOC_ETM_CH19_TASK_ID_S) @@ -1572,11 +1872,11 @@ extern "C" { #define SOC_ETM_CH19_TASK_ID_S 0 /** SOC_ETM_CH20_EVT_ID_REG register - * channel20 event id register + * Channel20 event ID register */ -#define SOC_ETM_CH20_EVT_ID_REG (DR_REG_SOC_BASE + 0xb8) +#define SOC_ETM_CH20_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb8) /** SOC_ETM_CH20_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch20_evt_id + * Configures the event ID of channel20. */ #define SOC_ETM_CH20_EVT_ID 0x000000FFU #define SOC_ETM_CH20_EVT_ID_M (SOC_ETM_CH20_EVT_ID_V << SOC_ETM_CH20_EVT_ID_S) @@ -1584,11 +1884,11 @@ extern "C" { #define SOC_ETM_CH20_EVT_ID_S 0 /** SOC_ETM_CH20_TASK_ID_REG register - * channel20 task id register + * Channel20 task ID register */ -#define SOC_ETM_CH20_TASK_ID_REG (DR_REG_SOC_BASE + 0xbc) +#define SOC_ETM_CH20_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xbc) /** SOC_ETM_CH20_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch20_task_id + * Configures the task ID of channel20. */ #define SOC_ETM_CH20_TASK_ID 0x000000FFU #define SOC_ETM_CH20_TASK_ID_M (SOC_ETM_CH20_TASK_ID_V << SOC_ETM_CH20_TASK_ID_S) @@ -1596,11 +1896,11 @@ extern "C" { #define SOC_ETM_CH20_TASK_ID_S 0 /** SOC_ETM_CH21_EVT_ID_REG register - * channel21 event id register + * Channel21 event ID register */ -#define SOC_ETM_CH21_EVT_ID_REG (DR_REG_SOC_BASE + 0xc0) +#define SOC_ETM_CH21_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc0) /** SOC_ETM_CH21_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch21_evt_id + * Configures the event ID of channel21. */ #define SOC_ETM_CH21_EVT_ID 0x000000FFU #define SOC_ETM_CH21_EVT_ID_M (SOC_ETM_CH21_EVT_ID_V << SOC_ETM_CH21_EVT_ID_S) @@ -1608,11 +1908,11 @@ extern "C" { #define SOC_ETM_CH21_EVT_ID_S 0 /** SOC_ETM_CH21_TASK_ID_REG register - * channel21 task id register + * Channel21 task ID register */ -#define SOC_ETM_CH21_TASK_ID_REG (DR_REG_SOC_BASE + 0xc4) +#define SOC_ETM_CH21_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xc4) /** SOC_ETM_CH21_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch21_task_id + * Configures the task ID of channel21. */ #define SOC_ETM_CH21_TASK_ID 0x000000FFU #define SOC_ETM_CH21_TASK_ID_M (SOC_ETM_CH21_TASK_ID_V << SOC_ETM_CH21_TASK_ID_S) @@ -1620,11 +1920,11 @@ extern "C" { #define SOC_ETM_CH21_TASK_ID_S 0 /** SOC_ETM_CH22_EVT_ID_REG register - * channel22 event id register + * Channel22 event ID register */ -#define SOC_ETM_CH22_EVT_ID_REG (DR_REG_SOC_BASE + 0xc8) +#define SOC_ETM_CH22_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc8) /** SOC_ETM_CH22_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch22_evt_id + * Configures the event ID of channel22. */ #define SOC_ETM_CH22_EVT_ID 0x000000FFU #define SOC_ETM_CH22_EVT_ID_M (SOC_ETM_CH22_EVT_ID_V << SOC_ETM_CH22_EVT_ID_S) @@ -1632,11 +1932,11 @@ extern "C" { #define SOC_ETM_CH22_EVT_ID_S 0 /** SOC_ETM_CH22_TASK_ID_REG register - * channel22 task id register + * Channel22 task ID register */ -#define SOC_ETM_CH22_TASK_ID_REG (DR_REG_SOC_BASE + 0xcc) +#define SOC_ETM_CH22_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xcc) /** SOC_ETM_CH22_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch22_task_id + * Configures the task ID of channel22. */ #define SOC_ETM_CH22_TASK_ID 0x000000FFU #define SOC_ETM_CH22_TASK_ID_M (SOC_ETM_CH22_TASK_ID_V << SOC_ETM_CH22_TASK_ID_S) @@ -1644,11 +1944,11 @@ extern "C" { #define SOC_ETM_CH22_TASK_ID_S 0 /** SOC_ETM_CH23_EVT_ID_REG register - * channel23 event id register + * Channel23 event ID register */ -#define SOC_ETM_CH23_EVT_ID_REG (DR_REG_SOC_BASE + 0xd0) +#define SOC_ETM_CH23_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd0) /** SOC_ETM_CH23_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch23_evt_id + * Configures the event ID of channel23. */ #define SOC_ETM_CH23_EVT_ID 0x000000FFU #define SOC_ETM_CH23_EVT_ID_M (SOC_ETM_CH23_EVT_ID_V << SOC_ETM_CH23_EVT_ID_S) @@ -1656,11 +1956,11 @@ extern "C" { #define SOC_ETM_CH23_EVT_ID_S 0 /** SOC_ETM_CH23_TASK_ID_REG register - * channel23 task id register + * Channel23 task ID register */ -#define SOC_ETM_CH23_TASK_ID_REG (DR_REG_SOC_BASE + 0xd4) +#define SOC_ETM_CH23_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xd4) /** SOC_ETM_CH23_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch23_task_id + * Configures the task ID of channel23. */ #define SOC_ETM_CH23_TASK_ID 0x000000FFU #define SOC_ETM_CH23_TASK_ID_M (SOC_ETM_CH23_TASK_ID_V << SOC_ETM_CH23_TASK_ID_S) @@ -1668,11 +1968,11 @@ extern "C" { #define SOC_ETM_CH23_TASK_ID_S 0 /** SOC_ETM_CH24_EVT_ID_REG register - * channel24 event id register + * Channel24 event ID register */ -#define SOC_ETM_CH24_EVT_ID_REG (DR_REG_SOC_BASE + 0xd8) +#define SOC_ETM_CH24_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd8) /** SOC_ETM_CH24_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch24_evt_id + * Configures the event ID of channel24. */ #define SOC_ETM_CH24_EVT_ID 0x000000FFU #define SOC_ETM_CH24_EVT_ID_M (SOC_ETM_CH24_EVT_ID_V << SOC_ETM_CH24_EVT_ID_S) @@ -1680,11 +1980,11 @@ extern "C" { #define SOC_ETM_CH24_EVT_ID_S 0 /** SOC_ETM_CH24_TASK_ID_REG register - * channel24 task id register + * Channel24 task ID register */ -#define SOC_ETM_CH24_TASK_ID_REG (DR_REG_SOC_BASE + 0xdc) +#define SOC_ETM_CH24_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xdc) /** SOC_ETM_CH24_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch24_task_id + * Configures the task ID of channel24. */ #define SOC_ETM_CH24_TASK_ID 0x000000FFU #define SOC_ETM_CH24_TASK_ID_M (SOC_ETM_CH24_TASK_ID_V << SOC_ETM_CH24_TASK_ID_S) @@ -1692,11 +1992,11 @@ extern "C" { #define SOC_ETM_CH24_TASK_ID_S 0 /** SOC_ETM_CH25_EVT_ID_REG register - * channel25 event id register + * Channel25 event ID register */ -#define SOC_ETM_CH25_EVT_ID_REG (DR_REG_SOC_BASE + 0xe0) +#define SOC_ETM_CH25_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe0) /** SOC_ETM_CH25_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch25_evt_id + * Configures the event ID of channel25. */ #define SOC_ETM_CH25_EVT_ID 0x000000FFU #define SOC_ETM_CH25_EVT_ID_M (SOC_ETM_CH25_EVT_ID_V << SOC_ETM_CH25_EVT_ID_S) @@ -1704,11 +2004,11 @@ extern "C" { #define SOC_ETM_CH25_EVT_ID_S 0 /** SOC_ETM_CH25_TASK_ID_REG register - * channel25 task id register + * Channel25 task ID register */ -#define SOC_ETM_CH25_TASK_ID_REG (DR_REG_SOC_BASE + 0xe4) +#define SOC_ETM_CH25_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xe4) /** SOC_ETM_CH25_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch25_task_id + * Configures the task ID of channel25. */ #define SOC_ETM_CH25_TASK_ID 0x000000FFU #define SOC_ETM_CH25_TASK_ID_M (SOC_ETM_CH25_TASK_ID_V << SOC_ETM_CH25_TASK_ID_S) @@ -1716,11 +2016,11 @@ extern "C" { #define SOC_ETM_CH25_TASK_ID_S 0 /** SOC_ETM_CH26_EVT_ID_REG register - * channel26 event id register + * Channel26 event ID register */ -#define SOC_ETM_CH26_EVT_ID_REG (DR_REG_SOC_BASE + 0xe8) +#define SOC_ETM_CH26_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe8) /** SOC_ETM_CH26_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch26_evt_id + * Configures the event ID of channel26. */ #define SOC_ETM_CH26_EVT_ID 0x000000FFU #define SOC_ETM_CH26_EVT_ID_M (SOC_ETM_CH26_EVT_ID_V << SOC_ETM_CH26_EVT_ID_S) @@ -1728,11 +2028,11 @@ extern "C" { #define SOC_ETM_CH26_EVT_ID_S 0 /** SOC_ETM_CH26_TASK_ID_REG register - * channel26 task id register + * Channel26 task ID register */ -#define SOC_ETM_CH26_TASK_ID_REG (DR_REG_SOC_BASE + 0xec) +#define SOC_ETM_CH26_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xec) /** SOC_ETM_CH26_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch26_task_id + * Configures the task ID of channel26. */ #define SOC_ETM_CH26_TASK_ID 0x000000FFU #define SOC_ETM_CH26_TASK_ID_M (SOC_ETM_CH26_TASK_ID_V << SOC_ETM_CH26_TASK_ID_S) @@ -1740,11 +2040,11 @@ extern "C" { #define SOC_ETM_CH26_TASK_ID_S 0 /** SOC_ETM_CH27_EVT_ID_REG register - * channel27 event id register + * Channel27 event ID register */ -#define SOC_ETM_CH27_EVT_ID_REG (DR_REG_SOC_BASE + 0xf0) +#define SOC_ETM_CH27_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf0) /** SOC_ETM_CH27_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch27_evt_id + * Configures the event ID of channel27. */ #define SOC_ETM_CH27_EVT_ID 0x000000FFU #define SOC_ETM_CH27_EVT_ID_M (SOC_ETM_CH27_EVT_ID_V << SOC_ETM_CH27_EVT_ID_S) @@ -1752,11 +2052,11 @@ extern "C" { #define SOC_ETM_CH27_EVT_ID_S 0 /** SOC_ETM_CH27_TASK_ID_REG register - * channel27 task id register + * Channel27 task ID register */ -#define SOC_ETM_CH27_TASK_ID_REG (DR_REG_SOC_BASE + 0xf4) +#define SOC_ETM_CH27_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xf4) /** SOC_ETM_CH27_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch27_task_id + * Configures the task ID of channel27. */ #define SOC_ETM_CH27_TASK_ID 0x000000FFU #define SOC_ETM_CH27_TASK_ID_M (SOC_ETM_CH27_TASK_ID_V << SOC_ETM_CH27_TASK_ID_S) @@ -1764,11 +2064,11 @@ extern "C" { #define SOC_ETM_CH27_TASK_ID_S 0 /** SOC_ETM_CH28_EVT_ID_REG register - * channel28 event id register + * Channel28 event ID register */ -#define SOC_ETM_CH28_EVT_ID_REG (DR_REG_SOC_BASE + 0xf8) +#define SOC_ETM_CH28_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf8) /** SOC_ETM_CH28_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch28_evt_id + * Configures the event ID of channel28. */ #define SOC_ETM_CH28_EVT_ID 0x000000FFU #define SOC_ETM_CH28_EVT_ID_M (SOC_ETM_CH28_EVT_ID_V << SOC_ETM_CH28_EVT_ID_S) @@ -1776,11 +2076,11 @@ extern "C" { #define SOC_ETM_CH28_EVT_ID_S 0 /** SOC_ETM_CH28_TASK_ID_REG register - * channel28 task id register + * Channel28 task ID register */ -#define SOC_ETM_CH28_TASK_ID_REG (DR_REG_SOC_BASE + 0xfc) +#define SOC_ETM_CH28_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xfc) /** SOC_ETM_CH28_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch28_task_id + * Configures the task ID of channel28. */ #define SOC_ETM_CH28_TASK_ID 0x000000FFU #define SOC_ETM_CH28_TASK_ID_M (SOC_ETM_CH28_TASK_ID_V << SOC_ETM_CH28_TASK_ID_S) @@ -1788,11 +2088,11 @@ extern "C" { #define SOC_ETM_CH28_TASK_ID_S 0 /** SOC_ETM_CH29_EVT_ID_REG register - * channel29 event id register + * Channel29 event ID register */ -#define SOC_ETM_CH29_EVT_ID_REG (DR_REG_SOC_BASE + 0x100) +#define SOC_ETM_CH29_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x100) /** SOC_ETM_CH29_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch29_evt_id + * Configures the event ID of channel29. */ #define SOC_ETM_CH29_EVT_ID 0x000000FFU #define SOC_ETM_CH29_EVT_ID_M (SOC_ETM_CH29_EVT_ID_V << SOC_ETM_CH29_EVT_ID_S) @@ -1800,11 +2100,11 @@ extern "C" { #define SOC_ETM_CH29_EVT_ID_S 0 /** SOC_ETM_CH29_TASK_ID_REG register - * channel29 task id register + * Channel29 task ID register */ -#define SOC_ETM_CH29_TASK_ID_REG (DR_REG_SOC_BASE + 0x104) +#define SOC_ETM_CH29_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x104) /** SOC_ETM_CH29_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch29_task_id + * Configures the task ID of channel29. */ #define SOC_ETM_CH29_TASK_ID 0x000000FFU #define SOC_ETM_CH29_TASK_ID_M (SOC_ETM_CH29_TASK_ID_V << SOC_ETM_CH29_TASK_ID_S) @@ -1812,11 +2112,11 @@ extern "C" { #define SOC_ETM_CH29_TASK_ID_S 0 /** SOC_ETM_CH30_EVT_ID_REG register - * channel30 event id register + * Channel30 event ID register */ -#define SOC_ETM_CH30_EVT_ID_REG (DR_REG_SOC_BASE + 0x108) +#define SOC_ETM_CH30_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x108) /** SOC_ETM_CH30_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch30_evt_id + * Configures the event ID of channel30. */ #define SOC_ETM_CH30_EVT_ID 0x000000FFU #define SOC_ETM_CH30_EVT_ID_M (SOC_ETM_CH30_EVT_ID_V << SOC_ETM_CH30_EVT_ID_S) @@ -1824,11 +2124,11 @@ extern "C" { #define SOC_ETM_CH30_EVT_ID_S 0 /** SOC_ETM_CH30_TASK_ID_REG register - * channel30 task id register + * Channel30 task ID register */ -#define SOC_ETM_CH30_TASK_ID_REG (DR_REG_SOC_BASE + 0x10c) +#define SOC_ETM_CH30_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x10c) /** SOC_ETM_CH30_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch30_task_id + * Configures the task ID of channel30. */ #define SOC_ETM_CH30_TASK_ID 0x000000FFU #define SOC_ETM_CH30_TASK_ID_M (SOC_ETM_CH30_TASK_ID_V << SOC_ETM_CH30_TASK_ID_S) @@ -1836,11 +2136,11 @@ extern "C" { #define SOC_ETM_CH30_TASK_ID_S 0 /** SOC_ETM_CH31_EVT_ID_REG register - * channel31 event id register + * Channel31 event ID register */ -#define SOC_ETM_CH31_EVT_ID_REG (DR_REG_SOC_BASE + 0x110) +#define SOC_ETM_CH31_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x110) /** SOC_ETM_CH31_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch31_evt_id + * Configures the event ID of channel31. */ #define SOC_ETM_CH31_EVT_ID 0x000000FFU #define SOC_ETM_CH31_EVT_ID_M (SOC_ETM_CH31_EVT_ID_V << SOC_ETM_CH31_EVT_ID_S) @@ -1848,11 +2148,11 @@ extern "C" { #define SOC_ETM_CH31_EVT_ID_S 0 /** SOC_ETM_CH31_TASK_ID_REG register - * channel31 task id register + * Channel31 task ID register */ -#define SOC_ETM_CH31_TASK_ID_REG (DR_REG_SOC_BASE + 0x114) +#define SOC_ETM_CH31_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x114) /** SOC_ETM_CH31_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch31_task_id + * Configures the task ID of channel31. */ #define SOC_ETM_CH31_TASK_ID 0x000000FFU #define SOC_ETM_CH31_TASK_ID_M (SOC_ETM_CH31_TASK_ID_V << SOC_ETM_CH31_TASK_ID_S) @@ -1860,11 +2160,11 @@ extern "C" { #define SOC_ETM_CH31_TASK_ID_S 0 /** SOC_ETM_CH32_EVT_ID_REG register - * channel32 event id register + * Channel32 event ID register */ -#define SOC_ETM_CH32_EVT_ID_REG (DR_REG_SOC_BASE + 0x118) +#define SOC_ETM_CH32_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x118) /** SOC_ETM_CH32_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch32_evt_id + * Configures the event ID of channel32. */ #define SOC_ETM_CH32_EVT_ID 0x000000FFU #define SOC_ETM_CH32_EVT_ID_M (SOC_ETM_CH32_EVT_ID_V << SOC_ETM_CH32_EVT_ID_S) @@ -1872,11 +2172,11 @@ extern "C" { #define SOC_ETM_CH32_EVT_ID_S 0 /** SOC_ETM_CH32_TASK_ID_REG register - * channel32 task id register + * Channel32 task ID register */ -#define SOC_ETM_CH32_TASK_ID_REG (DR_REG_SOC_BASE + 0x11c) +#define SOC_ETM_CH32_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x11c) /** SOC_ETM_CH32_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch32_task_id + * Configures the task ID of channel32. */ #define SOC_ETM_CH32_TASK_ID 0x000000FFU #define SOC_ETM_CH32_TASK_ID_M (SOC_ETM_CH32_TASK_ID_V << SOC_ETM_CH32_TASK_ID_S) @@ -1884,11 +2184,11 @@ extern "C" { #define SOC_ETM_CH32_TASK_ID_S 0 /** SOC_ETM_CH33_EVT_ID_REG register - * channel33 event id register + * Channel33 event ID register */ -#define SOC_ETM_CH33_EVT_ID_REG (DR_REG_SOC_BASE + 0x120) +#define SOC_ETM_CH33_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x120) /** SOC_ETM_CH33_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch33_evt_id + * Configures the event ID of channel33. */ #define SOC_ETM_CH33_EVT_ID 0x000000FFU #define SOC_ETM_CH33_EVT_ID_M (SOC_ETM_CH33_EVT_ID_V << SOC_ETM_CH33_EVT_ID_S) @@ -1896,11 +2196,11 @@ extern "C" { #define SOC_ETM_CH33_EVT_ID_S 0 /** SOC_ETM_CH33_TASK_ID_REG register - * channel33 task id register + * Channel33 task ID register */ -#define SOC_ETM_CH33_TASK_ID_REG (DR_REG_SOC_BASE + 0x124) +#define SOC_ETM_CH33_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x124) /** SOC_ETM_CH33_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch33_task_id + * Configures the task ID of channel33. */ #define SOC_ETM_CH33_TASK_ID 0x000000FFU #define SOC_ETM_CH33_TASK_ID_M (SOC_ETM_CH33_TASK_ID_V << SOC_ETM_CH33_TASK_ID_S) @@ -1908,11 +2208,11 @@ extern "C" { #define SOC_ETM_CH33_TASK_ID_S 0 /** SOC_ETM_CH34_EVT_ID_REG register - * channel34 event id register + * Channel34 event ID register */ -#define SOC_ETM_CH34_EVT_ID_REG (DR_REG_SOC_BASE + 0x128) +#define SOC_ETM_CH34_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x128) /** SOC_ETM_CH34_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch34_evt_id + * Configures the event ID of channel34. */ #define SOC_ETM_CH34_EVT_ID 0x000000FFU #define SOC_ETM_CH34_EVT_ID_M (SOC_ETM_CH34_EVT_ID_V << SOC_ETM_CH34_EVT_ID_S) @@ -1920,11 +2220,11 @@ extern "C" { #define SOC_ETM_CH34_EVT_ID_S 0 /** SOC_ETM_CH34_TASK_ID_REG register - * channel34 task id register + * Channel34 task ID register */ -#define SOC_ETM_CH34_TASK_ID_REG (DR_REG_SOC_BASE + 0x12c) +#define SOC_ETM_CH34_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x12c) /** SOC_ETM_CH34_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch34_task_id + * Configures the task ID of channel34. */ #define SOC_ETM_CH34_TASK_ID 0x000000FFU #define SOC_ETM_CH34_TASK_ID_M (SOC_ETM_CH34_TASK_ID_V << SOC_ETM_CH34_TASK_ID_S) @@ -1932,11 +2232,11 @@ extern "C" { #define SOC_ETM_CH34_TASK_ID_S 0 /** SOC_ETM_CH35_EVT_ID_REG register - * channel35 event id register + * Channel35 event ID register */ -#define SOC_ETM_CH35_EVT_ID_REG (DR_REG_SOC_BASE + 0x130) +#define SOC_ETM_CH35_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x130) /** SOC_ETM_CH35_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch35_evt_id + * Configures the event ID of channel35. */ #define SOC_ETM_CH35_EVT_ID 0x000000FFU #define SOC_ETM_CH35_EVT_ID_M (SOC_ETM_CH35_EVT_ID_V << SOC_ETM_CH35_EVT_ID_S) @@ -1944,11 +2244,11 @@ extern "C" { #define SOC_ETM_CH35_EVT_ID_S 0 /** SOC_ETM_CH35_TASK_ID_REG register - * channel35 task id register + * Channel35 task ID register */ -#define SOC_ETM_CH35_TASK_ID_REG (DR_REG_SOC_BASE + 0x134) +#define SOC_ETM_CH35_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x134) /** SOC_ETM_CH35_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch35_task_id + * Configures the task ID of channel35. */ #define SOC_ETM_CH35_TASK_ID 0x000000FFU #define SOC_ETM_CH35_TASK_ID_M (SOC_ETM_CH35_TASK_ID_V << SOC_ETM_CH35_TASK_ID_S) @@ -1956,11 +2256,11 @@ extern "C" { #define SOC_ETM_CH35_TASK_ID_S 0 /** SOC_ETM_CH36_EVT_ID_REG register - * channel36 event id register + * Channel36 event ID register */ -#define SOC_ETM_CH36_EVT_ID_REG (DR_REG_SOC_BASE + 0x138) +#define SOC_ETM_CH36_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x138) /** SOC_ETM_CH36_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch36_evt_id + * Configures the event ID of channel36. */ #define SOC_ETM_CH36_EVT_ID 0x000000FFU #define SOC_ETM_CH36_EVT_ID_M (SOC_ETM_CH36_EVT_ID_V << SOC_ETM_CH36_EVT_ID_S) @@ -1968,11 +2268,11 @@ extern "C" { #define SOC_ETM_CH36_EVT_ID_S 0 /** SOC_ETM_CH36_TASK_ID_REG register - * channel36 task id register + * Channel36 task ID register */ -#define SOC_ETM_CH36_TASK_ID_REG (DR_REG_SOC_BASE + 0x13c) +#define SOC_ETM_CH36_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x13c) /** SOC_ETM_CH36_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch36_task_id + * Configures the task ID of channel36. */ #define SOC_ETM_CH36_TASK_ID 0x000000FFU #define SOC_ETM_CH36_TASK_ID_M (SOC_ETM_CH36_TASK_ID_V << SOC_ETM_CH36_TASK_ID_S) @@ -1980,11 +2280,11 @@ extern "C" { #define SOC_ETM_CH36_TASK_ID_S 0 /** SOC_ETM_CH37_EVT_ID_REG register - * channel37 event id register + * Channel37 event ID register */ -#define SOC_ETM_CH37_EVT_ID_REG (DR_REG_SOC_BASE + 0x140) +#define SOC_ETM_CH37_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x140) /** SOC_ETM_CH37_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch37_evt_id + * Configures the event ID of channel37. */ #define SOC_ETM_CH37_EVT_ID 0x000000FFU #define SOC_ETM_CH37_EVT_ID_M (SOC_ETM_CH37_EVT_ID_V << SOC_ETM_CH37_EVT_ID_S) @@ -1992,11 +2292,11 @@ extern "C" { #define SOC_ETM_CH37_EVT_ID_S 0 /** SOC_ETM_CH37_TASK_ID_REG register - * channel37 task id register + * Channel37 task ID register */ -#define SOC_ETM_CH37_TASK_ID_REG (DR_REG_SOC_BASE + 0x144) +#define SOC_ETM_CH37_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x144) /** SOC_ETM_CH37_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch37_task_id + * Configures the task ID of channel37. */ #define SOC_ETM_CH37_TASK_ID 0x000000FFU #define SOC_ETM_CH37_TASK_ID_M (SOC_ETM_CH37_TASK_ID_V << SOC_ETM_CH37_TASK_ID_S) @@ -2004,11 +2304,11 @@ extern "C" { #define SOC_ETM_CH37_TASK_ID_S 0 /** SOC_ETM_CH38_EVT_ID_REG register - * channel38 event id register + * Channel38 event ID register */ -#define SOC_ETM_CH38_EVT_ID_REG (DR_REG_SOC_BASE + 0x148) +#define SOC_ETM_CH38_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x148) /** SOC_ETM_CH38_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch38_evt_id + * Configures the event ID of channel38. */ #define SOC_ETM_CH38_EVT_ID 0x000000FFU #define SOC_ETM_CH38_EVT_ID_M (SOC_ETM_CH38_EVT_ID_V << SOC_ETM_CH38_EVT_ID_S) @@ -2016,11 +2316,11 @@ extern "C" { #define SOC_ETM_CH38_EVT_ID_S 0 /** SOC_ETM_CH38_TASK_ID_REG register - * channel38 task id register + * Channel38 task ID register */ -#define SOC_ETM_CH38_TASK_ID_REG (DR_REG_SOC_BASE + 0x14c) +#define SOC_ETM_CH38_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x14c) /** SOC_ETM_CH38_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch38_task_id + * Configures the task ID of channel38. */ #define SOC_ETM_CH38_TASK_ID 0x000000FFU #define SOC_ETM_CH38_TASK_ID_M (SOC_ETM_CH38_TASK_ID_V << SOC_ETM_CH38_TASK_ID_S) @@ -2028,11 +2328,11 @@ extern "C" { #define SOC_ETM_CH38_TASK_ID_S 0 /** SOC_ETM_CH39_EVT_ID_REG register - * channel39 event id register + * Channel39 event ID register */ -#define SOC_ETM_CH39_EVT_ID_REG (DR_REG_SOC_BASE + 0x150) +#define SOC_ETM_CH39_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x150) /** SOC_ETM_CH39_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch39_evt_id + * Configures the event ID of channel39. */ #define SOC_ETM_CH39_EVT_ID 0x000000FFU #define SOC_ETM_CH39_EVT_ID_M (SOC_ETM_CH39_EVT_ID_V << SOC_ETM_CH39_EVT_ID_S) @@ -2040,11 +2340,11 @@ extern "C" { #define SOC_ETM_CH39_EVT_ID_S 0 /** SOC_ETM_CH39_TASK_ID_REG register - * channel39 task id register + * Channel39 task ID register */ -#define SOC_ETM_CH39_TASK_ID_REG (DR_REG_SOC_BASE + 0x154) +#define SOC_ETM_CH39_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x154) /** SOC_ETM_CH39_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch39_task_id + * Configures the task ID of channel39. */ #define SOC_ETM_CH39_TASK_ID 0x000000FFU #define SOC_ETM_CH39_TASK_ID_M (SOC_ETM_CH39_TASK_ID_V << SOC_ETM_CH39_TASK_ID_S) @@ -2052,11 +2352,11 @@ extern "C" { #define SOC_ETM_CH39_TASK_ID_S 0 /** SOC_ETM_CH40_EVT_ID_REG register - * channel40 event id register + * Channel40 event ID register */ -#define SOC_ETM_CH40_EVT_ID_REG (DR_REG_SOC_BASE + 0x158) +#define SOC_ETM_CH40_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x158) /** SOC_ETM_CH40_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch40_evt_id + * Configures the event ID of channel40. */ #define SOC_ETM_CH40_EVT_ID 0x000000FFU #define SOC_ETM_CH40_EVT_ID_M (SOC_ETM_CH40_EVT_ID_V << SOC_ETM_CH40_EVT_ID_S) @@ -2064,11 +2364,11 @@ extern "C" { #define SOC_ETM_CH40_EVT_ID_S 0 /** SOC_ETM_CH40_TASK_ID_REG register - * channel40 task id register + * Channel40 task ID register */ -#define SOC_ETM_CH40_TASK_ID_REG (DR_REG_SOC_BASE + 0x15c) +#define SOC_ETM_CH40_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x15c) /** SOC_ETM_CH40_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch40_task_id + * Configures the task ID of channel40. */ #define SOC_ETM_CH40_TASK_ID 0x000000FFU #define SOC_ETM_CH40_TASK_ID_M (SOC_ETM_CH40_TASK_ID_V << SOC_ETM_CH40_TASK_ID_S) @@ -2076,11 +2376,11 @@ extern "C" { #define SOC_ETM_CH40_TASK_ID_S 0 /** SOC_ETM_CH41_EVT_ID_REG register - * channel41 event id register + * Channel41 event ID register */ -#define SOC_ETM_CH41_EVT_ID_REG (DR_REG_SOC_BASE + 0x160) +#define SOC_ETM_CH41_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x160) /** SOC_ETM_CH41_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch41_evt_id + * Configures the event ID of channel41. */ #define SOC_ETM_CH41_EVT_ID 0x000000FFU #define SOC_ETM_CH41_EVT_ID_M (SOC_ETM_CH41_EVT_ID_V << SOC_ETM_CH41_EVT_ID_S) @@ -2088,11 +2388,11 @@ extern "C" { #define SOC_ETM_CH41_EVT_ID_S 0 /** SOC_ETM_CH41_TASK_ID_REG register - * channel41 task id register + * Channel41 task ID register */ -#define SOC_ETM_CH41_TASK_ID_REG (DR_REG_SOC_BASE + 0x164) +#define SOC_ETM_CH41_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x164) /** SOC_ETM_CH41_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch41_task_id + * Configures the task ID of channel41. */ #define SOC_ETM_CH41_TASK_ID 0x000000FFU #define SOC_ETM_CH41_TASK_ID_M (SOC_ETM_CH41_TASK_ID_V << SOC_ETM_CH41_TASK_ID_S) @@ -2100,11 +2400,11 @@ extern "C" { #define SOC_ETM_CH41_TASK_ID_S 0 /** SOC_ETM_CH42_EVT_ID_REG register - * channel42 event id register + * Channel42 event ID register */ -#define SOC_ETM_CH42_EVT_ID_REG (DR_REG_SOC_BASE + 0x168) +#define SOC_ETM_CH42_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x168) /** SOC_ETM_CH42_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch42_evt_id + * Configures the event ID of channel42. */ #define SOC_ETM_CH42_EVT_ID 0x000000FFU #define SOC_ETM_CH42_EVT_ID_M (SOC_ETM_CH42_EVT_ID_V << SOC_ETM_CH42_EVT_ID_S) @@ -2112,11 +2412,11 @@ extern "C" { #define SOC_ETM_CH42_EVT_ID_S 0 /** SOC_ETM_CH42_TASK_ID_REG register - * channel42 task id register + * Channel42 task ID register */ -#define SOC_ETM_CH42_TASK_ID_REG (DR_REG_SOC_BASE + 0x16c) +#define SOC_ETM_CH42_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x16c) /** SOC_ETM_CH42_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch42_task_id + * Configures the task ID of channel42. */ #define SOC_ETM_CH42_TASK_ID 0x000000FFU #define SOC_ETM_CH42_TASK_ID_M (SOC_ETM_CH42_TASK_ID_V << SOC_ETM_CH42_TASK_ID_S) @@ -2124,11 +2424,11 @@ extern "C" { #define SOC_ETM_CH42_TASK_ID_S 0 /** SOC_ETM_CH43_EVT_ID_REG register - * channel43 event id register + * Channel43 event ID register */ -#define SOC_ETM_CH43_EVT_ID_REG (DR_REG_SOC_BASE + 0x170) +#define SOC_ETM_CH43_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x170) /** SOC_ETM_CH43_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch43_evt_id + * Configures the event ID of channel43. */ #define SOC_ETM_CH43_EVT_ID 0x000000FFU #define SOC_ETM_CH43_EVT_ID_M (SOC_ETM_CH43_EVT_ID_V << SOC_ETM_CH43_EVT_ID_S) @@ -2136,11 +2436,11 @@ extern "C" { #define SOC_ETM_CH43_EVT_ID_S 0 /** SOC_ETM_CH43_TASK_ID_REG register - * channel43 task id register + * Channel43 task ID register */ -#define SOC_ETM_CH43_TASK_ID_REG (DR_REG_SOC_BASE + 0x174) +#define SOC_ETM_CH43_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x174) /** SOC_ETM_CH43_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch43_task_id + * Configures the task ID of channel43. */ #define SOC_ETM_CH43_TASK_ID 0x000000FFU #define SOC_ETM_CH43_TASK_ID_M (SOC_ETM_CH43_TASK_ID_V << SOC_ETM_CH43_TASK_ID_S) @@ -2148,11 +2448,11 @@ extern "C" { #define SOC_ETM_CH43_TASK_ID_S 0 /** SOC_ETM_CH44_EVT_ID_REG register - * channel44 event id register + * Channel44 event ID register */ -#define SOC_ETM_CH44_EVT_ID_REG (DR_REG_SOC_BASE + 0x178) +#define SOC_ETM_CH44_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x178) /** SOC_ETM_CH44_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch44_evt_id + * Configures the event ID of channel44. */ #define SOC_ETM_CH44_EVT_ID 0x000000FFU #define SOC_ETM_CH44_EVT_ID_M (SOC_ETM_CH44_EVT_ID_V << SOC_ETM_CH44_EVT_ID_S) @@ -2160,11 +2460,11 @@ extern "C" { #define SOC_ETM_CH44_EVT_ID_S 0 /** SOC_ETM_CH44_TASK_ID_REG register - * channel44 task id register + * Channel44 task ID register */ -#define SOC_ETM_CH44_TASK_ID_REG (DR_REG_SOC_BASE + 0x17c) +#define SOC_ETM_CH44_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x17c) /** SOC_ETM_CH44_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch44_task_id + * Configures the task ID of channel44. */ #define SOC_ETM_CH44_TASK_ID 0x000000FFU #define SOC_ETM_CH44_TASK_ID_M (SOC_ETM_CH44_TASK_ID_V << SOC_ETM_CH44_TASK_ID_S) @@ -2172,11 +2472,11 @@ extern "C" { #define SOC_ETM_CH44_TASK_ID_S 0 /** SOC_ETM_CH45_EVT_ID_REG register - * channel45 event id register + * Channel45 event ID register */ -#define SOC_ETM_CH45_EVT_ID_REG (DR_REG_SOC_BASE + 0x180) +#define SOC_ETM_CH45_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x180) /** SOC_ETM_CH45_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch45_evt_id + * Configures the event ID of channel45. */ #define SOC_ETM_CH45_EVT_ID 0x000000FFU #define SOC_ETM_CH45_EVT_ID_M (SOC_ETM_CH45_EVT_ID_V << SOC_ETM_CH45_EVT_ID_S) @@ -2184,11 +2484,11 @@ extern "C" { #define SOC_ETM_CH45_EVT_ID_S 0 /** SOC_ETM_CH45_TASK_ID_REG register - * channel45 task id register + * Channel45 task ID register */ -#define SOC_ETM_CH45_TASK_ID_REG (DR_REG_SOC_BASE + 0x184) +#define SOC_ETM_CH45_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x184) /** SOC_ETM_CH45_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch45_task_id + * Configures the task ID of channel45. */ #define SOC_ETM_CH45_TASK_ID 0x000000FFU #define SOC_ETM_CH45_TASK_ID_M (SOC_ETM_CH45_TASK_ID_V << SOC_ETM_CH45_TASK_ID_S) @@ -2196,11 +2496,11 @@ extern "C" { #define SOC_ETM_CH45_TASK_ID_S 0 /** SOC_ETM_CH46_EVT_ID_REG register - * channel46 event id register + * Channel46 event ID register */ -#define SOC_ETM_CH46_EVT_ID_REG (DR_REG_SOC_BASE + 0x188) +#define SOC_ETM_CH46_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x188) /** SOC_ETM_CH46_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch46_evt_id + * Configures the event ID of channel46. */ #define SOC_ETM_CH46_EVT_ID 0x000000FFU #define SOC_ETM_CH46_EVT_ID_M (SOC_ETM_CH46_EVT_ID_V << SOC_ETM_CH46_EVT_ID_S) @@ -2208,11 +2508,11 @@ extern "C" { #define SOC_ETM_CH46_EVT_ID_S 0 /** SOC_ETM_CH46_TASK_ID_REG register - * channel46 task id register + * Channel46 task ID register */ -#define SOC_ETM_CH46_TASK_ID_REG (DR_REG_SOC_BASE + 0x18c) +#define SOC_ETM_CH46_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x18c) /** SOC_ETM_CH46_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch46_task_id + * Configures the task ID of channel46. */ #define SOC_ETM_CH46_TASK_ID 0x000000FFU #define SOC_ETM_CH46_TASK_ID_M (SOC_ETM_CH46_TASK_ID_V << SOC_ETM_CH46_TASK_ID_S) @@ -2220,11 +2520,11 @@ extern "C" { #define SOC_ETM_CH46_TASK_ID_S 0 /** SOC_ETM_CH47_EVT_ID_REG register - * channel47 event id register + * Channel47 event ID register */ -#define SOC_ETM_CH47_EVT_ID_REG (DR_REG_SOC_BASE + 0x190) +#define SOC_ETM_CH47_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x190) /** SOC_ETM_CH47_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch47_evt_id + * Configures the event ID of channel47. */ #define SOC_ETM_CH47_EVT_ID 0x000000FFU #define SOC_ETM_CH47_EVT_ID_M (SOC_ETM_CH47_EVT_ID_V << SOC_ETM_CH47_EVT_ID_S) @@ -2232,11 +2532,11 @@ extern "C" { #define SOC_ETM_CH47_EVT_ID_S 0 /** SOC_ETM_CH47_TASK_ID_REG register - * channel47 task id register + * Channel47 task ID register */ -#define SOC_ETM_CH47_TASK_ID_REG (DR_REG_SOC_BASE + 0x194) +#define SOC_ETM_CH47_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x194) /** SOC_ETM_CH47_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch47_task_id + * Configures the task ID of channel47. */ #define SOC_ETM_CH47_TASK_ID 0x000000FFU #define SOC_ETM_CH47_TASK_ID_M (SOC_ETM_CH47_TASK_ID_V << SOC_ETM_CH47_TASK_ID_S) @@ -2244,11 +2544,11 @@ extern "C" { #define SOC_ETM_CH47_TASK_ID_S 0 /** SOC_ETM_CH48_EVT_ID_REG register - * channel48 event id register + * Channel48 event ID register */ -#define SOC_ETM_CH48_EVT_ID_REG (DR_REG_SOC_BASE + 0x198) +#define SOC_ETM_CH48_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x198) /** SOC_ETM_CH48_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch48_evt_id + * Configures the event ID of channel48. */ #define SOC_ETM_CH48_EVT_ID 0x000000FFU #define SOC_ETM_CH48_EVT_ID_M (SOC_ETM_CH48_EVT_ID_V << SOC_ETM_CH48_EVT_ID_S) @@ -2256,11 +2556,11 @@ extern "C" { #define SOC_ETM_CH48_EVT_ID_S 0 /** SOC_ETM_CH48_TASK_ID_REG register - * channel48 task id register + * Channel48 task ID register */ -#define SOC_ETM_CH48_TASK_ID_REG (DR_REG_SOC_BASE + 0x19c) +#define SOC_ETM_CH48_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x19c) /** SOC_ETM_CH48_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch48_task_id + * Configures the task ID of channel48. */ #define SOC_ETM_CH48_TASK_ID 0x000000FFU #define SOC_ETM_CH48_TASK_ID_M (SOC_ETM_CH48_TASK_ID_V << SOC_ETM_CH48_TASK_ID_S) @@ -2268,11 +2568,11 @@ extern "C" { #define SOC_ETM_CH48_TASK_ID_S 0 /** SOC_ETM_CH49_EVT_ID_REG register - * channel49 event id register + * Channel49 event ID register */ -#define SOC_ETM_CH49_EVT_ID_REG (DR_REG_SOC_BASE + 0x1a0) +#define SOC_ETM_CH49_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a0) /** SOC_ETM_CH49_EVT_ID : R/W; bitpos: [7:0]; default: 0; - * ch49_evt_id + * Configures the event ID of channel49. */ #define SOC_ETM_CH49_EVT_ID 0x000000FFU #define SOC_ETM_CH49_EVT_ID_M (SOC_ETM_CH49_EVT_ID_V << SOC_ETM_CH49_EVT_ID_S) @@ -2280,11 +2580,11 @@ extern "C" { #define SOC_ETM_CH49_EVT_ID_S 0 /** SOC_ETM_CH49_TASK_ID_REG register - * channel49 task id register + * Channel49 task ID register */ -#define SOC_ETM_CH49_TASK_ID_REG (DR_REG_SOC_BASE + 0x1a4) +#define SOC_ETM_CH49_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a4) /** SOC_ETM_CH49_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * ch49_task_id + * Configures the task ID of channel49. */ #define SOC_ETM_CH49_TASK_ID 0x000000FFU #define SOC_ETM_CH49_TASK_ID_M (SOC_ETM_CH49_TASK_ID_V << SOC_ETM_CH49_TASK_ID_S) @@ -2292,11 +2592,13 @@ extern "C" { #define SOC_ETM_CH49_TASK_ID_S 0 /** SOC_ETM_CLK_EN_REG register - * etm clock enable register + * ETM clock enable register */ -#define SOC_ETM_CLK_EN_REG (DR_REG_SOC_BASE + 0x1a8) +#define SOC_ETM_CLK_EN_REG (DR_REG_SOC_ETM_BASE + 0x1a8) /** SOC_ETM_CLK_EN : R/W; bitpos: [0]; default: 0; - * clock enable + * Configures resister clock gating. + * 0: Support clock only when application writes registers + * 1: Force on clock gating for registers */ #define SOC_ETM_CLK_EN (BIT(0)) #define SOC_ETM_CLK_EN_M (SOC_ETM_CLK_EN_V << SOC_ETM_CLK_EN_S) @@ -2304,11 +2606,11 @@ extern "C" { #define SOC_ETM_CLK_EN_S 0 /** SOC_ETM_DATE_REG register - * etm date register + * Version control register */ -#define SOC_ETM_DATE_REG (DR_REG_SOC_BASE + 0x1ac) +#define SOC_ETM_DATE_REG (DR_REG_SOC_ETM_BASE + 0x1ac) /** SOC_ETM_DATE : R/W; bitpos: [27:0]; default: 35664018; - * date + * Version control register. */ #define SOC_ETM_DATE 0x0FFFFFFFU #define SOC_ETM_DATE_M (SOC_ETM_DATE_V << SOC_ETM_DATE_S) diff --git a/components/soc/esp32h21/register/soc/soc_etm_struct.h b/components/soc/esp32h21/register/soc/soc_etm_struct.h index e1d7e4bbd0..dc1a8c3a48 100644 --- a/components/soc/esp32h21/register/soc/soc_etm_struct.h +++ b/components/soc/esp32h21/register/soc/soc_etm_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,2072 +11,1002 @@ extern "C" { #endif /** Group: Configuration Register */ -/** Type of etm_ch_ena_ad0 register - * channel enable register +/** Type of ch_ena_ad0 register + * Channel enable status register */ typedef union { struct { - /** etm_ch_ena0 : R/WTC/WTS; bitpos: [0]; default: 0; - * ch0 enable + /** ch_enabled0 : R/WTC/SS; bitpos: [0]; default: 0; + * Represents channel0 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena0:1; - /** etm_ch_ena1 : R/WTC/WTS; bitpos: [1]; default: 0; - * ch1 enable + uint32_t ch_enabled0:1; + /** ch_enabled1 : R/WTC/SS; bitpos: [1]; default: 0; + * Represents channel1 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena1:1; - /** etm_ch_ena2 : R/WTC/WTS; bitpos: [2]; default: 0; - * ch2 enable + uint32_t ch_enabled1:1; + /** ch_enabled2 : R/WTC/SS; bitpos: [2]; default: 0; + * Represents channel2 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena2:1; - /** etm_ch_ena3 : R/WTC/WTS; bitpos: [3]; default: 0; - * ch3 enable + uint32_t ch_enabled2:1; + /** ch_enabled3 : R/WTC/SS; bitpos: [3]; default: 0; + * Represents channel3 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena3:1; - /** etm_ch_ena4 : R/WTC/WTS; bitpos: [4]; default: 0; - * ch4 enable + uint32_t ch_enabled3:1; + /** ch_enabled4 : R/WTC/SS; bitpos: [4]; default: 0; + * Represents channel4 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena4:1; - /** etm_ch_ena5 : R/WTC/WTS; bitpos: [5]; default: 0; - * ch5 enable + uint32_t ch_enabled4:1; + /** ch_enabled5 : R/WTC/SS; bitpos: [5]; default: 0; + * Represents channel5 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena5:1; - /** etm_ch_ena6 : R/WTC/WTS; bitpos: [6]; default: 0; - * ch6 enable + uint32_t ch_enabled5:1; + /** ch_enabled6 : R/WTC/SS; bitpos: [6]; default: 0; + * Represents channel6 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena6:1; - /** etm_ch_ena7 : R/WTC/WTS; bitpos: [7]; default: 0; - * ch7 enable + uint32_t ch_enabled6:1; + /** ch_enabled7 : R/WTC/SS; bitpos: [7]; default: 0; + * Represents channel7 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena7:1; - /** etm_ch_ena8 : R/WTC/WTS; bitpos: [8]; default: 0; - * ch8 enable + uint32_t ch_enabled7:1; + /** ch_enabled8 : R/WTC/SS; bitpos: [8]; default: 0; + * Represents channel8 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena8:1; - /** etm_ch_ena9 : R/WTC/WTS; bitpos: [9]; default: 0; - * ch9 enable + uint32_t ch_enabled8:1; + /** ch_enabled9 : R/WTC/SS; bitpos: [9]; default: 0; + * Represents channel9 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena9:1; - /** etm_ch_ena10 : R/WTC/WTS; bitpos: [10]; default: 0; - * ch10 enable + uint32_t ch_enabled9:1; + /** ch_enabled10 : R/WTC/SS; bitpos: [10]; default: 0; + * Represents channel10 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena10:1; - /** etm_ch_ena11 : R/WTC/WTS; bitpos: [11]; default: 0; - * ch11 enable + uint32_t ch_enabled10:1; + /** ch_enabled11 : R/WTC/SS; bitpos: [11]; default: 0; + * Represents channel11 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena11:1; - /** etm_ch_ena12 : R/WTC/WTS; bitpos: [12]; default: 0; - * ch12 enable + uint32_t ch_enabled11:1; + /** ch_enabled12 : R/WTC/SS; bitpos: [12]; default: 0; + * Represents channel12 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena12:1; - /** etm_ch_ena13 : R/WTC/WTS; bitpos: [13]; default: 0; - * ch13 enable + uint32_t ch_enabled12:1; + /** ch_enabled13 : R/WTC/SS; bitpos: [13]; default: 0; + * Represents channel13 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena13:1; - /** etm_ch_ena14 : R/WTC/WTS; bitpos: [14]; default: 0; - * ch14 enable + uint32_t ch_enabled13:1; + /** ch_enabled14 : R/WTC/SS; bitpos: [14]; default: 0; + * Represents channel14 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena14:1; - /** etm_ch_ena15 : R/WTC/WTS; bitpos: [15]; default: 0; - * ch15 enable + uint32_t ch_enabled14:1; + /** ch_enabled15 : R/WTC/SS; bitpos: [15]; default: 0; + * Represents channel15 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena15:1; - /** etm_ch_ena16 : R/WTC/WTS; bitpos: [16]; default: 0; - * ch16 enable + uint32_t ch_enabled15:1; + /** ch_enabled16 : R/WTC/SS; bitpos: [16]; default: 0; + * Represents channel16 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena16:1; - /** etm_ch_ena17 : R/WTC/WTS; bitpos: [17]; default: 0; - * ch17 enable + uint32_t ch_enabled16:1; + /** ch_enabled17 : R/WTC/SS; bitpos: [17]; default: 0; + * Represents channel17 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena17:1; - /** etm_ch_ena18 : R/WTC/WTS; bitpos: [18]; default: 0; - * ch18 enable + uint32_t ch_enabled17:1; + /** ch_enabled18 : R/WTC/SS; bitpos: [18]; default: 0; + * Represents channel18 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena18:1; - /** etm_ch_ena19 : R/WTC/WTS; bitpos: [19]; default: 0; - * ch19 enable + uint32_t ch_enabled18:1; + /** ch_enabled19 : R/WTC/SS; bitpos: [19]; default: 0; + * Represents channel19 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena19:1; - /** etm_ch_ena20 : R/WTC/WTS; bitpos: [20]; default: 0; - * ch20 enable + uint32_t ch_enabled19:1; + /** ch_enabled20 : R/WTC/SS; bitpos: [20]; default: 0; + * Represents channel20 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena20:1; - /** etm_ch_ena21 : R/WTC/WTS; bitpos: [21]; default: 0; - * ch21 enable + uint32_t ch_enabled20:1; + /** ch_enabled21 : R/WTC/SS; bitpos: [21]; default: 0; + * Represents channel21 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena21:1; - /** etm_ch_ena22 : R/WTC/WTS; bitpos: [22]; default: 0; - * ch22 enable + uint32_t ch_enabled21:1; + /** ch_enabled22 : R/WTC/SS; bitpos: [22]; default: 0; + * Represents channel22 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena22:1; - /** etm_ch_ena23 : R/WTC/WTS; bitpos: [23]; default: 0; - * ch23 enable + uint32_t ch_enabled22:1; + /** ch_enabled23 : R/WTC/SS; bitpos: [23]; default: 0; + * Represents channel23 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena23:1; - /** etm_ch_ena24 : R/WTC/WTS; bitpos: [24]; default: 0; - * ch24 enable + uint32_t ch_enabled23:1; + /** ch_enabled24 : R/WTC/SS; bitpos: [24]; default: 0; + * Represents channel24 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena24:1; - /** etm_ch_ena25 : R/WTC/WTS; bitpos: [25]; default: 0; - * ch25 enable + uint32_t ch_enabled24:1; + /** ch_enabled25 : R/WTC/SS; bitpos: [25]; default: 0; + * Represents channel25 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena25:1; - /** etm_ch_ena26 : R/WTC/WTS; bitpos: [26]; default: 0; - * ch26 enable + uint32_t ch_enabled25:1; + /** ch_enabled26 : R/WTC/SS; bitpos: [26]; default: 0; + * Represents channel26 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena26:1; - /** etm_ch_ena27 : R/WTC/WTS; bitpos: [27]; default: 0; - * ch27 enable + uint32_t ch_enabled26:1; + /** ch_enabled27 : R/WTC/SS; bitpos: [27]; default: 0; + * Represents channel27 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena27:1; - /** etm_ch_ena28 : R/WTC/WTS; bitpos: [28]; default: 0; - * ch28 enable + uint32_t ch_enabled27:1; + /** ch_enabled28 : R/WTC/SS; bitpos: [28]; default: 0; + * Represents channel28 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena28:1; - /** etm_ch_ena29 : R/WTC/WTS; bitpos: [29]; default: 0; - * ch29 enable + uint32_t ch_enabled28:1; + /** ch_enabled29 : R/WTC/SS; bitpos: [29]; default: 0; + * Represents channel29 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena29:1; - /** etm_ch_ena30 : R/WTC/WTS; bitpos: [30]; default: 0; - * ch30 enable + uint32_t ch_enabled29:1; + /** ch_enabled30 : R/WTC/SS; bitpos: [30]; default: 0; + * Represents channel30 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena30:1; - /** etm_ch_ena31 : R/WTC/WTS; bitpos: [31]; default: 0; - * ch31 enable + uint32_t ch_enabled30:1; + /** ch_enabled31 : R/WTC/SS; bitpos: [31]; default: 0; + * Represents channel31 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena31:1; + uint32_t ch_enabled31:1; }; uint32_t val; } soc_etm_ch_ena_ad0_reg_t; -/** Type of etm_ch_ena_ad0_set register - * channel enable set register +/** Type of ch_ena_ad0_set register + * Channel enable register */ typedef union { struct { - /** etm_ch_set0 : WT; bitpos: [0]; default: 0; - * ch0 set + /** ch_enable0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable channel0. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set0:1; - /** etm_ch_set1 : WT; bitpos: [1]; default: 0; - * ch1 set + uint32_t ch_enable0:1; + /** ch_enable1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable channel1. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set1:1; - /** etm_ch_set2 : WT; bitpos: [2]; default: 0; - * ch2 set + uint32_t ch_enable1:1; + /** ch_enable2 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable channel2. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set2:1; - /** etm_ch_set3 : WT; bitpos: [3]; default: 0; - * ch3 set + uint32_t ch_enable2:1; + /** ch_enable3 : WT; bitpos: [3]; default: 0; + * Configures whether or not to enable channel3. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set3:1; - /** etm_ch_set4 : WT; bitpos: [4]; default: 0; - * ch4 set + uint32_t ch_enable3:1; + /** ch_enable4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to enable channel4. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set4:1; - /** etm_ch_set5 : WT; bitpos: [5]; default: 0; - * ch5 set + uint32_t ch_enable4:1; + /** ch_enable5 : WT; bitpos: [5]; default: 0; + * Configures whether or not to enable channel5. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set5:1; - /** etm_ch_set6 : WT; bitpos: [6]; default: 0; - * ch6 set + uint32_t ch_enable5:1; + /** ch_enable6 : WT; bitpos: [6]; default: 0; + * Configures whether or not to enable channel6. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set6:1; - /** etm_ch_set7 : WT; bitpos: [7]; default: 0; - * ch7 set + uint32_t ch_enable6:1; + /** ch_enable7 : WT; bitpos: [7]; default: 0; + * Configures whether or not to enable channel7. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set7:1; - /** etm_ch_set8 : WT; bitpos: [8]; default: 0; - * ch8 set + uint32_t ch_enable7:1; + /** ch_enable8 : WT; bitpos: [8]; default: 0; + * Configures whether or not to enable channel8. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set8:1; - /** etm_ch_set9 : WT; bitpos: [9]; default: 0; - * ch9 set + uint32_t ch_enable8:1; + /** ch_enable9 : WT; bitpos: [9]; default: 0; + * Configures whether or not to enable channel9. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set9:1; - /** etm_ch_set10 : WT; bitpos: [10]; default: 0; - * ch10 set + uint32_t ch_enable9:1; + /** ch_enable10 : WT; bitpos: [10]; default: 0; + * Configures whether or not to enable channel10. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set10:1; - /** etm_ch_set11 : WT; bitpos: [11]; default: 0; - * ch11 set + uint32_t ch_enable10:1; + /** ch_enable11 : WT; bitpos: [11]; default: 0; + * Configures whether or not to enable channel11. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set11:1; - /** etm_ch_set12 : WT; bitpos: [12]; default: 0; - * ch12 set + uint32_t ch_enable11:1; + /** ch_enable12 : WT; bitpos: [12]; default: 0; + * Configures whether or not to enable channel12. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set12:1; - /** etm_ch_set13 : WT; bitpos: [13]; default: 0; - * ch13 set + uint32_t ch_enable12:1; + /** ch_enable13 : WT; bitpos: [13]; default: 0; + * Configures whether or not to enable channel13. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set13:1; - /** etm_ch_set14 : WT; bitpos: [14]; default: 0; - * ch14 set + uint32_t ch_enable13:1; + /** ch_enable14 : WT; bitpos: [14]; default: 0; + * Configures whether or not to enable channel14. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set14:1; - /** etm_ch_set15 : WT; bitpos: [15]; default: 0; - * ch15 set + uint32_t ch_enable14:1; + /** ch_enable15 : WT; bitpos: [15]; default: 0; + * Configures whether or not to enable channel15. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set15:1; - /** etm_ch_set16 : WT; bitpos: [16]; default: 0; - * ch16 set + uint32_t ch_enable15:1; + /** ch_enable16 : WT; bitpos: [16]; default: 0; + * Configures whether or not to enable channel16. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set16:1; - /** etm_ch_set17 : WT; bitpos: [17]; default: 0; - * ch17 set + uint32_t ch_enable16:1; + /** ch_enable17 : WT; bitpos: [17]; default: 0; + * Configures whether or not to enable channel17. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set17:1; - /** etm_ch_set18 : WT; bitpos: [18]; default: 0; - * ch18 set + uint32_t ch_enable17:1; + /** ch_enable18 : WT; bitpos: [18]; default: 0; + * Configures whether or not to enable channel18. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set18:1; - /** etm_ch_set19 : WT; bitpos: [19]; default: 0; - * ch19 set + uint32_t ch_enable18:1; + /** ch_enable19 : WT; bitpos: [19]; default: 0; + * Configures whether or not to enable channel19. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set19:1; - /** etm_ch_set20 : WT; bitpos: [20]; default: 0; - * ch20 set + uint32_t ch_enable19:1; + /** ch_enable20 : WT; bitpos: [20]; default: 0; + * Configures whether or not to enable channel20. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set20:1; - /** etm_ch_set21 : WT; bitpos: [21]; default: 0; - * ch21 set + uint32_t ch_enable20:1; + /** ch_enable21 : WT; bitpos: [21]; default: 0; + * Configures whether or not to enable channel21. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set21:1; - /** etm_ch_set22 : WT; bitpos: [22]; default: 0; - * ch22 set + uint32_t ch_enable21:1; + /** ch_enable22 : WT; bitpos: [22]; default: 0; + * Configures whether or not to enable channel22. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set22:1; - /** etm_ch_set23 : WT; bitpos: [23]; default: 0; - * ch23 set + uint32_t ch_enable22:1; + /** ch_enable23 : WT; bitpos: [23]; default: 0; + * Configures whether or not to enable channel23. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set23:1; - /** etm_ch_set24 : WT; bitpos: [24]; default: 0; - * ch24 set + uint32_t ch_enable23:1; + /** ch_enable24 : WT; bitpos: [24]; default: 0; + * Configures whether or not to enable channel24. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set24:1; - /** etm_ch_set25 : WT; bitpos: [25]; default: 0; - * ch25 set + uint32_t ch_enable24:1; + /** ch_enable25 : WT; bitpos: [25]; default: 0; + * Configures whether or not to enable channel25. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set25:1; - /** etm_ch_set26 : WT; bitpos: [26]; default: 0; - * ch26 set + uint32_t ch_enable25:1; + /** ch_enable26 : WT; bitpos: [26]; default: 0; + * Configures whether or not to enable channel26. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set26:1; - /** etm_ch_set27 : WT; bitpos: [27]; default: 0; - * ch27 set + uint32_t ch_enable26:1; + /** ch_enable27 : WT; bitpos: [27]; default: 0; + * Configures whether or not to enable channel27. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set27:1; - /** etm_ch_set28 : WT; bitpos: [28]; default: 0; - * ch28 set + uint32_t ch_enable27:1; + /** ch_enable28 : WT; bitpos: [28]; default: 0; + * Configures whether or not to enable channel28. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set28:1; - /** etm_ch_set29 : WT; bitpos: [29]; default: 0; - * ch29 set + uint32_t ch_enable28:1; + /** ch_enable29 : WT; bitpos: [29]; default: 0; + * Configures whether or not to enable channel29. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set29:1; - /** etm_ch_set30 : WT; bitpos: [30]; default: 0; - * ch30 set + uint32_t ch_enable29:1; + /** ch_enable30 : WT; bitpos: [30]; default: 0; + * Configures whether or not to enable channel30. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set30:1; - /** etm_ch_set31 : WT; bitpos: [31]; default: 0; - * ch31 set + uint32_t ch_enable30:1; + /** ch_enable31 : WT; bitpos: [31]; default: 0; + * Configures whether or not to enable channel31. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set31:1; + uint32_t ch_enable31:1; }; uint32_t val; } soc_etm_ch_ena_ad0_set_reg_t; -/** Type of etm_ch_ena_ad0_clr register - * channel enable clear register +/** Type of ch_ena_ad0_clr register + * Channel disable register */ typedef union { struct { - /** etm_ch_clr0 : WT; bitpos: [0]; default: 0; - * ch0 clear + /** ch_disable0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to disable channel0. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr0:1; - /** etm_ch_clr1 : WT; bitpos: [1]; default: 0; - * ch1 clear + uint32_t ch_disable0:1; + /** ch_disable1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to disable channel1. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr1:1; - /** etm_ch_clr2 : WT; bitpos: [2]; default: 0; - * ch2 clear + uint32_t ch_disable1:1; + /** ch_disable2 : WT; bitpos: [2]; default: 0; + * Configures whether or not to disable channel2. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr2:1; - /** etm_ch_clr3 : WT; bitpos: [3]; default: 0; - * ch3 clear + uint32_t ch_disable2:1; + /** ch_disable3 : WT; bitpos: [3]; default: 0; + * Configures whether or not to disable channel3. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr3:1; - /** etm_ch_clr4 : WT; bitpos: [4]; default: 0; - * ch4 clear + uint32_t ch_disable3:1; + /** ch_disable4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to disable channel4. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr4:1; - /** etm_ch_clr5 : WT; bitpos: [5]; default: 0; - * ch5 clear + uint32_t ch_disable4:1; + /** ch_disable5 : WT; bitpos: [5]; default: 0; + * Configures whether or not to disable channel5. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr5:1; - /** etm_ch_clr6 : WT; bitpos: [6]; default: 0; - * ch6 clear + uint32_t ch_disable5:1; + /** ch_disable6 : WT; bitpos: [6]; default: 0; + * Configures whether or not to disable channel6. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr6:1; - /** etm_ch_clr7 : WT; bitpos: [7]; default: 0; - * ch7 clear + uint32_t ch_disable6:1; + /** ch_disable7 : WT; bitpos: [7]; default: 0; + * Configures whether or not to disable channel7. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr7:1; - /** etm_ch_clr8 : WT; bitpos: [8]; default: 0; - * ch8 clear + uint32_t ch_disable7:1; + /** ch_disable8 : WT; bitpos: [8]; default: 0; + * Configures whether or not to disable channel8. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr8:1; - /** etm_ch_clr9 : WT; bitpos: [9]; default: 0; - * ch9 clear + uint32_t ch_disable8:1; + /** ch_disable9 : WT; bitpos: [9]; default: 0; + * Configures whether or not to disable channel9. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr9:1; - /** etm_ch_clr10 : WT; bitpos: [10]; default: 0; - * ch10 clear + uint32_t ch_disable9:1; + /** ch_disable10 : WT; bitpos: [10]; default: 0; + * Configures whether or not to disable channel10. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr10:1; - /** etm_ch_clr11 : WT; bitpos: [11]; default: 0; - * ch11 clear + uint32_t ch_disable10:1; + /** ch_disable11 : WT; bitpos: [11]; default: 0; + * Configures whether or not to disable channel11. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr11:1; - /** etm_ch_clr12 : WT; bitpos: [12]; default: 0; - * ch12 clear + uint32_t ch_disable11:1; + /** ch_disable12 : WT; bitpos: [12]; default: 0; + * Configures whether or not to disable channel12. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr12:1; - /** etm_ch_clr13 : WT; bitpos: [13]; default: 0; - * ch13 clear + uint32_t ch_disable12:1; + /** ch_disable13 : WT; bitpos: [13]; default: 0; + * Configures whether or not to disable channel13. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr13:1; - /** etm_ch_clr14 : WT; bitpos: [14]; default: 0; - * ch14 clear + uint32_t ch_disable13:1; + /** ch_disable14 : WT; bitpos: [14]; default: 0; + * Configures whether or not to disable channel14. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr14:1; - /** etm_ch_clr15 : WT; bitpos: [15]; default: 0; - * ch15 clear + uint32_t ch_disable14:1; + /** ch_disable15 : WT; bitpos: [15]; default: 0; + * Configures whether or not to disable channel15. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr15:1; - /** etm_ch_clr16 : WT; bitpos: [16]; default: 0; - * ch16 clear + uint32_t ch_disable15:1; + /** ch_disable16 : WT; bitpos: [16]; default: 0; + * Configures whether or not to disable channel16. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr16:1; - /** etm_ch_clr17 : WT; bitpos: [17]; default: 0; - * ch17 clear + uint32_t ch_disable16:1; + /** ch_disable17 : WT; bitpos: [17]; default: 0; + * Configures whether or not to disable channel17. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr17:1; - /** etm_ch_clr18 : WT; bitpos: [18]; default: 0; - * ch18 clear + uint32_t ch_disable17:1; + /** ch_disable18 : WT; bitpos: [18]; default: 0; + * Configures whether or not to disable channel18. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr18:1; - /** etm_ch_clr19 : WT; bitpos: [19]; default: 0; - * ch19 clear + uint32_t ch_disable18:1; + /** ch_disable19 : WT; bitpos: [19]; default: 0; + * Configures whether or not to disable channel19. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr19:1; - /** etm_ch_clr20 : WT; bitpos: [20]; default: 0; - * ch20 clear + uint32_t ch_disable19:1; + /** ch_disable20 : WT; bitpos: [20]; default: 0; + * Configures whether or not to disable channel20. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr20:1; - /** etm_ch_clr21 : WT; bitpos: [21]; default: 0; - * ch21 clear + uint32_t ch_disable20:1; + /** ch_disable21 : WT; bitpos: [21]; default: 0; + * Configures whether or not to disable channel21. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr21:1; - /** etm_ch_clr22 : WT; bitpos: [22]; default: 0; - * ch22 clear + uint32_t ch_disable21:1; + /** ch_disable22 : WT; bitpos: [22]; default: 0; + * Configures whether or not to disable channel22. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr22:1; - /** etm_ch_clr23 : WT; bitpos: [23]; default: 0; - * ch23 clear + uint32_t ch_disable22:1; + /** ch_disable23 : WT; bitpos: [23]; default: 0; + * Configures whether or not to disable channel23. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr23:1; - /** etm_ch_clr24 : WT; bitpos: [24]; default: 0; - * ch24 clear + uint32_t ch_disable23:1; + /** ch_disable24 : WT; bitpos: [24]; default: 0; + * Configures whether or not to disable channel24. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr24:1; - /** etm_ch_clr25 : WT; bitpos: [25]; default: 0; - * ch25 clear + uint32_t ch_disable24:1; + /** ch_disable25 : WT; bitpos: [25]; default: 0; + * Configures whether or not to disable channel25. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr25:1; - /** etm_ch_clr26 : WT; bitpos: [26]; default: 0; - * ch26 clear + uint32_t ch_disable25:1; + /** ch_disable26 : WT; bitpos: [26]; default: 0; + * Configures whether or not to disable channel26. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr26:1; - /** etm_ch_clr27 : WT; bitpos: [27]; default: 0; - * ch27 clear + uint32_t ch_disable26:1; + /** ch_disable27 : WT; bitpos: [27]; default: 0; + * Configures whether or not to disable channel27. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr27:1; - /** etm_ch_clr28 : WT; bitpos: [28]; default: 0; - * ch28 clear + uint32_t ch_disable27:1; + /** ch_disable28 : WT; bitpos: [28]; default: 0; + * Configures whether or not to disable channel28. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr28:1; - /** etm_ch_clr29 : WT; bitpos: [29]; default: 0; - * ch29 clear + uint32_t ch_disable28:1; + /** ch_disable29 : WT; bitpos: [29]; default: 0; + * Configures whether or not to disable channel29. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr29:1; - /** etm_ch_clr30 : WT; bitpos: [30]; default: 0; - * ch30 clear + uint32_t ch_disable29:1; + /** ch_disable30 : WT; bitpos: [30]; default: 0; + * Configures whether or not to disable channel30. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr30:1; - /** etm_ch_clr31 : WT; bitpos: [31]; default: 0; - * ch31 clear + uint32_t ch_disable30:1; + /** ch_disable31 : WT; bitpos: [31]; default: 0; + * Configures whether or not to disable channel31. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr31:1; + uint32_t ch_disable31:1; }; uint32_t val; } soc_etm_ch_ena_ad0_clr_reg_t; -/** Type of etm_ch_ena_ad1 register - * channel enable register +/** Type of ch_ena_ad1 register + * Channel enable status register */ typedef union { struct { - /** etm_ch_ena32 : R/WTC/WTS; bitpos: [0]; default: 0; - * ch32 enable + /** ch_enabled32 : R/WTC/SS; bitpos: [0]; default: 0; + * Represents channel32 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena32:1; - /** etm_ch_ena33 : R/WTC/WTS; bitpos: [1]; default: 0; - * ch33 enable + uint32_t ch_enabled32:1; + /** ch_enabled33 : R/WTC/SS; bitpos: [1]; default: 0; + * Represents channel33 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena33:1; - /** etm_ch_ena34 : R/WTC/WTS; bitpos: [2]; default: 0; - * ch34 enable + uint32_t ch_enabled33:1; + /** ch_enabled34 : R/WTC/SS; bitpos: [2]; default: 0; + * Represents channel34 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena34:1; - /** etm_ch_ena35 : R/WTC/WTS; bitpos: [3]; default: 0; - * ch35 enable + uint32_t ch_enabled34:1; + /** ch_enabled35 : R/WTC/SS; bitpos: [3]; default: 0; + * Represents channel35 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena35:1; - /** etm_ch_ena36 : R/WTC/WTS; bitpos: [4]; default: 0; - * ch36 enable + uint32_t ch_enabled35:1; + /** ch_enabled36 : R/WTC/SS; bitpos: [4]; default: 0; + * Represents channel36 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena36:1; - /** etm_ch_ena37 : R/WTC/WTS; bitpos: [5]; default: 0; - * ch37 enable + uint32_t ch_enabled36:1; + /** ch_enabled37 : R/WTC/SS; bitpos: [5]; default: 0; + * Represents channel37 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena37:1; - /** etm_ch_ena38 : R/WTC/WTS; bitpos: [6]; default: 0; - * ch38 enable + uint32_t ch_enabled37:1; + /** ch_enabled38 : R/WTC/SS; bitpos: [6]; default: 0; + * Represents channel38 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena38:1; - /** etm_ch_ena39 : R/WTC/WTS; bitpos: [7]; default: 0; - * ch39 enable + uint32_t ch_enabled38:1; + /** ch_enabled39 : R/WTC/SS; bitpos: [7]; default: 0; + * Represents channel39 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena39:1; - /** etm_ch_ena40 : R/WTC/WTS; bitpos: [8]; default: 0; - * ch40 enable + uint32_t ch_enabled39:1; + /** ch_enabled40 : R/WTC/SS; bitpos: [8]; default: 0; + * Represents channel40 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena40:1; - /** etm_ch_ena41 : R/WTC/WTS; bitpos: [9]; default: 0; - * ch41 enable + uint32_t ch_enabled40:1; + /** ch_enabled41 : R/WTC/SS; bitpos: [9]; default: 0; + * Represents channel41 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena41:1; - /** etm_ch_ena42 : R/WTC/WTS; bitpos: [10]; default: 0; - * ch42 enable + uint32_t ch_enabled41:1; + /** ch_enabled42 : R/WTC/SS; bitpos: [10]; default: 0; + * Represents channel42 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena42:1; - /** etm_ch_ena43 : R/WTC/WTS; bitpos: [11]; default: 0; - * ch43 enable + uint32_t ch_enabled42:1; + /** ch_enabled43 : R/WTC/SS; bitpos: [11]; default: 0; + * Represents channel43 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena43:1; - /** etm_ch_ena44 : R/WTC/WTS; bitpos: [12]; default: 0; - * ch44 enable + uint32_t ch_enabled43:1; + /** ch_enabled44 : R/WTC/SS; bitpos: [12]; default: 0; + * Represents channel44 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena44:1; - /** etm_ch_ena45 : R/WTC/WTS; bitpos: [13]; default: 0; - * ch45 enable + uint32_t ch_enabled44:1; + /** ch_enabled45 : R/WTC/SS; bitpos: [13]; default: 0; + * Represents channel45 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena45:1; - /** etm_ch_ena46 : R/WTC/WTS; bitpos: [14]; default: 0; - * ch46 enable + uint32_t ch_enabled45:1; + /** ch_enabled46 : R/WTC/SS; bitpos: [14]; default: 0; + * Represents channel46 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena46:1; - /** etm_ch_ena47 : R/WTC/WTS; bitpos: [15]; default: 0; - * ch47 enable + uint32_t ch_enabled46:1; + /** ch_enabled47 : R/WTC/SS; bitpos: [15]; default: 0; + * Represents channel47 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena47:1; - /** etm_ch_ena48 : R/WTC/WTS; bitpos: [16]; default: 0; - * ch48 enable + uint32_t ch_enabled47:1; + /** ch_enabled48 : R/WTC/SS; bitpos: [16]; default: 0; + * Represents channel48 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena48:1; - /** etm_ch_ena49 : R/WTC/WTS; bitpos: [17]; default: 0; - * ch49 enable + uint32_t ch_enabled48:1; + /** ch_enabled49 : R/WTC/SS; bitpos: [17]; default: 0; + * Represents channel49 enable status. + * 0: Disable + * 1: Enable */ - uint32_t etm_ch_ena49:1; + uint32_t ch_enabled49:1; uint32_t reserved_18:14; }; uint32_t val; } soc_etm_ch_ena_ad1_reg_t; -/** Type of etm_ch_ena_ad1_set register - * channel enable set register +/** Type of ch_ena_ad1_set register + * Channel enable register */ typedef union { struct { - /** etm_ch_set32 : WT; bitpos: [0]; default: 0; - * ch32 set + /** ch_enable32 : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable channel32. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set32:1; - /** etm_ch_set33 : WT; bitpos: [1]; default: 0; - * ch33 set + uint32_t ch_enable32:1; + /** ch_enable33 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable channel33. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set33:1; - /** etm_ch_set34 : WT; bitpos: [2]; default: 0; - * ch34 set + uint32_t ch_enable33:1; + /** ch_enable34 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable channel34. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set34:1; - /** etm_ch_set35 : WT; bitpos: [3]; default: 0; - * ch35 set + uint32_t ch_enable34:1; + /** ch_enable35 : WT; bitpos: [3]; default: 0; + * Configures whether or not to enable channel35. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set35:1; - /** etm_ch_set36 : WT; bitpos: [4]; default: 0; - * ch36 set + uint32_t ch_enable35:1; + /** ch_enable36 : WT; bitpos: [4]; default: 0; + * Configures whether or not to enable channel36. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set36:1; - /** etm_ch_set37 : WT; bitpos: [5]; default: 0; - * ch37 set + uint32_t ch_enable36:1; + /** ch_enable37 : WT; bitpos: [5]; default: 0; + * Configures whether or not to enable channel37. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set37:1; - /** etm_ch_set38 : WT; bitpos: [6]; default: 0; - * ch38 set + uint32_t ch_enable37:1; + /** ch_enable38 : WT; bitpos: [6]; default: 0; + * Configures whether or not to enable channel38. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set38:1; - /** etm_ch_set39 : WT; bitpos: [7]; default: 0; - * ch39 set + uint32_t ch_enable38:1; + /** ch_enable39 : WT; bitpos: [7]; default: 0; + * Configures whether or not to enable channel39. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set39:1; - /** etm_ch_set40 : WT; bitpos: [8]; default: 0; - * ch40 set + uint32_t ch_enable39:1; + /** ch_enable40 : WT; bitpos: [8]; default: 0; + * Configures whether or not to enable channel40. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set40:1; - /** etm_ch_set41 : WT; bitpos: [9]; default: 0; - * ch41 set + uint32_t ch_enable40:1; + /** ch_enable41 : WT; bitpos: [9]; default: 0; + * Configures whether or not to enable channel41. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set41:1; - /** etm_ch_set42 : WT; bitpos: [10]; default: 0; - * ch42 set + uint32_t ch_enable41:1; + /** ch_enable42 : WT; bitpos: [10]; default: 0; + * Configures whether or not to enable channel42. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set42:1; - /** etm_ch_set43 : WT; bitpos: [11]; default: 0; - * ch43 set + uint32_t ch_enable42:1; + /** ch_enable43 : WT; bitpos: [11]; default: 0; + * Configures whether or not to enable channel43. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set43:1; - /** etm_ch_set44 : WT; bitpos: [12]; default: 0; - * ch44 set + uint32_t ch_enable43:1; + /** ch_enable44 : WT; bitpos: [12]; default: 0; + * Configures whether or not to enable channel44. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set44:1; - /** etm_ch_set45 : WT; bitpos: [13]; default: 0; - * ch45 set + uint32_t ch_enable44:1; + /** ch_enable45 : WT; bitpos: [13]; default: 0; + * Configures whether or not to enable channel45. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set45:1; - /** etm_ch_set46 : WT; bitpos: [14]; default: 0; - * ch46 set + uint32_t ch_enable45:1; + /** ch_enable46 : WT; bitpos: [14]; default: 0; + * Configures whether or not to enable channel46. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set46:1; - /** etm_ch_set47 : WT; bitpos: [15]; default: 0; - * ch47 set + uint32_t ch_enable46:1; + /** ch_enable47 : WT; bitpos: [15]; default: 0; + * Configures whether or not to enable channel47. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set47:1; - /** etm_ch_set48 : WT; bitpos: [16]; default: 0; - * ch48 set + uint32_t ch_enable47:1; + /** ch_enable48 : WT; bitpos: [16]; default: 0; + * Configures whether or not to enable channel48. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set48:1; - /** etm_ch_set49 : WT; bitpos: [17]; default: 0; - * ch49 set + uint32_t ch_enable48:1; + /** ch_enable49 : WT; bitpos: [17]; default: 0; + * Configures whether or not to enable channel49. + * 0: Invalid. No effect + * 1: Enable */ - uint32_t etm_ch_set49:1; + uint32_t ch_enable49:1; uint32_t reserved_18:14; }; uint32_t val; } soc_etm_ch_ena_ad1_set_reg_t; -/** Type of etm_ch_ena_ad1_clr register - * channel enable clear register +/** Type of ch_ena_ad1_clr register + * Channel disable register */ typedef union { struct { - /** etm_ch_clr32 : WT; bitpos: [0]; default: 0; - * ch32 clear + /** ch_disable32 : WT; bitpos: [0]; default: 0; + * Configures whether or not to disable channel32. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr32:1; - /** etm_ch_clr33 : WT; bitpos: [1]; default: 0; - * ch33 clear + uint32_t ch_disable32:1; + /** ch_disable33 : WT; bitpos: [1]; default: 0; + * Configures whether or not to disable channel33. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr33:1; - /** etm_ch_clr34 : WT; bitpos: [2]; default: 0; - * ch34 clear + uint32_t ch_disable33:1; + /** ch_disable34 : WT; bitpos: [2]; default: 0; + * Configures whether or not to disable channel34. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr34:1; - /** etm_ch_clr35 : WT; bitpos: [3]; default: 0; - * ch35 clear + uint32_t ch_disable34:1; + /** ch_disable35 : WT; bitpos: [3]; default: 0; + * Configures whether or not to disable channel35. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr35:1; - /** etm_ch_clr36 : WT; bitpos: [4]; default: 0; - * ch36 clear + uint32_t ch_disable35:1; + /** ch_disable36 : WT; bitpos: [4]; default: 0; + * Configures whether or not to disable channel36. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr36:1; - /** etm_ch_clr37 : WT; bitpos: [5]; default: 0; - * ch37 clear + uint32_t ch_disable36:1; + /** ch_disable37 : WT; bitpos: [5]; default: 0; + * Configures whether or not to disable channel37. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr37:1; - /** etm_ch_clr38 : WT; bitpos: [6]; default: 0; - * ch38 clear + uint32_t ch_disable37:1; + /** ch_disable38 : WT; bitpos: [6]; default: 0; + * Configures whether or not to disable channel38. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr38:1; - /** etm_ch_clr39 : WT; bitpos: [7]; default: 0; - * ch39 clear + uint32_t ch_disable38:1; + /** ch_disable39 : WT; bitpos: [7]; default: 0; + * Configures whether or not to disable channel39. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr39:1; - /** etm_ch_clr40 : WT; bitpos: [8]; default: 0; - * ch40 clear + uint32_t ch_disable39:1; + /** ch_disable40 : WT; bitpos: [8]; default: 0; + * Configures whether or not to disable channel40. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr40:1; - /** etm_ch_clr41 : WT; bitpos: [9]; default: 0; - * ch41 clear + uint32_t ch_disable40:1; + /** ch_disable41 : WT; bitpos: [9]; default: 0; + * Configures whether or not to disable channel41. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr41:1; - /** etm_ch_clr42 : WT; bitpos: [10]; default: 0; - * ch42 clear + uint32_t ch_disable41:1; + /** ch_disable42 : WT; bitpos: [10]; default: 0; + * Configures whether or not to disable channel42. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr42:1; - /** etm_ch_clr43 : WT; bitpos: [11]; default: 0; - * ch43 clear + uint32_t ch_disable42:1; + /** ch_disable43 : WT; bitpos: [11]; default: 0; + * Configures whether or not to disable channel43. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr43:1; - /** etm_ch_clr44 : WT; bitpos: [12]; default: 0; - * ch44 clear + uint32_t ch_disable43:1; + /** ch_disable44 : WT; bitpos: [12]; default: 0; + * Configures whether or not to disable channel44. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr44:1; - /** etm_ch_clr45 : WT; bitpos: [13]; default: 0; - * ch45 clear + uint32_t ch_disable44:1; + /** ch_disable45 : WT; bitpos: [13]; default: 0; + * Configures whether or not to disable channel45. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr45:1; - /** etm_ch_clr46 : WT; bitpos: [14]; default: 0; - * ch46 clear + uint32_t ch_disable45:1; + /** ch_disable46 : WT; bitpos: [14]; default: 0; + * Configures whether or not to disable channel46. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr46:1; - /** etm_ch_clr47 : WT; bitpos: [15]; default: 0; - * ch47 clear + uint32_t ch_disable46:1; + /** ch_disable47 : WT; bitpos: [15]; default: 0; + * Configures whether or not to disable channel47. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr47:1; - /** etm_ch_clr48 : WT; bitpos: [16]; default: 0; - * ch48 clear + uint32_t ch_disable47:1; + /** ch_disable48 : WT; bitpos: [16]; default: 0; + * Configures whether or not to disable channel48. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr48:1; - /** etm_ch_clr49 : WT; bitpos: [17]; default: 0; - * ch49 clear + uint32_t ch_disable48:1; + /** ch_disable49 : WT; bitpos: [17]; default: 0; + * Configures whether or not to disable channel49. + * 0: Invalid. No effect + * 1: Clear */ - uint32_t etm_ch_clr49:1; + uint32_t ch_disable49:1; uint32_t reserved_18:14; }; uint32_t val; } soc_etm_ch_ena_ad1_clr_reg_t; -/** Type of etm_ch0_evt_id register - * channel0 event id register +/** Type of chn_evt_id register + * Channeln event ID register */ typedef union { struct { - /** etm_ch0_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch0_evt_id + /** chn_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures the event ID of channeln. */ - uint32_t etm_ch0_evt_id:8; + uint32_t chn_evt_id:8; uint32_t reserved_8:24; }; uint32_t val; -} soc_etm_ch0_evt_id_reg_t; +} soc_etm_chn_evt_id_reg_t; -/** Type of etm_ch0_task_id register - * channel0 task id register +/** Type of chn_task_id register + * Channeln task ID register */ typedef union { struct { - /** etm_ch0_task_id : R/W; bitpos: [7:0]; default: 0; - * ch0_task_id + /** chn_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures the task ID of channeln. */ - uint32_t etm_ch0_task_id:8; + uint32_t chn_task_id:8; uint32_t reserved_8:24; }; uint32_t val; -} soc_etm_ch0_task_id_reg_t; +} soc_etm_chn_task_id_reg_t; -/** Type of etm_ch1_evt_id register - * channel1 event id register +/** Type of clk_en register + * ETM clock enable register */ typedef union { struct { - /** etm_ch1_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch1_evt_id + /** clk_en : R/W; bitpos: [0]; default: 0; + * Configures resister clock gating. + * 0: Support clock only when application writes registers + * 1: Force on clock gating for registers */ - uint32_t etm_ch1_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch1_evt_id_reg_t; - -/** Type of etm_ch1_task_id register - * channel1 task id register - */ -typedef union { - struct { - /** etm_ch1_task_id : R/W; bitpos: [7:0]; default: 0; - * ch1_task_id - */ - uint32_t etm_ch1_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch1_task_id_reg_t; - -/** Type of etm_ch2_evt_id register - * channel2 event id register - */ -typedef union { - struct { - /** etm_ch2_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch2_evt_id - */ - uint32_t etm_ch2_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch2_evt_id_reg_t; - -/** Type of etm_ch2_task_id register - * channel2 task id register - */ -typedef union { - struct { - /** etm_ch2_task_id : R/W; bitpos: [7:0]; default: 0; - * ch2_task_id - */ - uint32_t etm_ch2_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch2_task_id_reg_t; - -/** Type of etm_ch3_evt_id register - * channel3 event id register - */ -typedef union { - struct { - /** etm_ch3_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch3_evt_id - */ - uint32_t etm_ch3_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch3_evt_id_reg_t; - -/** Type of etm_ch3_task_id register - * channel3 task id register - */ -typedef union { - struct { - /** etm_ch3_task_id : R/W; bitpos: [7:0]; default: 0; - * ch3_task_id - */ - uint32_t etm_ch3_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch3_task_id_reg_t; - -/** Type of etm_ch4_evt_id register - * channel4 event id register - */ -typedef union { - struct { - /** etm_ch4_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch4_evt_id - */ - uint32_t etm_ch4_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch4_evt_id_reg_t; - -/** Type of etm_ch4_task_id register - * channel4 task id register - */ -typedef union { - struct { - /** etm_ch4_task_id : R/W; bitpos: [7:0]; default: 0; - * ch4_task_id - */ - uint32_t etm_ch4_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch4_task_id_reg_t; - -/** Type of etm_ch5_evt_id register - * channel5 event id register - */ -typedef union { - struct { - /** etm_ch5_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch5_evt_id - */ - uint32_t etm_ch5_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch5_evt_id_reg_t; - -/** Type of etm_ch5_task_id register - * channel5 task id register - */ -typedef union { - struct { - /** etm_ch5_task_id : R/W; bitpos: [7:0]; default: 0; - * ch5_task_id - */ - uint32_t etm_ch5_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch5_task_id_reg_t; - -/** Type of etm_ch6_evt_id register - * channel6 event id register - */ -typedef union { - struct { - /** etm_ch6_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch6_evt_id - */ - uint32_t etm_ch6_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch6_evt_id_reg_t; - -/** Type of etm_ch6_task_id register - * channel6 task id register - */ -typedef union { - struct { - /** etm_ch6_task_id : R/W; bitpos: [7:0]; default: 0; - * ch6_task_id - */ - uint32_t etm_ch6_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch6_task_id_reg_t; - -/** Type of etm_ch7_evt_id register - * channel7 event id register - */ -typedef union { - struct { - /** etm_ch7_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch7_evt_id - */ - uint32_t etm_ch7_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch7_evt_id_reg_t; - -/** Type of etm_ch7_task_id register - * channel7 task id register - */ -typedef union { - struct { - /** etm_ch7_task_id : R/W; bitpos: [7:0]; default: 0; - * ch7_task_id - */ - uint32_t etm_ch7_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch7_task_id_reg_t; - -/** Type of etm_ch8_evt_id register - * channel8 event id register - */ -typedef union { - struct { - /** etm_ch8_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch8_evt_id - */ - uint32_t etm_ch8_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch8_evt_id_reg_t; - -/** Type of etm_ch8_task_id register - * channel8 task id register - */ -typedef union { - struct { - /** etm_ch8_task_id : R/W; bitpos: [7:0]; default: 0; - * ch8_task_id - */ - uint32_t etm_ch8_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch8_task_id_reg_t; - -/** Type of etm_ch9_evt_id register - * channel9 event id register - */ -typedef union { - struct { - /** etm_ch9_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch9_evt_id - */ - uint32_t etm_ch9_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch9_evt_id_reg_t; - -/** Type of etm_ch9_task_id register - * channel9 task id register - */ -typedef union { - struct { - /** etm_ch9_task_id : R/W; bitpos: [7:0]; default: 0; - * ch9_task_id - */ - uint32_t etm_ch9_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch9_task_id_reg_t; - -/** Type of etm_ch10_evt_id register - * channel10 event id register - */ -typedef union { - struct { - /** etm_ch10_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch10_evt_id - */ - uint32_t etm_ch10_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch10_evt_id_reg_t; - -/** Type of etm_ch10_task_id register - * channel10 task id register - */ -typedef union { - struct { - /** etm_ch10_task_id : R/W; bitpos: [7:0]; default: 0; - * ch10_task_id - */ - uint32_t etm_ch10_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch10_task_id_reg_t; - -/** Type of etm_ch11_evt_id register - * channel11 event id register - */ -typedef union { - struct { - /** etm_ch11_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch11_evt_id - */ - uint32_t etm_ch11_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch11_evt_id_reg_t; - -/** Type of etm_ch11_task_id register - * channel11 task id register - */ -typedef union { - struct { - /** etm_ch11_task_id : R/W; bitpos: [7:0]; default: 0; - * ch11_task_id - */ - uint32_t etm_ch11_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch11_task_id_reg_t; - -/** Type of etm_ch12_evt_id register - * channel12 event id register - */ -typedef union { - struct { - /** etm_ch12_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch12_evt_id - */ - uint32_t etm_ch12_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch12_evt_id_reg_t; - -/** Type of etm_ch12_task_id register - * channel12 task id register - */ -typedef union { - struct { - /** etm_ch12_task_id : R/W; bitpos: [7:0]; default: 0; - * ch12_task_id - */ - uint32_t etm_ch12_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch12_task_id_reg_t; - -/** Type of etm_ch13_evt_id register - * channel13 event id register - */ -typedef union { - struct { - /** etm_ch13_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch13_evt_id - */ - uint32_t etm_ch13_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch13_evt_id_reg_t; - -/** Type of etm_ch13_task_id register - * channel13 task id register - */ -typedef union { - struct { - /** etm_ch13_task_id : R/W; bitpos: [7:0]; default: 0; - * ch13_task_id - */ - uint32_t etm_ch13_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch13_task_id_reg_t; - -/** Type of etm_ch14_evt_id register - * channel14 event id register - */ -typedef union { - struct { - /** etm_ch14_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch14_evt_id - */ - uint32_t etm_ch14_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch14_evt_id_reg_t; - -/** Type of etm_ch14_task_id register - * channel14 task id register - */ -typedef union { - struct { - /** etm_ch14_task_id : R/W; bitpos: [7:0]; default: 0; - * ch14_task_id - */ - uint32_t etm_ch14_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch14_task_id_reg_t; - -/** Type of etm_ch15_evt_id register - * channel15 event id register - */ -typedef union { - struct { - /** etm_ch15_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch15_evt_id - */ - uint32_t etm_ch15_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch15_evt_id_reg_t; - -/** Type of etm_ch15_task_id register - * channel15 task id register - */ -typedef union { - struct { - /** etm_ch15_task_id : R/W; bitpos: [7:0]; default: 0; - * ch15_task_id - */ - uint32_t etm_ch15_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch15_task_id_reg_t; - -/** Type of etm_ch16_evt_id register - * channel16 event id register - */ -typedef union { - struct { - /** etm_ch16_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch16_evt_id - */ - uint32_t etm_ch16_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch16_evt_id_reg_t; - -/** Type of etm_ch16_task_id register - * channel16 task id register - */ -typedef union { - struct { - /** etm_ch16_task_id : R/W; bitpos: [7:0]; default: 0; - * ch16_task_id - */ - uint32_t etm_ch16_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch16_task_id_reg_t; - -/** Type of etm_ch17_evt_id register - * channel17 event id register - */ -typedef union { - struct { - /** etm_ch17_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch17_evt_id - */ - uint32_t etm_ch17_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch17_evt_id_reg_t; - -/** Type of etm_ch17_task_id register - * channel17 task id register - */ -typedef union { - struct { - /** etm_ch17_task_id : R/W; bitpos: [7:0]; default: 0; - * ch17_task_id - */ - uint32_t etm_ch17_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch17_task_id_reg_t; - -/** Type of etm_ch18_evt_id register - * channel18 event id register - */ -typedef union { - struct { - /** etm_ch18_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch18_evt_id - */ - uint32_t etm_ch18_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch18_evt_id_reg_t; - -/** Type of etm_ch18_task_id register - * channel18 task id register - */ -typedef union { - struct { - /** etm_ch18_task_id : R/W; bitpos: [7:0]; default: 0; - * ch18_task_id - */ - uint32_t etm_ch18_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch18_task_id_reg_t; - -/** Type of etm_ch19_evt_id register - * channel19 event id register - */ -typedef union { - struct { - /** etm_ch19_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch19_evt_id - */ - uint32_t etm_ch19_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch19_evt_id_reg_t; - -/** Type of etm_ch19_task_id register - * channel19 task id register - */ -typedef union { - struct { - /** etm_ch19_task_id : R/W; bitpos: [7:0]; default: 0; - * ch19_task_id - */ - uint32_t etm_ch19_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch19_task_id_reg_t; - -/** Type of etm_ch20_evt_id register - * channel20 event id register - */ -typedef union { - struct { - /** etm_ch20_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch20_evt_id - */ - uint32_t etm_ch20_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch20_evt_id_reg_t; - -/** Type of etm_ch20_task_id register - * channel20 task id register - */ -typedef union { - struct { - /** etm_ch20_task_id : R/W; bitpos: [7:0]; default: 0; - * ch20_task_id - */ - uint32_t etm_ch20_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch20_task_id_reg_t; - -/** Type of etm_ch21_evt_id register - * channel21 event id register - */ -typedef union { - struct { - /** etm_ch21_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch21_evt_id - */ - uint32_t etm_ch21_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch21_evt_id_reg_t; - -/** Type of etm_ch21_task_id register - * channel21 task id register - */ -typedef union { - struct { - /** etm_ch21_task_id : R/W; bitpos: [7:0]; default: 0; - * ch21_task_id - */ - uint32_t etm_ch21_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch21_task_id_reg_t; - -/** Type of etm_ch22_evt_id register - * channel22 event id register - */ -typedef union { - struct { - /** etm_ch22_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch22_evt_id - */ - uint32_t etm_ch22_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch22_evt_id_reg_t; - -/** Type of etm_ch22_task_id register - * channel22 task id register - */ -typedef union { - struct { - /** etm_ch22_task_id : R/W; bitpos: [7:0]; default: 0; - * ch22_task_id - */ - uint32_t etm_ch22_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch22_task_id_reg_t; - -/** Type of etm_ch23_evt_id register - * channel23 event id register - */ -typedef union { - struct { - /** etm_ch23_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch23_evt_id - */ - uint32_t etm_ch23_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch23_evt_id_reg_t; - -/** Type of etm_ch23_task_id register - * channel23 task id register - */ -typedef union { - struct { - /** etm_ch23_task_id : R/W; bitpos: [7:0]; default: 0; - * ch23_task_id - */ - uint32_t etm_ch23_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch23_task_id_reg_t; - -/** Type of etm_ch24_evt_id register - * channel24 event id register - */ -typedef union { - struct { - /** etm_ch24_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch24_evt_id - */ - uint32_t etm_ch24_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch24_evt_id_reg_t; - -/** Type of etm_ch24_task_id register - * channel24 task id register - */ -typedef union { - struct { - /** etm_ch24_task_id : R/W; bitpos: [7:0]; default: 0; - * ch24_task_id - */ - uint32_t etm_ch24_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch24_task_id_reg_t; - -/** Type of etm_ch25_evt_id register - * channel25 event id register - */ -typedef union { - struct { - /** etm_ch25_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch25_evt_id - */ - uint32_t etm_ch25_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch25_evt_id_reg_t; - -/** Type of etm_ch25_task_id register - * channel25 task id register - */ -typedef union { - struct { - /** etm_ch25_task_id : R/W; bitpos: [7:0]; default: 0; - * ch25_task_id - */ - uint32_t etm_ch25_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch25_task_id_reg_t; - -/** Type of etm_ch26_evt_id register - * channel26 event id register - */ -typedef union { - struct { - /** etm_ch26_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch26_evt_id - */ - uint32_t etm_ch26_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch26_evt_id_reg_t; - -/** Type of etm_ch26_task_id register - * channel26 task id register - */ -typedef union { - struct { - /** etm_ch26_task_id : R/W; bitpos: [7:0]; default: 0; - * ch26_task_id - */ - uint32_t etm_ch26_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch26_task_id_reg_t; - -/** Type of etm_ch27_evt_id register - * channel27 event id register - */ -typedef union { - struct { - /** etm_ch27_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch27_evt_id - */ - uint32_t etm_ch27_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch27_evt_id_reg_t; - -/** Type of etm_ch27_task_id register - * channel27 task id register - */ -typedef union { - struct { - /** etm_ch27_task_id : R/W; bitpos: [7:0]; default: 0; - * ch27_task_id - */ - uint32_t etm_ch27_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch27_task_id_reg_t; - -/** Type of etm_ch28_evt_id register - * channel28 event id register - */ -typedef union { - struct { - /** etm_ch28_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch28_evt_id - */ - uint32_t etm_ch28_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch28_evt_id_reg_t; - -/** Type of etm_ch28_task_id register - * channel28 task id register - */ -typedef union { - struct { - /** etm_ch28_task_id : R/W; bitpos: [7:0]; default: 0; - * ch28_task_id - */ - uint32_t etm_ch28_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch28_task_id_reg_t; - -/** Type of etm_ch29_evt_id register - * channel29 event id register - */ -typedef union { - struct { - /** etm_ch29_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch29_evt_id - */ - uint32_t etm_ch29_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch29_evt_id_reg_t; - -/** Type of etm_ch29_task_id register - * channel29 task id register - */ -typedef union { - struct { - /** etm_ch29_task_id : R/W; bitpos: [7:0]; default: 0; - * ch29_task_id - */ - uint32_t etm_ch29_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch29_task_id_reg_t; - -/** Type of etm_ch30_evt_id register - * channel30 event id register - */ -typedef union { - struct { - /** etm_ch30_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch30_evt_id - */ - uint32_t etm_ch30_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch30_evt_id_reg_t; - -/** Type of etm_ch30_task_id register - * channel30 task id register - */ -typedef union { - struct { - /** etm_ch30_task_id : R/W; bitpos: [7:0]; default: 0; - * ch30_task_id - */ - uint32_t etm_ch30_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch30_task_id_reg_t; - -/** Type of etm_ch31_evt_id register - * channel31 event id register - */ -typedef union { - struct { - /** etm_ch31_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch31_evt_id - */ - uint32_t etm_ch31_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch31_evt_id_reg_t; - -/** Type of etm_ch31_task_id register - * channel31 task id register - */ -typedef union { - struct { - /** etm_ch31_task_id : R/W; bitpos: [7:0]; default: 0; - * ch31_task_id - */ - uint32_t etm_ch31_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch31_task_id_reg_t; - -/** Type of etm_ch32_evt_id register - * channel32 event id register - */ -typedef union { - struct { - /** etm_ch32_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch32_evt_id - */ - uint32_t etm_ch32_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch32_evt_id_reg_t; - -/** Type of etm_ch32_task_id register - * channel32 task id register - */ -typedef union { - struct { - /** etm_ch32_task_id : R/W; bitpos: [7:0]; default: 0; - * ch32_task_id - */ - uint32_t etm_ch32_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch32_task_id_reg_t; - -/** Type of etm_ch33_evt_id register - * channel33 event id register - */ -typedef union { - struct { - /** etm_ch33_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch33_evt_id - */ - uint32_t etm_ch33_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch33_evt_id_reg_t; - -/** Type of etm_ch33_task_id register - * channel33 task id register - */ -typedef union { - struct { - /** etm_ch33_task_id : R/W; bitpos: [7:0]; default: 0; - * ch33_task_id - */ - uint32_t etm_ch33_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch33_task_id_reg_t; - -/** Type of etm_ch34_evt_id register - * channel34 event id register - */ -typedef union { - struct { - /** etm_ch34_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch34_evt_id - */ - uint32_t etm_ch34_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch34_evt_id_reg_t; - -/** Type of etm_ch34_task_id register - * channel34 task id register - */ -typedef union { - struct { - /** etm_ch34_task_id : R/W; bitpos: [7:0]; default: 0; - * ch34_task_id - */ - uint32_t etm_ch34_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch34_task_id_reg_t; - -/** Type of etm_ch35_evt_id register - * channel35 event id register - */ -typedef union { - struct { - /** etm_ch35_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch35_evt_id - */ - uint32_t etm_ch35_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch35_evt_id_reg_t; - -/** Type of etm_ch35_task_id register - * channel35 task id register - */ -typedef union { - struct { - /** etm_ch35_task_id : R/W; bitpos: [7:0]; default: 0; - * ch35_task_id - */ - uint32_t etm_ch35_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch35_task_id_reg_t; - -/** Type of etm_ch36_evt_id register - * channel36 event id register - */ -typedef union { - struct { - /** etm_ch36_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch36_evt_id - */ - uint32_t etm_ch36_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch36_evt_id_reg_t; - -/** Type of etm_ch36_task_id register - * channel36 task id register - */ -typedef union { - struct { - /** etm_ch36_task_id : R/W; bitpos: [7:0]; default: 0; - * ch36_task_id - */ - uint32_t etm_ch36_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch36_task_id_reg_t; - -/** Type of etm_ch37_evt_id register - * channel37 event id register - */ -typedef union { - struct { - /** etm_ch37_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch37_evt_id - */ - uint32_t etm_ch37_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch37_evt_id_reg_t; - -/** Type of etm_ch37_task_id register - * channel37 task id register - */ -typedef union { - struct { - /** etm_ch37_task_id : R/W; bitpos: [7:0]; default: 0; - * ch37_task_id - */ - uint32_t etm_ch37_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch37_task_id_reg_t; - -/** Type of etm_ch38_evt_id register - * channel38 event id register - */ -typedef union { - struct { - /** etm_ch38_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch38_evt_id - */ - uint32_t etm_ch38_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch38_evt_id_reg_t; - -/** Type of etm_ch38_task_id register - * channel38 task id register - */ -typedef union { - struct { - /** etm_ch38_task_id : R/W; bitpos: [7:0]; default: 0; - * ch38_task_id - */ - uint32_t etm_ch38_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch38_task_id_reg_t; - -/** Type of etm_ch39_evt_id register - * channel39 event id register - */ -typedef union { - struct { - /** etm_ch39_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch39_evt_id - */ - uint32_t etm_ch39_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch39_evt_id_reg_t; - -/** Type of etm_ch39_task_id register - * channel39 task id register - */ -typedef union { - struct { - /** etm_ch39_task_id : R/W; bitpos: [7:0]; default: 0; - * ch39_task_id - */ - uint32_t etm_ch39_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch39_task_id_reg_t; - -/** Type of etm_ch40_evt_id register - * channel40 event id register - */ -typedef union { - struct { - /** etm_ch40_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch40_evt_id - */ - uint32_t etm_ch40_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch40_evt_id_reg_t; - -/** Type of etm_ch40_task_id register - * channel40 task id register - */ -typedef union { - struct { - /** etm_ch40_task_id : R/W; bitpos: [7:0]; default: 0; - * ch40_task_id - */ - uint32_t etm_ch40_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch40_task_id_reg_t; - -/** Type of etm_ch41_evt_id register - * channel41 event id register - */ -typedef union { - struct { - /** etm_ch41_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch41_evt_id - */ - uint32_t etm_ch41_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch41_evt_id_reg_t; - -/** Type of etm_ch41_task_id register - * channel41 task id register - */ -typedef union { - struct { - /** etm_ch41_task_id : R/W; bitpos: [7:0]; default: 0; - * ch41_task_id - */ - uint32_t etm_ch41_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch41_task_id_reg_t; - -/** Type of etm_ch42_evt_id register - * channel42 event id register - */ -typedef union { - struct { - /** etm_ch42_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch42_evt_id - */ - uint32_t etm_ch42_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch42_evt_id_reg_t; - -/** Type of etm_ch42_task_id register - * channel42 task id register - */ -typedef union { - struct { - /** etm_ch42_task_id : R/W; bitpos: [7:0]; default: 0; - * ch42_task_id - */ - uint32_t etm_ch42_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch42_task_id_reg_t; - -/** Type of etm_ch43_evt_id register - * channel43 event id register - */ -typedef union { - struct { - /** etm_ch43_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch43_evt_id - */ - uint32_t etm_ch43_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch43_evt_id_reg_t; - -/** Type of etm_ch43_task_id register - * channel43 task id register - */ -typedef union { - struct { - /** etm_ch43_task_id : R/W; bitpos: [7:0]; default: 0; - * ch43_task_id - */ - uint32_t etm_ch43_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch43_task_id_reg_t; - -/** Type of etm_ch44_evt_id register - * channel44 event id register - */ -typedef union { - struct { - /** etm_ch44_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch44_evt_id - */ - uint32_t etm_ch44_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch44_evt_id_reg_t; - -/** Type of etm_ch44_task_id register - * channel44 task id register - */ -typedef union { - struct { - /** etm_ch44_task_id : R/W; bitpos: [7:0]; default: 0; - * ch44_task_id - */ - uint32_t etm_ch44_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch44_task_id_reg_t; - -/** Type of etm_ch45_evt_id register - * channel45 event id register - */ -typedef union { - struct { - /** etm_ch45_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch45_evt_id - */ - uint32_t etm_ch45_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch45_evt_id_reg_t; - -/** Type of etm_ch45_task_id register - * channel45 task id register - */ -typedef union { - struct { - /** etm_ch45_task_id : R/W; bitpos: [7:0]; default: 0; - * ch45_task_id - */ - uint32_t etm_ch45_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch45_task_id_reg_t; - -/** Type of etm_ch46_evt_id register - * channel46 event id register - */ -typedef union { - struct { - /** etm_ch46_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch46_evt_id - */ - uint32_t etm_ch46_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch46_evt_id_reg_t; - -/** Type of etm_ch46_task_id register - * channel46 task id register - */ -typedef union { - struct { - /** etm_ch46_task_id : R/W; bitpos: [7:0]; default: 0; - * ch46_task_id - */ - uint32_t etm_ch46_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch46_task_id_reg_t; - -/** Type of etm_ch47_evt_id register - * channel47 event id register - */ -typedef union { - struct { - /** etm_ch47_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch47_evt_id - */ - uint32_t etm_ch47_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch47_evt_id_reg_t; - -/** Type of etm_ch47_task_id register - * channel47 task id register - */ -typedef union { - struct { - /** etm_ch47_task_id : R/W; bitpos: [7:0]; default: 0; - * ch47_task_id - */ - uint32_t etm_ch47_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch47_task_id_reg_t; - -/** Type of etm_ch48_evt_id register - * channel48 event id register - */ -typedef union { - struct { - /** etm_ch48_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch48_evt_id - */ - uint32_t etm_ch48_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch48_evt_id_reg_t; - -/** Type of etm_ch48_task_id register - * channel48 task id register - */ -typedef union { - struct { - /** etm_ch48_task_id : R/W; bitpos: [7:0]; default: 0; - * ch48_task_id - */ - uint32_t etm_ch48_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch48_task_id_reg_t; - -/** Type of etm_ch49_evt_id register - * channel49 event id register - */ -typedef union { - struct { - /** etm_ch49_evt_id : R/W; bitpos: [7:0]; default: 0; - * ch49_evt_id - */ - uint32_t etm_ch49_evt_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch49_evt_id_reg_t; - -/** Type of etm_ch49_task_id register - * channel49 task id register - */ -typedef union { - struct { - /** etm_ch49_task_id : R/W; bitpos: [7:0]; default: 0; - * ch49_task_id - */ - uint32_t etm_ch49_task_id:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} soc_etm_ch49_task_id_reg_t; - -/** Type of etm_clk_en register - * etm clock enable register - */ -typedef union { - struct { - /** etm_clk_en : R/W; bitpos: [0]; default: 0; - * clock enable - */ - uint32_t etm_clk_en:1; + uint32_t clk_en:1; uint32_t reserved_1:31; }; uint32_t val; @@ -2084,15 +1014,15 @@ typedef union { /** Group: Version Register */ -/** Type of etm_date register - * etm date register +/** Type of date register + * Version control register */ typedef union { struct { - /** etm_date : R/W; bitpos: [27:0]; default: 35664018; - * date + /** date : R/W; bitpos: [27:0]; default: 35664018; + * Version control register. */ - uint32_t etm_date:28; + uint32_t date:28; uint32_t reserved_28:4; }; uint32_t val; @@ -2100,114 +1030,18 @@ typedef union { typedef struct { - volatile soc_etm_ch_ena_ad0_reg_t etm_ch_ena_ad0; - volatile soc_etm_ch_ena_ad0_set_reg_t etm_ch_ena_ad0_set; - volatile soc_etm_ch_ena_ad0_clr_reg_t etm_ch_ena_ad0_clr; - volatile soc_etm_ch_ena_ad1_reg_t etm_ch_ena_ad1; - volatile soc_etm_ch_ena_ad1_set_reg_t etm_ch_ena_ad1_set; - volatile soc_etm_ch_ena_ad1_clr_reg_t etm_ch_ena_ad1_clr; - volatile soc_etm_ch0_evt_id_reg_t etm_ch0_evt_id; - volatile soc_etm_ch0_task_id_reg_t etm_ch0_task_id; - volatile soc_etm_ch1_evt_id_reg_t etm_ch1_evt_id; - volatile soc_etm_ch1_task_id_reg_t etm_ch1_task_id; - volatile soc_etm_ch2_evt_id_reg_t etm_ch2_evt_id; - volatile soc_etm_ch2_task_id_reg_t etm_ch2_task_id; - volatile soc_etm_ch3_evt_id_reg_t etm_ch3_evt_id; - volatile soc_etm_ch3_task_id_reg_t etm_ch3_task_id; - volatile soc_etm_ch4_evt_id_reg_t etm_ch4_evt_id; - volatile soc_etm_ch4_task_id_reg_t etm_ch4_task_id; - volatile soc_etm_ch5_evt_id_reg_t etm_ch5_evt_id; - volatile soc_etm_ch5_task_id_reg_t etm_ch5_task_id; - volatile soc_etm_ch6_evt_id_reg_t etm_ch6_evt_id; - volatile soc_etm_ch6_task_id_reg_t etm_ch6_task_id; - volatile soc_etm_ch7_evt_id_reg_t etm_ch7_evt_id; - volatile soc_etm_ch7_task_id_reg_t etm_ch7_task_id; - volatile soc_etm_ch8_evt_id_reg_t etm_ch8_evt_id; - volatile soc_etm_ch8_task_id_reg_t etm_ch8_task_id; - volatile soc_etm_ch9_evt_id_reg_t etm_ch9_evt_id; - volatile soc_etm_ch9_task_id_reg_t etm_ch9_task_id; - volatile soc_etm_ch10_evt_id_reg_t etm_ch10_evt_id; - volatile soc_etm_ch10_task_id_reg_t etm_ch10_task_id; - volatile soc_etm_ch11_evt_id_reg_t etm_ch11_evt_id; - volatile soc_etm_ch11_task_id_reg_t etm_ch11_task_id; - volatile soc_etm_ch12_evt_id_reg_t etm_ch12_evt_id; - volatile soc_etm_ch12_task_id_reg_t etm_ch12_task_id; - volatile soc_etm_ch13_evt_id_reg_t etm_ch13_evt_id; - volatile soc_etm_ch13_task_id_reg_t etm_ch13_task_id; - volatile soc_etm_ch14_evt_id_reg_t etm_ch14_evt_id; - volatile soc_etm_ch14_task_id_reg_t etm_ch14_task_id; - volatile soc_etm_ch15_evt_id_reg_t etm_ch15_evt_id; - volatile soc_etm_ch15_task_id_reg_t etm_ch15_task_id; - volatile soc_etm_ch16_evt_id_reg_t etm_ch16_evt_id; - volatile soc_etm_ch16_task_id_reg_t etm_ch16_task_id; - volatile soc_etm_ch17_evt_id_reg_t etm_ch17_evt_id; - volatile soc_etm_ch17_task_id_reg_t etm_ch17_task_id; - volatile soc_etm_ch18_evt_id_reg_t etm_ch18_evt_id; - volatile soc_etm_ch18_task_id_reg_t etm_ch18_task_id; - volatile soc_etm_ch19_evt_id_reg_t etm_ch19_evt_id; - volatile soc_etm_ch19_task_id_reg_t etm_ch19_task_id; - volatile soc_etm_ch20_evt_id_reg_t etm_ch20_evt_id; - volatile soc_etm_ch20_task_id_reg_t etm_ch20_task_id; - volatile soc_etm_ch21_evt_id_reg_t etm_ch21_evt_id; - volatile soc_etm_ch21_task_id_reg_t etm_ch21_task_id; - volatile soc_etm_ch22_evt_id_reg_t etm_ch22_evt_id; - volatile soc_etm_ch22_task_id_reg_t etm_ch22_task_id; - volatile soc_etm_ch23_evt_id_reg_t etm_ch23_evt_id; - volatile soc_etm_ch23_task_id_reg_t etm_ch23_task_id; - volatile soc_etm_ch24_evt_id_reg_t etm_ch24_evt_id; - volatile soc_etm_ch24_task_id_reg_t etm_ch24_task_id; - volatile soc_etm_ch25_evt_id_reg_t etm_ch25_evt_id; - volatile soc_etm_ch25_task_id_reg_t etm_ch25_task_id; - volatile soc_etm_ch26_evt_id_reg_t etm_ch26_evt_id; - volatile soc_etm_ch26_task_id_reg_t etm_ch26_task_id; - volatile soc_etm_ch27_evt_id_reg_t etm_ch27_evt_id; - volatile soc_etm_ch27_task_id_reg_t etm_ch27_task_id; - volatile soc_etm_ch28_evt_id_reg_t etm_ch28_evt_id; - volatile soc_etm_ch28_task_id_reg_t etm_ch28_task_id; - volatile soc_etm_ch29_evt_id_reg_t etm_ch29_evt_id; - volatile soc_etm_ch29_task_id_reg_t etm_ch29_task_id; - volatile soc_etm_ch30_evt_id_reg_t etm_ch30_evt_id; - volatile soc_etm_ch30_task_id_reg_t etm_ch30_task_id; - volatile soc_etm_ch31_evt_id_reg_t etm_ch31_evt_id; - volatile soc_etm_ch31_task_id_reg_t etm_ch31_task_id; - volatile soc_etm_ch32_evt_id_reg_t etm_ch32_evt_id; - volatile soc_etm_ch32_task_id_reg_t etm_ch32_task_id; - volatile soc_etm_ch33_evt_id_reg_t etm_ch33_evt_id; - volatile soc_etm_ch33_task_id_reg_t etm_ch33_task_id; - volatile soc_etm_ch34_evt_id_reg_t etm_ch34_evt_id; - volatile soc_etm_ch34_task_id_reg_t etm_ch34_task_id; - volatile soc_etm_ch35_evt_id_reg_t etm_ch35_evt_id; - volatile soc_etm_ch35_task_id_reg_t etm_ch35_task_id; - volatile soc_etm_ch36_evt_id_reg_t etm_ch36_evt_id; - volatile soc_etm_ch36_task_id_reg_t etm_ch36_task_id; - volatile soc_etm_ch37_evt_id_reg_t etm_ch37_evt_id; - volatile soc_etm_ch37_task_id_reg_t etm_ch37_task_id; - volatile soc_etm_ch38_evt_id_reg_t etm_ch38_evt_id; - volatile soc_etm_ch38_task_id_reg_t etm_ch38_task_id; - volatile soc_etm_ch39_evt_id_reg_t etm_ch39_evt_id; - volatile soc_etm_ch39_task_id_reg_t etm_ch39_task_id; - volatile soc_etm_ch40_evt_id_reg_t etm_ch40_evt_id; - volatile soc_etm_ch40_task_id_reg_t etm_ch40_task_id; - volatile soc_etm_ch41_evt_id_reg_t etm_ch41_evt_id; - volatile soc_etm_ch41_task_id_reg_t etm_ch41_task_id; - volatile soc_etm_ch42_evt_id_reg_t etm_ch42_evt_id; - volatile soc_etm_ch42_task_id_reg_t etm_ch42_task_id; - volatile soc_etm_ch43_evt_id_reg_t etm_ch43_evt_id; - volatile soc_etm_ch43_task_id_reg_t etm_ch43_task_id; - volatile soc_etm_ch44_evt_id_reg_t etm_ch44_evt_id; - volatile soc_etm_ch44_task_id_reg_t etm_ch44_task_id; - volatile soc_etm_ch45_evt_id_reg_t etm_ch45_evt_id; - volatile soc_etm_ch45_task_id_reg_t etm_ch45_task_id; - volatile soc_etm_ch46_evt_id_reg_t etm_ch46_evt_id; - volatile soc_etm_ch46_task_id_reg_t etm_ch46_task_id; - volatile soc_etm_ch47_evt_id_reg_t etm_ch47_evt_id; - volatile soc_etm_ch47_task_id_reg_t etm_ch47_task_id; - volatile soc_etm_ch48_evt_id_reg_t etm_ch48_evt_id; - volatile soc_etm_ch48_task_id_reg_t etm_ch48_task_id; - volatile soc_etm_ch49_evt_id_reg_t etm_ch49_evt_id; - volatile soc_etm_ch49_task_id_reg_t etm_ch49_task_id; - volatile soc_etm_clk_en_reg_t etm_clk_en; - volatile soc_etm_date_reg_t etm_date; + volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0; + volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set; + volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr; + volatile soc_etm_ch_ena_ad1_reg_t ch_ena_ad1; + volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set; + volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr; + volatile struct { + soc_etm_chn_evt_id_reg_t eid; + soc_etm_chn_task_id_reg_t tid; + } channel[50]; + volatile soc_etm_clk_en_reg_t clk_en; + volatile soc_etm_date_reg_t date; } soc_etm_dev_t; extern soc_etm_dev_t SOC_ETM; From 78a2e2cb2f561c2896242ba40086949102649734 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Fri, 23 May 2025 14:28:28 +0800 Subject: [PATCH 2/3] change(apm): update apm soc headers of c5 --- .../soc/esp32c5/register/soc/cpu_apm_reg.h | 320 ++-- .../soc/esp32c5/register/soc/cpu_apm_struct.h | 140 +- .../soc/esp32c5/register/soc/hp_apm_reg.h | 650 ++++--- .../soc/esp32c5/register/soc/hp_apm_struct.h | 254 ++- .../soc/esp32c5/register/soc/lp_apm0_reg.h | 288 +-- .../soc/esp32c5/register/soc/lp_apm0_struct.h | 100 +- .../soc/esp32c5/register/soc/lp_apm_reg.h | 314 ++-- .../soc/esp32c5/register/soc/lp_apm_struct.h | 134 +- .../soc/esp32c5/register/soc/lp_tee_reg.h | 143 +- .../soc/esp32c5/register/soc/lp_tee_struct.h | 138 +- components/soc/esp32c5/register/soc/tee_reg.h | 1619 +++++------------ .../soc/esp32c5/register/soc/tee_struct.h | 820 ++------- 12 files changed, 1791 insertions(+), 3129 deletions(-) diff --git a/components/soc/esp32c5/register/soc/cpu_apm_reg.h b/components/soc/esp32c5/register/soc/cpu_apm_reg.h index 9c6a7cbe52..daf755e202 100644 --- a/components/soc/esp32c5/register/soc/cpu_apm_reg.h +++ b/components/soc/esp32c5/register/soc/cpu_apm_reg.h @@ -12,13 +12,13 @@ extern "C" { #endif /** CPU_APM_REGION_FILTER_EN_REG register - * Region filter enable register + * Region enable register */ #define CPU_APM_REGION_FILTER_EN_REG (DR_REG_CPU_APM_BASE + 0x0) /** CPU_APM_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1; - * Configure bit $n (0-7) to enable region $n. - * 0: disable - * 1: enable + * Configures bit $n (0-7) to enable region $n (0-7). + * 0: Disable + * 1: Enable */ #define CPU_APM_REGION_FILTER_EN 0x000000FFU #define CPU_APM_REGION_FILTER_EN_M (CPU_APM_REGION_FILTER_EN_V << CPU_APM_REGION_FILTER_EN_S) @@ -37,7 +37,7 @@ extern "C" { #define CPU_APM_REGION0_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION0_ADDR_START_L_S 0 /** CPU_APM_REGION0_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 0. + * Configures the start address of region 0. */ #define CPU_APM_REGION0_ADDR_START 0x0000007FU #define CPU_APM_REGION0_ADDR_START_M (CPU_APM_REGION0_ADDR_START_V << CPU_APM_REGION0_ADDR_START_S) @@ -63,7 +63,7 @@ extern "C" { #define CPU_APM_REGION0_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION0_ADDR_END_L_S 0 /** CPU_APM_REGION0_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 0. + * Configures the end address of region 0. */ #define CPU_APM_REGION0_ADDR_END 0x0000007FU #define CPU_APM_REGION0_ADDR_END_M (CPU_APM_REGION0_ADDR_END_V << CPU_APM_REGION0_ADDR_END_S) @@ -78,74 +78,78 @@ extern "C" { #define CPU_APM_REGION0_ADDR_END_H_S 19 /** CPU_APM_REGION0_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION0_ATTR_REG (DR_REG_CPU_APM_BASE + 0xc) /** CPU_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 0. + * Configures the execution permission in region 0 in REE0 mode. */ #define CPU_APM_REGION0_R0_X (BIT(0)) #define CPU_APM_REGION0_R0_X_M (CPU_APM_REGION0_R0_X_V << CPU_APM_REGION0_R0_X_S) #define CPU_APM_REGION0_R0_X_V 0x00000001U #define CPU_APM_REGION0_R0_X_S 0 /** CPU_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 0. + * Configures the write permission in region 0 in REE0 mode. */ #define CPU_APM_REGION0_R0_W (BIT(1)) #define CPU_APM_REGION0_R0_W_M (CPU_APM_REGION0_R0_W_V << CPU_APM_REGION0_R0_W_S) #define CPU_APM_REGION0_R0_W_V 0x00000001U #define CPU_APM_REGION0_R0_W_S 1 /** CPU_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 0. + * Configures the read permission in region 0 in REE0 mode. */ #define CPU_APM_REGION0_R0_R (BIT(2)) #define CPU_APM_REGION0_R0_R_M (CPU_APM_REGION0_R0_R_V << CPU_APM_REGION0_R0_R_S) #define CPU_APM_REGION0_R0_R_V 0x00000001U #define CPU_APM_REGION0_R0_R_S 2 /** CPU_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 0. + * Configures the execution permission in region 0 in REE1 mode. */ #define CPU_APM_REGION0_R1_X (BIT(4)) #define CPU_APM_REGION0_R1_X_M (CPU_APM_REGION0_R1_X_V << CPU_APM_REGION0_R1_X_S) #define CPU_APM_REGION0_R1_X_V 0x00000001U #define CPU_APM_REGION0_R1_X_S 4 /** CPU_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 0. + * Configures the write permission in region 0 in REE1 mode. */ #define CPU_APM_REGION0_R1_W (BIT(5)) #define CPU_APM_REGION0_R1_W_M (CPU_APM_REGION0_R1_W_V << CPU_APM_REGION0_R1_W_S) #define CPU_APM_REGION0_R1_W_V 0x00000001U #define CPU_APM_REGION0_R1_W_S 5 /** CPU_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 0. + * Configures the read permission in region 0 in REE1 mode. */ #define CPU_APM_REGION0_R1_R (BIT(6)) #define CPU_APM_REGION0_R1_R_M (CPU_APM_REGION0_R1_R_V << CPU_APM_REGION0_R1_R_S) #define CPU_APM_REGION0_R1_R_V 0x00000001U #define CPU_APM_REGION0_R1_R_S 6 /** CPU_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 0. + * Configures the execution permission in region 0 in REE2 mode. */ #define CPU_APM_REGION0_R2_X (BIT(8)) #define CPU_APM_REGION0_R2_X_M (CPU_APM_REGION0_R2_X_V << CPU_APM_REGION0_R2_X_S) #define CPU_APM_REGION0_R2_X_V 0x00000001U #define CPU_APM_REGION0_R2_X_S 8 /** CPU_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 0. + * Configures the write permission in region 0 in REE2 mode. */ #define CPU_APM_REGION0_R2_W (BIT(9)) #define CPU_APM_REGION0_R2_W_M (CPU_APM_REGION0_R2_W_V << CPU_APM_REGION0_R2_W_S) #define CPU_APM_REGION0_R2_W_V 0x00000001U #define CPU_APM_REGION0_R2_W_S 9 /** CPU_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 0. + * Configures the read permission in region 0 in REE2 mode. */ #define CPU_APM_REGION0_R2_R (BIT(10)) #define CPU_APM_REGION0_R2_R_M (CPU_APM_REGION0_R2_R_V << CPU_APM_REGION0_R2_R_S) #define CPU_APM_REGION0_R2_R_V 0x00000001U #define CPU_APM_REGION0_R2_R_S 10 /** CPU_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 0's configuration registers + * (CPU_APM_REGION0_ADDR_START_REG, CPU_APM_REGION0_ADDR_END_REG, and + * CPU_APM_REGION0_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION0_LOCK (BIT(11)) #define CPU_APM_REGION0_LOCK_M (CPU_APM_REGION0_LOCK_V << CPU_APM_REGION0_LOCK_S) @@ -164,7 +168,7 @@ extern "C" { #define CPU_APM_REGION1_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION1_ADDR_START_L_S 0 /** CPU_APM_REGION1_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 1. + * Configures the start address of region 1. */ #define CPU_APM_REGION1_ADDR_START 0x0000007FU #define CPU_APM_REGION1_ADDR_START_M (CPU_APM_REGION1_ADDR_START_V << CPU_APM_REGION1_ADDR_START_S) @@ -190,7 +194,7 @@ extern "C" { #define CPU_APM_REGION1_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION1_ADDR_END_L_S 0 /** CPU_APM_REGION1_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 1. + * Configures the end address of region 1. */ #define CPU_APM_REGION1_ADDR_END 0x0000007FU #define CPU_APM_REGION1_ADDR_END_M (CPU_APM_REGION1_ADDR_END_V << CPU_APM_REGION1_ADDR_END_S) @@ -205,74 +209,78 @@ extern "C" { #define CPU_APM_REGION1_ADDR_END_H_S 19 /** CPU_APM_REGION1_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION1_ATTR_REG (DR_REG_CPU_APM_BASE + 0x18) /** CPU_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 1. + * Configures the execution permission in region 1 in REE0 mode. */ #define CPU_APM_REGION1_R0_X (BIT(0)) #define CPU_APM_REGION1_R0_X_M (CPU_APM_REGION1_R0_X_V << CPU_APM_REGION1_R0_X_S) #define CPU_APM_REGION1_R0_X_V 0x00000001U #define CPU_APM_REGION1_R0_X_S 0 /** CPU_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 1. + * Configures the write permission in region 1 in REE0 mode. */ #define CPU_APM_REGION1_R0_W (BIT(1)) #define CPU_APM_REGION1_R0_W_M (CPU_APM_REGION1_R0_W_V << CPU_APM_REGION1_R0_W_S) #define CPU_APM_REGION1_R0_W_V 0x00000001U #define CPU_APM_REGION1_R0_W_S 1 /** CPU_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 1. + * Configures the read permission in region 1 in REE0 mode. */ #define CPU_APM_REGION1_R0_R (BIT(2)) #define CPU_APM_REGION1_R0_R_M (CPU_APM_REGION1_R0_R_V << CPU_APM_REGION1_R0_R_S) #define CPU_APM_REGION1_R0_R_V 0x00000001U #define CPU_APM_REGION1_R0_R_S 2 /** CPU_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 1. + * Configures the execution permission in region 1 in REE1 mode. */ #define CPU_APM_REGION1_R1_X (BIT(4)) #define CPU_APM_REGION1_R1_X_M (CPU_APM_REGION1_R1_X_V << CPU_APM_REGION1_R1_X_S) #define CPU_APM_REGION1_R1_X_V 0x00000001U #define CPU_APM_REGION1_R1_X_S 4 /** CPU_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 1. + * Configures the write permission in region 1 in REE1 mode. */ #define CPU_APM_REGION1_R1_W (BIT(5)) #define CPU_APM_REGION1_R1_W_M (CPU_APM_REGION1_R1_W_V << CPU_APM_REGION1_R1_W_S) #define CPU_APM_REGION1_R1_W_V 0x00000001U #define CPU_APM_REGION1_R1_W_S 5 /** CPU_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 1. + * Configures the read permission in region 1 in REE1 mode. */ #define CPU_APM_REGION1_R1_R (BIT(6)) #define CPU_APM_REGION1_R1_R_M (CPU_APM_REGION1_R1_R_V << CPU_APM_REGION1_R1_R_S) #define CPU_APM_REGION1_R1_R_V 0x00000001U #define CPU_APM_REGION1_R1_R_S 6 /** CPU_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 1. + * Configures the execution permission in region 1 in REE2 mode. */ #define CPU_APM_REGION1_R2_X (BIT(8)) #define CPU_APM_REGION1_R2_X_M (CPU_APM_REGION1_R2_X_V << CPU_APM_REGION1_R2_X_S) #define CPU_APM_REGION1_R2_X_V 0x00000001U #define CPU_APM_REGION1_R2_X_S 8 /** CPU_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 1. + * Configures the write permission in region 1 in REE2 mode. */ #define CPU_APM_REGION1_R2_W (BIT(9)) #define CPU_APM_REGION1_R2_W_M (CPU_APM_REGION1_R2_W_V << CPU_APM_REGION1_R2_W_S) #define CPU_APM_REGION1_R2_W_V 0x00000001U #define CPU_APM_REGION1_R2_W_S 9 /** CPU_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 1. + * Configures the read permission in region 1 in REE2 mode. */ #define CPU_APM_REGION1_R2_R (BIT(10)) #define CPU_APM_REGION1_R2_R_M (CPU_APM_REGION1_R2_R_V << CPU_APM_REGION1_R2_R_S) #define CPU_APM_REGION1_R2_R_V 0x00000001U #define CPU_APM_REGION1_R2_R_S 10 /** CPU_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 1's configuration registers + * (CPU_APM_REGION1_ADDR_START_REG, CPU_APM_REGION1_ADDR_END_REG, and + * CPU_APM_REGION1_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION1_LOCK (BIT(11)) #define CPU_APM_REGION1_LOCK_M (CPU_APM_REGION1_LOCK_V << CPU_APM_REGION1_LOCK_S) @@ -291,7 +299,7 @@ extern "C" { #define CPU_APM_REGION2_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION2_ADDR_START_L_S 0 /** CPU_APM_REGION2_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 2. + * Configures the start address of region 2. */ #define CPU_APM_REGION2_ADDR_START 0x0000007FU #define CPU_APM_REGION2_ADDR_START_M (CPU_APM_REGION2_ADDR_START_V << CPU_APM_REGION2_ADDR_START_S) @@ -317,7 +325,7 @@ extern "C" { #define CPU_APM_REGION2_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION2_ADDR_END_L_S 0 /** CPU_APM_REGION2_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 2. + * Configures the end address of region 2. */ #define CPU_APM_REGION2_ADDR_END 0x0000007FU #define CPU_APM_REGION2_ADDR_END_M (CPU_APM_REGION2_ADDR_END_V << CPU_APM_REGION2_ADDR_END_S) @@ -332,74 +340,78 @@ extern "C" { #define CPU_APM_REGION2_ADDR_END_H_S 19 /** CPU_APM_REGION2_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION2_ATTR_REG (DR_REG_CPU_APM_BASE + 0x24) /** CPU_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 2. + * Configures the execution permission in region 2 in REE0 mode. */ #define CPU_APM_REGION2_R0_X (BIT(0)) #define CPU_APM_REGION2_R0_X_M (CPU_APM_REGION2_R0_X_V << CPU_APM_REGION2_R0_X_S) #define CPU_APM_REGION2_R0_X_V 0x00000001U #define CPU_APM_REGION2_R0_X_S 0 /** CPU_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 2. + * Configures the write permission in region 2 in REE0 mode. */ #define CPU_APM_REGION2_R0_W (BIT(1)) #define CPU_APM_REGION2_R0_W_M (CPU_APM_REGION2_R0_W_V << CPU_APM_REGION2_R0_W_S) #define CPU_APM_REGION2_R0_W_V 0x00000001U #define CPU_APM_REGION2_R0_W_S 1 /** CPU_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 2. + * Configures the read permission in region 2 in REE0 mode. */ #define CPU_APM_REGION2_R0_R (BIT(2)) #define CPU_APM_REGION2_R0_R_M (CPU_APM_REGION2_R0_R_V << CPU_APM_REGION2_R0_R_S) #define CPU_APM_REGION2_R0_R_V 0x00000001U #define CPU_APM_REGION2_R0_R_S 2 /** CPU_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 2. + * Configures the execution permission in region 2 in REE1 mode. */ #define CPU_APM_REGION2_R1_X (BIT(4)) #define CPU_APM_REGION2_R1_X_M (CPU_APM_REGION2_R1_X_V << CPU_APM_REGION2_R1_X_S) #define CPU_APM_REGION2_R1_X_V 0x00000001U #define CPU_APM_REGION2_R1_X_S 4 /** CPU_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 2. + * Configures the write permission in region 2 in REE1 mode. */ #define CPU_APM_REGION2_R1_W (BIT(5)) #define CPU_APM_REGION2_R1_W_M (CPU_APM_REGION2_R1_W_V << CPU_APM_REGION2_R1_W_S) #define CPU_APM_REGION2_R1_W_V 0x00000001U #define CPU_APM_REGION2_R1_W_S 5 /** CPU_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 2. + * Configures the read permission in region 2 in REE1 mode. */ #define CPU_APM_REGION2_R1_R (BIT(6)) #define CPU_APM_REGION2_R1_R_M (CPU_APM_REGION2_R1_R_V << CPU_APM_REGION2_R1_R_S) #define CPU_APM_REGION2_R1_R_V 0x00000001U #define CPU_APM_REGION2_R1_R_S 6 /** CPU_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 2. + * Configures the execution permission in region 2 in REE2 mode. */ #define CPU_APM_REGION2_R2_X (BIT(8)) #define CPU_APM_REGION2_R2_X_M (CPU_APM_REGION2_R2_X_V << CPU_APM_REGION2_R2_X_S) #define CPU_APM_REGION2_R2_X_V 0x00000001U #define CPU_APM_REGION2_R2_X_S 8 /** CPU_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 2. + * Configures the write permission in region 2 in REE2 mode. */ #define CPU_APM_REGION2_R2_W (BIT(9)) #define CPU_APM_REGION2_R2_W_M (CPU_APM_REGION2_R2_W_V << CPU_APM_REGION2_R2_W_S) #define CPU_APM_REGION2_R2_W_V 0x00000001U #define CPU_APM_REGION2_R2_W_S 9 /** CPU_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 2. + * Configures the read permission in region 2 in REE2 mode. */ #define CPU_APM_REGION2_R2_R (BIT(10)) #define CPU_APM_REGION2_R2_R_M (CPU_APM_REGION2_R2_R_V << CPU_APM_REGION2_R2_R_S) #define CPU_APM_REGION2_R2_R_V 0x00000001U #define CPU_APM_REGION2_R2_R_S 10 /** CPU_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 2's configuration registers + * (CPU_APM_REGION2_ADDR_START_REG, CPU_APM_REGION2_ADDR_END_REG, and + * CPU_APM_REGION2_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION2_LOCK (BIT(11)) #define CPU_APM_REGION2_LOCK_M (CPU_APM_REGION2_LOCK_V << CPU_APM_REGION2_LOCK_S) @@ -418,7 +430,7 @@ extern "C" { #define CPU_APM_REGION3_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION3_ADDR_START_L_S 0 /** CPU_APM_REGION3_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 3. + * Configures the start address of region 3. */ #define CPU_APM_REGION3_ADDR_START 0x0000007FU #define CPU_APM_REGION3_ADDR_START_M (CPU_APM_REGION3_ADDR_START_V << CPU_APM_REGION3_ADDR_START_S) @@ -444,7 +456,7 @@ extern "C" { #define CPU_APM_REGION3_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION3_ADDR_END_L_S 0 /** CPU_APM_REGION3_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 3. + * Configures the end address of region 3. */ #define CPU_APM_REGION3_ADDR_END 0x0000007FU #define CPU_APM_REGION3_ADDR_END_M (CPU_APM_REGION3_ADDR_END_V << CPU_APM_REGION3_ADDR_END_S) @@ -459,74 +471,78 @@ extern "C" { #define CPU_APM_REGION3_ADDR_END_H_S 19 /** CPU_APM_REGION3_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION3_ATTR_REG (DR_REG_CPU_APM_BASE + 0x30) /** CPU_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 3. + * Configures the execution permission in region 3 in REE0 mode. */ #define CPU_APM_REGION3_R0_X (BIT(0)) #define CPU_APM_REGION3_R0_X_M (CPU_APM_REGION3_R0_X_V << CPU_APM_REGION3_R0_X_S) #define CPU_APM_REGION3_R0_X_V 0x00000001U #define CPU_APM_REGION3_R0_X_S 0 /** CPU_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 3. + * Configures the write permission in region 3 in REE0 mode. */ #define CPU_APM_REGION3_R0_W (BIT(1)) #define CPU_APM_REGION3_R0_W_M (CPU_APM_REGION3_R0_W_V << CPU_APM_REGION3_R0_W_S) #define CPU_APM_REGION3_R0_W_V 0x00000001U #define CPU_APM_REGION3_R0_W_S 1 /** CPU_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 3. + * Configures the read permission in region 3 in REE0 mode. */ #define CPU_APM_REGION3_R0_R (BIT(2)) #define CPU_APM_REGION3_R0_R_M (CPU_APM_REGION3_R0_R_V << CPU_APM_REGION3_R0_R_S) #define CPU_APM_REGION3_R0_R_V 0x00000001U #define CPU_APM_REGION3_R0_R_S 2 /** CPU_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 3. + * Configures the execution permission in region 3 in REE1 mode. */ #define CPU_APM_REGION3_R1_X (BIT(4)) #define CPU_APM_REGION3_R1_X_M (CPU_APM_REGION3_R1_X_V << CPU_APM_REGION3_R1_X_S) #define CPU_APM_REGION3_R1_X_V 0x00000001U #define CPU_APM_REGION3_R1_X_S 4 /** CPU_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 3. + * Configures the write permission in region 3 in REE1 mode. */ #define CPU_APM_REGION3_R1_W (BIT(5)) #define CPU_APM_REGION3_R1_W_M (CPU_APM_REGION3_R1_W_V << CPU_APM_REGION3_R1_W_S) #define CPU_APM_REGION3_R1_W_V 0x00000001U #define CPU_APM_REGION3_R1_W_S 5 /** CPU_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 3. + * Configures the read permission in region 3 in REE1 mode. */ #define CPU_APM_REGION3_R1_R (BIT(6)) #define CPU_APM_REGION3_R1_R_M (CPU_APM_REGION3_R1_R_V << CPU_APM_REGION3_R1_R_S) #define CPU_APM_REGION3_R1_R_V 0x00000001U #define CPU_APM_REGION3_R1_R_S 6 /** CPU_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 3. + * Configures the execution permission in region 3 in REE2 mode. */ #define CPU_APM_REGION3_R2_X (BIT(8)) #define CPU_APM_REGION3_R2_X_M (CPU_APM_REGION3_R2_X_V << CPU_APM_REGION3_R2_X_S) #define CPU_APM_REGION3_R2_X_V 0x00000001U #define CPU_APM_REGION3_R2_X_S 8 /** CPU_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 3. + * Configures the write permission in region 3 in REE2 mode. */ #define CPU_APM_REGION3_R2_W (BIT(9)) #define CPU_APM_REGION3_R2_W_M (CPU_APM_REGION3_R2_W_V << CPU_APM_REGION3_R2_W_S) #define CPU_APM_REGION3_R2_W_V 0x00000001U #define CPU_APM_REGION3_R2_W_S 9 /** CPU_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 3. + * Configures the read permission in region 3 in REE2 mode. */ #define CPU_APM_REGION3_R2_R (BIT(10)) #define CPU_APM_REGION3_R2_R_M (CPU_APM_REGION3_R2_R_V << CPU_APM_REGION3_R2_R_S) #define CPU_APM_REGION3_R2_R_V 0x00000001U #define CPU_APM_REGION3_R2_R_S 10 /** CPU_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 3's configuration registers + * (CPU_APM_REGION3_ADDR_START_REG, CPU_APM_REGION3_ADDR_END_REG, and + * CPU_APM_REGION3_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION3_LOCK (BIT(11)) #define CPU_APM_REGION3_LOCK_M (CPU_APM_REGION3_LOCK_V << CPU_APM_REGION3_LOCK_S) @@ -545,7 +561,7 @@ extern "C" { #define CPU_APM_REGION4_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION4_ADDR_START_L_S 0 /** CPU_APM_REGION4_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 4. + * Configures the start address of region 4. */ #define CPU_APM_REGION4_ADDR_START 0x0000007FU #define CPU_APM_REGION4_ADDR_START_M (CPU_APM_REGION4_ADDR_START_V << CPU_APM_REGION4_ADDR_START_S) @@ -571,7 +587,7 @@ extern "C" { #define CPU_APM_REGION4_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION4_ADDR_END_L_S 0 /** CPU_APM_REGION4_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 4. + * Configures the end address of region 4. */ #define CPU_APM_REGION4_ADDR_END 0x0000007FU #define CPU_APM_REGION4_ADDR_END_M (CPU_APM_REGION4_ADDR_END_V << CPU_APM_REGION4_ADDR_END_S) @@ -586,74 +602,78 @@ extern "C" { #define CPU_APM_REGION4_ADDR_END_H_S 19 /** CPU_APM_REGION4_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION4_ATTR_REG (DR_REG_CPU_APM_BASE + 0x3c) /** CPU_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 4. + * Configures the execution permission in region 4 in REE0 mode. */ #define CPU_APM_REGION4_R0_X (BIT(0)) #define CPU_APM_REGION4_R0_X_M (CPU_APM_REGION4_R0_X_V << CPU_APM_REGION4_R0_X_S) #define CPU_APM_REGION4_R0_X_V 0x00000001U #define CPU_APM_REGION4_R0_X_S 0 /** CPU_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 4. + * Configures the write permission in region 4 in REE0 mode. */ #define CPU_APM_REGION4_R0_W (BIT(1)) #define CPU_APM_REGION4_R0_W_M (CPU_APM_REGION4_R0_W_V << CPU_APM_REGION4_R0_W_S) #define CPU_APM_REGION4_R0_W_V 0x00000001U #define CPU_APM_REGION4_R0_W_S 1 /** CPU_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 4. + * Configures the read permission in region 4 in REE0 mode. */ #define CPU_APM_REGION4_R0_R (BIT(2)) #define CPU_APM_REGION4_R0_R_M (CPU_APM_REGION4_R0_R_V << CPU_APM_REGION4_R0_R_S) #define CPU_APM_REGION4_R0_R_V 0x00000001U #define CPU_APM_REGION4_R0_R_S 2 /** CPU_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 4. + * Configures the execution permission in region 4 in REE1 mode. */ #define CPU_APM_REGION4_R1_X (BIT(4)) #define CPU_APM_REGION4_R1_X_M (CPU_APM_REGION4_R1_X_V << CPU_APM_REGION4_R1_X_S) #define CPU_APM_REGION4_R1_X_V 0x00000001U #define CPU_APM_REGION4_R1_X_S 4 /** CPU_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 4. + * Configures the write permission in region 4 in REE1 mode. */ #define CPU_APM_REGION4_R1_W (BIT(5)) #define CPU_APM_REGION4_R1_W_M (CPU_APM_REGION4_R1_W_V << CPU_APM_REGION4_R1_W_S) #define CPU_APM_REGION4_R1_W_V 0x00000001U #define CPU_APM_REGION4_R1_W_S 5 /** CPU_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 4. + * Configures the read permission in region 4 in REE1 mode. */ #define CPU_APM_REGION4_R1_R (BIT(6)) #define CPU_APM_REGION4_R1_R_M (CPU_APM_REGION4_R1_R_V << CPU_APM_REGION4_R1_R_S) #define CPU_APM_REGION4_R1_R_V 0x00000001U #define CPU_APM_REGION4_R1_R_S 6 /** CPU_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 4. + * Configures the execution permission in region 4 in REE2 mode. */ #define CPU_APM_REGION4_R2_X (BIT(8)) #define CPU_APM_REGION4_R2_X_M (CPU_APM_REGION4_R2_X_V << CPU_APM_REGION4_R2_X_S) #define CPU_APM_REGION4_R2_X_V 0x00000001U #define CPU_APM_REGION4_R2_X_S 8 /** CPU_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 4. + * Configures the write permission in region 4 in REE2 mode. */ #define CPU_APM_REGION4_R2_W (BIT(9)) #define CPU_APM_REGION4_R2_W_M (CPU_APM_REGION4_R2_W_V << CPU_APM_REGION4_R2_W_S) #define CPU_APM_REGION4_R2_W_V 0x00000001U #define CPU_APM_REGION4_R2_W_S 9 /** CPU_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 4. + * Configures the read permission in region 4 in REE2 mode. */ #define CPU_APM_REGION4_R2_R (BIT(10)) #define CPU_APM_REGION4_R2_R_M (CPU_APM_REGION4_R2_R_V << CPU_APM_REGION4_R2_R_S) #define CPU_APM_REGION4_R2_R_V 0x00000001U #define CPU_APM_REGION4_R2_R_S 10 /** CPU_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 4's configuration registers + * (CPU_APM_REGION4_ADDR_START_REG, CPU_APM_REGION4_ADDR_END_REG, and + * CPU_APM_REGION4_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION4_LOCK (BIT(11)) #define CPU_APM_REGION4_LOCK_M (CPU_APM_REGION4_LOCK_V << CPU_APM_REGION4_LOCK_S) @@ -672,7 +692,7 @@ extern "C" { #define CPU_APM_REGION5_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION5_ADDR_START_L_S 0 /** CPU_APM_REGION5_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 5. + * Configures the start address of region 5. */ #define CPU_APM_REGION5_ADDR_START 0x0000007FU #define CPU_APM_REGION5_ADDR_START_M (CPU_APM_REGION5_ADDR_START_V << CPU_APM_REGION5_ADDR_START_S) @@ -698,7 +718,7 @@ extern "C" { #define CPU_APM_REGION5_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION5_ADDR_END_L_S 0 /** CPU_APM_REGION5_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 5. + * Configures the end address of region 5. */ #define CPU_APM_REGION5_ADDR_END 0x0000007FU #define CPU_APM_REGION5_ADDR_END_M (CPU_APM_REGION5_ADDR_END_V << CPU_APM_REGION5_ADDR_END_S) @@ -713,74 +733,78 @@ extern "C" { #define CPU_APM_REGION5_ADDR_END_H_S 19 /** CPU_APM_REGION5_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION5_ATTR_REG (DR_REG_CPU_APM_BASE + 0x48) /** CPU_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 5. + * Configures the execution permission in region 5 in REE0 mode. */ #define CPU_APM_REGION5_R0_X (BIT(0)) #define CPU_APM_REGION5_R0_X_M (CPU_APM_REGION5_R0_X_V << CPU_APM_REGION5_R0_X_S) #define CPU_APM_REGION5_R0_X_V 0x00000001U #define CPU_APM_REGION5_R0_X_S 0 /** CPU_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 5. + * Configures the write permission in region 5 in REE0 mode. */ #define CPU_APM_REGION5_R0_W (BIT(1)) #define CPU_APM_REGION5_R0_W_M (CPU_APM_REGION5_R0_W_V << CPU_APM_REGION5_R0_W_S) #define CPU_APM_REGION5_R0_W_V 0x00000001U #define CPU_APM_REGION5_R0_W_S 1 /** CPU_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 5. + * Configures the read permission in region 5 in REE0 mode. */ #define CPU_APM_REGION5_R0_R (BIT(2)) #define CPU_APM_REGION5_R0_R_M (CPU_APM_REGION5_R0_R_V << CPU_APM_REGION5_R0_R_S) #define CPU_APM_REGION5_R0_R_V 0x00000001U #define CPU_APM_REGION5_R0_R_S 2 /** CPU_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 5. + * Configures the execution permission in region 5 in REE1 mode. */ #define CPU_APM_REGION5_R1_X (BIT(4)) #define CPU_APM_REGION5_R1_X_M (CPU_APM_REGION5_R1_X_V << CPU_APM_REGION5_R1_X_S) #define CPU_APM_REGION5_R1_X_V 0x00000001U #define CPU_APM_REGION5_R1_X_S 4 /** CPU_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 5. + * Configures the write permission in region 5 in REE1 mode. */ #define CPU_APM_REGION5_R1_W (BIT(5)) #define CPU_APM_REGION5_R1_W_M (CPU_APM_REGION5_R1_W_V << CPU_APM_REGION5_R1_W_S) #define CPU_APM_REGION5_R1_W_V 0x00000001U #define CPU_APM_REGION5_R1_W_S 5 /** CPU_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 5. + * Configures the read permission in region 5 in REE1 mode. */ #define CPU_APM_REGION5_R1_R (BIT(6)) #define CPU_APM_REGION5_R1_R_M (CPU_APM_REGION5_R1_R_V << CPU_APM_REGION5_R1_R_S) #define CPU_APM_REGION5_R1_R_V 0x00000001U #define CPU_APM_REGION5_R1_R_S 6 /** CPU_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 5. + * Configures the execution permission in region 5 in REE2 mode. */ #define CPU_APM_REGION5_R2_X (BIT(8)) #define CPU_APM_REGION5_R2_X_M (CPU_APM_REGION5_R2_X_V << CPU_APM_REGION5_R2_X_S) #define CPU_APM_REGION5_R2_X_V 0x00000001U #define CPU_APM_REGION5_R2_X_S 8 /** CPU_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 5. + * Configures the write permission in region 5 in REE2 mode. */ #define CPU_APM_REGION5_R2_W (BIT(9)) #define CPU_APM_REGION5_R2_W_M (CPU_APM_REGION5_R2_W_V << CPU_APM_REGION5_R2_W_S) #define CPU_APM_REGION5_R2_W_V 0x00000001U #define CPU_APM_REGION5_R2_W_S 9 /** CPU_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 5. + * Configures the read permission in region 5 in REE2 mode. */ #define CPU_APM_REGION5_R2_R (BIT(10)) #define CPU_APM_REGION5_R2_R_M (CPU_APM_REGION5_R2_R_V << CPU_APM_REGION5_R2_R_S) #define CPU_APM_REGION5_R2_R_V 0x00000001U #define CPU_APM_REGION5_R2_R_S 10 /** CPU_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 5's configuration registers + * (CPU_APM_REGION5_ADDR_START_REG, CPU_APM_REGION5_ADDR_END_REG, and + * CPU_APM_REGION5_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION5_LOCK (BIT(11)) #define CPU_APM_REGION5_LOCK_M (CPU_APM_REGION5_LOCK_V << CPU_APM_REGION5_LOCK_S) @@ -799,7 +823,7 @@ extern "C" { #define CPU_APM_REGION6_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION6_ADDR_START_L_S 0 /** CPU_APM_REGION6_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 6. + * Configures the start address of region 6. */ #define CPU_APM_REGION6_ADDR_START 0x0000007FU #define CPU_APM_REGION6_ADDR_START_M (CPU_APM_REGION6_ADDR_START_V << CPU_APM_REGION6_ADDR_START_S) @@ -825,7 +849,7 @@ extern "C" { #define CPU_APM_REGION6_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION6_ADDR_END_L_S 0 /** CPU_APM_REGION6_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 6. + * Configures the end address of region 6. */ #define CPU_APM_REGION6_ADDR_END 0x0000007FU #define CPU_APM_REGION6_ADDR_END_M (CPU_APM_REGION6_ADDR_END_V << CPU_APM_REGION6_ADDR_END_S) @@ -840,74 +864,78 @@ extern "C" { #define CPU_APM_REGION6_ADDR_END_H_S 19 /** CPU_APM_REGION6_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION6_ATTR_REG (DR_REG_CPU_APM_BASE + 0x54) /** CPU_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 6. + * Configures the execution permission in region 6 in REE0 mode. */ #define CPU_APM_REGION6_R0_X (BIT(0)) #define CPU_APM_REGION6_R0_X_M (CPU_APM_REGION6_R0_X_V << CPU_APM_REGION6_R0_X_S) #define CPU_APM_REGION6_R0_X_V 0x00000001U #define CPU_APM_REGION6_R0_X_S 0 /** CPU_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 6. + * Configures the write permission in region 6 in REE0 mode. */ #define CPU_APM_REGION6_R0_W (BIT(1)) #define CPU_APM_REGION6_R0_W_M (CPU_APM_REGION6_R0_W_V << CPU_APM_REGION6_R0_W_S) #define CPU_APM_REGION6_R0_W_V 0x00000001U #define CPU_APM_REGION6_R0_W_S 1 /** CPU_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 6. + * Configures the read permission in region 6 in REE0 mode. */ #define CPU_APM_REGION6_R0_R (BIT(2)) #define CPU_APM_REGION6_R0_R_M (CPU_APM_REGION6_R0_R_V << CPU_APM_REGION6_R0_R_S) #define CPU_APM_REGION6_R0_R_V 0x00000001U #define CPU_APM_REGION6_R0_R_S 2 /** CPU_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 6. + * Configures the execution permission in region 6 in REE1 mode. */ #define CPU_APM_REGION6_R1_X (BIT(4)) #define CPU_APM_REGION6_R1_X_M (CPU_APM_REGION6_R1_X_V << CPU_APM_REGION6_R1_X_S) #define CPU_APM_REGION6_R1_X_V 0x00000001U #define CPU_APM_REGION6_R1_X_S 4 /** CPU_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 6. + * Configures the write permission in region 6 in REE1 mode. */ #define CPU_APM_REGION6_R1_W (BIT(5)) #define CPU_APM_REGION6_R1_W_M (CPU_APM_REGION6_R1_W_V << CPU_APM_REGION6_R1_W_S) #define CPU_APM_REGION6_R1_W_V 0x00000001U #define CPU_APM_REGION6_R1_W_S 5 /** CPU_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 6. + * Configures the read permission in region 6 in REE1 mode. */ #define CPU_APM_REGION6_R1_R (BIT(6)) #define CPU_APM_REGION6_R1_R_M (CPU_APM_REGION6_R1_R_V << CPU_APM_REGION6_R1_R_S) #define CPU_APM_REGION6_R1_R_V 0x00000001U #define CPU_APM_REGION6_R1_R_S 6 /** CPU_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 6. + * Configures the execution permission in region 6 in REE2 mode. */ #define CPU_APM_REGION6_R2_X (BIT(8)) #define CPU_APM_REGION6_R2_X_M (CPU_APM_REGION6_R2_X_V << CPU_APM_REGION6_R2_X_S) #define CPU_APM_REGION6_R2_X_V 0x00000001U #define CPU_APM_REGION6_R2_X_S 8 /** CPU_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 6. + * Configures the write permission in region 6 in REE2 mode. */ #define CPU_APM_REGION6_R2_W (BIT(9)) #define CPU_APM_REGION6_R2_W_M (CPU_APM_REGION6_R2_W_V << CPU_APM_REGION6_R2_W_S) #define CPU_APM_REGION6_R2_W_V 0x00000001U #define CPU_APM_REGION6_R2_W_S 9 /** CPU_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 6. + * Configures the read permission in region 6 in REE2 mode. */ #define CPU_APM_REGION6_R2_R (BIT(10)) #define CPU_APM_REGION6_R2_R_M (CPU_APM_REGION6_R2_R_V << CPU_APM_REGION6_R2_R_S) #define CPU_APM_REGION6_R2_R_V 0x00000001U #define CPU_APM_REGION6_R2_R_S 10 /** CPU_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 6's configuration registers + * (CPU_APM_REGION6_ADDR_START_REG, CPU_APM_REGION6_ADDR_END_REG, and + * CPU_APM_REGION6_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION6_LOCK (BIT(11)) #define CPU_APM_REGION6_LOCK_M (CPU_APM_REGION6_LOCK_V << CPU_APM_REGION6_LOCK_S) @@ -926,7 +954,7 @@ extern "C" { #define CPU_APM_REGION7_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION7_ADDR_START_L_S 0 /** CPU_APM_REGION7_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 7. + * Configures the start address of region 7. */ #define CPU_APM_REGION7_ADDR_START 0x0000007FU #define CPU_APM_REGION7_ADDR_START_M (CPU_APM_REGION7_ADDR_START_V << CPU_APM_REGION7_ADDR_START_S) @@ -952,7 +980,7 @@ extern "C" { #define CPU_APM_REGION7_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION7_ADDR_END_L_S 0 /** CPU_APM_REGION7_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 7. + * Configures the end address of region 7. */ #define CPU_APM_REGION7_ADDR_END 0x0000007FU #define CPU_APM_REGION7_ADDR_END_M (CPU_APM_REGION7_ADDR_END_V << CPU_APM_REGION7_ADDR_END_S) @@ -967,74 +995,78 @@ extern "C" { #define CPU_APM_REGION7_ADDR_END_H_S 19 /** CPU_APM_REGION7_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION7_ATTR_REG (DR_REG_CPU_APM_BASE + 0x60) /** CPU_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 7. + * Configures the execution permission in region 7 in REE0 mode. */ #define CPU_APM_REGION7_R0_X (BIT(0)) #define CPU_APM_REGION7_R0_X_M (CPU_APM_REGION7_R0_X_V << CPU_APM_REGION7_R0_X_S) #define CPU_APM_REGION7_R0_X_V 0x00000001U #define CPU_APM_REGION7_R0_X_S 0 /** CPU_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 7. + * Configures the write permission in region 7 in REE0 mode. */ #define CPU_APM_REGION7_R0_W (BIT(1)) #define CPU_APM_REGION7_R0_W_M (CPU_APM_REGION7_R0_W_V << CPU_APM_REGION7_R0_W_S) #define CPU_APM_REGION7_R0_W_V 0x00000001U #define CPU_APM_REGION7_R0_W_S 1 /** CPU_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 7. + * Configures the read permission in region 7 in REE0 mode. */ #define CPU_APM_REGION7_R0_R (BIT(2)) #define CPU_APM_REGION7_R0_R_M (CPU_APM_REGION7_R0_R_V << CPU_APM_REGION7_R0_R_S) #define CPU_APM_REGION7_R0_R_V 0x00000001U #define CPU_APM_REGION7_R0_R_S 2 /** CPU_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 7. + * Configures the execution permission in region 7 in REE1 mode. */ #define CPU_APM_REGION7_R1_X (BIT(4)) #define CPU_APM_REGION7_R1_X_M (CPU_APM_REGION7_R1_X_V << CPU_APM_REGION7_R1_X_S) #define CPU_APM_REGION7_R1_X_V 0x00000001U #define CPU_APM_REGION7_R1_X_S 4 /** CPU_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 7. + * Configures the write permission in region 7 in REE1 mode. */ #define CPU_APM_REGION7_R1_W (BIT(5)) #define CPU_APM_REGION7_R1_W_M (CPU_APM_REGION7_R1_W_V << CPU_APM_REGION7_R1_W_S) #define CPU_APM_REGION7_R1_W_V 0x00000001U #define CPU_APM_REGION7_R1_W_S 5 /** CPU_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 7. + * Configures the read permission in region 7 in REE1 mode. */ #define CPU_APM_REGION7_R1_R (BIT(6)) #define CPU_APM_REGION7_R1_R_M (CPU_APM_REGION7_R1_R_V << CPU_APM_REGION7_R1_R_S) #define CPU_APM_REGION7_R1_R_V 0x00000001U #define CPU_APM_REGION7_R1_R_S 6 /** CPU_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 7. + * Configures the execution permission in region 7 in REE2 mode. */ #define CPU_APM_REGION7_R2_X (BIT(8)) #define CPU_APM_REGION7_R2_X_M (CPU_APM_REGION7_R2_X_V << CPU_APM_REGION7_R2_X_S) #define CPU_APM_REGION7_R2_X_V 0x00000001U #define CPU_APM_REGION7_R2_X_S 8 /** CPU_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 7. + * Configures the write permission in region 7 in REE2 mode. */ #define CPU_APM_REGION7_R2_W (BIT(9)) #define CPU_APM_REGION7_R2_W_M (CPU_APM_REGION7_R2_W_V << CPU_APM_REGION7_R2_W_S) #define CPU_APM_REGION7_R2_W_V 0x00000001U #define CPU_APM_REGION7_R2_W_S 9 /** CPU_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 7. + * Configures the read permission in region 7 in REE2 mode. */ #define CPU_APM_REGION7_R2_R (BIT(10)) #define CPU_APM_REGION7_R2_R_M (CPU_APM_REGION7_R2_R_V << CPU_APM_REGION7_R2_R_S) #define CPU_APM_REGION7_R2_R_V 0x00000001U #define CPU_APM_REGION7_R2_R_S 10 /** CPU_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 7's configuration registers + * (CPU_APM_REGION7_ADDR_START_REG, CPU_APM_REGION7_ADDR_END_REG, and + * CPU_APM_REGION7_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION7_LOCK (BIT(11)) #define CPU_APM_REGION7_LOCK_M (CPU_APM_REGION7_LOCK_V << CPU_APM_REGION7_LOCK_S) @@ -1042,18 +1074,22 @@ extern "C" { #define CPU_APM_REGION7_LOCK_S 11 /** CPU_APM_FUNC_CTRL_REG register - * APM function control register + * APM access path permission management register */ #define CPU_APM_FUNC_CTRL_REG (DR_REG_CPU_APM_BASE + 0xc4) /** CPU_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures whether to enable permission management for CPU_APM_CTRL M0. + * 0: Disable + * 1: Enable */ #define CPU_APM_M0_FUNC_EN (BIT(0)) #define CPU_APM_M0_FUNC_EN_M (CPU_APM_M0_FUNC_EN_V << CPU_APM_M0_FUNC_EN_S) #define CPU_APM_M0_FUNC_EN_V 0x00000001U #define CPU_APM_M0_FUNC_EN_S 0 /** CPU_APM_M1_FUNC_EN : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable + * Configures whether to enable permission management for CPU_APM_CTRL M1. + * 0: Disable + * 1: Enable */ #define CPU_APM_M1_FUNC_EN (BIT(1)) #define CPU_APM_M1_FUNC_EN_M (CPU_APM_M1_FUNC_EN_V << CPU_APM_M1_FUNC_EN_S) @@ -1061,13 +1097,13 @@ extern "C" { #define CPU_APM_M1_FUNC_EN_S 1 /** CPU_APM_M0_STATUS_REG register - * M0 status register + * CPU_APM_CTRL M0 status register */ #define CPU_APM_M0_STATUS_REG (DR_REG_CPU_APM_BASE + 0xc8) /** CPU_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define CPU_APM_M0_EXCEPTION_STATUS 0x00000003U #define CPU_APM_M0_EXCEPTION_STATUS_M (CPU_APM_M0_EXCEPTION_STATUS_V << CPU_APM_M0_EXCEPTION_STATUS_S) @@ -1075,11 +1111,11 @@ extern "C" { #define CPU_APM_M0_EXCEPTION_STATUS_S 0 /** CPU_APM_M0_STATUS_CLR_REG register - * M0 status clear register + * CPU_APM_CTRL M0 status clear register */ #define CPU_APM_M0_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xcc) /** CPU_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; - * Configures to clear exception status. + * Write 1 to clear exception status. */ #define CPU_APM_M0_EXCEPTION_STATUS_CLR (BIT(0)) #define CPU_APM_M0_EXCEPTION_STATUS_CLR_M (CPU_APM_M0_EXCEPTION_STATUS_CLR_V << CPU_APM_M0_EXCEPTION_STATUS_CLR_S) @@ -1087,25 +1123,25 @@ extern "C" { #define CPU_APM_M0_EXCEPTION_STATUS_CLR_S 0 /** CPU_APM_M0_EXCEPTION_INFO0_REG register - * M0 exception_info0 register + * CPU_APM_CTRL M0 exception information register */ #define CPU_APM_M0_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xd0) /** CPU_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define CPU_APM_M0_EXCEPTION_REGION 0x0000FFFFU #define CPU_APM_M0_EXCEPTION_REGION_M (CPU_APM_M0_EXCEPTION_REGION_V << CPU_APM_M0_EXCEPTION_REGION_S) #define CPU_APM_M0_EXCEPTION_REGION_V 0x0000FFFFU #define CPU_APM_M0_EXCEPTION_REGION_S 0 /** CPU_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define CPU_APM_M0_EXCEPTION_MODE 0x00000003U #define CPU_APM_M0_EXCEPTION_MODE_M (CPU_APM_M0_EXCEPTION_MODE_V << CPU_APM_M0_EXCEPTION_MODE_S) #define CPU_APM_M0_EXCEPTION_MODE_V 0x00000003U #define CPU_APM_M0_EXCEPTION_MODE_S 16 /** CPU_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define CPU_APM_M0_EXCEPTION_ID 0x0000001FU #define CPU_APM_M0_EXCEPTION_ID_M (CPU_APM_M0_EXCEPTION_ID_V << CPU_APM_M0_EXCEPTION_ID_S) @@ -1113,11 +1149,11 @@ extern "C" { #define CPU_APM_M0_EXCEPTION_ID_S 18 /** CPU_APM_M0_EXCEPTION_INFO1_REG register - * M0 exception_info1 register + * CPU_APM_CTRL M0 exception information register */ #define CPU_APM_M0_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xd4) /** CPU_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define CPU_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU #define CPU_APM_M0_EXCEPTION_ADDR_M (CPU_APM_M0_EXCEPTION_ADDR_V << CPU_APM_M0_EXCEPTION_ADDR_S) @@ -1125,13 +1161,13 @@ extern "C" { #define CPU_APM_M0_EXCEPTION_ADDR_S 0 /** CPU_APM_M1_STATUS_REG register - * M1 status register + * CPU_APM_CTRL M1 status register */ #define CPU_APM_M1_STATUS_REG (DR_REG_CPU_APM_BASE + 0xd8) /** CPU_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define CPU_APM_M1_EXCEPTION_STATUS 0x00000003U #define CPU_APM_M1_EXCEPTION_STATUS_M (CPU_APM_M1_EXCEPTION_STATUS_V << CPU_APM_M1_EXCEPTION_STATUS_S) @@ -1139,11 +1175,11 @@ extern "C" { #define CPU_APM_M1_EXCEPTION_STATUS_S 0 /** CPU_APM_M1_STATUS_CLR_REG register - * M1 status clear register + * CPU_APM_CTRL M1 status clear register */ #define CPU_APM_M1_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xdc) /** CPU_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; - * Configures to clear exception status. + * Write 1 to clear exception status. */ #define CPU_APM_M1_EXCEPTION_STATUS_CLR (BIT(0)) #define CPU_APM_M1_EXCEPTION_STATUS_CLR_M (CPU_APM_M1_EXCEPTION_STATUS_CLR_V << CPU_APM_M1_EXCEPTION_STATUS_CLR_S) @@ -1151,25 +1187,25 @@ extern "C" { #define CPU_APM_M1_EXCEPTION_STATUS_CLR_S 0 /** CPU_APM_M1_EXCEPTION_INFO0_REG register - * M1 exception_info0 register + * CPU_APM_CTRL M1 exception information register */ #define CPU_APM_M1_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xe0) /** CPU_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define CPU_APM_M1_EXCEPTION_REGION 0x0000FFFFU #define CPU_APM_M1_EXCEPTION_REGION_M (CPU_APM_M1_EXCEPTION_REGION_V << CPU_APM_M1_EXCEPTION_REGION_S) #define CPU_APM_M1_EXCEPTION_REGION_V 0x0000FFFFU #define CPU_APM_M1_EXCEPTION_REGION_S 0 /** CPU_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define CPU_APM_M1_EXCEPTION_MODE 0x00000003U #define CPU_APM_M1_EXCEPTION_MODE_M (CPU_APM_M1_EXCEPTION_MODE_V << CPU_APM_M1_EXCEPTION_MODE_S) #define CPU_APM_M1_EXCEPTION_MODE_V 0x00000003U #define CPU_APM_M1_EXCEPTION_MODE_S 16 /** CPU_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define CPU_APM_M1_EXCEPTION_ID 0x0000001FU #define CPU_APM_M1_EXCEPTION_ID_M (CPU_APM_M1_EXCEPTION_ID_V << CPU_APM_M1_EXCEPTION_ID_S) @@ -1177,11 +1213,11 @@ extern "C" { #define CPU_APM_M1_EXCEPTION_ID_S 18 /** CPU_APM_M1_EXCEPTION_INFO1_REG register - * M1 exception_info1 register + * CPU_APM_CTRL M1 exception information register */ #define CPU_APM_M1_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xe4) /** CPU_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define CPU_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU #define CPU_APM_M1_EXCEPTION_ADDR_M (CPU_APM_M1_EXCEPTION_ADDR_V << CPU_APM_M1_EXCEPTION_ADDR_S) @@ -1189,22 +1225,22 @@ extern "C" { #define CPU_APM_M1_EXCEPTION_ADDR_S 0 /** CPU_APM_INT_EN_REG register - * APM interrupt enable register + * CPU_APM_CTRL M0/1 interrupt enable register */ #define CPU_APM_INT_EN_REG (DR_REG_CPU_APM_BASE + 0x118) /** CPU_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; - * Configures to enable APM M0 interrupt. - * 0: disable - * 1: enable + * Configures whether to enable CPU_APM_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ #define CPU_APM_M0_APM_INT_EN (BIT(0)) #define CPU_APM_M0_APM_INT_EN_M (CPU_APM_M0_APM_INT_EN_V << CPU_APM_M0_APM_INT_EN_S) #define CPU_APM_M0_APM_INT_EN_V 0x00000001U #define CPU_APM_M0_APM_INT_EN_S 0 /** CPU_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; - * Configures to enable APM M1 interrupt. - * 0: disable - * 1: enable + * Configures whether to enable CPU_APM_CTRL M1 interrupt. + * 0: Disable + * 1: Enable */ #define CPU_APM_M1_APM_INT_EN (BIT(1)) #define CPU_APM_M1_APM_INT_EN_M (CPU_APM_M1_APM_INT_EN_V << CPU_APM_M1_APM_INT_EN_S) @@ -1217,8 +1253,8 @@ extern "C" { #define CPU_APM_CLOCK_GATE_REG (DR_REG_CPU_APM_BASE + 0x7f8) /** CPU_APM_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ #define CPU_APM_CLK_EN (BIT(0)) #define CPU_APM_CLK_EN_M (CPU_APM_CLK_EN_V << CPU_APM_CLK_EN_S) diff --git a/components/soc/esp32c5/register/soc/cpu_apm_struct.h b/components/soc/esp32c5/register/soc/cpu_apm_struct.h index c8198eeecb..49d283b39c 100644 --- a/components/soc/esp32c5/register/soc/cpu_apm_struct.h +++ b/components/soc/esp32c5/register/soc/cpu_apm_struct.h @@ -10,16 +10,16 @@ extern "C" { #endif -/** Group: Region filter enable register */ +/** Group: Configuration Registers */ /** Type of region_filter_en register - * Region filter enable register + * Region enable register */ typedef union { struct { /** region_filter_en : R/W; bitpos: [7:0]; default: 1; - * Configure bit $n (0-7) to enable region $n. - * 0: disable - * 1: enable + * Configures bit $n (0-7) to enable region $n (0-7). + * 0: Disable + * 1: Enable */ uint32_t region_filter_en:8; uint32_t reserved_8:24; @@ -28,7 +28,7 @@ typedef union { } cpu_apm_region_filter_en_reg_t; -/** Group: Region address register */ +/** Group: Region Address Registers */ /** Type of regionn_addr_start register * Region address register */ @@ -39,7 +39,7 @@ typedef union { */ uint32_t regionn_addr_start_l:12; /** regionn_addr_start : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region n. + * Configures the start address of region n. */ uint32_t regionn_addr_start:7; /** regionn_addr_start_h : HRO; bitpos: [31:19]; default: 2064; @@ -60,7 +60,7 @@ typedef union { */ uint32_t regionn_addr_end_l:12; /** regionn_addr_end : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region n. + * Configures the end address of region n. */ uint32_t regionn_addr_end:7; /** regionn_addr_end_h : HRO; bitpos: [31:19]; default: 2064; @@ -71,53 +71,55 @@ typedef union { uint32_t val; } cpu_apm_regionn_addr_end_reg_t; - -/** Group: Region access authority attribute register */ /** Type of regionn_attr register - * Region access authority attribute register + * Region access permissions configuration register */ typedef union { struct { /** regionn_r0_x : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region n. + * Configures the execution permission in region n in REE0 mode. */ uint32_t regionn_r0_x:1; /** regionn_r0_w : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region n. + * Configures the write permission in region n in REE0 mode. */ uint32_t regionn_r0_w:1; /** regionn_r0_r : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region n. + * Configures the read permission in region n in REE0 mode. */ uint32_t regionn_r0_r:1; uint32_t reserved_3:1; /** regionn_r1_x : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region n. + * Configures the execution permission in region n in REE1 mode. */ uint32_t regionn_r1_x:1; /** regionn_r1_w : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region n. + * Configures the write permission in region n in REE1 mode. */ uint32_t regionn_r1_w:1; /** regionn_r1_r : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region n. + * Configures the read permission in region n in REE1 mode. */ uint32_t regionn_r1_r:1; uint32_t reserved_7:1; /** regionn_r2_x : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region n. + * Configures the execution permission in region n in REE2 mode. */ uint32_t regionn_r2_x:1; /** regionn_r2_w : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region n. + * Configures the write permission in region n in REE2 mode. */ uint32_t regionn_r2_w:1; /** regionn_r2_r : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region n. + * Configures the read permission in region n in REE2 mode. */ uint32_t regionn_r2_r:1; /** regionn_lock : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region n's configuration registers + * (CPU_APM_REGIONn_ADDR_START_REG, CPU_APM_REGIONn_ADDR_END_REG, and + * CPU_APM_REGIONn_ATTR_REG). + * 0: Do not lock + * 1: Lock */ uint32_t regionn_lock:1; uint32_t reserved_12:20; @@ -125,19 +127,21 @@ typedef union { uint32_t val; } cpu_apm_regionn_attr_reg_t; - -/** Group: function control register */ /** Type of func_ctrl register - * APM function control register + * APM access path permission management register */ typedef union { struct { /** m0_func_en : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures whether to enable permission management for CPU_APM_CTRL M0. + * 0: Disable + * 1: Enable */ uint32_t m0_func_en:1; /** m1_func_en : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable + * Configures whether to enable permission management for CPU_APM_CTRL M1. + * 0: Disable + * 1: Enable */ uint32_t m1_func_en:1; uint32_t reserved_2:30; @@ -146,16 +150,16 @@ typedef union { } cpu_apm_func_ctrl_reg_t; -/** Group: M0 status register */ +/** Group: Status Registers */ /** Type of m0_status register - * M0 status register + * CPU_APM_CTRL M0 status register */ typedef union { struct { /** m0_exception_status : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m0_exception_status:2; uint32_t reserved_2:30; @@ -163,15 +167,13 @@ typedef union { uint32_t val; } cpu_apm_m0_status_reg_t; - -/** Group: M0 status clear register */ /** Type of m0_status_clr register - * M0 status clear register + * CPU_APM_CTRL M0 status clear register */ typedef union { struct { /** m0_exception_status_clr : WT; bitpos: [0]; default: 0; - * Configures to clear exception status. + * Write 1 to clear exception status. */ uint32_t m0_exception_status_clr:1; uint32_t reserved_1:31; @@ -179,23 +181,21 @@ typedef union { uint32_t val; } cpu_apm_m0_status_clr_reg_t; - -/** Group: M0 exception_info0 register */ /** Type of m0_exception_info0 register - * M0 exception_info0 register + * CPU_APM_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m0_exception_region:16; /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m0_exception_mode:2; /** m0_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m0_exception_id:5; uint32_t reserved_23:9; @@ -203,32 +203,28 @@ typedef union { uint32_t val; } cpu_apm_m0_exception_info0_reg_t; - -/** Group: M0 exception_info1 register */ /** Type of m0_exception_info1 register - * M0 exception_info1 register + * CPU_APM_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m0_exception_addr:32; }; uint32_t val; } cpu_apm_m0_exception_info1_reg_t; - -/** Group: M1 status register */ /** Type of m1_status register - * M1 status register + * CPU_APM_CTRL M1 status register */ typedef union { struct { /** m1_exception_status : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m1_exception_status:2; uint32_t reserved_2:30; @@ -236,15 +232,13 @@ typedef union { uint32_t val; } cpu_apm_m1_status_reg_t; - -/** Group: M1 status clear register */ /** Type of m1_status_clr register - * M1 status clear register + * CPU_APM_CTRL M1 status clear register */ typedef union { struct { /** m1_exception_status_clr : WT; bitpos: [0]; default: 0; - * Configures to clear exception status. + * Write 1 to clear exception status. */ uint32_t m1_exception_status_clr:1; uint32_t reserved_1:31; @@ -252,23 +246,21 @@ typedef union { uint32_t val; } cpu_apm_m1_status_clr_reg_t; - -/** Group: M1 exception_info0 register */ /** Type of m1_exception_info0 register - * M1 exception_info0 register + * CPU_APM_CTRL M1 exception information register */ typedef union { struct { /** m1_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m1_exception_region:16; /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m1_exception_mode:2; /** m1_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m1_exception_id:5; uint32_t reserved_23:9; @@ -276,15 +268,13 @@ typedef union { uint32_t val; } cpu_apm_m1_exception_info0_reg_t; - -/** Group: M1 exception_info1 register */ /** Type of m1_exception_info1 register - * M1 exception_info1 register + * CPU_APM_CTRL M1 exception information register */ typedef union { struct { /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m1_exception_addr:32; }; @@ -292,22 +282,22 @@ typedef union { } cpu_apm_m1_exception_info1_reg_t; -/** Group: APM interrupt enable register */ +/** Group: Interrupt Registers */ /** Type of int_en register - * APM interrupt enable register + * CPU_APM_CTRL M0/1 interrupt enable register */ typedef union { struct { /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; - * Configures to enable APM M0 interrupt. - * 0: disable - * 1: enable + * Configures whether to enable CPU_APM_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m0_apm_int_en:1; /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; - * Configures to enable APM M1 interrupt. - * 0: disable - * 1: enable + * Configures whether to enable CPU_APM_CTRL M1 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m1_apm_int_en:1; uint32_t reserved_2:30; @@ -316,7 +306,7 @@ typedef union { } cpu_apm_int_en_reg_t; -/** Group: Clock gating register */ +/** Group: Clock Gating Registers */ /** Type of clock_gate register * Clock gating register */ @@ -324,8 +314,8 @@ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -334,7 +324,7 @@ typedef union { } cpu_apm_clock_gate_reg_t; -/** Group: Version control register */ +/** Group: Version Control Registers */ /** Type of date register * Version control register */ diff --git a/components/soc/esp32c5/register/soc/hp_apm_reg.h b/components/soc/esp32c5/register/soc/hp_apm_reg.h index ae587c5944..4179bf0815 100644 --- a/components/soc/esp32c5/register/soc/hp_apm_reg.h +++ b/components/soc/esp32c5/register/soc/hp_apm_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,13 +12,13 @@ extern "C" { #endif /** HP_APM_REGION_FILTER_EN_REG register - * Region filter enable register + * Region enable register */ #define HP_APM_REGION_FILTER_EN_REG (DR_REG_HP_APM_BASE + 0x0) /** HP_APM_REGION_FILTER_EN : R/W; bitpos: [15:0]; default: 1; - * Configure bit $n (0-15) to enable region $n.\\ - * 0: disable \\ - * 1: enable \\ + * Configure bit $n (0-15) to enable region $n (0-15). + * 0: Disable + * 1: Enable */ #define HP_APM_REGION_FILTER_EN 0x0000FFFFU #define HP_APM_REGION_FILTER_EN_M (HP_APM_REGION_FILTER_EN_V << HP_APM_REGION_FILTER_EN_S) @@ -30,7 +30,7 @@ extern "C" { */ #define HP_APM_REGION0_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4) /** HP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 0. + * Configures the start address of region 0. */ #define HP_APM_REGION0_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION0_ADDR_START_M (HP_APM_REGION0_ADDR_START_V << HP_APM_REGION0_ADDR_START_S) @@ -42,7 +42,7 @@ extern "C" { */ #define HP_APM_REGION0_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8) /** HP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 0. + * Configures the end address of region 0. */ #define HP_APM_REGION0_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION0_ADDR_END_M (HP_APM_REGION0_ADDR_END_V << HP_APM_REGION0_ADDR_END_S) @@ -50,74 +50,78 @@ extern "C" { #define HP_APM_REGION0_ADDR_END_S 0 /** HP_APM_REGION0_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION0_ATTR_REG (DR_REG_HP_APM_BASE + 0xc) /** HP_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 0. + * Configures the execution permission in region 0 in REE0 mode. */ #define HP_APM_REGION0_R0_X (BIT(0)) #define HP_APM_REGION0_R0_X_M (HP_APM_REGION0_R0_X_V << HP_APM_REGION0_R0_X_S) #define HP_APM_REGION0_R0_X_V 0x00000001U #define HP_APM_REGION0_R0_X_S 0 /** HP_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 0. + * Configures the write permission in region 0 in REE0 mode. */ #define HP_APM_REGION0_R0_W (BIT(1)) #define HP_APM_REGION0_R0_W_M (HP_APM_REGION0_R0_W_V << HP_APM_REGION0_R0_W_S) #define HP_APM_REGION0_R0_W_V 0x00000001U #define HP_APM_REGION0_R0_W_S 1 /** HP_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 0. + * Configures the read permission in region 0 in REE0 mode. */ #define HP_APM_REGION0_R0_R (BIT(2)) #define HP_APM_REGION0_R0_R_M (HP_APM_REGION0_R0_R_V << HP_APM_REGION0_R0_R_S) #define HP_APM_REGION0_R0_R_V 0x00000001U #define HP_APM_REGION0_R0_R_S 2 /** HP_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 0. + * Configures the execution permission in region 0 in REE1 mode. */ #define HP_APM_REGION0_R1_X (BIT(4)) #define HP_APM_REGION0_R1_X_M (HP_APM_REGION0_R1_X_V << HP_APM_REGION0_R1_X_S) #define HP_APM_REGION0_R1_X_V 0x00000001U #define HP_APM_REGION0_R1_X_S 4 /** HP_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 0. + * Configures the write permission in region 0 in REE1 mode. */ #define HP_APM_REGION0_R1_W (BIT(5)) #define HP_APM_REGION0_R1_W_M (HP_APM_REGION0_R1_W_V << HP_APM_REGION0_R1_W_S) #define HP_APM_REGION0_R1_W_V 0x00000001U #define HP_APM_REGION0_R1_W_S 5 /** HP_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 0. + * Configures the read permission in region 0 in REE1 mode. */ #define HP_APM_REGION0_R1_R (BIT(6)) #define HP_APM_REGION0_R1_R_M (HP_APM_REGION0_R1_R_V << HP_APM_REGION0_R1_R_S) #define HP_APM_REGION0_R1_R_V 0x00000001U #define HP_APM_REGION0_R1_R_S 6 /** HP_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 0. + * Configures the execution permission in region 0 in REE2 mode. */ #define HP_APM_REGION0_R2_X (BIT(8)) #define HP_APM_REGION0_R2_X_M (HP_APM_REGION0_R2_X_V << HP_APM_REGION0_R2_X_S) #define HP_APM_REGION0_R2_X_V 0x00000001U #define HP_APM_REGION0_R2_X_S 8 /** HP_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 0. + * Configures the write permission in region 0 in REE2 mode. */ #define HP_APM_REGION0_R2_W (BIT(9)) #define HP_APM_REGION0_R2_W_M (HP_APM_REGION0_R2_W_V << HP_APM_REGION0_R2_W_S) #define HP_APM_REGION0_R2_W_V 0x00000001U #define HP_APM_REGION0_R2_W_S 9 /** HP_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 0. + * Configures the read permission in region 0 in REE2 mode. */ #define HP_APM_REGION0_R2_R (BIT(10)) #define HP_APM_REGION0_R2_R_M (HP_APM_REGION0_R2_R_V << HP_APM_REGION0_R2_R_S) #define HP_APM_REGION0_R2_R_V 0x00000001U #define HP_APM_REGION0_R2_R_S 10 /** HP_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 0 configuration registers + * (HP_APM_REGION0_ADDR_START_REG, HP_APM_REGION0_ADDR_END_REG and + * HP_APM_REGION0_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION0_LOCK (BIT(11)) #define HP_APM_REGION0_LOCK_M (HP_APM_REGION0_LOCK_V << HP_APM_REGION0_LOCK_S) @@ -129,7 +133,7 @@ extern "C" { */ #define HP_APM_REGION1_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x10) /** HP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 1. + * Configures the start address of region 1. */ #define HP_APM_REGION1_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION1_ADDR_START_M (HP_APM_REGION1_ADDR_START_V << HP_APM_REGION1_ADDR_START_S) @@ -141,7 +145,7 @@ extern "C" { */ #define HP_APM_REGION1_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x14) /** HP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 1. + * Configures the end address of region 1. */ #define HP_APM_REGION1_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION1_ADDR_END_M (HP_APM_REGION1_ADDR_END_V << HP_APM_REGION1_ADDR_END_S) @@ -149,74 +153,78 @@ extern "C" { #define HP_APM_REGION1_ADDR_END_S 0 /** HP_APM_REGION1_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION1_ATTR_REG (DR_REG_HP_APM_BASE + 0x18) /** HP_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 1. + * Configures the execution permission in region 1 in REE0 mode. */ #define HP_APM_REGION1_R0_X (BIT(0)) #define HP_APM_REGION1_R0_X_M (HP_APM_REGION1_R0_X_V << HP_APM_REGION1_R0_X_S) #define HP_APM_REGION1_R0_X_V 0x00000001U #define HP_APM_REGION1_R0_X_S 0 /** HP_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 1. + * Configures the write permission in region 1 in REE0 mode. */ #define HP_APM_REGION1_R0_W (BIT(1)) #define HP_APM_REGION1_R0_W_M (HP_APM_REGION1_R0_W_V << HP_APM_REGION1_R0_W_S) #define HP_APM_REGION1_R0_W_V 0x00000001U #define HP_APM_REGION1_R0_W_S 1 /** HP_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 1. + * Configures the read permission in region 1 in REE0 mode. */ #define HP_APM_REGION1_R0_R (BIT(2)) #define HP_APM_REGION1_R0_R_M (HP_APM_REGION1_R0_R_V << HP_APM_REGION1_R0_R_S) #define HP_APM_REGION1_R0_R_V 0x00000001U #define HP_APM_REGION1_R0_R_S 2 /** HP_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 1. + * Configures the execution permission in region 1 in REE1 mode. */ #define HP_APM_REGION1_R1_X (BIT(4)) #define HP_APM_REGION1_R1_X_M (HP_APM_REGION1_R1_X_V << HP_APM_REGION1_R1_X_S) #define HP_APM_REGION1_R1_X_V 0x00000001U #define HP_APM_REGION1_R1_X_S 4 /** HP_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 1. + * Configures the write permission in region 1 in REE1 mode. */ #define HP_APM_REGION1_R1_W (BIT(5)) #define HP_APM_REGION1_R1_W_M (HP_APM_REGION1_R1_W_V << HP_APM_REGION1_R1_W_S) #define HP_APM_REGION1_R1_W_V 0x00000001U #define HP_APM_REGION1_R1_W_S 5 /** HP_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 1. + * Configures the read permission in region 1 in REE1 mode. */ #define HP_APM_REGION1_R1_R (BIT(6)) #define HP_APM_REGION1_R1_R_M (HP_APM_REGION1_R1_R_V << HP_APM_REGION1_R1_R_S) #define HP_APM_REGION1_R1_R_V 0x00000001U #define HP_APM_REGION1_R1_R_S 6 /** HP_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 1. + * Configures the execution permission in region 1 in REE2 mode. */ #define HP_APM_REGION1_R2_X (BIT(8)) #define HP_APM_REGION1_R2_X_M (HP_APM_REGION1_R2_X_V << HP_APM_REGION1_R2_X_S) #define HP_APM_REGION1_R2_X_V 0x00000001U #define HP_APM_REGION1_R2_X_S 8 /** HP_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 1. + * Configures the write permission in region 1 in REE2 mode. */ #define HP_APM_REGION1_R2_W (BIT(9)) #define HP_APM_REGION1_R2_W_M (HP_APM_REGION1_R2_W_V << HP_APM_REGION1_R2_W_S) #define HP_APM_REGION1_R2_W_V 0x00000001U #define HP_APM_REGION1_R2_W_S 9 /** HP_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 1. + * Configures the read permission in region 1 in REE2 mode. */ #define HP_APM_REGION1_R2_R (BIT(10)) #define HP_APM_REGION1_R2_R_M (HP_APM_REGION1_R2_R_V << HP_APM_REGION1_R2_R_S) #define HP_APM_REGION1_R2_R_V 0x00000001U #define HP_APM_REGION1_R2_R_S 10 /** HP_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 1 configuration registers + * (HP_APM_REGION1_ADDR_START_REG, HP_APM_REGION1_ADDR_END_REG and + * HP_APM_REGION1_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION1_LOCK (BIT(11)) #define HP_APM_REGION1_LOCK_M (HP_APM_REGION1_LOCK_V << HP_APM_REGION1_LOCK_S) @@ -228,7 +236,7 @@ extern "C" { */ #define HP_APM_REGION2_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x1c) /** HP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 2. + * Configures the start address of region 2. */ #define HP_APM_REGION2_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION2_ADDR_START_M (HP_APM_REGION2_ADDR_START_V << HP_APM_REGION2_ADDR_START_S) @@ -240,7 +248,7 @@ extern "C" { */ #define HP_APM_REGION2_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x20) /** HP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 2. + * Configures the end address of region 2. */ #define HP_APM_REGION2_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION2_ADDR_END_M (HP_APM_REGION2_ADDR_END_V << HP_APM_REGION2_ADDR_END_S) @@ -248,74 +256,78 @@ extern "C" { #define HP_APM_REGION2_ADDR_END_S 0 /** HP_APM_REGION2_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION2_ATTR_REG (DR_REG_HP_APM_BASE + 0x24) /** HP_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 2. + * Configures the execution permission in region 2 in REE0 mode. */ #define HP_APM_REGION2_R0_X (BIT(0)) #define HP_APM_REGION2_R0_X_M (HP_APM_REGION2_R0_X_V << HP_APM_REGION2_R0_X_S) #define HP_APM_REGION2_R0_X_V 0x00000001U #define HP_APM_REGION2_R0_X_S 0 /** HP_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 2. + * Configures the write permission in region 2 in REE0 mode. */ #define HP_APM_REGION2_R0_W (BIT(1)) #define HP_APM_REGION2_R0_W_M (HP_APM_REGION2_R0_W_V << HP_APM_REGION2_R0_W_S) #define HP_APM_REGION2_R0_W_V 0x00000001U #define HP_APM_REGION2_R0_W_S 1 /** HP_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 2. + * Configures the read permission in region 2 in REE0 mode. */ #define HP_APM_REGION2_R0_R (BIT(2)) #define HP_APM_REGION2_R0_R_M (HP_APM_REGION2_R0_R_V << HP_APM_REGION2_R0_R_S) #define HP_APM_REGION2_R0_R_V 0x00000001U #define HP_APM_REGION2_R0_R_S 2 /** HP_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 2. + * Configures the execution permission in region 2 in REE1 mode. */ #define HP_APM_REGION2_R1_X (BIT(4)) #define HP_APM_REGION2_R1_X_M (HP_APM_REGION2_R1_X_V << HP_APM_REGION2_R1_X_S) #define HP_APM_REGION2_R1_X_V 0x00000001U #define HP_APM_REGION2_R1_X_S 4 /** HP_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 2. + * Configures the write permission in region 2 in REE1 mode. */ #define HP_APM_REGION2_R1_W (BIT(5)) #define HP_APM_REGION2_R1_W_M (HP_APM_REGION2_R1_W_V << HP_APM_REGION2_R1_W_S) #define HP_APM_REGION2_R1_W_V 0x00000001U #define HP_APM_REGION2_R1_W_S 5 /** HP_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 2. + * Configures the read permission in region 2 in REE1 mode. */ #define HP_APM_REGION2_R1_R (BIT(6)) #define HP_APM_REGION2_R1_R_M (HP_APM_REGION2_R1_R_V << HP_APM_REGION2_R1_R_S) #define HP_APM_REGION2_R1_R_V 0x00000001U #define HP_APM_REGION2_R1_R_S 6 /** HP_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 2. + * Configures the execution permission in region 2 in REE2 mode. */ #define HP_APM_REGION2_R2_X (BIT(8)) #define HP_APM_REGION2_R2_X_M (HP_APM_REGION2_R2_X_V << HP_APM_REGION2_R2_X_S) #define HP_APM_REGION2_R2_X_V 0x00000001U #define HP_APM_REGION2_R2_X_S 8 /** HP_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 2. + * Configures the write permission in region 2 in REE2 mode. */ #define HP_APM_REGION2_R2_W (BIT(9)) #define HP_APM_REGION2_R2_W_M (HP_APM_REGION2_R2_W_V << HP_APM_REGION2_R2_W_S) #define HP_APM_REGION2_R2_W_V 0x00000001U #define HP_APM_REGION2_R2_W_S 9 /** HP_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 2. + * Configures the read permission in region 2 in REE2 mode. */ #define HP_APM_REGION2_R2_R (BIT(10)) #define HP_APM_REGION2_R2_R_M (HP_APM_REGION2_R2_R_V << HP_APM_REGION2_R2_R_S) #define HP_APM_REGION2_R2_R_V 0x00000001U #define HP_APM_REGION2_R2_R_S 10 /** HP_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 2 configuration registers + * (HP_APM_REGION2_ADDR_START_REG, HP_APM_REGION2_ADDR_END_REG and + * HP_APM_REGION2_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION2_LOCK (BIT(11)) #define HP_APM_REGION2_LOCK_M (HP_APM_REGION2_LOCK_V << HP_APM_REGION2_LOCK_S) @@ -327,7 +339,7 @@ extern "C" { */ #define HP_APM_REGION3_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x28) /** HP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 3. + * Configures the start address of region 3. */ #define HP_APM_REGION3_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION3_ADDR_START_M (HP_APM_REGION3_ADDR_START_V << HP_APM_REGION3_ADDR_START_S) @@ -339,7 +351,7 @@ extern "C" { */ #define HP_APM_REGION3_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x2c) /** HP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 3. + * Configures the end address of region 3. */ #define HP_APM_REGION3_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION3_ADDR_END_M (HP_APM_REGION3_ADDR_END_V << HP_APM_REGION3_ADDR_END_S) @@ -347,74 +359,78 @@ extern "C" { #define HP_APM_REGION3_ADDR_END_S 0 /** HP_APM_REGION3_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION3_ATTR_REG (DR_REG_HP_APM_BASE + 0x30) /** HP_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 3. + * Configures the execution permission in region 3 in REE0 mode. */ #define HP_APM_REGION3_R0_X (BIT(0)) #define HP_APM_REGION3_R0_X_M (HP_APM_REGION3_R0_X_V << HP_APM_REGION3_R0_X_S) #define HP_APM_REGION3_R0_X_V 0x00000001U #define HP_APM_REGION3_R0_X_S 0 /** HP_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 3. + * Configures the write permission in region 3 in REE0 mode. */ #define HP_APM_REGION3_R0_W (BIT(1)) #define HP_APM_REGION3_R0_W_M (HP_APM_REGION3_R0_W_V << HP_APM_REGION3_R0_W_S) #define HP_APM_REGION3_R0_W_V 0x00000001U #define HP_APM_REGION3_R0_W_S 1 /** HP_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 3. + * Configures the read permission in region 3 in REE0 mode. */ #define HP_APM_REGION3_R0_R (BIT(2)) #define HP_APM_REGION3_R0_R_M (HP_APM_REGION3_R0_R_V << HP_APM_REGION3_R0_R_S) #define HP_APM_REGION3_R0_R_V 0x00000001U #define HP_APM_REGION3_R0_R_S 2 /** HP_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 3. + * Configures the execution permission in region 3 in REE1 mode. */ #define HP_APM_REGION3_R1_X (BIT(4)) #define HP_APM_REGION3_R1_X_M (HP_APM_REGION3_R1_X_V << HP_APM_REGION3_R1_X_S) #define HP_APM_REGION3_R1_X_V 0x00000001U #define HP_APM_REGION3_R1_X_S 4 /** HP_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 3. + * Configures the write permission in region 3 in REE1 mode. */ #define HP_APM_REGION3_R1_W (BIT(5)) #define HP_APM_REGION3_R1_W_M (HP_APM_REGION3_R1_W_V << HP_APM_REGION3_R1_W_S) #define HP_APM_REGION3_R1_W_V 0x00000001U #define HP_APM_REGION3_R1_W_S 5 /** HP_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 3. + * Configures the read permission in region 3 in REE1 mode. */ #define HP_APM_REGION3_R1_R (BIT(6)) #define HP_APM_REGION3_R1_R_M (HP_APM_REGION3_R1_R_V << HP_APM_REGION3_R1_R_S) #define HP_APM_REGION3_R1_R_V 0x00000001U #define HP_APM_REGION3_R1_R_S 6 /** HP_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 3. + * Configures the execution permission in region 3 in REE2 mode. */ #define HP_APM_REGION3_R2_X (BIT(8)) #define HP_APM_REGION3_R2_X_M (HP_APM_REGION3_R2_X_V << HP_APM_REGION3_R2_X_S) #define HP_APM_REGION3_R2_X_V 0x00000001U #define HP_APM_REGION3_R2_X_S 8 /** HP_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 3. + * Configures the write permission in region 3 in REE2 mode. */ #define HP_APM_REGION3_R2_W (BIT(9)) #define HP_APM_REGION3_R2_W_M (HP_APM_REGION3_R2_W_V << HP_APM_REGION3_R2_W_S) #define HP_APM_REGION3_R2_W_V 0x00000001U #define HP_APM_REGION3_R2_W_S 9 /** HP_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 3. + * Configures the read permission in region 3 in REE2 mode. */ #define HP_APM_REGION3_R2_R (BIT(10)) #define HP_APM_REGION3_R2_R_M (HP_APM_REGION3_R2_R_V << HP_APM_REGION3_R2_R_S) #define HP_APM_REGION3_R2_R_V 0x00000001U #define HP_APM_REGION3_R2_R_S 10 /** HP_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 3 configuration registers + * (HP_APM_REGION3_ADDR_START_REG, HP_APM_REGION3_ADDR_END_REG and + * HP_APM_REGION3_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION3_LOCK (BIT(11)) #define HP_APM_REGION3_LOCK_M (HP_APM_REGION3_LOCK_V << HP_APM_REGION3_LOCK_S) @@ -426,7 +442,7 @@ extern "C" { */ #define HP_APM_REGION4_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x34) /** HP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 4. + * Configures the start address of region 4. */ #define HP_APM_REGION4_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION4_ADDR_START_M (HP_APM_REGION4_ADDR_START_V << HP_APM_REGION4_ADDR_START_S) @@ -438,7 +454,7 @@ extern "C" { */ #define HP_APM_REGION4_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x38) /** HP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 4. + * Configures the end address of region 4. */ #define HP_APM_REGION4_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION4_ADDR_END_M (HP_APM_REGION4_ADDR_END_V << HP_APM_REGION4_ADDR_END_S) @@ -446,74 +462,78 @@ extern "C" { #define HP_APM_REGION4_ADDR_END_S 0 /** HP_APM_REGION4_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION4_ATTR_REG (DR_REG_HP_APM_BASE + 0x3c) /** HP_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 4. + * Configures the execution permission in region 4 in REE0 mode. */ #define HP_APM_REGION4_R0_X (BIT(0)) #define HP_APM_REGION4_R0_X_M (HP_APM_REGION4_R0_X_V << HP_APM_REGION4_R0_X_S) #define HP_APM_REGION4_R0_X_V 0x00000001U #define HP_APM_REGION4_R0_X_S 0 /** HP_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 4. + * Configures the write permission in region 4 in REE0 mode. */ #define HP_APM_REGION4_R0_W (BIT(1)) #define HP_APM_REGION4_R0_W_M (HP_APM_REGION4_R0_W_V << HP_APM_REGION4_R0_W_S) #define HP_APM_REGION4_R0_W_V 0x00000001U #define HP_APM_REGION4_R0_W_S 1 /** HP_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 4. + * Configures the read permission in region 4 in REE0 mode. */ #define HP_APM_REGION4_R0_R (BIT(2)) #define HP_APM_REGION4_R0_R_M (HP_APM_REGION4_R0_R_V << HP_APM_REGION4_R0_R_S) #define HP_APM_REGION4_R0_R_V 0x00000001U #define HP_APM_REGION4_R0_R_S 2 /** HP_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 4. + * Configures the execution permission in region 4 in REE1 mode. */ #define HP_APM_REGION4_R1_X (BIT(4)) #define HP_APM_REGION4_R1_X_M (HP_APM_REGION4_R1_X_V << HP_APM_REGION4_R1_X_S) #define HP_APM_REGION4_R1_X_V 0x00000001U #define HP_APM_REGION4_R1_X_S 4 /** HP_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 4. + * Configures the write permission in region 4 in REE1 mode. */ #define HP_APM_REGION4_R1_W (BIT(5)) #define HP_APM_REGION4_R1_W_M (HP_APM_REGION4_R1_W_V << HP_APM_REGION4_R1_W_S) #define HP_APM_REGION4_R1_W_V 0x00000001U #define HP_APM_REGION4_R1_W_S 5 /** HP_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 4. + * Configures the read permission in region 4 in REE1 mode. */ #define HP_APM_REGION4_R1_R (BIT(6)) #define HP_APM_REGION4_R1_R_M (HP_APM_REGION4_R1_R_V << HP_APM_REGION4_R1_R_S) #define HP_APM_REGION4_R1_R_V 0x00000001U #define HP_APM_REGION4_R1_R_S 6 /** HP_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 4. + * Configures the execution permission in region 4 in REE2 mode. */ #define HP_APM_REGION4_R2_X (BIT(8)) #define HP_APM_REGION4_R2_X_M (HP_APM_REGION4_R2_X_V << HP_APM_REGION4_R2_X_S) #define HP_APM_REGION4_R2_X_V 0x00000001U #define HP_APM_REGION4_R2_X_S 8 /** HP_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 4. + * Configures the write permission in region 4 in REE2 mode. */ #define HP_APM_REGION4_R2_W (BIT(9)) #define HP_APM_REGION4_R2_W_M (HP_APM_REGION4_R2_W_V << HP_APM_REGION4_R2_W_S) #define HP_APM_REGION4_R2_W_V 0x00000001U #define HP_APM_REGION4_R2_W_S 9 /** HP_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 4. + * Configures the read permission in region 4 in REE2 mode. */ #define HP_APM_REGION4_R2_R (BIT(10)) #define HP_APM_REGION4_R2_R_M (HP_APM_REGION4_R2_R_V << HP_APM_REGION4_R2_R_S) #define HP_APM_REGION4_R2_R_V 0x00000001U #define HP_APM_REGION4_R2_R_S 10 /** HP_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 4 configuration registers + * (HP_APM_REGION4_ADDR_START_REG, HP_APM_REGION4_ADDR_END_REG and + * HP_APM_REGION4_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION4_LOCK (BIT(11)) #define HP_APM_REGION4_LOCK_M (HP_APM_REGION4_LOCK_V << HP_APM_REGION4_LOCK_S) @@ -525,7 +545,7 @@ extern "C" { */ #define HP_APM_REGION5_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x40) /** HP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 5. + * Configures the start address of region 5. */ #define HP_APM_REGION5_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION5_ADDR_START_M (HP_APM_REGION5_ADDR_START_V << HP_APM_REGION5_ADDR_START_S) @@ -537,7 +557,7 @@ extern "C" { */ #define HP_APM_REGION5_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x44) /** HP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 5. + * Configures the end address of region 5. */ #define HP_APM_REGION5_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION5_ADDR_END_M (HP_APM_REGION5_ADDR_END_V << HP_APM_REGION5_ADDR_END_S) @@ -545,74 +565,78 @@ extern "C" { #define HP_APM_REGION5_ADDR_END_S 0 /** HP_APM_REGION5_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION5_ATTR_REG (DR_REG_HP_APM_BASE + 0x48) /** HP_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 5. + * Configures the execution permission in region 5 in REE0 mode. */ #define HP_APM_REGION5_R0_X (BIT(0)) #define HP_APM_REGION5_R0_X_M (HP_APM_REGION5_R0_X_V << HP_APM_REGION5_R0_X_S) #define HP_APM_REGION5_R0_X_V 0x00000001U #define HP_APM_REGION5_R0_X_S 0 /** HP_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 5. + * Configures the write permission in region 5 in REE0 mode. */ #define HP_APM_REGION5_R0_W (BIT(1)) #define HP_APM_REGION5_R0_W_M (HP_APM_REGION5_R0_W_V << HP_APM_REGION5_R0_W_S) #define HP_APM_REGION5_R0_W_V 0x00000001U #define HP_APM_REGION5_R0_W_S 1 /** HP_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 5. + * Configures the read permission in region 5 in REE0 mode. */ #define HP_APM_REGION5_R0_R (BIT(2)) #define HP_APM_REGION5_R0_R_M (HP_APM_REGION5_R0_R_V << HP_APM_REGION5_R0_R_S) #define HP_APM_REGION5_R0_R_V 0x00000001U #define HP_APM_REGION5_R0_R_S 2 /** HP_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 5. + * Configures the execution permission in region 5 in REE1 mode. */ #define HP_APM_REGION5_R1_X (BIT(4)) #define HP_APM_REGION5_R1_X_M (HP_APM_REGION5_R1_X_V << HP_APM_REGION5_R1_X_S) #define HP_APM_REGION5_R1_X_V 0x00000001U #define HP_APM_REGION5_R1_X_S 4 /** HP_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 5. + * Configures the write permission in region 5 in REE1 mode. */ #define HP_APM_REGION5_R1_W (BIT(5)) #define HP_APM_REGION5_R1_W_M (HP_APM_REGION5_R1_W_V << HP_APM_REGION5_R1_W_S) #define HP_APM_REGION5_R1_W_V 0x00000001U #define HP_APM_REGION5_R1_W_S 5 /** HP_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 5. + * Configures the read permission in region 5 in REE1 mode. */ #define HP_APM_REGION5_R1_R (BIT(6)) #define HP_APM_REGION5_R1_R_M (HP_APM_REGION5_R1_R_V << HP_APM_REGION5_R1_R_S) #define HP_APM_REGION5_R1_R_V 0x00000001U #define HP_APM_REGION5_R1_R_S 6 /** HP_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 5. + * Configures the execution permission in region 5 in REE2 mode. */ #define HP_APM_REGION5_R2_X (BIT(8)) #define HP_APM_REGION5_R2_X_M (HP_APM_REGION5_R2_X_V << HP_APM_REGION5_R2_X_S) #define HP_APM_REGION5_R2_X_V 0x00000001U #define HP_APM_REGION5_R2_X_S 8 /** HP_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 5. + * Configures the write permission in region 5 in REE2 mode. */ #define HP_APM_REGION5_R2_W (BIT(9)) #define HP_APM_REGION5_R2_W_M (HP_APM_REGION5_R2_W_V << HP_APM_REGION5_R2_W_S) #define HP_APM_REGION5_R2_W_V 0x00000001U #define HP_APM_REGION5_R2_W_S 9 /** HP_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 5. + * Configures the read permission in region 5 in REE2 mode. */ #define HP_APM_REGION5_R2_R (BIT(10)) #define HP_APM_REGION5_R2_R_M (HP_APM_REGION5_R2_R_V << HP_APM_REGION5_R2_R_S) #define HP_APM_REGION5_R2_R_V 0x00000001U #define HP_APM_REGION5_R2_R_S 10 /** HP_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 5 configuration registers + * (HP_APM_REGION5_ADDR_START_REG, HP_APM_REGION5_ADDR_END_REG and + * HP_APM_REGION5_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION5_LOCK (BIT(11)) #define HP_APM_REGION5_LOCK_M (HP_APM_REGION5_LOCK_V << HP_APM_REGION5_LOCK_S) @@ -624,7 +648,7 @@ extern "C" { */ #define HP_APM_REGION6_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4c) /** HP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 6. + * Configures the start address of region 6. */ #define HP_APM_REGION6_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION6_ADDR_START_M (HP_APM_REGION6_ADDR_START_V << HP_APM_REGION6_ADDR_START_S) @@ -636,7 +660,7 @@ extern "C" { */ #define HP_APM_REGION6_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x50) /** HP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 6. + * Configures the end address of region 6. */ #define HP_APM_REGION6_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION6_ADDR_END_M (HP_APM_REGION6_ADDR_END_V << HP_APM_REGION6_ADDR_END_S) @@ -644,74 +668,78 @@ extern "C" { #define HP_APM_REGION6_ADDR_END_S 0 /** HP_APM_REGION6_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION6_ATTR_REG (DR_REG_HP_APM_BASE + 0x54) /** HP_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 6. + * Configures the execution permission in region 6 in REE0 mode. */ #define HP_APM_REGION6_R0_X (BIT(0)) #define HP_APM_REGION6_R0_X_M (HP_APM_REGION6_R0_X_V << HP_APM_REGION6_R0_X_S) #define HP_APM_REGION6_R0_X_V 0x00000001U #define HP_APM_REGION6_R0_X_S 0 /** HP_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 6. + * Configures the write permission in region 6 in REE0 mode. */ #define HP_APM_REGION6_R0_W (BIT(1)) #define HP_APM_REGION6_R0_W_M (HP_APM_REGION6_R0_W_V << HP_APM_REGION6_R0_W_S) #define HP_APM_REGION6_R0_W_V 0x00000001U #define HP_APM_REGION6_R0_W_S 1 /** HP_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 6. + * Configures the read permission in region 6 in REE0 mode. */ #define HP_APM_REGION6_R0_R (BIT(2)) #define HP_APM_REGION6_R0_R_M (HP_APM_REGION6_R0_R_V << HP_APM_REGION6_R0_R_S) #define HP_APM_REGION6_R0_R_V 0x00000001U #define HP_APM_REGION6_R0_R_S 2 /** HP_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 6. + * Configures the execution permission in region 6 in REE1 mode. */ #define HP_APM_REGION6_R1_X (BIT(4)) #define HP_APM_REGION6_R1_X_M (HP_APM_REGION6_R1_X_V << HP_APM_REGION6_R1_X_S) #define HP_APM_REGION6_R1_X_V 0x00000001U #define HP_APM_REGION6_R1_X_S 4 /** HP_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 6. + * Configures the write permission in region 6 in REE1 mode. */ #define HP_APM_REGION6_R1_W (BIT(5)) #define HP_APM_REGION6_R1_W_M (HP_APM_REGION6_R1_W_V << HP_APM_REGION6_R1_W_S) #define HP_APM_REGION6_R1_W_V 0x00000001U #define HP_APM_REGION6_R1_W_S 5 /** HP_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 6. + * Configures the read permission in region 6 in REE1 mode. */ #define HP_APM_REGION6_R1_R (BIT(6)) #define HP_APM_REGION6_R1_R_M (HP_APM_REGION6_R1_R_V << HP_APM_REGION6_R1_R_S) #define HP_APM_REGION6_R1_R_V 0x00000001U #define HP_APM_REGION6_R1_R_S 6 /** HP_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 6. + * Configures the execution permission in region 6 in REE2 mode. */ #define HP_APM_REGION6_R2_X (BIT(8)) #define HP_APM_REGION6_R2_X_M (HP_APM_REGION6_R2_X_V << HP_APM_REGION6_R2_X_S) #define HP_APM_REGION6_R2_X_V 0x00000001U #define HP_APM_REGION6_R2_X_S 8 /** HP_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 6. + * Configures the write permission in region 6 in REE2 mode. */ #define HP_APM_REGION6_R2_W (BIT(9)) #define HP_APM_REGION6_R2_W_M (HP_APM_REGION6_R2_W_V << HP_APM_REGION6_R2_W_S) #define HP_APM_REGION6_R2_W_V 0x00000001U #define HP_APM_REGION6_R2_W_S 9 /** HP_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 6. + * Configures the read permission in region 6 in REE2 mode. */ #define HP_APM_REGION6_R2_R (BIT(10)) #define HP_APM_REGION6_R2_R_M (HP_APM_REGION6_R2_R_V << HP_APM_REGION6_R2_R_S) #define HP_APM_REGION6_R2_R_V 0x00000001U #define HP_APM_REGION6_R2_R_S 10 /** HP_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 6 configuration registers + * (HP_APM_REGION6_ADDR_START_REG, HP_APM_REGION6_ADDR_END_REG and + * HP_APM_REGION6_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION6_LOCK (BIT(11)) #define HP_APM_REGION6_LOCK_M (HP_APM_REGION6_LOCK_V << HP_APM_REGION6_LOCK_S) @@ -723,7 +751,7 @@ extern "C" { */ #define HP_APM_REGION7_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x58) /** HP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 7. + * Configures the start address of region 7. */ #define HP_APM_REGION7_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION7_ADDR_START_M (HP_APM_REGION7_ADDR_START_V << HP_APM_REGION7_ADDR_START_S) @@ -735,7 +763,7 @@ extern "C" { */ #define HP_APM_REGION7_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x5c) /** HP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 7. + * Configures the end address of region 7. */ #define HP_APM_REGION7_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION7_ADDR_END_M (HP_APM_REGION7_ADDR_END_V << HP_APM_REGION7_ADDR_END_S) @@ -743,74 +771,78 @@ extern "C" { #define HP_APM_REGION7_ADDR_END_S 0 /** HP_APM_REGION7_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION7_ATTR_REG (DR_REG_HP_APM_BASE + 0x60) /** HP_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 7. + * Configures the execution permission in region 7 in REE0 mode. */ #define HP_APM_REGION7_R0_X (BIT(0)) #define HP_APM_REGION7_R0_X_M (HP_APM_REGION7_R0_X_V << HP_APM_REGION7_R0_X_S) #define HP_APM_REGION7_R0_X_V 0x00000001U #define HP_APM_REGION7_R0_X_S 0 /** HP_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 7. + * Configures the write permission in region 7 in REE0 mode. */ #define HP_APM_REGION7_R0_W (BIT(1)) #define HP_APM_REGION7_R0_W_M (HP_APM_REGION7_R0_W_V << HP_APM_REGION7_R0_W_S) #define HP_APM_REGION7_R0_W_V 0x00000001U #define HP_APM_REGION7_R0_W_S 1 /** HP_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 7. + * Configures the read permission in region 7 in REE0 mode. */ #define HP_APM_REGION7_R0_R (BIT(2)) #define HP_APM_REGION7_R0_R_M (HP_APM_REGION7_R0_R_V << HP_APM_REGION7_R0_R_S) #define HP_APM_REGION7_R0_R_V 0x00000001U #define HP_APM_REGION7_R0_R_S 2 /** HP_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 7. + * Configures the execution permission in region 7 in REE1 mode. */ #define HP_APM_REGION7_R1_X (BIT(4)) #define HP_APM_REGION7_R1_X_M (HP_APM_REGION7_R1_X_V << HP_APM_REGION7_R1_X_S) #define HP_APM_REGION7_R1_X_V 0x00000001U #define HP_APM_REGION7_R1_X_S 4 /** HP_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 7. + * Configures the write permission in region 7 in REE1 mode. */ #define HP_APM_REGION7_R1_W (BIT(5)) #define HP_APM_REGION7_R1_W_M (HP_APM_REGION7_R1_W_V << HP_APM_REGION7_R1_W_S) #define HP_APM_REGION7_R1_W_V 0x00000001U #define HP_APM_REGION7_R1_W_S 5 /** HP_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 7. + * Configures the read permission in region 7 in REE1 mode. */ #define HP_APM_REGION7_R1_R (BIT(6)) #define HP_APM_REGION7_R1_R_M (HP_APM_REGION7_R1_R_V << HP_APM_REGION7_R1_R_S) #define HP_APM_REGION7_R1_R_V 0x00000001U #define HP_APM_REGION7_R1_R_S 6 /** HP_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 7. + * Configures the execution permission in region 7 in REE2 mode. */ #define HP_APM_REGION7_R2_X (BIT(8)) #define HP_APM_REGION7_R2_X_M (HP_APM_REGION7_R2_X_V << HP_APM_REGION7_R2_X_S) #define HP_APM_REGION7_R2_X_V 0x00000001U #define HP_APM_REGION7_R2_X_S 8 /** HP_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 7. + * Configures the write permission in region 7 in REE2 mode. */ #define HP_APM_REGION7_R2_W (BIT(9)) #define HP_APM_REGION7_R2_W_M (HP_APM_REGION7_R2_W_V << HP_APM_REGION7_R2_W_S) #define HP_APM_REGION7_R2_W_V 0x00000001U #define HP_APM_REGION7_R2_W_S 9 /** HP_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 7. + * Configures the read permission in region 7 in REE2 mode. */ #define HP_APM_REGION7_R2_R (BIT(10)) #define HP_APM_REGION7_R2_R_M (HP_APM_REGION7_R2_R_V << HP_APM_REGION7_R2_R_S) #define HP_APM_REGION7_R2_R_V 0x00000001U #define HP_APM_REGION7_R2_R_S 10 /** HP_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 7 configuration registers + * (HP_APM_REGION7_ADDR_START_REG, HP_APM_REGION7_ADDR_END_REG and + * HP_APM_REGION7_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION7_LOCK (BIT(11)) #define HP_APM_REGION7_LOCK_M (HP_APM_REGION7_LOCK_V << HP_APM_REGION7_LOCK_S) @@ -822,7 +854,7 @@ extern "C" { */ #define HP_APM_REGION8_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x64) /** HP_APM_REGION8_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 8. + * Configures the start address of region 8. */ #define HP_APM_REGION8_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION8_ADDR_START_M (HP_APM_REGION8_ADDR_START_V << HP_APM_REGION8_ADDR_START_S) @@ -834,7 +866,7 @@ extern "C" { */ #define HP_APM_REGION8_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x68) /** HP_APM_REGION8_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 8. + * Configures the end address of region 8. */ #define HP_APM_REGION8_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION8_ADDR_END_M (HP_APM_REGION8_ADDR_END_V << HP_APM_REGION8_ADDR_END_S) @@ -842,74 +874,78 @@ extern "C" { #define HP_APM_REGION8_ADDR_END_S 0 /** HP_APM_REGION8_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION8_ATTR_REG (DR_REG_HP_APM_BASE + 0x6c) /** HP_APM_REGION8_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 8. + * Configures the execution permission in region 8 in REE0 mode. */ #define HP_APM_REGION8_R0_X (BIT(0)) #define HP_APM_REGION8_R0_X_M (HP_APM_REGION8_R0_X_V << HP_APM_REGION8_R0_X_S) #define HP_APM_REGION8_R0_X_V 0x00000001U #define HP_APM_REGION8_R0_X_S 0 /** HP_APM_REGION8_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 8. + * Configures the write permission in region 8 in REE0 mode. */ #define HP_APM_REGION8_R0_W (BIT(1)) #define HP_APM_REGION8_R0_W_M (HP_APM_REGION8_R0_W_V << HP_APM_REGION8_R0_W_S) #define HP_APM_REGION8_R0_W_V 0x00000001U #define HP_APM_REGION8_R0_W_S 1 /** HP_APM_REGION8_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 8. + * Configures the read permission in region 8 in REE0 mode. */ #define HP_APM_REGION8_R0_R (BIT(2)) #define HP_APM_REGION8_R0_R_M (HP_APM_REGION8_R0_R_V << HP_APM_REGION8_R0_R_S) #define HP_APM_REGION8_R0_R_V 0x00000001U #define HP_APM_REGION8_R0_R_S 2 /** HP_APM_REGION8_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 8. + * Configures the execution permission in region 8 in REE1 mode. */ #define HP_APM_REGION8_R1_X (BIT(4)) #define HP_APM_REGION8_R1_X_M (HP_APM_REGION8_R1_X_V << HP_APM_REGION8_R1_X_S) #define HP_APM_REGION8_R1_X_V 0x00000001U #define HP_APM_REGION8_R1_X_S 4 /** HP_APM_REGION8_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 8. + * Configures the write permission in region 8 in REE1 mode. */ #define HP_APM_REGION8_R1_W (BIT(5)) #define HP_APM_REGION8_R1_W_M (HP_APM_REGION8_R1_W_V << HP_APM_REGION8_R1_W_S) #define HP_APM_REGION8_R1_W_V 0x00000001U #define HP_APM_REGION8_R1_W_S 5 /** HP_APM_REGION8_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 8. + * Configures the read permission in region 8 in REE1 mode. */ #define HP_APM_REGION8_R1_R (BIT(6)) #define HP_APM_REGION8_R1_R_M (HP_APM_REGION8_R1_R_V << HP_APM_REGION8_R1_R_S) #define HP_APM_REGION8_R1_R_V 0x00000001U #define HP_APM_REGION8_R1_R_S 6 /** HP_APM_REGION8_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 8. + * Configures the execution permission in region 8 in REE2 mode. */ #define HP_APM_REGION8_R2_X (BIT(8)) #define HP_APM_REGION8_R2_X_M (HP_APM_REGION8_R2_X_V << HP_APM_REGION8_R2_X_S) #define HP_APM_REGION8_R2_X_V 0x00000001U #define HP_APM_REGION8_R2_X_S 8 /** HP_APM_REGION8_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 8. + * Configures the write permission in region 8 in REE2 mode. */ #define HP_APM_REGION8_R2_W (BIT(9)) #define HP_APM_REGION8_R2_W_M (HP_APM_REGION8_R2_W_V << HP_APM_REGION8_R2_W_S) #define HP_APM_REGION8_R2_W_V 0x00000001U #define HP_APM_REGION8_R2_W_S 9 /** HP_APM_REGION8_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 8. + * Configures the read permission in region 8 in REE2 mode. */ #define HP_APM_REGION8_R2_R (BIT(10)) #define HP_APM_REGION8_R2_R_M (HP_APM_REGION8_R2_R_V << HP_APM_REGION8_R2_R_S) #define HP_APM_REGION8_R2_R_V 0x00000001U #define HP_APM_REGION8_R2_R_S 10 /** HP_APM_REGION8_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 8 configuration registers + * (HP_APM_REGION8_ADDR_START_REG, HP_APM_REGION8_ADDR_END_REG and + * HP_APM_REGION8_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION8_LOCK (BIT(11)) #define HP_APM_REGION8_LOCK_M (HP_APM_REGION8_LOCK_V << HP_APM_REGION8_LOCK_S) @@ -921,7 +957,7 @@ extern "C" { */ #define HP_APM_REGION9_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x70) /** HP_APM_REGION9_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 9. + * Configures the start address of region 9. */ #define HP_APM_REGION9_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION9_ADDR_START_M (HP_APM_REGION9_ADDR_START_V << HP_APM_REGION9_ADDR_START_S) @@ -933,7 +969,7 @@ extern "C" { */ #define HP_APM_REGION9_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x74) /** HP_APM_REGION9_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 9. + * Configures the end address of region 9. */ #define HP_APM_REGION9_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION9_ADDR_END_M (HP_APM_REGION9_ADDR_END_V << HP_APM_REGION9_ADDR_END_S) @@ -941,74 +977,78 @@ extern "C" { #define HP_APM_REGION9_ADDR_END_S 0 /** HP_APM_REGION9_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION9_ATTR_REG (DR_REG_HP_APM_BASE + 0x78) /** HP_APM_REGION9_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 9. + * Configures the execution permission in region 9 in REE0 mode. */ #define HP_APM_REGION9_R0_X (BIT(0)) #define HP_APM_REGION9_R0_X_M (HP_APM_REGION9_R0_X_V << HP_APM_REGION9_R0_X_S) #define HP_APM_REGION9_R0_X_V 0x00000001U #define HP_APM_REGION9_R0_X_S 0 /** HP_APM_REGION9_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 9. + * Configures the write permission in region 9 in REE0 mode. */ #define HP_APM_REGION9_R0_W (BIT(1)) #define HP_APM_REGION9_R0_W_M (HP_APM_REGION9_R0_W_V << HP_APM_REGION9_R0_W_S) #define HP_APM_REGION9_R0_W_V 0x00000001U #define HP_APM_REGION9_R0_W_S 1 /** HP_APM_REGION9_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 9. + * Configures the read permission in region 9 in REE0 mode. */ #define HP_APM_REGION9_R0_R (BIT(2)) #define HP_APM_REGION9_R0_R_M (HP_APM_REGION9_R0_R_V << HP_APM_REGION9_R0_R_S) #define HP_APM_REGION9_R0_R_V 0x00000001U #define HP_APM_REGION9_R0_R_S 2 /** HP_APM_REGION9_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 9. + * Configures the execution permission in region 9 in REE1 mode. */ #define HP_APM_REGION9_R1_X (BIT(4)) #define HP_APM_REGION9_R1_X_M (HP_APM_REGION9_R1_X_V << HP_APM_REGION9_R1_X_S) #define HP_APM_REGION9_R1_X_V 0x00000001U #define HP_APM_REGION9_R1_X_S 4 /** HP_APM_REGION9_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 9. + * Configures the write permission in region 9 in REE1 mode. */ #define HP_APM_REGION9_R1_W (BIT(5)) #define HP_APM_REGION9_R1_W_M (HP_APM_REGION9_R1_W_V << HP_APM_REGION9_R1_W_S) #define HP_APM_REGION9_R1_W_V 0x00000001U #define HP_APM_REGION9_R1_W_S 5 /** HP_APM_REGION9_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 9. + * Configures the read permission in region 9 in REE1 mode. */ #define HP_APM_REGION9_R1_R (BIT(6)) #define HP_APM_REGION9_R1_R_M (HP_APM_REGION9_R1_R_V << HP_APM_REGION9_R1_R_S) #define HP_APM_REGION9_R1_R_V 0x00000001U #define HP_APM_REGION9_R1_R_S 6 /** HP_APM_REGION9_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 9. + * Configures the execution permission in region 9 in REE2 mode. */ #define HP_APM_REGION9_R2_X (BIT(8)) #define HP_APM_REGION9_R2_X_M (HP_APM_REGION9_R2_X_V << HP_APM_REGION9_R2_X_S) #define HP_APM_REGION9_R2_X_V 0x00000001U #define HP_APM_REGION9_R2_X_S 8 /** HP_APM_REGION9_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 9. + * Configures the write permission in region 9 in REE2 mode. */ #define HP_APM_REGION9_R2_W (BIT(9)) #define HP_APM_REGION9_R2_W_M (HP_APM_REGION9_R2_W_V << HP_APM_REGION9_R2_W_S) #define HP_APM_REGION9_R2_W_V 0x00000001U #define HP_APM_REGION9_R2_W_S 9 /** HP_APM_REGION9_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 9. + * Configures the read permission in region 9 in REE2 mode. */ #define HP_APM_REGION9_R2_R (BIT(10)) #define HP_APM_REGION9_R2_R_M (HP_APM_REGION9_R2_R_V << HP_APM_REGION9_R2_R_S) #define HP_APM_REGION9_R2_R_V 0x00000001U #define HP_APM_REGION9_R2_R_S 10 /** HP_APM_REGION9_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 9 configuration registers + * (HP_APM_REGION9_ADDR_START_REG, HP_APM_REGION9_ADDR_END_REG and + * HP_APM_REGION9_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION9_LOCK (BIT(11)) #define HP_APM_REGION9_LOCK_M (HP_APM_REGION9_LOCK_V << HP_APM_REGION9_LOCK_S) @@ -1020,7 +1060,7 @@ extern "C" { */ #define HP_APM_REGION10_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x7c) /** HP_APM_REGION10_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 10. + * Configures the start address of region 10. */ #define HP_APM_REGION10_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION10_ADDR_START_M (HP_APM_REGION10_ADDR_START_V << HP_APM_REGION10_ADDR_START_S) @@ -1032,7 +1072,7 @@ extern "C" { */ #define HP_APM_REGION10_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x80) /** HP_APM_REGION10_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 10. + * Configures the end address of region 10. */ #define HP_APM_REGION10_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION10_ADDR_END_M (HP_APM_REGION10_ADDR_END_V << HP_APM_REGION10_ADDR_END_S) @@ -1040,74 +1080,78 @@ extern "C" { #define HP_APM_REGION10_ADDR_END_S 0 /** HP_APM_REGION10_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION10_ATTR_REG (DR_REG_HP_APM_BASE + 0x84) /** HP_APM_REGION10_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 10. + * Configures the execution permission in region 10 in REE0 mode. */ #define HP_APM_REGION10_R0_X (BIT(0)) #define HP_APM_REGION10_R0_X_M (HP_APM_REGION10_R0_X_V << HP_APM_REGION10_R0_X_S) #define HP_APM_REGION10_R0_X_V 0x00000001U #define HP_APM_REGION10_R0_X_S 0 /** HP_APM_REGION10_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 10. + * Configures the write permission in region 10 in REE0 mode. */ #define HP_APM_REGION10_R0_W (BIT(1)) #define HP_APM_REGION10_R0_W_M (HP_APM_REGION10_R0_W_V << HP_APM_REGION10_R0_W_S) #define HP_APM_REGION10_R0_W_V 0x00000001U #define HP_APM_REGION10_R0_W_S 1 /** HP_APM_REGION10_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 10. + * Configures the read permission in region 10 in REE0 mode. */ #define HP_APM_REGION10_R0_R (BIT(2)) #define HP_APM_REGION10_R0_R_M (HP_APM_REGION10_R0_R_V << HP_APM_REGION10_R0_R_S) #define HP_APM_REGION10_R0_R_V 0x00000001U #define HP_APM_REGION10_R0_R_S 2 /** HP_APM_REGION10_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 10. + * Configures the execution permission in region 10 in REE1 mode. */ #define HP_APM_REGION10_R1_X (BIT(4)) #define HP_APM_REGION10_R1_X_M (HP_APM_REGION10_R1_X_V << HP_APM_REGION10_R1_X_S) #define HP_APM_REGION10_R1_X_V 0x00000001U #define HP_APM_REGION10_R1_X_S 4 /** HP_APM_REGION10_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 10. + * Configures the write permission in region 10 in REE1 mode. */ #define HP_APM_REGION10_R1_W (BIT(5)) #define HP_APM_REGION10_R1_W_M (HP_APM_REGION10_R1_W_V << HP_APM_REGION10_R1_W_S) #define HP_APM_REGION10_R1_W_V 0x00000001U #define HP_APM_REGION10_R1_W_S 5 /** HP_APM_REGION10_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 10. + * Configures the read permission in region 10 in REE1 mode. */ #define HP_APM_REGION10_R1_R (BIT(6)) #define HP_APM_REGION10_R1_R_M (HP_APM_REGION10_R1_R_V << HP_APM_REGION10_R1_R_S) #define HP_APM_REGION10_R1_R_V 0x00000001U #define HP_APM_REGION10_R1_R_S 6 /** HP_APM_REGION10_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 10. + * Configures the execution permission in region 10 in REE2 mode. */ #define HP_APM_REGION10_R2_X (BIT(8)) #define HP_APM_REGION10_R2_X_M (HP_APM_REGION10_R2_X_V << HP_APM_REGION10_R2_X_S) #define HP_APM_REGION10_R2_X_V 0x00000001U #define HP_APM_REGION10_R2_X_S 8 /** HP_APM_REGION10_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 10. + * Configures the write permission in region 10 in REE2 mode. */ #define HP_APM_REGION10_R2_W (BIT(9)) #define HP_APM_REGION10_R2_W_M (HP_APM_REGION10_R2_W_V << HP_APM_REGION10_R2_W_S) #define HP_APM_REGION10_R2_W_V 0x00000001U #define HP_APM_REGION10_R2_W_S 9 /** HP_APM_REGION10_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 10. + * Configures the read permission in region 10 in REE2 mode. */ #define HP_APM_REGION10_R2_R (BIT(10)) #define HP_APM_REGION10_R2_R_M (HP_APM_REGION10_R2_R_V << HP_APM_REGION10_R2_R_S) #define HP_APM_REGION10_R2_R_V 0x00000001U #define HP_APM_REGION10_R2_R_S 10 /** HP_APM_REGION10_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 10 configuration registers + * (HP_APM_REGION10_ADDR_START_REG, HP_APM_REGION10_ADDR_END_REG and + * HP_APM_REGION10_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION10_LOCK (BIT(11)) #define HP_APM_REGION10_LOCK_M (HP_APM_REGION10_LOCK_V << HP_APM_REGION10_LOCK_S) @@ -1119,7 +1163,7 @@ extern "C" { */ #define HP_APM_REGION11_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x88) /** HP_APM_REGION11_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 11. + * Configures the start address of region 11. */ #define HP_APM_REGION11_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION11_ADDR_START_M (HP_APM_REGION11_ADDR_START_V << HP_APM_REGION11_ADDR_START_S) @@ -1131,7 +1175,7 @@ extern "C" { */ #define HP_APM_REGION11_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8c) /** HP_APM_REGION11_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 11. + * Configures the end address of region 11. */ #define HP_APM_REGION11_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION11_ADDR_END_M (HP_APM_REGION11_ADDR_END_V << HP_APM_REGION11_ADDR_END_S) @@ -1139,74 +1183,78 @@ extern "C" { #define HP_APM_REGION11_ADDR_END_S 0 /** HP_APM_REGION11_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION11_ATTR_REG (DR_REG_HP_APM_BASE + 0x90) /** HP_APM_REGION11_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 11. + * Configures the execution permission in region 11 in REE0 mode. */ #define HP_APM_REGION11_R0_X (BIT(0)) #define HP_APM_REGION11_R0_X_M (HP_APM_REGION11_R0_X_V << HP_APM_REGION11_R0_X_S) #define HP_APM_REGION11_R0_X_V 0x00000001U #define HP_APM_REGION11_R0_X_S 0 /** HP_APM_REGION11_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 11. + * Configures the write permission in region 11 in REE0 mode. */ #define HP_APM_REGION11_R0_W (BIT(1)) #define HP_APM_REGION11_R0_W_M (HP_APM_REGION11_R0_W_V << HP_APM_REGION11_R0_W_S) #define HP_APM_REGION11_R0_W_V 0x00000001U #define HP_APM_REGION11_R0_W_S 1 /** HP_APM_REGION11_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 11. + * Configures the read permission in region 11 in REE0 mode. */ #define HP_APM_REGION11_R0_R (BIT(2)) #define HP_APM_REGION11_R0_R_M (HP_APM_REGION11_R0_R_V << HP_APM_REGION11_R0_R_S) #define HP_APM_REGION11_R0_R_V 0x00000001U #define HP_APM_REGION11_R0_R_S 2 /** HP_APM_REGION11_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 11. + * Configures the execution permission in region 11 in REE1 mode. */ #define HP_APM_REGION11_R1_X (BIT(4)) #define HP_APM_REGION11_R1_X_M (HP_APM_REGION11_R1_X_V << HP_APM_REGION11_R1_X_S) #define HP_APM_REGION11_R1_X_V 0x00000001U #define HP_APM_REGION11_R1_X_S 4 /** HP_APM_REGION11_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 11. + * Configures the write permission in region 11 in REE1 mode. */ #define HP_APM_REGION11_R1_W (BIT(5)) #define HP_APM_REGION11_R1_W_M (HP_APM_REGION11_R1_W_V << HP_APM_REGION11_R1_W_S) #define HP_APM_REGION11_R1_W_V 0x00000001U #define HP_APM_REGION11_R1_W_S 5 /** HP_APM_REGION11_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 11. + * Configures the read permission in region 11 in REE1 mode. */ #define HP_APM_REGION11_R1_R (BIT(6)) #define HP_APM_REGION11_R1_R_M (HP_APM_REGION11_R1_R_V << HP_APM_REGION11_R1_R_S) #define HP_APM_REGION11_R1_R_V 0x00000001U #define HP_APM_REGION11_R1_R_S 6 /** HP_APM_REGION11_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 11. + * Configures the execution permission in region 11 in REE2 mode. */ #define HP_APM_REGION11_R2_X (BIT(8)) #define HP_APM_REGION11_R2_X_M (HP_APM_REGION11_R2_X_V << HP_APM_REGION11_R2_X_S) #define HP_APM_REGION11_R2_X_V 0x00000001U #define HP_APM_REGION11_R2_X_S 8 /** HP_APM_REGION11_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 11. + * Configures the write permission in region 11 in REE2 mode. */ #define HP_APM_REGION11_R2_W (BIT(9)) #define HP_APM_REGION11_R2_W_M (HP_APM_REGION11_R2_W_V << HP_APM_REGION11_R2_W_S) #define HP_APM_REGION11_R2_W_V 0x00000001U #define HP_APM_REGION11_R2_W_S 9 /** HP_APM_REGION11_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 11. + * Configures the read permission in region 11 in REE2 mode. */ #define HP_APM_REGION11_R2_R (BIT(10)) #define HP_APM_REGION11_R2_R_M (HP_APM_REGION11_R2_R_V << HP_APM_REGION11_R2_R_S) #define HP_APM_REGION11_R2_R_V 0x00000001U #define HP_APM_REGION11_R2_R_S 10 /** HP_APM_REGION11_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 11 configuration registers + * (HP_APM_REGION11_ADDR_START_REG, HP_APM_REGION11_ADDR_END_REG and + * HP_APM_REGION11_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION11_LOCK (BIT(11)) #define HP_APM_REGION11_LOCK_M (HP_APM_REGION11_LOCK_V << HP_APM_REGION11_LOCK_S) @@ -1218,7 +1266,7 @@ extern "C" { */ #define HP_APM_REGION12_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x94) /** HP_APM_REGION12_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 12. + * Configures the start address of region 12. */ #define HP_APM_REGION12_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION12_ADDR_START_M (HP_APM_REGION12_ADDR_START_V << HP_APM_REGION12_ADDR_START_S) @@ -1230,7 +1278,7 @@ extern "C" { */ #define HP_APM_REGION12_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x98) /** HP_APM_REGION12_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 12. + * Configures the end address of region 12. */ #define HP_APM_REGION12_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION12_ADDR_END_M (HP_APM_REGION12_ADDR_END_V << HP_APM_REGION12_ADDR_END_S) @@ -1238,74 +1286,78 @@ extern "C" { #define HP_APM_REGION12_ADDR_END_S 0 /** HP_APM_REGION12_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION12_ATTR_REG (DR_REG_HP_APM_BASE + 0x9c) /** HP_APM_REGION12_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 12. + * Configures the execution permission in region 12 in REE0 mode. */ #define HP_APM_REGION12_R0_X (BIT(0)) #define HP_APM_REGION12_R0_X_M (HP_APM_REGION12_R0_X_V << HP_APM_REGION12_R0_X_S) #define HP_APM_REGION12_R0_X_V 0x00000001U #define HP_APM_REGION12_R0_X_S 0 /** HP_APM_REGION12_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 12. + * Configures the write permission in region 12 in REE0 mode. */ #define HP_APM_REGION12_R0_W (BIT(1)) #define HP_APM_REGION12_R0_W_M (HP_APM_REGION12_R0_W_V << HP_APM_REGION12_R0_W_S) #define HP_APM_REGION12_R0_W_V 0x00000001U #define HP_APM_REGION12_R0_W_S 1 /** HP_APM_REGION12_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 12. + * Configures the read permission in region 12 in REE0 mode. */ #define HP_APM_REGION12_R0_R (BIT(2)) #define HP_APM_REGION12_R0_R_M (HP_APM_REGION12_R0_R_V << HP_APM_REGION12_R0_R_S) #define HP_APM_REGION12_R0_R_V 0x00000001U #define HP_APM_REGION12_R0_R_S 2 /** HP_APM_REGION12_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 12. + * Configures the execution permission in region 12 in REE1 mode. */ #define HP_APM_REGION12_R1_X (BIT(4)) #define HP_APM_REGION12_R1_X_M (HP_APM_REGION12_R1_X_V << HP_APM_REGION12_R1_X_S) #define HP_APM_REGION12_R1_X_V 0x00000001U #define HP_APM_REGION12_R1_X_S 4 /** HP_APM_REGION12_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 12. + * Configures the write permission in region 12 in REE1 mode. */ #define HP_APM_REGION12_R1_W (BIT(5)) #define HP_APM_REGION12_R1_W_M (HP_APM_REGION12_R1_W_V << HP_APM_REGION12_R1_W_S) #define HP_APM_REGION12_R1_W_V 0x00000001U #define HP_APM_REGION12_R1_W_S 5 /** HP_APM_REGION12_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 12. + * Configures the read permission in region 12 in REE1 mode. */ #define HP_APM_REGION12_R1_R (BIT(6)) #define HP_APM_REGION12_R1_R_M (HP_APM_REGION12_R1_R_V << HP_APM_REGION12_R1_R_S) #define HP_APM_REGION12_R1_R_V 0x00000001U #define HP_APM_REGION12_R1_R_S 6 /** HP_APM_REGION12_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 12. + * Configures the execution permission in region 12 in REE2 mode. */ #define HP_APM_REGION12_R2_X (BIT(8)) #define HP_APM_REGION12_R2_X_M (HP_APM_REGION12_R2_X_V << HP_APM_REGION12_R2_X_S) #define HP_APM_REGION12_R2_X_V 0x00000001U #define HP_APM_REGION12_R2_X_S 8 /** HP_APM_REGION12_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 12. + * Configures the write permission in region 12 in REE2 mode. */ #define HP_APM_REGION12_R2_W (BIT(9)) #define HP_APM_REGION12_R2_W_M (HP_APM_REGION12_R2_W_V << HP_APM_REGION12_R2_W_S) #define HP_APM_REGION12_R2_W_V 0x00000001U #define HP_APM_REGION12_R2_W_S 9 /** HP_APM_REGION12_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 12. + * Configures the read permission in region 12 in REE2 mode. */ #define HP_APM_REGION12_R2_R (BIT(10)) #define HP_APM_REGION12_R2_R_M (HP_APM_REGION12_R2_R_V << HP_APM_REGION12_R2_R_S) #define HP_APM_REGION12_R2_R_V 0x00000001U #define HP_APM_REGION12_R2_R_S 10 /** HP_APM_REGION12_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 12 configuration registers + * (HP_APM_REGION12_ADDR_START_REG, HP_APM_REGION12_ADDR_END_REG and + * HP_APM_REGION12_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION12_LOCK (BIT(11)) #define HP_APM_REGION12_LOCK_M (HP_APM_REGION12_LOCK_V << HP_APM_REGION12_LOCK_S) @@ -1317,7 +1369,7 @@ extern "C" { */ #define HP_APM_REGION13_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xa0) /** HP_APM_REGION13_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 13. + * Configures the start address of region 13. */ #define HP_APM_REGION13_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION13_ADDR_START_M (HP_APM_REGION13_ADDR_START_V << HP_APM_REGION13_ADDR_START_S) @@ -1329,7 +1381,7 @@ extern "C" { */ #define HP_APM_REGION13_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xa4) /** HP_APM_REGION13_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 13. + * Configures the end address of region 13. */ #define HP_APM_REGION13_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION13_ADDR_END_M (HP_APM_REGION13_ADDR_END_V << HP_APM_REGION13_ADDR_END_S) @@ -1337,74 +1389,78 @@ extern "C" { #define HP_APM_REGION13_ADDR_END_S 0 /** HP_APM_REGION13_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION13_ATTR_REG (DR_REG_HP_APM_BASE + 0xa8) /** HP_APM_REGION13_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 13. + * Configures the execution permission in region 13 in REE0 mode. */ #define HP_APM_REGION13_R0_X (BIT(0)) #define HP_APM_REGION13_R0_X_M (HP_APM_REGION13_R0_X_V << HP_APM_REGION13_R0_X_S) #define HP_APM_REGION13_R0_X_V 0x00000001U #define HP_APM_REGION13_R0_X_S 0 /** HP_APM_REGION13_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 13. + * Configures the write permission in region 13 in REE0 mode. */ #define HP_APM_REGION13_R0_W (BIT(1)) #define HP_APM_REGION13_R0_W_M (HP_APM_REGION13_R0_W_V << HP_APM_REGION13_R0_W_S) #define HP_APM_REGION13_R0_W_V 0x00000001U #define HP_APM_REGION13_R0_W_S 1 /** HP_APM_REGION13_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 13. + * Configures the read permission in region 13 in REE0 mode. */ #define HP_APM_REGION13_R0_R (BIT(2)) #define HP_APM_REGION13_R0_R_M (HP_APM_REGION13_R0_R_V << HP_APM_REGION13_R0_R_S) #define HP_APM_REGION13_R0_R_V 0x00000001U #define HP_APM_REGION13_R0_R_S 2 /** HP_APM_REGION13_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 13. + * Configures the execution permission in region 13 in REE1 mode. */ #define HP_APM_REGION13_R1_X (BIT(4)) #define HP_APM_REGION13_R1_X_M (HP_APM_REGION13_R1_X_V << HP_APM_REGION13_R1_X_S) #define HP_APM_REGION13_R1_X_V 0x00000001U #define HP_APM_REGION13_R1_X_S 4 /** HP_APM_REGION13_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 13. + * Configures the write permission in region 13 in REE1 mode. */ #define HP_APM_REGION13_R1_W (BIT(5)) #define HP_APM_REGION13_R1_W_M (HP_APM_REGION13_R1_W_V << HP_APM_REGION13_R1_W_S) #define HP_APM_REGION13_R1_W_V 0x00000001U #define HP_APM_REGION13_R1_W_S 5 /** HP_APM_REGION13_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 13. + * Configures the read permission in region 13 in REE1 mode. */ #define HP_APM_REGION13_R1_R (BIT(6)) #define HP_APM_REGION13_R1_R_M (HP_APM_REGION13_R1_R_V << HP_APM_REGION13_R1_R_S) #define HP_APM_REGION13_R1_R_V 0x00000001U #define HP_APM_REGION13_R1_R_S 6 /** HP_APM_REGION13_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 13. + * Configures the execution permission in region 13 in REE2 mode. */ #define HP_APM_REGION13_R2_X (BIT(8)) #define HP_APM_REGION13_R2_X_M (HP_APM_REGION13_R2_X_V << HP_APM_REGION13_R2_X_S) #define HP_APM_REGION13_R2_X_V 0x00000001U #define HP_APM_REGION13_R2_X_S 8 /** HP_APM_REGION13_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 13. + * Configures the write permission in region 13 in REE2 mode. */ #define HP_APM_REGION13_R2_W (BIT(9)) #define HP_APM_REGION13_R2_W_M (HP_APM_REGION13_R2_W_V << HP_APM_REGION13_R2_W_S) #define HP_APM_REGION13_R2_W_V 0x00000001U #define HP_APM_REGION13_R2_W_S 9 /** HP_APM_REGION13_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 13. + * Configures the read permission in region 13 in REE2 mode. */ #define HP_APM_REGION13_R2_R (BIT(10)) #define HP_APM_REGION13_R2_R_M (HP_APM_REGION13_R2_R_V << HP_APM_REGION13_R2_R_S) #define HP_APM_REGION13_R2_R_V 0x00000001U #define HP_APM_REGION13_R2_R_S 10 /** HP_APM_REGION13_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 13 configuration registers + * (HP_APM_REGION13_ADDR_START_REG, HP_APM_REGION13_ADDR_END_REG and + * HP_APM_REGION13_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION13_LOCK (BIT(11)) #define HP_APM_REGION13_LOCK_M (HP_APM_REGION13_LOCK_V << HP_APM_REGION13_LOCK_S) @@ -1416,7 +1472,7 @@ extern "C" { */ #define HP_APM_REGION14_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xac) /** HP_APM_REGION14_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 14. + * Configures the start address of region 14. */ #define HP_APM_REGION14_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION14_ADDR_START_M (HP_APM_REGION14_ADDR_START_V << HP_APM_REGION14_ADDR_START_S) @@ -1428,7 +1484,7 @@ extern "C" { */ #define HP_APM_REGION14_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xb0) /** HP_APM_REGION14_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 14. + * Configures the end address of region 14. */ #define HP_APM_REGION14_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION14_ADDR_END_M (HP_APM_REGION14_ADDR_END_V << HP_APM_REGION14_ADDR_END_S) @@ -1436,74 +1492,78 @@ extern "C" { #define HP_APM_REGION14_ADDR_END_S 0 /** HP_APM_REGION14_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION14_ATTR_REG (DR_REG_HP_APM_BASE + 0xb4) /** HP_APM_REGION14_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 14. + * Configures the execution permission in region 14 in REE0 mode. */ #define HP_APM_REGION14_R0_X (BIT(0)) #define HP_APM_REGION14_R0_X_M (HP_APM_REGION14_R0_X_V << HP_APM_REGION14_R0_X_S) #define HP_APM_REGION14_R0_X_V 0x00000001U #define HP_APM_REGION14_R0_X_S 0 /** HP_APM_REGION14_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 14. + * Configures the write permission in region 14 in REE0 mode. */ #define HP_APM_REGION14_R0_W (BIT(1)) #define HP_APM_REGION14_R0_W_M (HP_APM_REGION14_R0_W_V << HP_APM_REGION14_R0_W_S) #define HP_APM_REGION14_R0_W_V 0x00000001U #define HP_APM_REGION14_R0_W_S 1 /** HP_APM_REGION14_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 14. + * Configures the read permission in region 14 in REE0 mode. */ #define HP_APM_REGION14_R0_R (BIT(2)) #define HP_APM_REGION14_R0_R_M (HP_APM_REGION14_R0_R_V << HP_APM_REGION14_R0_R_S) #define HP_APM_REGION14_R0_R_V 0x00000001U #define HP_APM_REGION14_R0_R_S 2 /** HP_APM_REGION14_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 14. + * Configures the execution permission in region 14 in REE1 mode. */ #define HP_APM_REGION14_R1_X (BIT(4)) #define HP_APM_REGION14_R1_X_M (HP_APM_REGION14_R1_X_V << HP_APM_REGION14_R1_X_S) #define HP_APM_REGION14_R1_X_V 0x00000001U #define HP_APM_REGION14_R1_X_S 4 /** HP_APM_REGION14_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 14. + * Configures the write permission in region 14 in REE1 mode. */ #define HP_APM_REGION14_R1_W (BIT(5)) #define HP_APM_REGION14_R1_W_M (HP_APM_REGION14_R1_W_V << HP_APM_REGION14_R1_W_S) #define HP_APM_REGION14_R1_W_V 0x00000001U #define HP_APM_REGION14_R1_W_S 5 /** HP_APM_REGION14_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 14. + * Configures the read permission in region 14 in REE1 mode. */ #define HP_APM_REGION14_R1_R (BIT(6)) #define HP_APM_REGION14_R1_R_M (HP_APM_REGION14_R1_R_V << HP_APM_REGION14_R1_R_S) #define HP_APM_REGION14_R1_R_V 0x00000001U #define HP_APM_REGION14_R1_R_S 6 /** HP_APM_REGION14_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 14. + * Configures the execution permission in region 14 in REE2 mode. */ #define HP_APM_REGION14_R2_X (BIT(8)) #define HP_APM_REGION14_R2_X_M (HP_APM_REGION14_R2_X_V << HP_APM_REGION14_R2_X_S) #define HP_APM_REGION14_R2_X_V 0x00000001U #define HP_APM_REGION14_R2_X_S 8 /** HP_APM_REGION14_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 14. + * Configures the write permission in region 14 in REE2 mode. */ #define HP_APM_REGION14_R2_W (BIT(9)) #define HP_APM_REGION14_R2_W_M (HP_APM_REGION14_R2_W_V << HP_APM_REGION14_R2_W_S) #define HP_APM_REGION14_R2_W_V 0x00000001U #define HP_APM_REGION14_R2_W_S 9 /** HP_APM_REGION14_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 14. + * Configures the read permission in region 14 in REE2 mode. */ #define HP_APM_REGION14_R2_R (BIT(10)) #define HP_APM_REGION14_R2_R_M (HP_APM_REGION14_R2_R_V << HP_APM_REGION14_R2_R_S) #define HP_APM_REGION14_R2_R_V 0x00000001U #define HP_APM_REGION14_R2_R_S 10 /** HP_APM_REGION14_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 14 configuration registers + * (HP_APM_REGION14_ADDR_START_REG, HP_APM_REGION14_ADDR_END_REG and + * HP_APM_REGION14_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION14_LOCK (BIT(11)) #define HP_APM_REGION14_LOCK_M (HP_APM_REGION14_LOCK_V << HP_APM_REGION14_LOCK_S) @@ -1515,7 +1575,7 @@ extern "C" { */ #define HP_APM_REGION15_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xb8) /** HP_APM_REGION15_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 15. + * Configures the start address of region 15. */ #define HP_APM_REGION15_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION15_ADDR_START_M (HP_APM_REGION15_ADDR_START_V << HP_APM_REGION15_ADDR_START_S) @@ -1527,7 +1587,7 @@ extern "C" { */ #define HP_APM_REGION15_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xbc) /** HP_APM_REGION15_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 15. + * Configures the end address of region 15. */ #define HP_APM_REGION15_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION15_ADDR_END_M (HP_APM_REGION15_ADDR_END_V << HP_APM_REGION15_ADDR_END_S) @@ -1535,74 +1595,78 @@ extern "C" { #define HP_APM_REGION15_ADDR_END_S 0 /** HP_APM_REGION15_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION15_ATTR_REG (DR_REG_HP_APM_BASE + 0xc0) /** HP_APM_REGION15_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 15. + * Configures the execution permission in region 15 in REE0 mode. */ #define HP_APM_REGION15_R0_X (BIT(0)) #define HP_APM_REGION15_R0_X_M (HP_APM_REGION15_R0_X_V << HP_APM_REGION15_R0_X_S) #define HP_APM_REGION15_R0_X_V 0x00000001U #define HP_APM_REGION15_R0_X_S 0 /** HP_APM_REGION15_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 15. + * Configures the write permission in region 15 in REE0 mode. */ #define HP_APM_REGION15_R0_W (BIT(1)) #define HP_APM_REGION15_R0_W_M (HP_APM_REGION15_R0_W_V << HP_APM_REGION15_R0_W_S) #define HP_APM_REGION15_R0_W_V 0x00000001U #define HP_APM_REGION15_R0_W_S 1 /** HP_APM_REGION15_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 15. + * Configures the read permission in region 15 in REE0 mode. */ #define HP_APM_REGION15_R0_R (BIT(2)) #define HP_APM_REGION15_R0_R_M (HP_APM_REGION15_R0_R_V << HP_APM_REGION15_R0_R_S) #define HP_APM_REGION15_R0_R_V 0x00000001U #define HP_APM_REGION15_R0_R_S 2 /** HP_APM_REGION15_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 15. + * Configures the execution permission in region 15 in REE1 mode. */ #define HP_APM_REGION15_R1_X (BIT(4)) #define HP_APM_REGION15_R1_X_M (HP_APM_REGION15_R1_X_V << HP_APM_REGION15_R1_X_S) #define HP_APM_REGION15_R1_X_V 0x00000001U #define HP_APM_REGION15_R1_X_S 4 /** HP_APM_REGION15_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 15. + * Configures the write permission in region 15 in REE1 mode. */ #define HP_APM_REGION15_R1_W (BIT(5)) #define HP_APM_REGION15_R1_W_M (HP_APM_REGION15_R1_W_V << HP_APM_REGION15_R1_W_S) #define HP_APM_REGION15_R1_W_V 0x00000001U #define HP_APM_REGION15_R1_W_S 5 /** HP_APM_REGION15_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 15. + * Configures the read permission in region 15 in REE1 mode. */ #define HP_APM_REGION15_R1_R (BIT(6)) #define HP_APM_REGION15_R1_R_M (HP_APM_REGION15_R1_R_V << HP_APM_REGION15_R1_R_S) #define HP_APM_REGION15_R1_R_V 0x00000001U #define HP_APM_REGION15_R1_R_S 6 /** HP_APM_REGION15_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 15. + * Configures the execution permission in region 15 in REE2 mode. */ #define HP_APM_REGION15_R2_X (BIT(8)) #define HP_APM_REGION15_R2_X_M (HP_APM_REGION15_R2_X_V << HP_APM_REGION15_R2_X_S) #define HP_APM_REGION15_R2_X_V 0x00000001U #define HP_APM_REGION15_R2_X_S 8 /** HP_APM_REGION15_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 15. + * Configures the write permission in region 15 in REE2 mode. */ #define HP_APM_REGION15_R2_W (BIT(9)) #define HP_APM_REGION15_R2_W_M (HP_APM_REGION15_R2_W_V << HP_APM_REGION15_R2_W_S) #define HP_APM_REGION15_R2_W_V 0x00000001U #define HP_APM_REGION15_R2_W_S 9 /** HP_APM_REGION15_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 15. + * Configures the read permission in region 15 in REE2 mode. */ #define HP_APM_REGION15_R2_R (BIT(10)) #define HP_APM_REGION15_R2_R_M (HP_APM_REGION15_R2_R_V << HP_APM_REGION15_R2_R_S) #define HP_APM_REGION15_R2_R_V 0x00000001U #define HP_APM_REGION15_R2_R_S 10 /** HP_APM_REGION15_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 15 configuration registers + * (HP_APM_REGION15_ADDR_START_REG, HP_APM_REGION15_ADDR_END_REG and + * HP_APM_REGION15_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION15_LOCK (BIT(11)) #define HP_APM_REGION15_LOCK_M (HP_APM_REGION15_LOCK_V << HP_APM_REGION15_LOCK_S) @@ -1610,39 +1674,39 @@ extern "C" { #define HP_APM_REGION15_LOCK_S 11 /** HP_APM_FUNC_CTRL_REG register - * APM function control register + * APM access path permission management register */ #define HP_APM_FUNC_CTRL_REG (DR_REG_HP_APM_BASE + 0xc4) /** HP_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures to enable permission management for HP_APM_CTRL M0. */ #define HP_APM_M0_FUNC_EN (BIT(0)) #define HP_APM_M0_FUNC_EN_M (HP_APM_M0_FUNC_EN_V << HP_APM_M0_FUNC_EN_S) #define HP_APM_M0_FUNC_EN_V 0x00000001U #define HP_APM_M0_FUNC_EN_S 0 /** HP_APM_M1_FUNC_EN : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable + * Configures to enable permission management for HP_APM_CTRL M1. */ #define HP_APM_M1_FUNC_EN (BIT(1)) #define HP_APM_M1_FUNC_EN_M (HP_APM_M1_FUNC_EN_V << HP_APM_M1_FUNC_EN_S) #define HP_APM_M1_FUNC_EN_V 0x00000001U #define HP_APM_M1_FUNC_EN_S 1 /** HP_APM_M2_FUNC_EN : R/W; bitpos: [2]; default: 1; - * PMS M2 function enable + * Configures to enable permission management for HP_APM_CTRL M2. */ #define HP_APM_M2_FUNC_EN (BIT(2)) #define HP_APM_M2_FUNC_EN_M (HP_APM_M2_FUNC_EN_V << HP_APM_M2_FUNC_EN_S) #define HP_APM_M2_FUNC_EN_V 0x00000001U #define HP_APM_M2_FUNC_EN_S 2 /** HP_APM_M3_FUNC_EN : R/W; bitpos: [3]; default: 1; - * PMS M3 function enable + * Configures to enable permission management for HP_APM_CTRL M3. */ #define HP_APM_M3_FUNC_EN (BIT(3)) #define HP_APM_M3_FUNC_EN_M (HP_APM_M3_FUNC_EN_V << HP_APM_M3_FUNC_EN_S) #define HP_APM_M3_FUNC_EN_V 0x00000001U #define HP_APM_M3_FUNC_EN_S 3 /** HP_APM_M4_FUNC_EN : R/W; bitpos: [4]; default: 1; - * PMS M4 function enable + * Configures to enable permission management for HP_APM_CTRL M4. */ #define HP_APM_M4_FUNC_EN (BIT(4)) #define HP_APM_M4_FUNC_EN_M (HP_APM_M4_FUNC_EN_V << HP_APM_M4_FUNC_EN_S) @@ -1650,13 +1714,13 @@ extern "C" { #define HP_APM_M4_FUNC_EN_S 4 /** HP_APM_M0_STATUS_REG register - * M0 status register + * HP_APM_CTRL M0 status register */ #define HP_APM_M0_STATUS_REG (DR_REG_HP_APM_BASE + 0xc8) /** HP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define HP_APM_M0_EXCEPTION_STATUS 0x00000003U #define HP_APM_M0_EXCEPTION_STATUS_M (HP_APM_M0_EXCEPTION_STATUS_V << HP_APM_M0_EXCEPTION_STATUS_S) @@ -1664,7 +1728,7 @@ extern "C" { #define HP_APM_M0_EXCEPTION_STATUS_S 0 /** HP_APM_M0_STATUS_CLR_REG register - * M0 status clear register + * HP_APM_CTRL M0 status clear register */ #define HP_APM_M0_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xcc) /** HP_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -1676,25 +1740,25 @@ extern "C" { #define HP_APM_M0_EXCEPTION_STATUS_CLR_S 0 /** HP_APM_M0_EXCEPTION_INFO0_REG register - * M0 exception_info0 register + * HP_APM_CTRL M0 exception information register */ #define HP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xd0) /** HP_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define HP_APM_M0_EXCEPTION_REGION 0x0000FFFFU #define HP_APM_M0_EXCEPTION_REGION_M (HP_APM_M0_EXCEPTION_REGION_V << HP_APM_M0_EXCEPTION_REGION_S) #define HP_APM_M0_EXCEPTION_REGION_V 0x0000FFFFU #define HP_APM_M0_EXCEPTION_REGION_S 0 /** HP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define HP_APM_M0_EXCEPTION_MODE 0x00000003U #define HP_APM_M0_EXCEPTION_MODE_M (HP_APM_M0_EXCEPTION_MODE_V << HP_APM_M0_EXCEPTION_MODE_S) #define HP_APM_M0_EXCEPTION_MODE_V 0x00000003U #define HP_APM_M0_EXCEPTION_MODE_S 16 /** HP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define HP_APM_M0_EXCEPTION_ID 0x0000001FU #define HP_APM_M0_EXCEPTION_ID_M (HP_APM_M0_EXCEPTION_ID_V << HP_APM_M0_EXCEPTION_ID_S) @@ -1702,11 +1766,11 @@ extern "C" { #define HP_APM_M0_EXCEPTION_ID_S 18 /** HP_APM_M0_EXCEPTION_INFO1_REG register - * M0 exception_info1 register + * HP_APM_CTRL M0 exception information register */ #define HP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xd4) /** HP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define HP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU #define HP_APM_M0_EXCEPTION_ADDR_M (HP_APM_M0_EXCEPTION_ADDR_V << HP_APM_M0_EXCEPTION_ADDR_S) @@ -1714,13 +1778,13 @@ extern "C" { #define HP_APM_M0_EXCEPTION_ADDR_S 0 /** HP_APM_M1_STATUS_REG register - * M1 status register + * HP_APM_CTRL M1 status register */ #define HP_APM_M1_STATUS_REG (DR_REG_HP_APM_BASE + 0xd8) /** HP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define HP_APM_M1_EXCEPTION_STATUS 0x00000003U #define HP_APM_M1_EXCEPTION_STATUS_M (HP_APM_M1_EXCEPTION_STATUS_V << HP_APM_M1_EXCEPTION_STATUS_S) @@ -1728,7 +1792,7 @@ extern "C" { #define HP_APM_M1_EXCEPTION_STATUS_S 0 /** HP_APM_M1_STATUS_CLR_REG register - * M1 status clear register + * HP_APM_CTRL M1 status clear register */ #define HP_APM_M1_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xdc) /** HP_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -1740,25 +1804,25 @@ extern "C" { #define HP_APM_M1_EXCEPTION_STATUS_CLR_S 0 /** HP_APM_M1_EXCEPTION_INFO0_REG register - * M1 exception_info0 register + * HP_APM_CTRL M1 exception information register */ #define HP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xe0) /** HP_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define HP_APM_M1_EXCEPTION_REGION 0x0000FFFFU #define HP_APM_M1_EXCEPTION_REGION_M (HP_APM_M1_EXCEPTION_REGION_V << HP_APM_M1_EXCEPTION_REGION_S) #define HP_APM_M1_EXCEPTION_REGION_V 0x0000FFFFU #define HP_APM_M1_EXCEPTION_REGION_S 0 /** HP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define HP_APM_M1_EXCEPTION_MODE 0x00000003U #define HP_APM_M1_EXCEPTION_MODE_M (HP_APM_M1_EXCEPTION_MODE_V << HP_APM_M1_EXCEPTION_MODE_S) #define HP_APM_M1_EXCEPTION_MODE_V 0x00000003U #define HP_APM_M1_EXCEPTION_MODE_S 16 /** HP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define HP_APM_M1_EXCEPTION_ID 0x0000001FU #define HP_APM_M1_EXCEPTION_ID_M (HP_APM_M1_EXCEPTION_ID_V << HP_APM_M1_EXCEPTION_ID_S) @@ -1766,11 +1830,11 @@ extern "C" { #define HP_APM_M1_EXCEPTION_ID_S 18 /** HP_APM_M1_EXCEPTION_INFO1_REG register - * M1 exception_info1 register + * HP_APM_CTRL M1 exception information register */ #define HP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xe4) /** HP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define HP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU #define HP_APM_M1_EXCEPTION_ADDR_M (HP_APM_M1_EXCEPTION_ADDR_V << HP_APM_M1_EXCEPTION_ADDR_S) @@ -1778,13 +1842,13 @@ extern "C" { #define HP_APM_M1_EXCEPTION_ADDR_S 0 /** HP_APM_M2_STATUS_REG register - * M2 status register + * HP_APM_CTRL M2 status register */ #define HP_APM_M2_STATUS_REG (DR_REG_HP_APM_BASE + 0xe8) /** HP_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define HP_APM_M2_EXCEPTION_STATUS 0x00000003U #define HP_APM_M2_EXCEPTION_STATUS_M (HP_APM_M2_EXCEPTION_STATUS_V << HP_APM_M2_EXCEPTION_STATUS_S) @@ -1792,7 +1856,7 @@ extern "C" { #define HP_APM_M2_EXCEPTION_STATUS_S 0 /** HP_APM_M2_STATUS_CLR_REG register - * M2 status clear register + * HP_APM_CTRL M2 status clear register */ #define HP_APM_M2_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xec) /** HP_APM_M2_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -1804,25 +1868,25 @@ extern "C" { #define HP_APM_M2_EXCEPTION_STATUS_CLR_S 0 /** HP_APM_M2_EXCEPTION_INFO0_REG register - * M2 exception_info0 register + * HP_APM_CTRL M2 exception information register */ #define HP_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xf0) /** HP_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define HP_APM_M2_EXCEPTION_REGION 0x0000FFFFU #define HP_APM_M2_EXCEPTION_REGION_M (HP_APM_M2_EXCEPTION_REGION_V << HP_APM_M2_EXCEPTION_REGION_S) #define HP_APM_M2_EXCEPTION_REGION_V 0x0000FFFFU #define HP_APM_M2_EXCEPTION_REGION_S 0 /** HP_APM_M2_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define HP_APM_M2_EXCEPTION_MODE 0x00000003U #define HP_APM_M2_EXCEPTION_MODE_M (HP_APM_M2_EXCEPTION_MODE_V << HP_APM_M2_EXCEPTION_MODE_S) #define HP_APM_M2_EXCEPTION_MODE_V 0x00000003U #define HP_APM_M2_EXCEPTION_MODE_S 16 /** HP_APM_M2_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define HP_APM_M2_EXCEPTION_ID 0x0000001FU #define HP_APM_M2_EXCEPTION_ID_M (HP_APM_M2_EXCEPTION_ID_V << HP_APM_M2_EXCEPTION_ID_S) @@ -1830,11 +1894,11 @@ extern "C" { #define HP_APM_M2_EXCEPTION_ID_S 18 /** HP_APM_M2_EXCEPTION_INFO1_REG register - * M2 exception_info1 register + * HP_APM_CTRL M2 exception information register */ #define HP_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xf4) /** HP_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define HP_APM_M2_EXCEPTION_ADDR 0xFFFFFFFFU #define HP_APM_M2_EXCEPTION_ADDR_M (HP_APM_M2_EXCEPTION_ADDR_V << HP_APM_M2_EXCEPTION_ADDR_S) @@ -1842,13 +1906,13 @@ extern "C" { #define HP_APM_M2_EXCEPTION_ADDR_S 0 /** HP_APM_M3_STATUS_REG register - * M3 status register + * HP_APM_CTRL M3 status register */ #define HP_APM_M3_STATUS_REG (DR_REG_HP_APM_BASE + 0xf8) /** HP_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define HP_APM_M3_EXCEPTION_STATUS 0x00000003U #define HP_APM_M3_EXCEPTION_STATUS_M (HP_APM_M3_EXCEPTION_STATUS_V << HP_APM_M3_EXCEPTION_STATUS_S) @@ -1856,7 +1920,7 @@ extern "C" { #define HP_APM_M3_EXCEPTION_STATUS_S 0 /** HP_APM_M3_STATUS_CLR_REG register - * M3 status clear register + * HP_APM_CTRL M3 status clear register */ #define HP_APM_M3_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xfc) /** HP_APM_M3_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -1868,25 +1932,25 @@ extern "C" { #define HP_APM_M3_EXCEPTION_STATUS_CLR_S 0 /** HP_APM_M3_EXCEPTION_INFO0_REG register - * M3 exception_info0 register + * HP_APM_CTRL M3 exception information register */ #define HP_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x100) /** HP_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define HP_APM_M3_EXCEPTION_REGION 0x0000FFFFU #define HP_APM_M3_EXCEPTION_REGION_M (HP_APM_M3_EXCEPTION_REGION_V << HP_APM_M3_EXCEPTION_REGION_S) #define HP_APM_M3_EXCEPTION_REGION_V 0x0000FFFFU #define HP_APM_M3_EXCEPTION_REGION_S 0 /** HP_APM_M3_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define HP_APM_M3_EXCEPTION_MODE 0x00000003U #define HP_APM_M3_EXCEPTION_MODE_M (HP_APM_M3_EXCEPTION_MODE_V << HP_APM_M3_EXCEPTION_MODE_S) #define HP_APM_M3_EXCEPTION_MODE_V 0x00000003U #define HP_APM_M3_EXCEPTION_MODE_S 16 /** HP_APM_M3_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define HP_APM_M3_EXCEPTION_ID 0x0000001FU #define HP_APM_M3_EXCEPTION_ID_M (HP_APM_M3_EXCEPTION_ID_V << HP_APM_M3_EXCEPTION_ID_S) @@ -1894,11 +1958,11 @@ extern "C" { #define HP_APM_M3_EXCEPTION_ID_S 18 /** HP_APM_M3_EXCEPTION_INFO1_REG register - * M3 exception_info1 register + * HP_APM_CTRL M3 exception information register */ #define HP_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x104) /** HP_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define HP_APM_M3_EXCEPTION_ADDR 0xFFFFFFFFU #define HP_APM_M3_EXCEPTION_ADDR_M (HP_APM_M3_EXCEPTION_ADDR_V << HP_APM_M3_EXCEPTION_ADDR_S) @@ -1906,13 +1970,13 @@ extern "C" { #define HP_APM_M3_EXCEPTION_ADDR_S 0 /** HP_APM_M4_STATUS_REG register - * M4 status register + * HP_APM_CTRL M4 status register */ #define HP_APM_M4_STATUS_REG (DR_REG_HP_APM_BASE + 0x108) /** HP_APM_M4_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define HP_APM_M4_EXCEPTION_STATUS 0x00000003U #define HP_APM_M4_EXCEPTION_STATUS_M (HP_APM_M4_EXCEPTION_STATUS_V << HP_APM_M4_EXCEPTION_STATUS_S) @@ -1920,7 +1984,7 @@ extern "C" { #define HP_APM_M4_EXCEPTION_STATUS_S 0 /** HP_APM_M4_STATUS_CLR_REG register - * M4 status clear register + * HP_APM_CTRL M4 status clear register */ #define HP_APM_M4_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0x10c) /** HP_APM_M4_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -1932,25 +1996,25 @@ extern "C" { #define HP_APM_M4_EXCEPTION_STATUS_CLR_S 0 /** HP_APM_M4_EXCEPTION_INFO0_REG register - * M4 exception_info0 register + * HP_APM_CTRL M4 exception information register */ #define HP_APM_M4_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x110) /** HP_APM_M4_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define HP_APM_M4_EXCEPTION_REGION 0x0000FFFFU #define HP_APM_M4_EXCEPTION_REGION_M (HP_APM_M4_EXCEPTION_REGION_V << HP_APM_M4_EXCEPTION_REGION_S) #define HP_APM_M4_EXCEPTION_REGION_V 0x0000FFFFU #define HP_APM_M4_EXCEPTION_REGION_S 0 /** HP_APM_M4_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define HP_APM_M4_EXCEPTION_MODE 0x00000003U #define HP_APM_M4_EXCEPTION_MODE_M (HP_APM_M4_EXCEPTION_MODE_V << HP_APM_M4_EXCEPTION_MODE_S) #define HP_APM_M4_EXCEPTION_MODE_V 0x00000003U #define HP_APM_M4_EXCEPTION_MODE_S 16 /** HP_APM_M4_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define HP_APM_M4_EXCEPTION_ID 0x0000001FU #define HP_APM_M4_EXCEPTION_ID_M (HP_APM_M4_EXCEPTION_ID_V << HP_APM_M4_EXCEPTION_ID_S) @@ -1958,11 +2022,11 @@ extern "C" { #define HP_APM_M4_EXCEPTION_ID_S 18 /** HP_APM_M4_EXCEPTION_INFO1_REG register - * M4 exception_info1 register + * HP_APM_CTRL M4 exception information register */ #define HP_APM_M4_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x114) /** HP_APM_M4_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define HP_APM_M4_EXCEPTION_ADDR 0xFFFFFFFFU #define HP_APM_M4_EXCEPTION_ADDR_M (HP_APM_M4_EXCEPTION_ADDR_V << HP_APM_M4_EXCEPTION_ADDR_S) @@ -1970,49 +2034,49 @@ extern "C" { #define HP_APM_M4_EXCEPTION_ADDR_S 0 /** HP_APM_INT_EN_REG register - * APM interrupt enable register + * HP_APM_CTRL M0/1/2/3/4 interrupt enable register */ #define HP_APM_INT_EN_REG (DR_REG_HP_APM_BASE + 0x118) /** HP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; - * Configures to enable APM M0 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ #define HP_APM_M0_APM_INT_EN (BIT(0)) #define HP_APM_M0_APM_INT_EN_M (HP_APM_M0_APM_INT_EN_V << HP_APM_M0_APM_INT_EN_S) #define HP_APM_M0_APM_INT_EN_V 0x00000001U #define HP_APM_M0_APM_INT_EN_S 0 /** HP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; - * Configures to enable APM M1 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M1 interrupt. + * 0: Disable + * 1: Enable */ #define HP_APM_M1_APM_INT_EN (BIT(1)) #define HP_APM_M1_APM_INT_EN_M (HP_APM_M1_APM_INT_EN_V << HP_APM_M1_APM_INT_EN_S) #define HP_APM_M1_APM_INT_EN_V 0x00000001U #define HP_APM_M1_APM_INT_EN_S 1 /** HP_APM_M2_APM_INT_EN : R/W; bitpos: [2]; default: 0; - * Configures to enable APM M2 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M2 interrupt. + * 0: Disable + * 1: Enable */ #define HP_APM_M2_APM_INT_EN (BIT(2)) #define HP_APM_M2_APM_INT_EN_M (HP_APM_M2_APM_INT_EN_V << HP_APM_M2_APM_INT_EN_S) #define HP_APM_M2_APM_INT_EN_V 0x00000001U #define HP_APM_M2_APM_INT_EN_S 2 /** HP_APM_M3_APM_INT_EN : R/W; bitpos: [3]; default: 0; - * Configures to enable APM M3 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M3 interrupt. + * 0: Disable + * 1: Enable */ #define HP_APM_M3_APM_INT_EN (BIT(3)) #define HP_APM_M3_APM_INT_EN_M (HP_APM_M3_APM_INT_EN_V << HP_APM_M3_APM_INT_EN_S) #define HP_APM_M3_APM_INT_EN_V 0x00000001U #define HP_APM_M3_APM_INT_EN_S 3 /** HP_APM_M4_APM_INT_EN : R/W; bitpos: [4]; default: 0; - * Configures to enable APM M4 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M4 interrupt. + * 0: Disable + * 1: Enable */ #define HP_APM_M4_APM_INT_EN (BIT(4)) #define HP_APM_M4_APM_INT_EN_M (HP_APM_M4_APM_INT_EN_V << HP_APM_M4_APM_INT_EN_S) @@ -2024,9 +2088,9 @@ extern "C" { */ #define HP_APM_CLOCK_GATE_REG (DR_REG_HP_APM_BASE + 0x7f8) /** HP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; - * Configures whether to keep the clock always on.\\ - * 0: enable automatic clock gating \\ - * 1: keep the clock always on \\ + * Configures whether to keep the clock always on. + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ #define HP_APM_CLK_EN (BIT(0)) #define HP_APM_CLK_EN_M (HP_APM_CLK_EN_V << HP_APM_CLK_EN_S) diff --git a/components/soc/esp32c5/register/soc/hp_apm_struct.h b/components/soc/esp32c5/register/soc/hp_apm_struct.h index 87648ad8c3..0f3335eb0c 100644 --- a/components/soc/esp32c5/register/soc/hp_apm_struct.h +++ b/components/soc/esp32c5/register/soc/hp_apm_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,16 +10,16 @@ extern "C" { #endif -/** Group: Region filter enable register */ +/** Group: Configuration Registers */ /** Type of region_filter_en register - * Region filter enable register + * Region enable register */ typedef union { struct { /** region_filter_en : R/W; bitpos: [15:0]; default: 1; - * Configure bit $n (0-15) to enable region $n.\\ - * 0: disable \\ - * 1: enable \\ + * Configure bit $n (0-15) to enable region $n (0-15). + * 0: Disable + * 1: Enable */ uint32_t region_filter_en:16; uint32_t reserved_16:16; @@ -27,15 +27,13 @@ typedef union { uint32_t val; } hp_apm_region_filter_en_reg_t; - -/** Group: Region address register */ /** Type of regionn_addr_start register * Region address register */ typedef union { struct { /** regionn_addr_start : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region n. + * Configures the start address of region n. */ uint32_t regionn_addr_start:32; }; @@ -48,60 +46,62 @@ typedef union { typedef union { struct { /** regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region n. + * Configures the end address of region n. */ uint32_t regionn_addr_end:32; }; uint32_t val; } hp_apm_regionn_addr_end_reg_t; - -/** Group: Region access authority attribute register */ /** Type of regionn_attr register - * Region access authority attribute register + * Region access permissions configuration register */ typedef union { struct { /** regionn_r0_x : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region n. + * Configures the execution permission in region n in REE0 mode. */ uint32_t regionn_r0_x:1; /** regionn_r0_w : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region n. + * Configures the write permission in region n in REE0 mode. */ uint32_t regionn_r0_w:1; /** regionn_r0_r : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region n. + * Configures the read permission in region n in REE0 mode. */ uint32_t regionn_r0_r:1; uint32_t reserved_3:1; /** regionn_r1_x : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region n. + * Configures the execution permission in region n in REE1 mode. */ uint32_t regionn_r1_x:1; /** regionn_r1_w : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region n. + * Configures the write permission in region n in REE1 mode. */ uint32_t regionn_r1_w:1; /** regionn_r1_r : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region n. + * Configures the read permission in region n in REE1 mode. */ uint32_t regionn_r1_r:1; uint32_t reserved_7:1; /** regionn_r2_x : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region n. + * Configures the execution permission in region n in REE2 mode. */ uint32_t regionn_r2_x:1; /** regionn_r2_w : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region n. + * Configures the write permission in region n in REE2 mode. */ uint32_t regionn_r2_w:1; /** regionn_r2_r : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region n. + * Configures the read permission in region n in REE2 mode. */ uint32_t regionn_r2_r:1; /** regionn_lock : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region n configuration registers + * (HP_APM_REGIONn_ADDR_START_REG, HP_APM_REGIONn_ADDR_END_REG and + * HP_APM_REGIONn_ATTR_REG). + * 0: Do not lock + * 1: Lock */ uint32_t regionn_lock:1; uint32_t reserved_12:20; @@ -109,31 +109,29 @@ typedef union { uint32_t val; } hp_apm_regionn_attr_reg_t; - -/** Group: function control register */ /** Type of func_ctrl register - * APM function control register + * APM access path permission management register */ typedef union { struct { /** m0_func_en : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures to enable permission management for HP_APM_CTRL M0. */ uint32_t m0_func_en:1; /** m1_func_en : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable + * Configures to enable permission management for HP_APM_CTRL M1. */ uint32_t m1_func_en:1; /** m2_func_en : R/W; bitpos: [2]; default: 1; - * PMS M2 function enable + * Configures to enable permission management for HP_APM_CTRL M2. */ uint32_t m2_func_en:1; /** m3_func_en : R/W; bitpos: [3]; default: 1; - * PMS M3 function enable + * Configures to enable permission management for HP_APM_CTRL M3. */ uint32_t m3_func_en:1; /** m4_func_en : R/W; bitpos: [4]; default: 1; - * PMS M4 function enable + * Configures to enable permission management for HP_APM_CTRL M4. */ uint32_t m4_func_en:1; uint32_t reserved_5:27; @@ -142,16 +140,16 @@ typedef union { } hp_apm_func_ctrl_reg_t; -/** Group: M0 status register */ +/** Group: Status Registers */ /** Type of m0_status register - * M0 status register + * HP_APM_CTRL M0 status register */ typedef union { struct { /** m0_exception_status : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m0_exception_status:2; uint32_t reserved_2:30; @@ -159,10 +157,8 @@ typedef union { uint32_t val; } hp_apm_m0_status_reg_t; - -/** Group: M0 status clear register */ /** Type of m0_status_clr register - * M0 status clear register + * HP_APM_CTRL M0 status clear register */ typedef union { struct { @@ -175,23 +171,21 @@ typedef union { uint32_t val; } hp_apm_m0_status_clr_reg_t; - -/** Group: M0 exception_info0 register */ /** Type of m0_exception_info0 register - * M0 exception_info0 register + * HP_APM_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m0_exception_region:16; /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m0_exception_mode:2; /** m0_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m0_exception_id:5; uint32_t reserved_23:9; @@ -199,32 +193,28 @@ typedef union { uint32_t val; } hp_apm_m0_exception_info0_reg_t; - -/** Group: M0 exception_info1 register */ /** Type of m0_exception_info1 register - * M0 exception_info1 register + * HP_APM_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m0_exception_addr:32; }; uint32_t val; } hp_apm_m0_exception_info1_reg_t; - -/** Group: M1 status register */ /** Type of m1_status register - * M1 status register + * HP_APM_CTRL M1 status register */ typedef union { struct { /** m1_exception_status : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m1_exception_status:2; uint32_t reserved_2:30; @@ -232,10 +222,8 @@ typedef union { uint32_t val; } hp_apm_m1_status_reg_t; - -/** Group: M1 status clear register */ /** Type of m1_status_clr register - * M1 status clear register + * HP_APM_CTRL M1 status clear register */ typedef union { struct { @@ -248,23 +236,21 @@ typedef union { uint32_t val; } hp_apm_m1_status_clr_reg_t; - -/** Group: M1 exception_info0 register */ /** Type of m1_exception_info0 register - * M1 exception_info0 register + * HP_APM_CTRL M1 exception information register */ typedef union { struct { /** m1_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m1_exception_region:16; /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m1_exception_mode:2; /** m1_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m1_exception_id:5; uint32_t reserved_23:9; @@ -272,32 +258,28 @@ typedef union { uint32_t val; } hp_apm_m1_exception_info0_reg_t; - -/** Group: M1 exception_info1 register */ /** Type of m1_exception_info1 register - * M1 exception_info1 register + * HP_APM_CTRL M1 exception information register */ typedef union { struct { /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m1_exception_addr:32; }; uint32_t val; } hp_apm_m1_exception_info1_reg_t; - -/** Group: M2 status register */ /** Type of m2_status register - * M2 status register + * HP_APM_CTRL M2 status register */ typedef union { struct { /** m2_exception_status : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m2_exception_status:2; uint32_t reserved_2:30; @@ -305,10 +287,8 @@ typedef union { uint32_t val; } hp_apm_m2_status_reg_t; - -/** Group: M2 status clear register */ /** Type of m2_status_clr register - * M2 status clear register + * HP_APM_CTRL M2 status clear register */ typedef union { struct { @@ -321,23 +301,21 @@ typedef union { uint32_t val; } hp_apm_m2_status_clr_reg_t; - -/** Group: M2 exception_info0 register */ /** Type of m2_exception_info0 register - * M2 exception_info0 register + * HP_APM_CTRL M2 exception information register */ typedef union { struct { /** m2_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m2_exception_region:16; /** m2_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m2_exception_mode:2; /** m2_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m2_exception_id:5; uint32_t reserved_23:9; @@ -345,32 +323,28 @@ typedef union { uint32_t val; } hp_apm_m2_exception_info0_reg_t; - -/** Group: M2 exception_info1 register */ /** Type of m2_exception_info1 register - * M2 exception_info1 register + * HP_APM_CTRL M2 exception information register */ typedef union { struct { /** m2_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m2_exception_addr:32; }; uint32_t val; } hp_apm_m2_exception_info1_reg_t; - -/** Group: M3 status register */ /** Type of m3_status register - * M3 status register + * HP_APM_CTRL M3 status register */ typedef union { struct { /** m3_exception_status : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m3_exception_status:2; uint32_t reserved_2:30; @@ -378,10 +352,8 @@ typedef union { uint32_t val; } hp_apm_m3_status_reg_t; - -/** Group: M3 status clear register */ /** Type of m3_status_clr register - * M3 status clear register + * HP_APM_CTRL M3 status clear register */ typedef union { struct { @@ -394,23 +366,21 @@ typedef union { uint32_t val; } hp_apm_m3_status_clr_reg_t; - -/** Group: M3 exception_info0 register */ /** Type of m3_exception_info0 register - * M3 exception_info0 register + * HP_APM_CTRL M3 exception information register */ typedef union { struct { /** m3_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m3_exception_region:16; /** m3_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m3_exception_mode:2; /** m3_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m3_exception_id:5; uint32_t reserved_23:9; @@ -418,32 +388,28 @@ typedef union { uint32_t val; } hp_apm_m3_exception_info0_reg_t; - -/** Group: M3 exception_info1 register */ /** Type of m3_exception_info1 register - * M3 exception_info1 register + * HP_APM_CTRL M3 exception information register */ typedef union { struct { /** m3_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m3_exception_addr:32; }; uint32_t val; } hp_apm_m3_exception_info1_reg_t; - -/** Group: M4 status register */ /** Type of m4_status register - * M4 status register + * HP_APM_CTRL M4 status register */ typedef union { struct { /** m4_exception_status : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m4_exception_status:2; uint32_t reserved_2:30; @@ -451,10 +417,8 @@ typedef union { uint32_t val; } hp_apm_m4_status_reg_t; - -/** Group: M4 status clear register */ /** Type of m4_status_clr register - * M4 status clear register + * HP_APM_CTRL M4 status clear register */ typedef union { struct { @@ -467,23 +431,21 @@ typedef union { uint32_t val; } hp_apm_m4_status_clr_reg_t; - -/** Group: M4 exception_info0 register */ /** Type of m4_exception_info0 register - * M4 exception_info0 register + * HP_APM_CTRL M4 exception information register */ typedef union { struct { /** m4_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m4_exception_region:16; /** m4_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m4_exception_mode:2; /** m4_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m4_exception_id:5; uint32_t reserved_23:9; @@ -491,15 +453,13 @@ typedef union { uint32_t val; } hp_apm_m4_exception_info0_reg_t; - -/** Group: M4 exception_info1 register */ /** Type of m4_exception_info1 register - * M4 exception_info1 register + * HP_APM_CTRL M4 exception information register */ typedef union { struct { /** m4_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m4_exception_addr:32; }; @@ -507,40 +467,40 @@ typedef union { } hp_apm_m4_exception_info1_reg_t; -/** Group: APM interrupt enable register */ +/** Group: Interrupt Registers */ /** Type of int_en register - * APM interrupt enable register + * HP_APM_CTRL M0/1/2/3/4 interrupt enable register */ typedef union { struct { /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; - * Configures to enable APM M0 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m0_apm_int_en:1; /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; - * Configures to enable APM M1 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M1 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m1_apm_int_en:1; /** m2_apm_int_en : R/W; bitpos: [2]; default: 0; - * Configures to enable APM M2 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M2 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m2_apm_int_en:1; /** m3_apm_int_en : R/W; bitpos: [3]; default: 0; - * Configures to enable APM M3 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M3 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m3_apm_int_en:1; /** m4_apm_int_en : R/W; bitpos: [4]; default: 0; - * Configures to enable APM M4 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M4 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m4_apm_int_en:1; uint32_t reserved_5:27; @@ -549,16 +509,16 @@ typedef union { } hp_apm_int_en_reg_t; -/** Group: Clock gating register */ +/** Group: Clock Gating Registers */ /** Type of clock_gate register * Clock gating register */ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; - * Configures whether to keep the clock always on.\\ - * 0: enable automatic clock gating \\ - * 1: keep the clock always on \\ + * Configures whether to keep the clock always on. + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -567,7 +527,7 @@ typedef union { } hp_apm_clock_gate_reg_t; -/** Group: Version control register */ +/** Group: Version Control Registers */ /** Type of date register * Version control register */ diff --git a/components/soc/esp32c5/register/soc/lp_apm0_reg.h b/components/soc/esp32c5/register/soc/lp_apm0_reg.h index 789db5cd27..c9850a0f10 100644 --- a/components/soc/esp32c5/register/soc/lp_apm0_reg.h +++ b/components/soc/esp32c5/register/soc/lp_apm0_reg.h @@ -12,13 +12,13 @@ extern "C" { #endif /** LP_APM0_REGION_FILTER_EN_REG register - * Region filter enable register + * Region enable register */ #define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0) /** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1; - * Configure bit $n(0-7) to enable region $n. - * 0: disable - * 1: enable + * Configure bit $n (0-7) to enable region $n (0-7). + * 0: Disable + * 1: Enable */ #define LP_APM0_REGION_FILTER_EN 0x000000FFU #define LP_APM0_REGION_FILTER_EN_M (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S) @@ -30,7 +30,7 @@ extern "C" { */ #define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4) /** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 0 + * Configures the start address of region 0. */ #define LP_APM0_REGION0_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION0_ADDR_START_M (LP_APM0_REGION0_ADDR_START_V << LP_APM0_REGION0_ADDR_START_S) @@ -42,7 +42,7 @@ extern "C" { */ #define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x8) /** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 0 + * Configures the end address of region 0. */ #define LP_APM0_REGION0_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION0_ADDR_END_M (LP_APM0_REGION0_ADDR_END_V << LP_APM0_REGION0_ADDR_END_S) @@ -50,74 +50,78 @@ extern "C" { #define LP_APM0_REGION0_ADDR_END_S 0 /** LP_APM0_REGION0_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION0_ATTR_REG (DR_REG_LP_APM0_BASE + 0xc) /** LP_APM0_REGION0_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 0. + * Configures the execution permission in region 0 in REE0 mode. */ #define LP_APM0_REGION0_R0_X (BIT(0)) #define LP_APM0_REGION0_R0_X_M (LP_APM0_REGION0_R0_X_V << LP_APM0_REGION0_R0_X_S) #define LP_APM0_REGION0_R0_X_V 0x00000001U #define LP_APM0_REGION0_R0_X_S 0 /** LP_APM0_REGION0_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 0. + * Configures the write permission in region 0 in REE0 mode. */ #define LP_APM0_REGION0_R0_W (BIT(1)) #define LP_APM0_REGION0_R0_W_M (LP_APM0_REGION0_R0_W_V << LP_APM0_REGION0_R0_W_S) #define LP_APM0_REGION0_R0_W_V 0x00000001U #define LP_APM0_REGION0_R0_W_S 1 /** LP_APM0_REGION0_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 0. + * Configures the read permission in region 0 in REE0 mode. */ #define LP_APM0_REGION0_R0_R (BIT(2)) #define LP_APM0_REGION0_R0_R_M (LP_APM0_REGION0_R0_R_V << LP_APM0_REGION0_R0_R_S) #define LP_APM0_REGION0_R0_R_V 0x00000001U #define LP_APM0_REGION0_R0_R_S 2 /** LP_APM0_REGION0_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 0. + * Configures the execution permission in region 0 in REE1 mode. */ #define LP_APM0_REGION0_R1_X (BIT(4)) #define LP_APM0_REGION0_R1_X_M (LP_APM0_REGION0_R1_X_V << LP_APM0_REGION0_R1_X_S) #define LP_APM0_REGION0_R1_X_V 0x00000001U #define LP_APM0_REGION0_R1_X_S 4 /** LP_APM0_REGION0_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 0. + * Configures the write permission in region 0 in REE1 mode. */ #define LP_APM0_REGION0_R1_W (BIT(5)) #define LP_APM0_REGION0_R1_W_M (LP_APM0_REGION0_R1_W_V << LP_APM0_REGION0_R1_W_S) #define LP_APM0_REGION0_R1_W_V 0x00000001U #define LP_APM0_REGION0_R1_W_S 5 /** LP_APM0_REGION0_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 0. + * Configures the read permission in region 0 in REE1 mode. */ #define LP_APM0_REGION0_R1_R (BIT(6)) #define LP_APM0_REGION0_R1_R_M (LP_APM0_REGION0_R1_R_V << LP_APM0_REGION0_R1_R_S) #define LP_APM0_REGION0_R1_R_V 0x00000001U #define LP_APM0_REGION0_R1_R_S 6 /** LP_APM0_REGION0_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 0. + * Configures the execution permission in region 0 in REE2 mode. */ #define LP_APM0_REGION0_R2_X (BIT(8)) #define LP_APM0_REGION0_R2_X_M (LP_APM0_REGION0_R2_X_V << LP_APM0_REGION0_R2_X_S) #define LP_APM0_REGION0_R2_X_V 0x00000001U #define LP_APM0_REGION0_R2_X_S 8 /** LP_APM0_REGION0_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 0. + * Configures the write permission in region 0 in REE2 mode. */ #define LP_APM0_REGION0_R2_W (BIT(9)) #define LP_APM0_REGION0_R2_W_M (LP_APM0_REGION0_R2_W_V << LP_APM0_REGION0_R2_W_S) #define LP_APM0_REGION0_R2_W_V 0x00000001U #define LP_APM0_REGION0_R2_W_S 9 /** LP_APM0_REGION0_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 0. + * Configures the read permission in region 0 in REE2 mode. */ #define LP_APM0_REGION0_R2_R (BIT(10)) #define LP_APM0_REGION0_R2_R_M (LP_APM0_REGION0_R2_R_V << LP_APM0_REGION0_R2_R_S) #define LP_APM0_REGION0_R2_R_V 0x00000001U #define LP_APM0_REGION0_R2_R_S 10 /** LP_APM0_REGION0_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 0 configuration registers + * (LP_APM0_REGION0_ADDR_START_REG, LP_APM0_REGION0_ADDR_END_REG and + * LP_APM0_REGION0_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION0_LOCK (BIT(11)) #define LP_APM0_REGION0_LOCK_M (LP_APM0_REGION0_LOCK_V << LP_APM0_REGION0_LOCK_S) @@ -129,7 +133,7 @@ extern "C" { */ #define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x10) /** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 1 + * Configures the start address of region 1. */ #define LP_APM0_REGION1_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION1_ADDR_START_M (LP_APM0_REGION1_ADDR_START_V << LP_APM0_REGION1_ADDR_START_S) @@ -141,7 +145,7 @@ extern "C" { */ #define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x14) /** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 1 + * Configures the end address of region 1. */ #define LP_APM0_REGION1_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION1_ADDR_END_M (LP_APM0_REGION1_ADDR_END_V << LP_APM0_REGION1_ADDR_END_S) @@ -149,74 +153,78 @@ extern "C" { #define LP_APM0_REGION1_ADDR_END_S 0 /** LP_APM0_REGION1_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION1_ATTR_REG (DR_REG_LP_APM0_BASE + 0x18) /** LP_APM0_REGION1_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 1. + * Configures the execution permission in region 1 in REE0 mode. */ #define LP_APM0_REGION1_R0_X (BIT(0)) #define LP_APM0_REGION1_R0_X_M (LP_APM0_REGION1_R0_X_V << LP_APM0_REGION1_R0_X_S) #define LP_APM0_REGION1_R0_X_V 0x00000001U #define LP_APM0_REGION1_R0_X_S 0 /** LP_APM0_REGION1_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 1. + * Configures the write permission in region 1 in REE0 mode. */ #define LP_APM0_REGION1_R0_W (BIT(1)) #define LP_APM0_REGION1_R0_W_M (LP_APM0_REGION1_R0_W_V << LP_APM0_REGION1_R0_W_S) #define LP_APM0_REGION1_R0_W_V 0x00000001U #define LP_APM0_REGION1_R0_W_S 1 /** LP_APM0_REGION1_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 1. + * Configures the read permission in region 1 in REE0 mode. */ #define LP_APM0_REGION1_R0_R (BIT(2)) #define LP_APM0_REGION1_R0_R_M (LP_APM0_REGION1_R0_R_V << LP_APM0_REGION1_R0_R_S) #define LP_APM0_REGION1_R0_R_V 0x00000001U #define LP_APM0_REGION1_R0_R_S 2 /** LP_APM0_REGION1_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 1. + * Configures the execution permission in region 1 in REE1 mode. */ #define LP_APM0_REGION1_R1_X (BIT(4)) #define LP_APM0_REGION1_R1_X_M (LP_APM0_REGION1_R1_X_V << LP_APM0_REGION1_R1_X_S) #define LP_APM0_REGION1_R1_X_V 0x00000001U #define LP_APM0_REGION1_R1_X_S 4 /** LP_APM0_REGION1_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 1. + * Configures the write permission in region 1 in REE1 mode. */ #define LP_APM0_REGION1_R1_W (BIT(5)) #define LP_APM0_REGION1_R1_W_M (LP_APM0_REGION1_R1_W_V << LP_APM0_REGION1_R1_W_S) #define LP_APM0_REGION1_R1_W_V 0x00000001U #define LP_APM0_REGION1_R1_W_S 5 /** LP_APM0_REGION1_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 1. + * Configures the read permission in region 1 in REE1 mode. */ #define LP_APM0_REGION1_R1_R (BIT(6)) #define LP_APM0_REGION1_R1_R_M (LP_APM0_REGION1_R1_R_V << LP_APM0_REGION1_R1_R_S) #define LP_APM0_REGION1_R1_R_V 0x00000001U #define LP_APM0_REGION1_R1_R_S 6 /** LP_APM0_REGION1_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 1. + * Configures the execution permission in region 1 in REE2 mode. */ #define LP_APM0_REGION1_R2_X (BIT(8)) #define LP_APM0_REGION1_R2_X_M (LP_APM0_REGION1_R2_X_V << LP_APM0_REGION1_R2_X_S) #define LP_APM0_REGION1_R2_X_V 0x00000001U #define LP_APM0_REGION1_R2_X_S 8 /** LP_APM0_REGION1_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 1. + * Configures the write permission in region 1 in REE2 mode. */ #define LP_APM0_REGION1_R2_W (BIT(9)) #define LP_APM0_REGION1_R2_W_M (LP_APM0_REGION1_R2_W_V << LP_APM0_REGION1_R2_W_S) #define LP_APM0_REGION1_R2_W_V 0x00000001U #define LP_APM0_REGION1_R2_W_S 9 /** LP_APM0_REGION1_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 1. + * Configures the read permission in region 1 in REE2 mode. */ #define LP_APM0_REGION1_R2_R (BIT(10)) #define LP_APM0_REGION1_R2_R_M (LP_APM0_REGION1_R2_R_V << LP_APM0_REGION1_R2_R_S) #define LP_APM0_REGION1_R2_R_V 0x00000001U #define LP_APM0_REGION1_R2_R_S 10 /** LP_APM0_REGION1_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 1 configuration registers + * (LP_APM0_REGION1_ADDR_START_REG, LP_APM0_REGION1_ADDR_END_REG and + * LP_APM0_REGION1_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION1_LOCK (BIT(11)) #define LP_APM0_REGION1_LOCK_M (LP_APM0_REGION1_LOCK_V << LP_APM0_REGION1_LOCK_S) @@ -228,7 +236,7 @@ extern "C" { */ #define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x1c) /** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 2 + * Configures the start address of region 2. */ #define LP_APM0_REGION2_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION2_ADDR_START_M (LP_APM0_REGION2_ADDR_START_V << LP_APM0_REGION2_ADDR_START_S) @@ -240,7 +248,7 @@ extern "C" { */ #define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x20) /** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 2 + * Configures the end address of region 2. */ #define LP_APM0_REGION2_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION2_ADDR_END_M (LP_APM0_REGION2_ADDR_END_V << LP_APM0_REGION2_ADDR_END_S) @@ -248,74 +256,78 @@ extern "C" { #define LP_APM0_REGION2_ADDR_END_S 0 /** LP_APM0_REGION2_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION2_ATTR_REG (DR_REG_LP_APM0_BASE + 0x24) /** LP_APM0_REGION2_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 2. + * Configures the execution permission in region 2 in REE0 mode. */ #define LP_APM0_REGION2_R0_X (BIT(0)) #define LP_APM0_REGION2_R0_X_M (LP_APM0_REGION2_R0_X_V << LP_APM0_REGION2_R0_X_S) #define LP_APM0_REGION2_R0_X_V 0x00000001U #define LP_APM0_REGION2_R0_X_S 0 /** LP_APM0_REGION2_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 2. + * Configures the write permission in region 2 in REE0 mode. */ #define LP_APM0_REGION2_R0_W (BIT(1)) #define LP_APM0_REGION2_R0_W_M (LP_APM0_REGION2_R0_W_V << LP_APM0_REGION2_R0_W_S) #define LP_APM0_REGION2_R0_W_V 0x00000001U #define LP_APM0_REGION2_R0_W_S 1 /** LP_APM0_REGION2_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 2. + * Configures the read permission in region 2 in REE0 mode. */ #define LP_APM0_REGION2_R0_R (BIT(2)) #define LP_APM0_REGION2_R0_R_M (LP_APM0_REGION2_R0_R_V << LP_APM0_REGION2_R0_R_S) #define LP_APM0_REGION2_R0_R_V 0x00000001U #define LP_APM0_REGION2_R0_R_S 2 /** LP_APM0_REGION2_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 2. + * Configures the execution permission in region 2 in REE1 mode. */ #define LP_APM0_REGION2_R1_X (BIT(4)) #define LP_APM0_REGION2_R1_X_M (LP_APM0_REGION2_R1_X_V << LP_APM0_REGION2_R1_X_S) #define LP_APM0_REGION2_R1_X_V 0x00000001U #define LP_APM0_REGION2_R1_X_S 4 /** LP_APM0_REGION2_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 2. + * Configures the write permission in region 2 in REE1 mode. */ #define LP_APM0_REGION2_R1_W (BIT(5)) #define LP_APM0_REGION2_R1_W_M (LP_APM0_REGION2_R1_W_V << LP_APM0_REGION2_R1_W_S) #define LP_APM0_REGION2_R1_W_V 0x00000001U #define LP_APM0_REGION2_R1_W_S 5 /** LP_APM0_REGION2_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 2. + * Configures the read permission in region 2 in REE1 mode. */ #define LP_APM0_REGION2_R1_R (BIT(6)) #define LP_APM0_REGION2_R1_R_M (LP_APM0_REGION2_R1_R_V << LP_APM0_REGION2_R1_R_S) #define LP_APM0_REGION2_R1_R_V 0x00000001U #define LP_APM0_REGION2_R1_R_S 6 /** LP_APM0_REGION2_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 2. + * Configures the execution permission in region 2 in REE2 mode. */ #define LP_APM0_REGION2_R2_X (BIT(8)) #define LP_APM0_REGION2_R2_X_M (LP_APM0_REGION2_R2_X_V << LP_APM0_REGION2_R2_X_S) #define LP_APM0_REGION2_R2_X_V 0x00000001U #define LP_APM0_REGION2_R2_X_S 8 /** LP_APM0_REGION2_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 2. + * Configures the write permission in region 2 in REE2 mode. */ #define LP_APM0_REGION2_R2_W (BIT(9)) #define LP_APM0_REGION2_R2_W_M (LP_APM0_REGION2_R2_W_V << LP_APM0_REGION2_R2_W_S) #define LP_APM0_REGION2_R2_W_V 0x00000001U #define LP_APM0_REGION2_R2_W_S 9 /** LP_APM0_REGION2_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 2. + * Configures the read permission in region 2 in REE2 mode. */ #define LP_APM0_REGION2_R2_R (BIT(10)) #define LP_APM0_REGION2_R2_R_M (LP_APM0_REGION2_R2_R_V << LP_APM0_REGION2_R2_R_S) #define LP_APM0_REGION2_R2_R_V 0x00000001U #define LP_APM0_REGION2_R2_R_S 10 /** LP_APM0_REGION2_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 2 configuration registers + * (LP_APM0_REGION2_ADDR_START_REG, LP_APM0_REGION2_ADDR_END_REG and + * LP_APM0_REGION2_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION2_LOCK (BIT(11)) #define LP_APM0_REGION2_LOCK_M (LP_APM0_REGION2_LOCK_V << LP_APM0_REGION2_LOCK_S) @@ -327,7 +339,7 @@ extern "C" { */ #define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x28) /** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 3 + * Configures the start address of region 3. */ #define LP_APM0_REGION3_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION3_ADDR_START_M (LP_APM0_REGION3_ADDR_START_V << LP_APM0_REGION3_ADDR_START_S) @@ -339,7 +351,7 @@ extern "C" { */ #define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x2c) /** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 3 + * Configures the end address of region 3. */ #define LP_APM0_REGION3_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION3_ADDR_END_M (LP_APM0_REGION3_ADDR_END_V << LP_APM0_REGION3_ADDR_END_S) @@ -347,74 +359,78 @@ extern "C" { #define LP_APM0_REGION3_ADDR_END_S 0 /** LP_APM0_REGION3_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION3_ATTR_REG (DR_REG_LP_APM0_BASE + 0x30) /** LP_APM0_REGION3_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 3. + * Configures the execution permission in region 3 in REE0 mode. */ #define LP_APM0_REGION3_R0_X (BIT(0)) #define LP_APM0_REGION3_R0_X_M (LP_APM0_REGION3_R0_X_V << LP_APM0_REGION3_R0_X_S) #define LP_APM0_REGION3_R0_X_V 0x00000001U #define LP_APM0_REGION3_R0_X_S 0 /** LP_APM0_REGION3_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 3. + * Configures the write permission in region 3 in REE0 mode. */ #define LP_APM0_REGION3_R0_W (BIT(1)) #define LP_APM0_REGION3_R0_W_M (LP_APM0_REGION3_R0_W_V << LP_APM0_REGION3_R0_W_S) #define LP_APM0_REGION3_R0_W_V 0x00000001U #define LP_APM0_REGION3_R0_W_S 1 /** LP_APM0_REGION3_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 3. + * Configures the read permission in region 3 in REE0 mode. */ #define LP_APM0_REGION3_R0_R (BIT(2)) #define LP_APM0_REGION3_R0_R_M (LP_APM0_REGION3_R0_R_V << LP_APM0_REGION3_R0_R_S) #define LP_APM0_REGION3_R0_R_V 0x00000001U #define LP_APM0_REGION3_R0_R_S 2 /** LP_APM0_REGION3_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 3. + * Configures the execution permission in region 3 in REE1 mode. */ #define LP_APM0_REGION3_R1_X (BIT(4)) #define LP_APM0_REGION3_R1_X_M (LP_APM0_REGION3_R1_X_V << LP_APM0_REGION3_R1_X_S) #define LP_APM0_REGION3_R1_X_V 0x00000001U #define LP_APM0_REGION3_R1_X_S 4 /** LP_APM0_REGION3_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 3. + * Configures the write permission in region 3 in REE1 mode. */ #define LP_APM0_REGION3_R1_W (BIT(5)) #define LP_APM0_REGION3_R1_W_M (LP_APM0_REGION3_R1_W_V << LP_APM0_REGION3_R1_W_S) #define LP_APM0_REGION3_R1_W_V 0x00000001U #define LP_APM0_REGION3_R1_W_S 5 /** LP_APM0_REGION3_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 3. + * Configures the read permission in region 3 in REE1 mode. */ #define LP_APM0_REGION3_R1_R (BIT(6)) #define LP_APM0_REGION3_R1_R_M (LP_APM0_REGION3_R1_R_V << LP_APM0_REGION3_R1_R_S) #define LP_APM0_REGION3_R1_R_V 0x00000001U #define LP_APM0_REGION3_R1_R_S 6 /** LP_APM0_REGION3_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 3. + * Configures the execution permission in region 3 in REE2 mode. */ #define LP_APM0_REGION3_R2_X (BIT(8)) #define LP_APM0_REGION3_R2_X_M (LP_APM0_REGION3_R2_X_V << LP_APM0_REGION3_R2_X_S) #define LP_APM0_REGION3_R2_X_V 0x00000001U #define LP_APM0_REGION3_R2_X_S 8 /** LP_APM0_REGION3_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 3. + * Configures the write permission in region 3 in REE2 mode. */ #define LP_APM0_REGION3_R2_W (BIT(9)) #define LP_APM0_REGION3_R2_W_M (LP_APM0_REGION3_R2_W_V << LP_APM0_REGION3_R2_W_S) #define LP_APM0_REGION3_R2_W_V 0x00000001U #define LP_APM0_REGION3_R2_W_S 9 /** LP_APM0_REGION3_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 3. + * Configures the read permission in region 3 in REE2 mode. */ #define LP_APM0_REGION3_R2_R (BIT(10)) #define LP_APM0_REGION3_R2_R_M (LP_APM0_REGION3_R2_R_V << LP_APM0_REGION3_R2_R_S) #define LP_APM0_REGION3_R2_R_V 0x00000001U #define LP_APM0_REGION3_R2_R_S 10 /** LP_APM0_REGION3_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 3 configuration registers + * (LP_APM0_REGION3_ADDR_START_REG, LP_APM0_REGION3_ADDR_END_REG and + * LP_APM0_REGION3_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION3_LOCK (BIT(11)) #define LP_APM0_REGION3_LOCK_M (LP_APM0_REGION3_LOCK_V << LP_APM0_REGION3_LOCK_S) @@ -426,7 +442,7 @@ extern "C" { */ #define LP_APM0_REGION4_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x34) /** LP_APM0_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 4 + * Configures the start address of region 4. */ #define LP_APM0_REGION4_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION4_ADDR_START_M (LP_APM0_REGION4_ADDR_START_V << LP_APM0_REGION4_ADDR_START_S) @@ -438,7 +454,7 @@ extern "C" { */ #define LP_APM0_REGION4_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x38) /** LP_APM0_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 4 + * Configures the end address of region 4. */ #define LP_APM0_REGION4_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION4_ADDR_END_M (LP_APM0_REGION4_ADDR_END_V << LP_APM0_REGION4_ADDR_END_S) @@ -446,74 +462,78 @@ extern "C" { #define LP_APM0_REGION4_ADDR_END_S 0 /** LP_APM0_REGION4_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION4_ATTR_REG (DR_REG_LP_APM0_BASE + 0x3c) /** LP_APM0_REGION4_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 4. + * Configures the execution permission in region 4 in REE0 mode. */ #define LP_APM0_REGION4_R0_X (BIT(0)) #define LP_APM0_REGION4_R0_X_M (LP_APM0_REGION4_R0_X_V << LP_APM0_REGION4_R0_X_S) #define LP_APM0_REGION4_R0_X_V 0x00000001U #define LP_APM0_REGION4_R0_X_S 0 /** LP_APM0_REGION4_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 4. + * Configures the write permission in region 4 in REE0 mode. */ #define LP_APM0_REGION4_R0_W (BIT(1)) #define LP_APM0_REGION4_R0_W_M (LP_APM0_REGION4_R0_W_V << LP_APM0_REGION4_R0_W_S) #define LP_APM0_REGION4_R0_W_V 0x00000001U #define LP_APM0_REGION4_R0_W_S 1 /** LP_APM0_REGION4_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 4. + * Configures the read permission in region 4 in REE0 mode. */ #define LP_APM0_REGION4_R0_R (BIT(2)) #define LP_APM0_REGION4_R0_R_M (LP_APM0_REGION4_R0_R_V << LP_APM0_REGION4_R0_R_S) #define LP_APM0_REGION4_R0_R_V 0x00000001U #define LP_APM0_REGION4_R0_R_S 2 /** LP_APM0_REGION4_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 4. + * Configures the execution permission in region 4 in REE1 mode. */ #define LP_APM0_REGION4_R1_X (BIT(4)) #define LP_APM0_REGION4_R1_X_M (LP_APM0_REGION4_R1_X_V << LP_APM0_REGION4_R1_X_S) #define LP_APM0_REGION4_R1_X_V 0x00000001U #define LP_APM0_REGION4_R1_X_S 4 /** LP_APM0_REGION4_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 4. + * Configures the write permission in region 4 in REE1 mode. */ #define LP_APM0_REGION4_R1_W (BIT(5)) #define LP_APM0_REGION4_R1_W_M (LP_APM0_REGION4_R1_W_V << LP_APM0_REGION4_R1_W_S) #define LP_APM0_REGION4_R1_W_V 0x00000001U #define LP_APM0_REGION4_R1_W_S 5 /** LP_APM0_REGION4_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 4. + * Configures the read permission in region 4 in REE1 mode. */ #define LP_APM0_REGION4_R1_R (BIT(6)) #define LP_APM0_REGION4_R1_R_M (LP_APM0_REGION4_R1_R_V << LP_APM0_REGION4_R1_R_S) #define LP_APM0_REGION4_R1_R_V 0x00000001U #define LP_APM0_REGION4_R1_R_S 6 /** LP_APM0_REGION4_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 4. + * Configures the execution permission in region 4 in REE2 mode. */ #define LP_APM0_REGION4_R2_X (BIT(8)) #define LP_APM0_REGION4_R2_X_M (LP_APM0_REGION4_R2_X_V << LP_APM0_REGION4_R2_X_S) #define LP_APM0_REGION4_R2_X_V 0x00000001U #define LP_APM0_REGION4_R2_X_S 8 /** LP_APM0_REGION4_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 4. + * Configures the write permission in region 4 in REE2 mode. */ #define LP_APM0_REGION4_R2_W (BIT(9)) #define LP_APM0_REGION4_R2_W_M (LP_APM0_REGION4_R2_W_V << LP_APM0_REGION4_R2_W_S) #define LP_APM0_REGION4_R2_W_V 0x00000001U #define LP_APM0_REGION4_R2_W_S 9 /** LP_APM0_REGION4_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 4. + * Configures the read permission in region 4 in REE2 mode. */ #define LP_APM0_REGION4_R2_R (BIT(10)) #define LP_APM0_REGION4_R2_R_M (LP_APM0_REGION4_R2_R_V << LP_APM0_REGION4_R2_R_S) #define LP_APM0_REGION4_R2_R_V 0x00000001U #define LP_APM0_REGION4_R2_R_S 10 /** LP_APM0_REGION4_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 4 configuration registers + * (LP_APM0_REGION4_ADDR_START_REG, LP_APM0_REGION4_ADDR_END_REG and + * LP_APM0_REGION4_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION4_LOCK (BIT(11)) #define LP_APM0_REGION4_LOCK_M (LP_APM0_REGION4_LOCK_V << LP_APM0_REGION4_LOCK_S) @@ -525,7 +545,7 @@ extern "C" { */ #define LP_APM0_REGION5_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x40) /** LP_APM0_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 5 + * Configures the start address of region 5. */ #define LP_APM0_REGION5_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION5_ADDR_START_M (LP_APM0_REGION5_ADDR_START_V << LP_APM0_REGION5_ADDR_START_S) @@ -537,7 +557,7 @@ extern "C" { */ #define LP_APM0_REGION5_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x44) /** LP_APM0_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 5 + * Configures the end address of region 5. */ #define LP_APM0_REGION5_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION5_ADDR_END_M (LP_APM0_REGION5_ADDR_END_V << LP_APM0_REGION5_ADDR_END_S) @@ -545,74 +565,78 @@ extern "C" { #define LP_APM0_REGION5_ADDR_END_S 0 /** LP_APM0_REGION5_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION5_ATTR_REG (DR_REG_LP_APM0_BASE + 0x48) /** LP_APM0_REGION5_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 5. + * Configures the execution permission in region 5 in REE0 mode. */ #define LP_APM0_REGION5_R0_X (BIT(0)) #define LP_APM0_REGION5_R0_X_M (LP_APM0_REGION5_R0_X_V << LP_APM0_REGION5_R0_X_S) #define LP_APM0_REGION5_R0_X_V 0x00000001U #define LP_APM0_REGION5_R0_X_S 0 /** LP_APM0_REGION5_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 5. + * Configures the write permission in region 5 in REE0 mode. */ #define LP_APM0_REGION5_R0_W (BIT(1)) #define LP_APM0_REGION5_R0_W_M (LP_APM0_REGION5_R0_W_V << LP_APM0_REGION5_R0_W_S) #define LP_APM0_REGION5_R0_W_V 0x00000001U #define LP_APM0_REGION5_R0_W_S 1 /** LP_APM0_REGION5_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 5. + * Configures the read permission in region 5 in REE0 mode. */ #define LP_APM0_REGION5_R0_R (BIT(2)) #define LP_APM0_REGION5_R0_R_M (LP_APM0_REGION5_R0_R_V << LP_APM0_REGION5_R0_R_S) #define LP_APM0_REGION5_R0_R_V 0x00000001U #define LP_APM0_REGION5_R0_R_S 2 /** LP_APM0_REGION5_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 5. + * Configures the execution permission in region 5 in REE1 mode. */ #define LP_APM0_REGION5_R1_X (BIT(4)) #define LP_APM0_REGION5_R1_X_M (LP_APM0_REGION5_R1_X_V << LP_APM0_REGION5_R1_X_S) #define LP_APM0_REGION5_R1_X_V 0x00000001U #define LP_APM0_REGION5_R1_X_S 4 /** LP_APM0_REGION5_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 5. + * Configures the write permission in region 5 in REE1 mode. */ #define LP_APM0_REGION5_R1_W (BIT(5)) #define LP_APM0_REGION5_R1_W_M (LP_APM0_REGION5_R1_W_V << LP_APM0_REGION5_R1_W_S) #define LP_APM0_REGION5_R1_W_V 0x00000001U #define LP_APM0_REGION5_R1_W_S 5 /** LP_APM0_REGION5_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 5. + * Configures the read permission in region 5 in REE1 mode. */ #define LP_APM0_REGION5_R1_R (BIT(6)) #define LP_APM0_REGION5_R1_R_M (LP_APM0_REGION5_R1_R_V << LP_APM0_REGION5_R1_R_S) #define LP_APM0_REGION5_R1_R_V 0x00000001U #define LP_APM0_REGION5_R1_R_S 6 /** LP_APM0_REGION5_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 5. + * Configures the execution permission in region 5 in REE2 mode. */ #define LP_APM0_REGION5_R2_X (BIT(8)) #define LP_APM0_REGION5_R2_X_M (LP_APM0_REGION5_R2_X_V << LP_APM0_REGION5_R2_X_S) #define LP_APM0_REGION5_R2_X_V 0x00000001U #define LP_APM0_REGION5_R2_X_S 8 /** LP_APM0_REGION5_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 5. + * Configures the write permission in region 5 in REE2 mode. */ #define LP_APM0_REGION5_R2_W (BIT(9)) #define LP_APM0_REGION5_R2_W_M (LP_APM0_REGION5_R2_W_V << LP_APM0_REGION5_R2_W_S) #define LP_APM0_REGION5_R2_W_V 0x00000001U #define LP_APM0_REGION5_R2_W_S 9 /** LP_APM0_REGION5_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 5. + * Configures the read permission in region 5 in REE2 mode. */ #define LP_APM0_REGION5_R2_R (BIT(10)) #define LP_APM0_REGION5_R2_R_M (LP_APM0_REGION5_R2_R_V << LP_APM0_REGION5_R2_R_S) #define LP_APM0_REGION5_R2_R_V 0x00000001U #define LP_APM0_REGION5_R2_R_S 10 /** LP_APM0_REGION5_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 5 configuration registers + * (LP_APM0_REGION5_ADDR_START_REG, LP_APM0_REGION5_ADDR_END_REG and + * LP_APM0_REGION5_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION5_LOCK (BIT(11)) #define LP_APM0_REGION5_LOCK_M (LP_APM0_REGION5_LOCK_V << LP_APM0_REGION5_LOCK_S) @@ -624,7 +648,7 @@ extern "C" { */ #define LP_APM0_REGION6_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4c) /** LP_APM0_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 6 + * Configures the start address of region 6. */ #define LP_APM0_REGION6_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION6_ADDR_START_M (LP_APM0_REGION6_ADDR_START_V << LP_APM0_REGION6_ADDR_START_S) @@ -636,7 +660,7 @@ extern "C" { */ #define LP_APM0_REGION6_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x50) /** LP_APM0_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 6 + * Configures the end address of region 6. */ #define LP_APM0_REGION6_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION6_ADDR_END_M (LP_APM0_REGION6_ADDR_END_V << LP_APM0_REGION6_ADDR_END_S) @@ -644,74 +668,78 @@ extern "C" { #define LP_APM0_REGION6_ADDR_END_S 0 /** LP_APM0_REGION6_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION6_ATTR_REG (DR_REG_LP_APM0_BASE + 0x54) /** LP_APM0_REGION6_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 6. + * Configures the execution permission in region 6 in REE0 mode. */ #define LP_APM0_REGION6_R0_X (BIT(0)) #define LP_APM0_REGION6_R0_X_M (LP_APM0_REGION6_R0_X_V << LP_APM0_REGION6_R0_X_S) #define LP_APM0_REGION6_R0_X_V 0x00000001U #define LP_APM0_REGION6_R0_X_S 0 /** LP_APM0_REGION6_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 6. + * Configures the write permission in region 6 in REE0 mode. */ #define LP_APM0_REGION6_R0_W (BIT(1)) #define LP_APM0_REGION6_R0_W_M (LP_APM0_REGION6_R0_W_V << LP_APM0_REGION6_R0_W_S) #define LP_APM0_REGION6_R0_W_V 0x00000001U #define LP_APM0_REGION6_R0_W_S 1 /** LP_APM0_REGION6_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 6. + * Configures the read permission in region 6 in REE0 mode. */ #define LP_APM0_REGION6_R0_R (BIT(2)) #define LP_APM0_REGION6_R0_R_M (LP_APM0_REGION6_R0_R_V << LP_APM0_REGION6_R0_R_S) #define LP_APM0_REGION6_R0_R_V 0x00000001U #define LP_APM0_REGION6_R0_R_S 2 /** LP_APM0_REGION6_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 6. + * Configures the execution permission in region 6 in REE1 mode. */ #define LP_APM0_REGION6_R1_X (BIT(4)) #define LP_APM0_REGION6_R1_X_M (LP_APM0_REGION6_R1_X_V << LP_APM0_REGION6_R1_X_S) #define LP_APM0_REGION6_R1_X_V 0x00000001U #define LP_APM0_REGION6_R1_X_S 4 /** LP_APM0_REGION6_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 6. + * Configures the write permission in region 6 in REE1 mode. */ #define LP_APM0_REGION6_R1_W (BIT(5)) #define LP_APM0_REGION6_R1_W_M (LP_APM0_REGION6_R1_W_V << LP_APM0_REGION6_R1_W_S) #define LP_APM0_REGION6_R1_W_V 0x00000001U #define LP_APM0_REGION6_R1_W_S 5 /** LP_APM0_REGION6_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 6. + * Configures the read permission in region 6 in REE1 mode. */ #define LP_APM0_REGION6_R1_R (BIT(6)) #define LP_APM0_REGION6_R1_R_M (LP_APM0_REGION6_R1_R_V << LP_APM0_REGION6_R1_R_S) #define LP_APM0_REGION6_R1_R_V 0x00000001U #define LP_APM0_REGION6_R1_R_S 6 /** LP_APM0_REGION6_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 6. + * Configures the execution permission in region 6 in REE2 mode. */ #define LP_APM0_REGION6_R2_X (BIT(8)) #define LP_APM0_REGION6_R2_X_M (LP_APM0_REGION6_R2_X_V << LP_APM0_REGION6_R2_X_S) #define LP_APM0_REGION6_R2_X_V 0x00000001U #define LP_APM0_REGION6_R2_X_S 8 /** LP_APM0_REGION6_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 6. + * Configures the write permission in region 6 in REE2 mode. */ #define LP_APM0_REGION6_R2_W (BIT(9)) #define LP_APM0_REGION6_R2_W_M (LP_APM0_REGION6_R2_W_V << LP_APM0_REGION6_R2_W_S) #define LP_APM0_REGION6_R2_W_V 0x00000001U #define LP_APM0_REGION6_R2_W_S 9 /** LP_APM0_REGION6_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 6. + * Configures the read permission in region 6 in REE2 mode. */ #define LP_APM0_REGION6_R2_R (BIT(10)) #define LP_APM0_REGION6_R2_R_M (LP_APM0_REGION6_R2_R_V << LP_APM0_REGION6_R2_R_S) #define LP_APM0_REGION6_R2_R_V 0x00000001U #define LP_APM0_REGION6_R2_R_S 10 /** LP_APM0_REGION6_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 6 configuration registers + * (LP_APM0_REGION6_ADDR_START_REG, LP_APM0_REGION6_ADDR_END_REG and + * LP_APM0_REGION6_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION6_LOCK (BIT(11)) #define LP_APM0_REGION6_LOCK_M (LP_APM0_REGION6_LOCK_V << LP_APM0_REGION6_LOCK_S) @@ -723,7 +751,7 @@ extern "C" { */ #define LP_APM0_REGION7_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x58) /** LP_APM0_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 7 + * Configures the start address of region 7. */ #define LP_APM0_REGION7_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION7_ADDR_START_M (LP_APM0_REGION7_ADDR_START_V << LP_APM0_REGION7_ADDR_START_S) @@ -735,7 +763,7 @@ extern "C" { */ #define LP_APM0_REGION7_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x5c) /** LP_APM0_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 7 + * Configures the end address of region 7. */ #define LP_APM0_REGION7_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION7_ADDR_END_M (LP_APM0_REGION7_ADDR_END_V << LP_APM0_REGION7_ADDR_END_S) @@ -743,74 +771,78 @@ extern "C" { #define LP_APM0_REGION7_ADDR_END_S 0 /** LP_APM0_REGION7_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION7_ATTR_REG (DR_REG_LP_APM0_BASE + 0x60) /** LP_APM0_REGION7_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 7. + * Configures the execution permission in region 7 in REE0 mode. */ #define LP_APM0_REGION7_R0_X (BIT(0)) #define LP_APM0_REGION7_R0_X_M (LP_APM0_REGION7_R0_X_V << LP_APM0_REGION7_R0_X_S) #define LP_APM0_REGION7_R0_X_V 0x00000001U #define LP_APM0_REGION7_R0_X_S 0 /** LP_APM0_REGION7_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 7. + * Configures the write permission in region 7 in REE0 mode. */ #define LP_APM0_REGION7_R0_W (BIT(1)) #define LP_APM0_REGION7_R0_W_M (LP_APM0_REGION7_R0_W_V << LP_APM0_REGION7_R0_W_S) #define LP_APM0_REGION7_R0_W_V 0x00000001U #define LP_APM0_REGION7_R0_W_S 1 /** LP_APM0_REGION7_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 7. + * Configures the read permission in region 7 in REE0 mode. */ #define LP_APM0_REGION7_R0_R (BIT(2)) #define LP_APM0_REGION7_R0_R_M (LP_APM0_REGION7_R0_R_V << LP_APM0_REGION7_R0_R_S) #define LP_APM0_REGION7_R0_R_V 0x00000001U #define LP_APM0_REGION7_R0_R_S 2 /** LP_APM0_REGION7_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 7. + * Configures the execution permission in region 7 in REE1 mode. */ #define LP_APM0_REGION7_R1_X (BIT(4)) #define LP_APM0_REGION7_R1_X_M (LP_APM0_REGION7_R1_X_V << LP_APM0_REGION7_R1_X_S) #define LP_APM0_REGION7_R1_X_V 0x00000001U #define LP_APM0_REGION7_R1_X_S 4 /** LP_APM0_REGION7_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 7. + * Configures the write permission in region 7 in REE1 mode. */ #define LP_APM0_REGION7_R1_W (BIT(5)) #define LP_APM0_REGION7_R1_W_M (LP_APM0_REGION7_R1_W_V << LP_APM0_REGION7_R1_W_S) #define LP_APM0_REGION7_R1_W_V 0x00000001U #define LP_APM0_REGION7_R1_W_S 5 /** LP_APM0_REGION7_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 7. + * Configures the read permission in region 7 in REE1 mode. */ #define LP_APM0_REGION7_R1_R (BIT(6)) #define LP_APM0_REGION7_R1_R_M (LP_APM0_REGION7_R1_R_V << LP_APM0_REGION7_R1_R_S) #define LP_APM0_REGION7_R1_R_V 0x00000001U #define LP_APM0_REGION7_R1_R_S 6 /** LP_APM0_REGION7_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 7. + * Configures the execution permission in region 7 in REE2 mode. */ #define LP_APM0_REGION7_R2_X (BIT(8)) #define LP_APM0_REGION7_R2_X_M (LP_APM0_REGION7_R2_X_V << LP_APM0_REGION7_R2_X_S) #define LP_APM0_REGION7_R2_X_V 0x00000001U #define LP_APM0_REGION7_R2_X_S 8 /** LP_APM0_REGION7_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 7. + * Configures the write permission in region 7 in REE2 mode. */ #define LP_APM0_REGION7_R2_W (BIT(9)) #define LP_APM0_REGION7_R2_W_M (LP_APM0_REGION7_R2_W_V << LP_APM0_REGION7_R2_W_S) #define LP_APM0_REGION7_R2_W_V 0x00000001U #define LP_APM0_REGION7_R2_W_S 9 /** LP_APM0_REGION7_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 7. + * Configures the read permission in region 7 in REE2 mode. */ #define LP_APM0_REGION7_R2_R (BIT(10)) #define LP_APM0_REGION7_R2_R_M (LP_APM0_REGION7_R2_R_V << LP_APM0_REGION7_R2_R_S) #define LP_APM0_REGION7_R2_R_V 0x00000001U #define LP_APM0_REGION7_R2_R_S 10 /** LP_APM0_REGION7_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 7 configuration registers + * (LP_APM0_REGION7_ADDR_START_REG, LP_APM0_REGION7_ADDR_END_REG and + * LP_APM0_REGION7_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION7_LOCK (BIT(11)) #define LP_APM0_REGION7_LOCK_M (LP_APM0_REGION7_LOCK_V << LP_APM0_REGION7_LOCK_S) @@ -818,11 +850,11 @@ extern "C" { #define LP_APM0_REGION7_LOCK_S 11 /** LP_APM0_FUNC_CTRL_REG register - * APM function control register + * APM access path permission management register */ #define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_APM0_BASE + 0xc4) /** LP_APM0_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures to enable permission management for LP_APM0_CTRL M0. */ #define LP_APM0_M0_FUNC_EN (BIT(0)) #define LP_APM0_M0_FUNC_EN_M (LP_APM0_M0_FUNC_EN_V << LP_APM0_M0_FUNC_EN_S) @@ -830,13 +862,13 @@ extern "C" { #define LP_APM0_M0_FUNC_EN_S 0 /** LP_APM0_M0_STATUS_REG register - * M0 status register + * LP_APM0_CTRL M0 status register */ #define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8) /** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define LP_APM0_M0_EXCEPTION_STATUS 0x00000003U #define LP_APM0_M0_EXCEPTION_STATUS_M (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S) @@ -844,11 +876,11 @@ extern "C" { #define LP_APM0_M0_EXCEPTION_STATUS_S 0 /** LP_APM0_M0_STATUS_CLR_REG register - * M0 status clear register + * LP_APM0_CTRL M0 status clear register */ #define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_APM0_BASE + 0xcc) /** LP_APM0_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; - * Configures to clear exception status + * Configures to clear exception status. */ #define LP_APM0_M0_EXCEPTION_STATUS_CLR (BIT(0)) #define LP_APM0_M0_EXCEPTION_STATUS_CLR_M (LP_APM0_M0_EXCEPTION_STATUS_CLR_V << LP_APM0_M0_EXCEPTION_STATUS_CLR_S) @@ -856,25 +888,25 @@ extern "C" { #define LP_APM0_M0_EXCEPTION_STATUS_CLR_S 0 /** LP_APM0_M0_EXCEPTION_INFO0_REG register - * M0 exception_info0 register + * LP_APM0_CTRL M0 exception information register */ #define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0) /** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0; - * Represents exception region + * Represents the region where an exception occurs. */ #define LP_APM0_M0_EXCEPTION_REGION 0x000000FFU #define LP_APM0_M0_EXCEPTION_REGION_M (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S) #define LP_APM0_M0_EXCEPTION_REGION_V 0x000000FFU #define LP_APM0_M0_EXCEPTION_REGION_S 0 /** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode + * Represents the master's security mode when an exception occurs. */ #define LP_APM0_M0_EXCEPTION_MODE 0x00000003U #define LP_APM0_M0_EXCEPTION_MODE_M (LP_APM0_M0_EXCEPTION_MODE_V << LP_APM0_M0_EXCEPTION_MODE_S) #define LP_APM0_M0_EXCEPTION_MODE_V 0x00000003U #define LP_APM0_M0_EXCEPTION_MODE_S 16 /** LP_APM0_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information + * Represents master ID when an exception occurs. */ #define LP_APM0_M0_EXCEPTION_ID 0x0000001FU #define LP_APM0_M0_EXCEPTION_ID_M (LP_APM0_M0_EXCEPTION_ID_V << LP_APM0_M0_EXCEPTION_ID_S) @@ -882,11 +914,11 @@ extern "C" { #define LP_APM0_M0_EXCEPTION_ID_S 18 /** LP_APM0_M0_EXCEPTION_INFO1_REG register - * M0 exception_info1 register + * LP_APM0_CTRL M0 exception information register */ #define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM0_BASE + 0xd4) /** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr + * Represents the access address when an exception occurs. */ #define LP_APM0_M0_EXCEPTION_ADDR 0xFFFFFFFFU #define LP_APM0_M0_EXCEPTION_ADDR_M (LP_APM0_M0_EXCEPTION_ADDR_V << LP_APM0_M0_EXCEPTION_ADDR_S) @@ -894,13 +926,13 @@ extern "C" { #define LP_APM0_M0_EXCEPTION_ADDR_S 0 /** LP_APM0_INT_EN_REG register - * APM interrupt enable register + * LP_APM0_CTRL interrupt enable register */ #define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8) /** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; - * Configures APM M0 interrupt enable. - * 0: disable - * 1: enable + * Configures to enable LP_APM0_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ #define LP_APM0_M0_APM_INT_EN (BIT(0)) #define LP_APM0_M0_APM_INT_EN_M (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S) @@ -913,8 +945,8 @@ extern "C" { #define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc) /** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ #define LP_APM0_CLK_EN (BIT(0)) #define LP_APM0_CLK_EN_M (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S) @@ -926,7 +958,7 @@ extern "C" { */ #define LP_APM0_DATE_REG (DR_REG_LP_APM0_BASE + 0x7fc) /** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35725664; - * Version control register + * Version control register. */ #define LP_APM0_DATE 0x0FFFFFFFU #define LP_APM0_DATE_M (LP_APM0_DATE_V << LP_APM0_DATE_S) diff --git a/components/soc/esp32c5/register/soc/lp_apm0_struct.h b/components/soc/esp32c5/register/soc/lp_apm0_struct.h index 542cbede30..bc09871187 100644 --- a/components/soc/esp32c5/register/soc/lp_apm0_struct.h +++ b/components/soc/esp32c5/register/soc/lp_apm0_struct.h @@ -10,16 +10,16 @@ extern "C" { #endif -/** Group: Region filter enable register */ +/** Group: Configuration Registers */ /** Type of region_filter_en register - * Region filter enable register + * Region enable register */ typedef union { struct { /** region_filter_en : R/W; bitpos: [7:0]; default: 1; - * Configure bit $n(0-7) to enable region $n. - * 0: disable - * 1: enable + * Configure bit $n (0-7) to enable region $n (0-7). + * 0: Disable + * 1: Enable */ uint32_t region_filter_en:8; uint32_t reserved_8:24; @@ -27,15 +27,13 @@ typedef union { uint32_t val; } lp_apm0_region_filter_en_reg_t; - -/** Group: Region address register */ /** Type of regionn_addr_start register * Region address register */ typedef union { struct { /** regionn_addr_start : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region n + * Configures the start address of region n. */ uint32_t regionn_addr_start:32; }; @@ -48,60 +46,62 @@ typedef union { typedef union { struct { /** regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region n + * Configures the end address of region n. */ uint32_t regionn_addr_end:32; }; uint32_t val; } lp_apm0_regionn_addr_end_reg_t; - -/** Group: Region access authority attribute register */ /** Type of regionn_attr register - * Region access authority attribute register + * Region access permissions configuration register */ typedef union { struct { /** regionn_r0_x : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region n. + * Configures the execution permission in region n in REE0 mode. */ uint32_t regionn_r0_x:1; /** regionn_r0_w : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region n. + * Configures the write permission in region n in REE0 mode. */ uint32_t regionn_r0_w:1; /** regionn_r0_r : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region n. + * Configures the read permission in region n in REE0 mode. */ uint32_t regionn_r0_r:1; uint32_t reserved_3:1; /** regionn_r1_x : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region n. + * Configures the execution permission in region n in REE1 mode. */ uint32_t regionn_r1_x:1; /** regionn_r1_w : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region n. + * Configures the write permission in region n in REE1 mode. */ uint32_t regionn_r1_w:1; /** regionn_r1_r : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region n. + * Configures the read permission in region n in REE1 mode. */ uint32_t regionn_r1_r:1; uint32_t reserved_7:1; /** regionn_r2_x : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region n. + * Configures the execution permission in region n in REE2 mode. */ uint32_t regionn_r2_x:1; /** regionn_r2_w : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region n. + * Configures the write permission in region n in REE2 mode. */ uint32_t regionn_r2_w:1; /** regionn_r2_r : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region n. + * Configures the read permission in region n in REE2 mode. */ uint32_t regionn_r2_r:1; /** regionn_lock : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region n configuration registers + * (LP_APM0_REGIONn_ADDR_START_REG, LP_APM0_REGIONn_ADDR_END_REG and + * LP_APM0_REGIONn_ATTR_REG). + * 0: Do not lock + * 1: Lock */ uint32_t regionn_lock:1; uint32_t reserved_12:20; @@ -109,15 +109,13 @@ typedef union { uint32_t val; } lp_apm0_regionn_attr_reg_t; - -/** Group: APM function control register */ /** Type of func_ctrl register - * APM function control register + * APM access path permission management register */ typedef union { struct { /** m0_func_en : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures to enable permission management for LP_APM0_CTRL M0. */ uint32_t m0_func_en:1; uint32_t reserved_1:31; @@ -126,16 +124,16 @@ typedef union { } lp_apm0_func_ctrl_reg_t; -/** Group: M0 status register */ +/** Group: Status Registers */ /** Type of m0_status register - * M0 status register + * LP_APM0_CTRL M0 status register */ typedef union { struct { /** m0_exception_status : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m0_exception_status:2; uint32_t reserved_2:30; @@ -143,15 +141,13 @@ typedef union { uint32_t val; } lp_apm0_m0_status_reg_t; - -/** Group: M0 status clear register */ /** Type of m0_status_clr register - * M0 status clear register + * LP_APM0_CTRL M0 status clear register */ typedef union { struct { /** m0_exception_status_clr : WT; bitpos: [0]; default: 0; - * Configures to clear exception status + * Configures to clear exception status. */ uint32_t m0_exception_status_clr:1; uint32_t reserved_1:31; @@ -159,24 +155,22 @@ typedef union { uint32_t val; } lp_apm0_m0_status_clr_reg_t; - -/** Group: M0 exception_info0 register */ /** Type of m0_exception_info0 register - * M0 exception_info0 register + * LP_APM0_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_region : RO; bitpos: [7:0]; default: 0; - * Represents exception region + * Represents the region where an exception occurs. */ uint32_t m0_exception_region:8; uint32_t reserved_8:8; /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode + * Represents the master's security mode when an exception occurs. */ uint32_t m0_exception_mode:2; /** m0_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information + * Represents master ID when an exception occurs. */ uint32_t m0_exception_id:5; uint32_t reserved_23:9; @@ -184,15 +178,13 @@ typedef union { uint32_t val; } lp_apm0_m0_exception_info0_reg_t; - -/** Group: M0 exception_info1 register */ /** Type of m0_exception_info1 register - * M0 exception_info1 register + * LP_APM0_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr + * Represents the access address when an exception occurs. */ uint32_t m0_exception_addr:32; }; @@ -200,16 +192,16 @@ typedef union { } lp_apm0_m0_exception_info1_reg_t; -/** Group: APM interrupt enable register */ +/** Group: Interrupt Registers */ /** Type of int_en register - * APM interrupt enable register + * LP_APM0_CTRL interrupt enable register */ typedef union { struct { /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; - * Configures APM M0 interrupt enable. - * 0: disable - * 1: enable + * Configures to enable LP_APM0_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m0_apm_int_en:1; uint32_t reserved_1:31; @@ -218,7 +210,7 @@ typedef union { } lp_apm0_int_en_reg_t; -/** Group: Clock gating register */ +/** Group: Clock Gating Registers */ /** Type of clock_gate register * Clock gating register */ @@ -226,8 +218,8 @@ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -236,14 +228,14 @@ typedef union { } lp_apm0_clock_gate_reg_t; -/** Group: Version control register */ +/** Group: Version Control Registers */ /** Type of date register * Version control register */ typedef union { struct { /** date : R/W; bitpos: [27:0]; default: 35725664; - * Version control register + * Version control register. */ uint32_t date:28; uint32_t reserved_28:4; diff --git a/components/soc/esp32c5/register/soc/lp_apm_reg.h b/components/soc/esp32c5/register/soc/lp_apm_reg.h index 9e4e42c55e..2a91284eca 100644 --- a/components/soc/esp32c5/register/soc/lp_apm_reg.h +++ b/components/soc/esp32c5/register/soc/lp_apm_reg.h @@ -12,13 +12,13 @@ extern "C" { #endif /** LP_APM_REGION_FILTER_EN_REG register - * Region filter enable register + * Region enable register */ #define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0) /** LP_APM_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1; - * Configure bit $n (0-7) to enable region $n. - * 0: disable - * 1: enable + * Configure bit $n (0-7) to enable region $n (0-7). + * 0: Disable + * 1: Enable */ #define LP_APM_REGION_FILTER_EN 0x000000FFU #define LP_APM_REGION_FILTER_EN_M (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S) @@ -30,7 +30,7 @@ extern "C" { */ #define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4) /** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 0. + * Configures the start address of region 0. */ #define LP_APM_REGION0_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION0_ADDR_START_M (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S) @@ -42,7 +42,7 @@ extern "C" { */ #define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8) /** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 0. + * Configures the end address of region 0. */ #define LP_APM_REGION0_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION0_ADDR_END_M (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S) @@ -50,74 +50,78 @@ extern "C" { #define LP_APM_REGION0_ADDR_END_S 0 /** LP_APM_REGION0_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION0_ATTR_REG (DR_REG_LP_APM_BASE + 0xc) /** LP_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 0. + * Configures the execution permission in region 0 in REE0 mode. */ #define LP_APM_REGION0_R0_X (BIT(0)) #define LP_APM_REGION0_R0_X_M (LP_APM_REGION0_R0_X_V << LP_APM_REGION0_R0_X_S) #define LP_APM_REGION0_R0_X_V 0x00000001U #define LP_APM_REGION0_R0_X_S 0 /** LP_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 0. + * Configures the write permission in region 0 in REE0 mode. */ #define LP_APM_REGION0_R0_W (BIT(1)) #define LP_APM_REGION0_R0_W_M (LP_APM_REGION0_R0_W_V << LP_APM_REGION0_R0_W_S) #define LP_APM_REGION0_R0_W_V 0x00000001U #define LP_APM_REGION0_R0_W_S 1 /** LP_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 0. + * Configures the read permission in region 0 in REE0 mode. */ #define LP_APM_REGION0_R0_R (BIT(2)) #define LP_APM_REGION0_R0_R_M (LP_APM_REGION0_R0_R_V << LP_APM_REGION0_R0_R_S) #define LP_APM_REGION0_R0_R_V 0x00000001U #define LP_APM_REGION0_R0_R_S 2 /** LP_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 0. + * Configures the execution permission in region 0 in REE1 mode. */ #define LP_APM_REGION0_R1_X (BIT(4)) #define LP_APM_REGION0_R1_X_M (LP_APM_REGION0_R1_X_V << LP_APM_REGION0_R1_X_S) #define LP_APM_REGION0_R1_X_V 0x00000001U #define LP_APM_REGION0_R1_X_S 4 /** LP_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 0. + * Configures the write permission in region 0 in REE1 mode. */ #define LP_APM_REGION0_R1_W (BIT(5)) #define LP_APM_REGION0_R1_W_M (LP_APM_REGION0_R1_W_V << LP_APM_REGION0_R1_W_S) #define LP_APM_REGION0_R1_W_V 0x00000001U #define LP_APM_REGION0_R1_W_S 5 /** LP_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 0. + * Configures the read permission in region 0 in REE1 mode. */ #define LP_APM_REGION0_R1_R (BIT(6)) #define LP_APM_REGION0_R1_R_M (LP_APM_REGION0_R1_R_V << LP_APM_REGION0_R1_R_S) #define LP_APM_REGION0_R1_R_V 0x00000001U #define LP_APM_REGION0_R1_R_S 6 /** LP_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 0. + * Configures the execution permission in region 0 in REE1 mode. */ #define LP_APM_REGION0_R2_X (BIT(8)) #define LP_APM_REGION0_R2_X_M (LP_APM_REGION0_R2_X_V << LP_APM_REGION0_R2_X_S) #define LP_APM_REGION0_R2_X_V 0x00000001U #define LP_APM_REGION0_R2_X_S 8 /** LP_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 0. + * Configures the write permission in region 0 in REE2 mode. */ #define LP_APM_REGION0_R2_W (BIT(9)) #define LP_APM_REGION0_R2_W_M (LP_APM_REGION0_R2_W_V << LP_APM_REGION0_R2_W_S) #define LP_APM_REGION0_R2_W_V 0x00000001U #define LP_APM_REGION0_R2_W_S 9 /** LP_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 0. + * Configures the read permission in region 0 in REE2 mode. */ #define LP_APM_REGION0_R2_R (BIT(10)) #define LP_APM_REGION0_R2_R_M (LP_APM_REGION0_R2_R_V << LP_APM_REGION0_R2_R_S) #define LP_APM_REGION0_R2_R_V 0x00000001U #define LP_APM_REGION0_R2_R_S 10 /** LP_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 0 configuration registers + * (LP_APM_REGION0_ADDR_START_REG, LP_APM_REGION0_ADDR_END_REG and + * LP_APM_REGION0_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION0_LOCK (BIT(11)) #define LP_APM_REGION0_LOCK_M (LP_APM_REGION0_LOCK_V << LP_APM_REGION0_LOCK_S) @@ -129,7 +133,7 @@ extern "C" { */ #define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10) /** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 1. + * Configures the start address of region 1. */ #define LP_APM_REGION1_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION1_ADDR_START_M (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S) @@ -141,7 +145,7 @@ extern "C" { */ #define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14) /** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 1. + * Configures the end address of region 1. */ #define LP_APM_REGION1_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION1_ADDR_END_M (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S) @@ -149,74 +153,78 @@ extern "C" { #define LP_APM_REGION1_ADDR_END_S 0 /** LP_APM_REGION1_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION1_ATTR_REG (DR_REG_LP_APM_BASE + 0x18) /** LP_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 1. + * Configures the execution permission in region 1 in REE0 mode. */ #define LP_APM_REGION1_R0_X (BIT(0)) #define LP_APM_REGION1_R0_X_M (LP_APM_REGION1_R0_X_V << LP_APM_REGION1_R0_X_S) #define LP_APM_REGION1_R0_X_V 0x00000001U #define LP_APM_REGION1_R0_X_S 0 /** LP_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 1. + * Configures the write permission in region 1 in REE0 mode. */ #define LP_APM_REGION1_R0_W (BIT(1)) #define LP_APM_REGION1_R0_W_M (LP_APM_REGION1_R0_W_V << LP_APM_REGION1_R0_W_S) #define LP_APM_REGION1_R0_W_V 0x00000001U #define LP_APM_REGION1_R0_W_S 1 /** LP_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 1. + * Configures the read permission in region 1 in REE0 mode. */ #define LP_APM_REGION1_R0_R (BIT(2)) #define LP_APM_REGION1_R0_R_M (LP_APM_REGION1_R0_R_V << LP_APM_REGION1_R0_R_S) #define LP_APM_REGION1_R0_R_V 0x00000001U #define LP_APM_REGION1_R0_R_S 2 /** LP_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 1. + * Configures the execution permission in region 1 in REE1 mode. */ #define LP_APM_REGION1_R1_X (BIT(4)) #define LP_APM_REGION1_R1_X_M (LP_APM_REGION1_R1_X_V << LP_APM_REGION1_R1_X_S) #define LP_APM_REGION1_R1_X_V 0x00000001U #define LP_APM_REGION1_R1_X_S 4 /** LP_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 1. + * Configures the write permission in region 1 in REE1 mode. */ #define LP_APM_REGION1_R1_W (BIT(5)) #define LP_APM_REGION1_R1_W_M (LP_APM_REGION1_R1_W_V << LP_APM_REGION1_R1_W_S) #define LP_APM_REGION1_R1_W_V 0x00000001U #define LP_APM_REGION1_R1_W_S 5 /** LP_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 1. + * Configures the read permission in region 1 in REE1 mode. */ #define LP_APM_REGION1_R1_R (BIT(6)) #define LP_APM_REGION1_R1_R_M (LP_APM_REGION1_R1_R_V << LP_APM_REGION1_R1_R_S) #define LP_APM_REGION1_R1_R_V 0x00000001U #define LP_APM_REGION1_R1_R_S 6 /** LP_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 1. + * Configures the execution permission in region 1 in REE1 mode. */ #define LP_APM_REGION1_R2_X (BIT(8)) #define LP_APM_REGION1_R2_X_M (LP_APM_REGION1_R2_X_V << LP_APM_REGION1_R2_X_S) #define LP_APM_REGION1_R2_X_V 0x00000001U #define LP_APM_REGION1_R2_X_S 8 /** LP_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 1. + * Configures the write permission in region 1 in REE2 mode. */ #define LP_APM_REGION1_R2_W (BIT(9)) #define LP_APM_REGION1_R2_W_M (LP_APM_REGION1_R2_W_V << LP_APM_REGION1_R2_W_S) #define LP_APM_REGION1_R2_W_V 0x00000001U #define LP_APM_REGION1_R2_W_S 9 /** LP_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 1. + * Configures the read permission in region 1 in REE2 mode. */ #define LP_APM_REGION1_R2_R (BIT(10)) #define LP_APM_REGION1_R2_R_M (LP_APM_REGION1_R2_R_V << LP_APM_REGION1_R2_R_S) #define LP_APM_REGION1_R2_R_V 0x00000001U #define LP_APM_REGION1_R2_R_S 10 /** LP_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 1 configuration registers + * (LP_APM_REGION1_ADDR_START_REG, LP_APM_REGION1_ADDR_END_REG and + * LP_APM_REGION1_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION1_LOCK (BIT(11)) #define LP_APM_REGION1_LOCK_M (LP_APM_REGION1_LOCK_V << LP_APM_REGION1_LOCK_S) @@ -228,7 +236,7 @@ extern "C" { */ #define LP_APM_REGION2_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x1c) /** LP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 2. + * Configures the start address of region 2. */ #define LP_APM_REGION2_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION2_ADDR_START_M (LP_APM_REGION2_ADDR_START_V << LP_APM_REGION2_ADDR_START_S) @@ -240,7 +248,7 @@ extern "C" { */ #define LP_APM_REGION2_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x20) /** LP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 2. + * Configures the end address of region 2. */ #define LP_APM_REGION2_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION2_ADDR_END_M (LP_APM_REGION2_ADDR_END_V << LP_APM_REGION2_ADDR_END_S) @@ -248,74 +256,78 @@ extern "C" { #define LP_APM_REGION2_ADDR_END_S 0 /** LP_APM_REGION2_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION2_ATTR_REG (DR_REG_LP_APM_BASE + 0x24) /** LP_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 2. + * Configures the execution permission in region 2 in REE0 mode. */ #define LP_APM_REGION2_R0_X (BIT(0)) #define LP_APM_REGION2_R0_X_M (LP_APM_REGION2_R0_X_V << LP_APM_REGION2_R0_X_S) #define LP_APM_REGION2_R0_X_V 0x00000001U #define LP_APM_REGION2_R0_X_S 0 /** LP_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 2. + * Configures the write permission in region 2 in REE0 mode. */ #define LP_APM_REGION2_R0_W (BIT(1)) #define LP_APM_REGION2_R0_W_M (LP_APM_REGION2_R0_W_V << LP_APM_REGION2_R0_W_S) #define LP_APM_REGION2_R0_W_V 0x00000001U #define LP_APM_REGION2_R0_W_S 1 /** LP_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 2. + * Configures the read permission in region 2 in REE0 mode. */ #define LP_APM_REGION2_R0_R (BIT(2)) #define LP_APM_REGION2_R0_R_M (LP_APM_REGION2_R0_R_V << LP_APM_REGION2_R0_R_S) #define LP_APM_REGION2_R0_R_V 0x00000001U #define LP_APM_REGION2_R0_R_S 2 /** LP_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 2. + * Configures the execution permission in region 2 in REE1 mode. */ #define LP_APM_REGION2_R1_X (BIT(4)) #define LP_APM_REGION2_R1_X_M (LP_APM_REGION2_R1_X_V << LP_APM_REGION2_R1_X_S) #define LP_APM_REGION2_R1_X_V 0x00000001U #define LP_APM_REGION2_R1_X_S 4 /** LP_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 2. + * Configures the write permission in region 2 in REE1 mode. */ #define LP_APM_REGION2_R1_W (BIT(5)) #define LP_APM_REGION2_R1_W_M (LP_APM_REGION2_R1_W_V << LP_APM_REGION2_R1_W_S) #define LP_APM_REGION2_R1_W_V 0x00000001U #define LP_APM_REGION2_R1_W_S 5 /** LP_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 2. + * Configures the read permission in region 2 in REE1 mode. */ #define LP_APM_REGION2_R1_R (BIT(6)) #define LP_APM_REGION2_R1_R_M (LP_APM_REGION2_R1_R_V << LP_APM_REGION2_R1_R_S) #define LP_APM_REGION2_R1_R_V 0x00000001U #define LP_APM_REGION2_R1_R_S 6 /** LP_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 2. + * Configures the execution permission in region 2 in REE1 mode. */ #define LP_APM_REGION2_R2_X (BIT(8)) #define LP_APM_REGION2_R2_X_M (LP_APM_REGION2_R2_X_V << LP_APM_REGION2_R2_X_S) #define LP_APM_REGION2_R2_X_V 0x00000001U #define LP_APM_REGION2_R2_X_S 8 /** LP_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 2. + * Configures the write permission in region 2 in REE2 mode. */ #define LP_APM_REGION2_R2_W (BIT(9)) #define LP_APM_REGION2_R2_W_M (LP_APM_REGION2_R2_W_V << LP_APM_REGION2_R2_W_S) #define LP_APM_REGION2_R2_W_V 0x00000001U #define LP_APM_REGION2_R2_W_S 9 /** LP_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 2. + * Configures the read permission in region 2 in REE2 mode. */ #define LP_APM_REGION2_R2_R (BIT(10)) #define LP_APM_REGION2_R2_R_M (LP_APM_REGION2_R2_R_V << LP_APM_REGION2_R2_R_S) #define LP_APM_REGION2_R2_R_V 0x00000001U #define LP_APM_REGION2_R2_R_S 10 /** LP_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 2 configuration registers + * (LP_APM_REGION2_ADDR_START_REG, LP_APM_REGION2_ADDR_END_REG and + * LP_APM_REGION2_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION2_LOCK (BIT(11)) #define LP_APM_REGION2_LOCK_M (LP_APM_REGION2_LOCK_V << LP_APM_REGION2_LOCK_S) @@ -327,7 +339,7 @@ extern "C" { */ #define LP_APM_REGION3_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x28) /** LP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 3. + * Configures the start address of region 3. */ #define LP_APM_REGION3_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION3_ADDR_START_M (LP_APM_REGION3_ADDR_START_V << LP_APM_REGION3_ADDR_START_S) @@ -339,7 +351,7 @@ extern "C" { */ #define LP_APM_REGION3_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x2c) /** LP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 3. + * Configures the end address of region 3. */ #define LP_APM_REGION3_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION3_ADDR_END_M (LP_APM_REGION3_ADDR_END_V << LP_APM_REGION3_ADDR_END_S) @@ -347,74 +359,78 @@ extern "C" { #define LP_APM_REGION3_ADDR_END_S 0 /** LP_APM_REGION3_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION3_ATTR_REG (DR_REG_LP_APM_BASE + 0x30) /** LP_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 3. + * Configures the execution permission in region 3 in REE0 mode. */ #define LP_APM_REGION3_R0_X (BIT(0)) #define LP_APM_REGION3_R0_X_M (LP_APM_REGION3_R0_X_V << LP_APM_REGION3_R0_X_S) #define LP_APM_REGION3_R0_X_V 0x00000001U #define LP_APM_REGION3_R0_X_S 0 /** LP_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 3. + * Configures the write permission in region 3 in REE0 mode. */ #define LP_APM_REGION3_R0_W (BIT(1)) #define LP_APM_REGION3_R0_W_M (LP_APM_REGION3_R0_W_V << LP_APM_REGION3_R0_W_S) #define LP_APM_REGION3_R0_W_V 0x00000001U #define LP_APM_REGION3_R0_W_S 1 /** LP_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 3. + * Configures the read permission in region 3 in REE0 mode. */ #define LP_APM_REGION3_R0_R (BIT(2)) #define LP_APM_REGION3_R0_R_M (LP_APM_REGION3_R0_R_V << LP_APM_REGION3_R0_R_S) #define LP_APM_REGION3_R0_R_V 0x00000001U #define LP_APM_REGION3_R0_R_S 2 /** LP_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 3. + * Configures the execution permission in region 3 in REE1 mode. */ #define LP_APM_REGION3_R1_X (BIT(4)) #define LP_APM_REGION3_R1_X_M (LP_APM_REGION3_R1_X_V << LP_APM_REGION3_R1_X_S) #define LP_APM_REGION3_R1_X_V 0x00000001U #define LP_APM_REGION3_R1_X_S 4 /** LP_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 3. + * Configures the write permission in region 3 in REE1 mode. */ #define LP_APM_REGION3_R1_W (BIT(5)) #define LP_APM_REGION3_R1_W_M (LP_APM_REGION3_R1_W_V << LP_APM_REGION3_R1_W_S) #define LP_APM_REGION3_R1_W_V 0x00000001U #define LP_APM_REGION3_R1_W_S 5 /** LP_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 3. + * Configures the read permission in region 3 in REE1 mode. */ #define LP_APM_REGION3_R1_R (BIT(6)) #define LP_APM_REGION3_R1_R_M (LP_APM_REGION3_R1_R_V << LP_APM_REGION3_R1_R_S) #define LP_APM_REGION3_R1_R_V 0x00000001U #define LP_APM_REGION3_R1_R_S 6 /** LP_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 3. + * Configures the execution permission in region 3 in REE1 mode. */ #define LP_APM_REGION3_R2_X (BIT(8)) #define LP_APM_REGION3_R2_X_M (LP_APM_REGION3_R2_X_V << LP_APM_REGION3_R2_X_S) #define LP_APM_REGION3_R2_X_V 0x00000001U #define LP_APM_REGION3_R2_X_S 8 /** LP_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 3. + * Configures the write permission in region 3 in REE2 mode. */ #define LP_APM_REGION3_R2_W (BIT(9)) #define LP_APM_REGION3_R2_W_M (LP_APM_REGION3_R2_W_V << LP_APM_REGION3_R2_W_S) #define LP_APM_REGION3_R2_W_V 0x00000001U #define LP_APM_REGION3_R2_W_S 9 /** LP_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 3. + * Configures the read permission in region 3 in REE2 mode. */ #define LP_APM_REGION3_R2_R (BIT(10)) #define LP_APM_REGION3_R2_R_M (LP_APM_REGION3_R2_R_V << LP_APM_REGION3_R2_R_S) #define LP_APM_REGION3_R2_R_V 0x00000001U #define LP_APM_REGION3_R2_R_S 10 /** LP_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 3 configuration registers + * (LP_APM_REGION3_ADDR_START_REG, LP_APM_REGION3_ADDR_END_REG and + * LP_APM_REGION3_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION3_LOCK (BIT(11)) #define LP_APM_REGION3_LOCK_M (LP_APM_REGION3_LOCK_V << LP_APM_REGION3_LOCK_S) @@ -426,7 +442,7 @@ extern "C" { */ #define LP_APM_REGION4_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x34) /** LP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 4. + * Configures the start address of region 4. */ #define LP_APM_REGION4_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION4_ADDR_START_M (LP_APM_REGION4_ADDR_START_V << LP_APM_REGION4_ADDR_START_S) @@ -438,7 +454,7 @@ extern "C" { */ #define LP_APM_REGION4_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x38) /** LP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 4. + * Configures the end address of region 4. */ #define LP_APM_REGION4_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION4_ADDR_END_M (LP_APM_REGION4_ADDR_END_V << LP_APM_REGION4_ADDR_END_S) @@ -446,74 +462,78 @@ extern "C" { #define LP_APM_REGION4_ADDR_END_S 0 /** LP_APM_REGION4_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION4_ATTR_REG (DR_REG_LP_APM_BASE + 0x3c) /** LP_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 4. + * Configures the execution permission in region 4 in REE0 mode. */ #define LP_APM_REGION4_R0_X (BIT(0)) #define LP_APM_REGION4_R0_X_M (LP_APM_REGION4_R0_X_V << LP_APM_REGION4_R0_X_S) #define LP_APM_REGION4_R0_X_V 0x00000001U #define LP_APM_REGION4_R0_X_S 0 /** LP_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 4. + * Configures the write permission in region 4 in REE0 mode. */ #define LP_APM_REGION4_R0_W (BIT(1)) #define LP_APM_REGION4_R0_W_M (LP_APM_REGION4_R0_W_V << LP_APM_REGION4_R0_W_S) #define LP_APM_REGION4_R0_W_V 0x00000001U #define LP_APM_REGION4_R0_W_S 1 /** LP_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 4. + * Configures the read permission in region 4 in REE0 mode. */ #define LP_APM_REGION4_R0_R (BIT(2)) #define LP_APM_REGION4_R0_R_M (LP_APM_REGION4_R0_R_V << LP_APM_REGION4_R0_R_S) #define LP_APM_REGION4_R0_R_V 0x00000001U #define LP_APM_REGION4_R0_R_S 2 /** LP_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 4. + * Configures the execution permission in region 4 in REE1 mode. */ #define LP_APM_REGION4_R1_X (BIT(4)) #define LP_APM_REGION4_R1_X_M (LP_APM_REGION4_R1_X_V << LP_APM_REGION4_R1_X_S) #define LP_APM_REGION4_R1_X_V 0x00000001U #define LP_APM_REGION4_R1_X_S 4 /** LP_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 4. + * Configures the write permission in region 4 in REE1 mode. */ #define LP_APM_REGION4_R1_W (BIT(5)) #define LP_APM_REGION4_R1_W_M (LP_APM_REGION4_R1_W_V << LP_APM_REGION4_R1_W_S) #define LP_APM_REGION4_R1_W_V 0x00000001U #define LP_APM_REGION4_R1_W_S 5 /** LP_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 4. + * Configures the read permission in region 4 in REE1 mode. */ #define LP_APM_REGION4_R1_R (BIT(6)) #define LP_APM_REGION4_R1_R_M (LP_APM_REGION4_R1_R_V << LP_APM_REGION4_R1_R_S) #define LP_APM_REGION4_R1_R_V 0x00000001U #define LP_APM_REGION4_R1_R_S 6 /** LP_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 4. + * Configures the execution permission in region 4 in REE1 mode. */ #define LP_APM_REGION4_R2_X (BIT(8)) #define LP_APM_REGION4_R2_X_M (LP_APM_REGION4_R2_X_V << LP_APM_REGION4_R2_X_S) #define LP_APM_REGION4_R2_X_V 0x00000001U #define LP_APM_REGION4_R2_X_S 8 /** LP_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 4. + * Configures the write permission in region 4 in REE2 mode. */ #define LP_APM_REGION4_R2_W (BIT(9)) #define LP_APM_REGION4_R2_W_M (LP_APM_REGION4_R2_W_V << LP_APM_REGION4_R2_W_S) #define LP_APM_REGION4_R2_W_V 0x00000001U #define LP_APM_REGION4_R2_W_S 9 /** LP_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 4. + * Configures the read permission in region 4 in REE2 mode. */ #define LP_APM_REGION4_R2_R (BIT(10)) #define LP_APM_REGION4_R2_R_M (LP_APM_REGION4_R2_R_V << LP_APM_REGION4_R2_R_S) #define LP_APM_REGION4_R2_R_V 0x00000001U #define LP_APM_REGION4_R2_R_S 10 /** LP_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 4 configuration registers + * (LP_APM_REGION4_ADDR_START_REG, LP_APM_REGION4_ADDR_END_REG and + * LP_APM_REGION4_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION4_LOCK (BIT(11)) #define LP_APM_REGION4_LOCK_M (LP_APM_REGION4_LOCK_V << LP_APM_REGION4_LOCK_S) @@ -525,7 +545,7 @@ extern "C" { */ #define LP_APM_REGION5_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x40) /** LP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 5. + * Configures the start address of region 5. */ #define LP_APM_REGION5_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION5_ADDR_START_M (LP_APM_REGION5_ADDR_START_V << LP_APM_REGION5_ADDR_START_S) @@ -537,7 +557,7 @@ extern "C" { */ #define LP_APM_REGION5_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x44) /** LP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 5. + * Configures the end address of region 5. */ #define LP_APM_REGION5_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION5_ADDR_END_M (LP_APM_REGION5_ADDR_END_V << LP_APM_REGION5_ADDR_END_S) @@ -545,74 +565,78 @@ extern "C" { #define LP_APM_REGION5_ADDR_END_S 0 /** LP_APM_REGION5_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION5_ATTR_REG (DR_REG_LP_APM_BASE + 0x48) /** LP_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 5. + * Configures the execution permission in region 5 in REE0 mode. */ #define LP_APM_REGION5_R0_X (BIT(0)) #define LP_APM_REGION5_R0_X_M (LP_APM_REGION5_R0_X_V << LP_APM_REGION5_R0_X_S) #define LP_APM_REGION5_R0_X_V 0x00000001U #define LP_APM_REGION5_R0_X_S 0 /** LP_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 5. + * Configures the write permission in region 5 in REE0 mode. */ #define LP_APM_REGION5_R0_W (BIT(1)) #define LP_APM_REGION5_R0_W_M (LP_APM_REGION5_R0_W_V << LP_APM_REGION5_R0_W_S) #define LP_APM_REGION5_R0_W_V 0x00000001U #define LP_APM_REGION5_R0_W_S 1 /** LP_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 5. + * Configures the read permission in region 5 in REE0 mode. */ #define LP_APM_REGION5_R0_R (BIT(2)) #define LP_APM_REGION5_R0_R_M (LP_APM_REGION5_R0_R_V << LP_APM_REGION5_R0_R_S) #define LP_APM_REGION5_R0_R_V 0x00000001U #define LP_APM_REGION5_R0_R_S 2 /** LP_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 5. + * Configures the execution permission in region 5 in REE1 mode. */ #define LP_APM_REGION5_R1_X (BIT(4)) #define LP_APM_REGION5_R1_X_M (LP_APM_REGION5_R1_X_V << LP_APM_REGION5_R1_X_S) #define LP_APM_REGION5_R1_X_V 0x00000001U #define LP_APM_REGION5_R1_X_S 4 /** LP_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 5. + * Configures the write permission in region 5 in REE1 mode. */ #define LP_APM_REGION5_R1_W (BIT(5)) #define LP_APM_REGION5_R1_W_M (LP_APM_REGION5_R1_W_V << LP_APM_REGION5_R1_W_S) #define LP_APM_REGION5_R1_W_V 0x00000001U #define LP_APM_REGION5_R1_W_S 5 /** LP_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 5. + * Configures the read permission in region 5 in REE1 mode. */ #define LP_APM_REGION5_R1_R (BIT(6)) #define LP_APM_REGION5_R1_R_M (LP_APM_REGION5_R1_R_V << LP_APM_REGION5_R1_R_S) #define LP_APM_REGION5_R1_R_V 0x00000001U #define LP_APM_REGION5_R1_R_S 6 /** LP_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 5. + * Configures the execution permission in region 5 in REE1 mode. */ #define LP_APM_REGION5_R2_X (BIT(8)) #define LP_APM_REGION5_R2_X_M (LP_APM_REGION5_R2_X_V << LP_APM_REGION5_R2_X_S) #define LP_APM_REGION5_R2_X_V 0x00000001U #define LP_APM_REGION5_R2_X_S 8 /** LP_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 5. + * Configures the write permission in region 5 in REE2 mode. */ #define LP_APM_REGION5_R2_W (BIT(9)) #define LP_APM_REGION5_R2_W_M (LP_APM_REGION5_R2_W_V << LP_APM_REGION5_R2_W_S) #define LP_APM_REGION5_R2_W_V 0x00000001U #define LP_APM_REGION5_R2_W_S 9 /** LP_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 5. + * Configures the read permission in region 5 in REE2 mode. */ #define LP_APM_REGION5_R2_R (BIT(10)) #define LP_APM_REGION5_R2_R_M (LP_APM_REGION5_R2_R_V << LP_APM_REGION5_R2_R_S) #define LP_APM_REGION5_R2_R_V 0x00000001U #define LP_APM_REGION5_R2_R_S 10 /** LP_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 5 configuration registers + * (LP_APM_REGION5_ADDR_START_REG, LP_APM_REGION5_ADDR_END_REG and + * LP_APM_REGION5_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION5_LOCK (BIT(11)) #define LP_APM_REGION5_LOCK_M (LP_APM_REGION5_LOCK_V << LP_APM_REGION5_LOCK_S) @@ -624,7 +648,7 @@ extern "C" { */ #define LP_APM_REGION6_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4c) /** LP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 6. + * Configures the start address of region 6. */ #define LP_APM_REGION6_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION6_ADDR_START_M (LP_APM_REGION6_ADDR_START_V << LP_APM_REGION6_ADDR_START_S) @@ -636,7 +660,7 @@ extern "C" { */ #define LP_APM_REGION6_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x50) /** LP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 6. + * Configures the end address of region 6. */ #define LP_APM_REGION6_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION6_ADDR_END_M (LP_APM_REGION6_ADDR_END_V << LP_APM_REGION6_ADDR_END_S) @@ -644,74 +668,78 @@ extern "C" { #define LP_APM_REGION6_ADDR_END_S 0 /** LP_APM_REGION6_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION6_ATTR_REG (DR_REG_LP_APM_BASE + 0x54) /** LP_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 6. + * Configures the execution permission in region 6 in REE0 mode. */ #define LP_APM_REGION6_R0_X (BIT(0)) #define LP_APM_REGION6_R0_X_M (LP_APM_REGION6_R0_X_V << LP_APM_REGION6_R0_X_S) #define LP_APM_REGION6_R0_X_V 0x00000001U #define LP_APM_REGION6_R0_X_S 0 /** LP_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 6. + * Configures the write permission in region 6 in REE0 mode. */ #define LP_APM_REGION6_R0_W (BIT(1)) #define LP_APM_REGION6_R0_W_M (LP_APM_REGION6_R0_W_V << LP_APM_REGION6_R0_W_S) #define LP_APM_REGION6_R0_W_V 0x00000001U #define LP_APM_REGION6_R0_W_S 1 /** LP_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 6. + * Configures the read permission in region 6 in REE0 mode. */ #define LP_APM_REGION6_R0_R (BIT(2)) #define LP_APM_REGION6_R0_R_M (LP_APM_REGION6_R0_R_V << LP_APM_REGION6_R0_R_S) #define LP_APM_REGION6_R0_R_V 0x00000001U #define LP_APM_REGION6_R0_R_S 2 /** LP_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 6. + * Configures the execution permission in region 6 in REE1 mode. */ #define LP_APM_REGION6_R1_X (BIT(4)) #define LP_APM_REGION6_R1_X_M (LP_APM_REGION6_R1_X_V << LP_APM_REGION6_R1_X_S) #define LP_APM_REGION6_R1_X_V 0x00000001U #define LP_APM_REGION6_R1_X_S 4 /** LP_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 6. + * Configures the write permission in region 6 in REE1 mode. */ #define LP_APM_REGION6_R1_W (BIT(5)) #define LP_APM_REGION6_R1_W_M (LP_APM_REGION6_R1_W_V << LP_APM_REGION6_R1_W_S) #define LP_APM_REGION6_R1_W_V 0x00000001U #define LP_APM_REGION6_R1_W_S 5 /** LP_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 6. + * Configures the read permission in region 6 in REE1 mode. */ #define LP_APM_REGION6_R1_R (BIT(6)) #define LP_APM_REGION6_R1_R_M (LP_APM_REGION6_R1_R_V << LP_APM_REGION6_R1_R_S) #define LP_APM_REGION6_R1_R_V 0x00000001U #define LP_APM_REGION6_R1_R_S 6 /** LP_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 6. + * Configures the execution permission in region 6 in REE1 mode. */ #define LP_APM_REGION6_R2_X (BIT(8)) #define LP_APM_REGION6_R2_X_M (LP_APM_REGION6_R2_X_V << LP_APM_REGION6_R2_X_S) #define LP_APM_REGION6_R2_X_V 0x00000001U #define LP_APM_REGION6_R2_X_S 8 /** LP_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 6. + * Configures the write permission in region 6 in REE2 mode. */ #define LP_APM_REGION6_R2_W (BIT(9)) #define LP_APM_REGION6_R2_W_M (LP_APM_REGION6_R2_W_V << LP_APM_REGION6_R2_W_S) #define LP_APM_REGION6_R2_W_V 0x00000001U #define LP_APM_REGION6_R2_W_S 9 /** LP_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 6. + * Configures the read permission in region 6 in REE2 mode. */ #define LP_APM_REGION6_R2_R (BIT(10)) #define LP_APM_REGION6_R2_R_M (LP_APM_REGION6_R2_R_V << LP_APM_REGION6_R2_R_S) #define LP_APM_REGION6_R2_R_V 0x00000001U #define LP_APM_REGION6_R2_R_S 10 /** LP_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 6 configuration registers + * (LP_APM_REGION6_ADDR_START_REG, LP_APM_REGION6_ADDR_END_REG and + * LP_APM_REGION6_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION6_LOCK (BIT(11)) #define LP_APM_REGION6_LOCK_M (LP_APM_REGION6_LOCK_V << LP_APM_REGION6_LOCK_S) @@ -723,7 +751,7 @@ extern "C" { */ #define LP_APM_REGION7_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x58) /** LP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 7. + * Configures the start address of region 7. */ #define LP_APM_REGION7_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION7_ADDR_START_M (LP_APM_REGION7_ADDR_START_V << LP_APM_REGION7_ADDR_START_S) @@ -735,7 +763,7 @@ extern "C" { */ #define LP_APM_REGION7_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x5c) /** LP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 7. + * Configures the end address of region 7. */ #define LP_APM_REGION7_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION7_ADDR_END_M (LP_APM_REGION7_ADDR_END_V << LP_APM_REGION7_ADDR_END_S) @@ -743,74 +771,78 @@ extern "C" { #define LP_APM_REGION7_ADDR_END_S 0 /** LP_APM_REGION7_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION7_ATTR_REG (DR_REG_LP_APM_BASE + 0x60) /** LP_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 7. + * Configures the execution permission in region 7 in REE0 mode. */ #define LP_APM_REGION7_R0_X (BIT(0)) #define LP_APM_REGION7_R0_X_M (LP_APM_REGION7_R0_X_V << LP_APM_REGION7_R0_X_S) #define LP_APM_REGION7_R0_X_V 0x00000001U #define LP_APM_REGION7_R0_X_S 0 /** LP_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 7. + * Configures the write permission in region 7 in REE0 mode. */ #define LP_APM_REGION7_R0_W (BIT(1)) #define LP_APM_REGION7_R0_W_M (LP_APM_REGION7_R0_W_V << LP_APM_REGION7_R0_W_S) #define LP_APM_REGION7_R0_W_V 0x00000001U #define LP_APM_REGION7_R0_W_S 1 /** LP_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 7. + * Configures the read permission in region 7 in REE0 mode. */ #define LP_APM_REGION7_R0_R (BIT(2)) #define LP_APM_REGION7_R0_R_M (LP_APM_REGION7_R0_R_V << LP_APM_REGION7_R0_R_S) #define LP_APM_REGION7_R0_R_V 0x00000001U #define LP_APM_REGION7_R0_R_S 2 /** LP_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 7. + * Configures the execution permission in region 7 in REE1 mode. */ #define LP_APM_REGION7_R1_X (BIT(4)) #define LP_APM_REGION7_R1_X_M (LP_APM_REGION7_R1_X_V << LP_APM_REGION7_R1_X_S) #define LP_APM_REGION7_R1_X_V 0x00000001U #define LP_APM_REGION7_R1_X_S 4 /** LP_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 7. + * Configures the write permission in region 7 in REE1 mode. */ #define LP_APM_REGION7_R1_W (BIT(5)) #define LP_APM_REGION7_R1_W_M (LP_APM_REGION7_R1_W_V << LP_APM_REGION7_R1_W_S) #define LP_APM_REGION7_R1_W_V 0x00000001U #define LP_APM_REGION7_R1_W_S 5 /** LP_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 7. + * Configures the read permission in region 7 in REE1 mode. */ #define LP_APM_REGION7_R1_R (BIT(6)) #define LP_APM_REGION7_R1_R_M (LP_APM_REGION7_R1_R_V << LP_APM_REGION7_R1_R_S) #define LP_APM_REGION7_R1_R_V 0x00000001U #define LP_APM_REGION7_R1_R_S 6 /** LP_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 7. + * Configures the execution permission in region 7 in REE1 mode. */ #define LP_APM_REGION7_R2_X (BIT(8)) #define LP_APM_REGION7_R2_X_M (LP_APM_REGION7_R2_X_V << LP_APM_REGION7_R2_X_S) #define LP_APM_REGION7_R2_X_V 0x00000001U #define LP_APM_REGION7_R2_X_S 8 /** LP_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 7. + * Configures the write permission in region 7 in REE2 mode. */ #define LP_APM_REGION7_R2_W (BIT(9)) #define LP_APM_REGION7_R2_W_M (LP_APM_REGION7_R2_W_V << LP_APM_REGION7_R2_W_S) #define LP_APM_REGION7_R2_W_V 0x00000001U #define LP_APM_REGION7_R2_W_S 9 /** LP_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 7. + * Configures the read permission in region 7 in REE2 mode. */ #define LP_APM_REGION7_R2_R (BIT(10)) #define LP_APM_REGION7_R2_R_M (LP_APM_REGION7_R2_R_V << LP_APM_REGION7_R2_R_S) #define LP_APM_REGION7_R2_R_V 0x00000001U #define LP_APM_REGION7_R2_R_S 10 /** LP_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 7 configuration registers + * (LP_APM_REGION7_ADDR_START_REG, LP_APM_REGION7_ADDR_END_REG and + * LP_APM_REGION7_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION7_LOCK (BIT(11)) #define LP_APM_REGION7_LOCK_M (LP_APM_REGION7_LOCK_V << LP_APM_REGION7_LOCK_S) @@ -818,18 +850,18 @@ extern "C" { #define LP_APM_REGION7_LOCK_S 11 /** LP_APM_FUNC_CTRL_REG register - * APM function control register + * APM access path permission management register */ #define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4) /** LP_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures to enable permission management for LP_APM_CTRL M0. */ #define LP_APM_M0_FUNC_EN (BIT(0)) #define LP_APM_M0_FUNC_EN_M (LP_APM_M0_FUNC_EN_V << LP_APM_M0_FUNC_EN_S) #define LP_APM_M0_FUNC_EN_V 0x00000001U #define LP_APM_M0_FUNC_EN_S 0 /** LP_APM_M1_FUNC_EN : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable + * Configures to enable permission management for LP_APM_CTRL M1. */ #define LP_APM_M1_FUNC_EN (BIT(1)) #define LP_APM_M1_FUNC_EN_M (LP_APM_M1_FUNC_EN_V << LP_APM_M1_FUNC_EN_S) @@ -837,13 +869,13 @@ extern "C" { #define LP_APM_M1_FUNC_EN_S 1 /** LP_APM_M0_STATUS_REG register - * M0 status register + * LP_APM_CTRL M0 status register */ #define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8) /** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define LP_APM_M0_EXCEPTION_STATUS 0x00000003U #define LP_APM_M0_EXCEPTION_STATUS_M (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S) @@ -851,7 +883,7 @@ extern "C" { #define LP_APM_M0_EXCEPTION_STATUS_S 0 /** LP_APM_M0_STATUS_CLR_REG register - * M0 status clear register + * LP_APM_CTRL M0 status clear register */ #define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc) /** LP_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -863,25 +895,25 @@ extern "C" { #define LP_APM_M0_EXCEPTION_STATUS_CLR_S 0 /** LP_APM_M0_EXCEPTION_INFO0_REG register - * M0 exception_info0 register + * LP_APM_CTRL M0 exception information register */ #define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0) /** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define LP_APM_M0_EXCEPTION_REGION 0x000000FFU #define LP_APM_M0_EXCEPTION_REGION_M (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S) #define LP_APM_M0_EXCEPTION_REGION_V 0x000000FFU #define LP_APM_M0_EXCEPTION_REGION_S 0 /** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define LP_APM_M0_EXCEPTION_MODE 0x00000003U #define LP_APM_M0_EXCEPTION_MODE_M (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S) #define LP_APM_M0_EXCEPTION_MODE_V 0x00000003U #define LP_APM_M0_EXCEPTION_MODE_S 16 /** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define LP_APM_M0_EXCEPTION_ID 0x0000001FU #define LP_APM_M0_EXCEPTION_ID_M (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S) @@ -889,11 +921,11 @@ extern "C" { #define LP_APM_M0_EXCEPTION_ID_S 18 /** LP_APM_M0_EXCEPTION_INFO1_REG register - * M0 exception_info1 register + * LP_APM_CTRL M0 exception information register */ #define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4) /** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define LP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU #define LP_APM_M0_EXCEPTION_ADDR_M (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S) @@ -901,13 +933,13 @@ extern "C" { #define LP_APM_M0_EXCEPTION_ADDR_S 0 /** LP_APM_M1_STATUS_REG register - * M1 status register + * LP_APM_CTRL M1 status register */ #define LP_APM_M1_STATUS_REG (DR_REG_LP_APM_BASE + 0xd8) /** LP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define LP_APM_M1_EXCEPTION_STATUS 0x00000003U #define LP_APM_M1_EXCEPTION_STATUS_M (LP_APM_M1_EXCEPTION_STATUS_V << LP_APM_M1_EXCEPTION_STATUS_S) @@ -915,7 +947,7 @@ extern "C" { #define LP_APM_M1_EXCEPTION_STATUS_S 0 /** LP_APM_M1_STATUS_CLR_REG register - * M1 status clear register + * LP_APM_CTRL M1 status clear register */ #define LP_APM_M1_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xdc) /** LP_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -927,25 +959,25 @@ extern "C" { #define LP_APM_M1_EXCEPTION_STATUS_CLR_S 0 /** LP_APM_M1_EXCEPTION_INFO0_REG register - * M1 exception_info0 register + * LP_APM_CTRL M1 exception information register */ #define LP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xe0) /** LP_APM_M1_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define LP_APM_M1_EXCEPTION_REGION 0x000000FFU #define LP_APM_M1_EXCEPTION_REGION_M (LP_APM_M1_EXCEPTION_REGION_V << LP_APM_M1_EXCEPTION_REGION_S) #define LP_APM_M1_EXCEPTION_REGION_V 0x000000FFU #define LP_APM_M1_EXCEPTION_REGION_S 0 /** LP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define LP_APM_M1_EXCEPTION_MODE 0x00000003U #define LP_APM_M1_EXCEPTION_MODE_M (LP_APM_M1_EXCEPTION_MODE_V << LP_APM_M1_EXCEPTION_MODE_S) #define LP_APM_M1_EXCEPTION_MODE_V 0x00000003U #define LP_APM_M1_EXCEPTION_MODE_S 16 /** LP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define LP_APM_M1_EXCEPTION_ID 0x0000001FU #define LP_APM_M1_EXCEPTION_ID_M (LP_APM_M1_EXCEPTION_ID_V << LP_APM_M1_EXCEPTION_ID_S) @@ -953,11 +985,11 @@ extern "C" { #define LP_APM_M1_EXCEPTION_ID_S 18 /** LP_APM_M1_EXCEPTION_INFO1_REG register - * M1 exception_info1 register + * LP_APM_CTRL M1 exception information register */ #define LP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xe4) /** LP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define LP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU #define LP_APM_M1_EXCEPTION_ADDR_M (LP_APM_M1_EXCEPTION_ADDR_V << LP_APM_M1_EXCEPTION_ADDR_S) @@ -965,22 +997,22 @@ extern "C" { #define LP_APM_M1_EXCEPTION_ADDR_S 0 /** LP_APM_INT_EN_REG register - * APM interrupt enable register + * LP_APM_CTRL M0/1 interrupt enable register */ #define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8) /** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; - * Configures to enable APM M0 interrupt. - * 0: disable - * 1: enable + * Configures to enable LP_APM_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ #define LP_APM_M0_APM_INT_EN (BIT(0)) #define LP_APM_M0_APM_INT_EN_M (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S) #define LP_APM_M0_APM_INT_EN_V 0x00000001U #define LP_APM_M0_APM_INT_EN_S 0 /** LP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; - * Configures to enable APM M1 interrupt. - * 0: disable - * 1: enable + * Configures to enable LP_APM_CTRL M1 interrupt. + * 0: Disable + * 1: Enable */ #define LP_APM_M1_APM_INT_EN (BIT(1)) #define LP_APM_M1_APM_INT_EN_M (LP_APM_M1_APM_INT_EN_V << LP_APM_M1_APM_INT_EN_S) @@ -988,13 +1020,13 @@ extern "C" { #define LP_APM_M1_APM_INT_EN_S 1 /** LP_APM_CLOCK_GATE_REG register - * clock gating register + * Clock gating register */ #define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec) /** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ #define LP_APM_CLK_EN (BIT(0)) #define LP_APM_CLK_EN_M (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S) diff --git a/components/soc/esp32c5/register/soc/lp_apm_struct.h b/components/soc/esp32c5/register/soc/lp_apm_struct.h index 3c7bc3fcc2..fe0bddb019 100644 --- a/components/soc/esp32c5/register/soc/lp_apm_struct.h +++ b/components/soc/esp32c5/register/soc/lp_apm_struct.h @@ -10,16 +10,16 @@ extern "C" { #endif -/** Group: Region filter enable register */ +/** Group: Configuration Registers */ /** Type of region_filter_en register - * Region filter enable register + * Region enable register */ typedef union { struct { /** region_filter_en : R/W; bitpos: [7:0]; default: 1; - * Configure bit $n (0-7) to enable region $n. - * 0: disable - * 1: enable + * Configure bit $n (0-7) to enable region $n (0-7). + * 0: Disable + * 1: Enable */ uint32_t region_filter_en:8; uint32_t reserved_8:24; @@ -27,15 +27,13 @@ typedef union { uint32_t val; } lp_apm_region_filter_en_reg_t; - -/** Group: Region address register */ /** Type of regionn_addr_start register * Region address register */ typedef union { struct { /** regionn_addr_start : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region n. + * Configures the start address of region n. */ uint32_t regionn_addr_start:32; }; @@ -48,60 +46,62 @@ typedef union { typedef union { struct { /** regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region n. + * Configures the end address of region n. */ uint32_t regionn_addr_end:32; }; uint32_t val; } lp_apm_regionn_addr_end_reg_t; - -/** Group: Region access authority attribute register */ /** Type of regionn_attr register - * Region access authority attribute register + * Region access permissions configuration register */ typedef union { struct { /** regionn_r0_x : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region n. + * Configures the execution permission in region n in REE0 mode. */ uint32_t regionn_r0_x:1; /** regionn_r0_w : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region n. + * Configures the write permission in region n in REE0 mode. */ uint32_t regionn_r0_w:1; /** regionn_r0_r : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region n. + * Configures the read permission in region n in REE0 mode. */ uint32_t regionn_r0_r:1; uint32_t reserved_3:1; /** regionn_r1_x : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region n. + * Configures the execution permission in region n in REE1 mode. */ uint32_t regionn_r1_x:1; /** regionn_r1_w : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region n. + * Configures the write permission in region n in REE1 mode. */ uint32_t regionn_r1_w:1; /** regionn_r1_r : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region n. + * Configures the read permission in region n in REE1 mode. */ uint32_t regionn_r1_r:1; uint32_t reserved_7:1; /** regionn_r2_x : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region n. + * Configures the execution permission in region n in REE1 mode. */ uint32_t regionn_r2_x:1; /** regionn_r2_w : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region n. + * Configures the write permission in region n in REE2 mode. */ uint32_t regionn_r2_w:1; /** regionn_r2_r : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region n. + * Configures the read permission in region n in REE2 mode. */ uint32_t regionn_r2_r:1; /** regionn_lock : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region n configuration registers + * (LP_APM_REGIONn_ADDR_START_REG, LP_APM_REGIONn_ADDR_END_REG and + * LP_APM_REGIONn_ATTR_REG). + * 0: Do not lock + * 1: Lock */ uint32_t regionn_lock:1; uint32_t reserved_12:20; @@ -109,19 +109,17 @@ typedef union { uint32_t val; } lp_apm_regionn_attr_reg_t; - -/** Group: function control register */ /** Type of func_ctrl register - * APM function control register + * APM access path permission management register */ typedef union { struct { /** m0_func_en : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures to enable permission management for LP_APM_CTRL M0. */ uint32_t m0_func_en:1; /** m1_func_en : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable + * Configures to enable permission management for LP_APM_CTRL M1. */ uint32_t m1_func_en:1; uint32_t reserved_2:30; @@ -130,16 +128,16 @@ typedef union { } lp_apm_func_ctrl_reg_t; -/** Group: M0 status register */ +/** Group: Status Registers */ /** Type of m0_status register - * M0 status register + * LP_APM_CTRL M0 status register */ typedef union { struct { /** m0_exception_status : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m0_exception_status:2; uint32_t reserved_2:30; @@ -147,10 +145,8 @@ typedef union { uint32_t val; } lp_apm_m0_status_reg_t; - -/** Group: M0 status clear register */ /** Type of m0_status_clr register - * M0 status clear register + * LP_APM_CTRL M0 status clear register */ typedef union { struct { @@ -163,24 +159,22 @@ typedef union { uint32_t val; } lp_apm_m0_status_clr_reg_t; - -/** Group: M0 exception_info0 register */ /** Type of m0_exception_info0 register - * M0 exception_info0 register + * LP_APM_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_region : RO; bitpos: [7:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m0_exception_region:8; uint32_t reserved_8:8; /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m0_exception_mode:2; /** m0_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m0_exception_id:5; uint32_t reserved_23:9; @@ -188,32 +182,28 @@ typedef union { uint32_t val; } lp_apm_m0_exception_info0_reg_t; - -/** Group: M0 exception_info1 register */ /** Type of m0_exception_info1 register - * M0 exception_info1 register + * LP_APM_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m0_exception_addr:32; }; uint32_t val; } lp_apm_m0_exception_info1_reg_t; - -/** Group: M1 status register */ /** Type of m1_status register - * M1 status register + * LP_APM_CTRL M1 status register */ typedef union { struct { /** m1_exception_status : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m1_exception_status:2; uint32_t reserved_2:30; @@ -221,10 +211,8 @@ typedef union { uint32_t val; } lp_apm_m1_status_reg_t; - -/** Group: M1 status clear register */ /** Type of m1_status_clr register - * M1 status clear register + * LP_APM_CTRL M1 status clear register */ typedef union { struct { @@ -237,24 +225,22 @@ typedef union { uint32_t val; } lp_apm_m1_status_clr_reg_t; - -/** Group: M1 exception_info0 register */ /** Type of m1_exception_info0 register - * M1 exception_info0 register + * LP_APM_CTRL M1 exception information register */ typedef union { struct { /** m1_exception_region : RO; bitpos: [7:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m1_exception_region:8; uint32_t reserved_8:8; /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m1_exception_mode:2; /** m1_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m1_exception_id:5; uint32_t reserved_23:9; @@ -262,15 +248,13 @@ typedef union { uint32_t val; } lp_apm_m1_exception_info0_reg_t; - -/** Group: M1 exception_info1 register */ /** Type of m1_exception_info1 register - * M1 exception_info1 register + * LP_APM_CTRL M1 exception information register */ typedef union { struct { /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m1_exception_addr:32; }; @@ -278,22 +262,22 @@ typedef union { } lp_apm_m1_exception_info1_reg_t; -/** Group: APM interrupt enable register */ +/** Group: Interrupt Registers */ /** Type of int_en register - * APM interrupt enable register + * LP_APM_CTRL M0/1 interrupt enable register */ typedef union { struct { /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; - * Configures to enable APM M0 interrupt. - * 0: disable - * 1: enable + * Configures to enable LP_APM_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m0_apm_int_en:1; /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; - * Configures to enable APM M1 interrupt. - * 0: disable - * 1: enable + * Configures to enable LP_APM_CTRL M1 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m1_apm_int_en:1; uint32_t reserved_2:30; @@ -302,16 +286,16 @@ typedef union { } lp_apm_int_en_reg_t; -/** Group: clock gating register */ +/** Group: Clock Gating Registers */ /** Type of clock_gate register - * clock gating register + * Clock gating register */ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -320,7 +304,7 @@ typedef union { } lp_apm_clock_gate_reg_t; -/** Group: Version control register */ +/** Group: Version Control Registers */ /** Type of date register * Version control register */ diff --git a/components/soc/esp32c5/register/soc/lp_tee_reg.h b/components/soc/esp32c5/register/soc/lp_tee_reg.h index e9eb72abe8..77abd8f4a9 100644 --- a/components/soc/esp32c5/register/soc/lp_tee_reg.h +++ b/components/soc/esp32c5/register/soc/lp_tee_reg.h @@ -12,22 +12,24 @@ extern "C" { #endif /** LP_TEE_M0_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define LP_TEE_M0_MODE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0) /** LP_TEE_M0_MODE : R/W; bitpos: [1:0]; default: 3; - * Configures M0 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for LP CPU. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define LP_TEE_M0_MODE 0x00000003U #define LP_TEE_M0_MODE_M (LP_TEE_M0_MODE_V << LP_TEE_M0_MODE_S) #define LP_TEE_M0_MODE_V 0x00000003U #define LP_TEE_M0_MODE_S 0 /** LP_TEE_M0_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures to lock the value of LP_TEE_M0_MODE. + * 0: Do not lock + * 1: Lock */ #define LP_TEE_M0_LOCK (BIT(2)) #define LP_TEE_M0_LOCK_M (LP_TEE_M0_LOCK_V << LP_TEE_M0_LOCK_S) @@ -35,7 +37,7 @@ extern "C" { #define LP_TEE_M0_LOCK_S 2 /** LP_TEE_EFUSE_CTRL_REG register - * efuse read/write control register + * eFuse read/write control register */ #define LP_TEE_EFUSE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x4) /** LP_TEE_READ_TEE_EFUSE : R/W; bitpos: [0]; default: 1; @@ -112,7 +114,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_EFUSE_S 7 /** LP_TEE_PMU_CTRL_REG register - * pmu read/write control register + * PMU read/write control register */ #define LP_TEE_PMU_CTRL_REG (DR_REG_LP_TEE_BASE + 0x8) /** LP_TEE_READ_TEE_PMU : R/W; bitpos: [0]; default: 1; @@ -189,7 +191,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_PMU_S 7 /** LP_TEE_CLKRST_CTRL_REG register - * clkrst read/write control register + * LP_CLKRST read/write control register */ #define LP_TEE_CLKRST_CTRL_REG (DR_REG_LP_TEE_BASE + 0xc) /** LP_TEE_READ_TEE_CLKRST : R/W; bitpos: [0]; default: 1; @@ -266,7 +268,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_CLKRST_S 7 /** LP_TEE_LP_AON_CTRL_CTRL_REG register - * lp_aon_ctrl read/write control register + * LP_AON read/write control register */ #define LP_TEE_LP_AON_CTRL_CTRL_REG (DR_REG_LP_TEE_BASE + 0x10) /** LP_TEE_READ_TEE_LP_AON_CTRL : R/W; bitpos: [0]; default: 1; @@ -343,7 +345,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_AON_CTRL_S 7 /** LP_TEE_LP_TIMER_CTRL_REG register - * lp_timer read/write control register + * LP_TIMER read/write control register */ #define LP_TEE_LP_TIMER_CTRL_REG (DR_REG_LP_TEE_BASE + 0x14) /** LP_TEE_READ_TEE_LP_TIMER : R/W; bitpos: [0]; default: 1; @@ -420,7 +422,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_TIMER_S 7 /** LP_TEE_LP_WDT_CTRL_REG register - * lp_wdt read/write control register + * LP_WDT read/write control register */ #define LP_TEE_LP_WDT_CTRL_REG (DR_REG_LP_TEE_BASE + 0x18) /** LP_TEE_READ_TEE_LP_WDT : R/W; bitpos: [0]; default: 1; @@ -497,7 +499,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_WDT_S 7 /** LP_TEE_LP_PERI_CTRL_REG register - * lp_peri read/write control register + * LPPERI read/write control register */ #define LP_TEE_LP_PERI_CTRL_REG (DR_REG_LP_TEE_BASE + 0x1c) /** LP_TEE_READ_TEE_LP_PERI : R/W; bitpos: [0]; default: 1; @@ -574,7 +576,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_PERI_S 7 /** LP_TEE_LP_ANA_PERI_CTRL_REG register - * lp_ana_peri read/write control register + * LP_ANA_PERI read/write control register */ #define LP_TEE_LP_ANA_PERI_CTRL_REG (DR_REG_LP_TEE_BASE + 0x20) /** LP_TEE_READ_TEE_LP_ANA_PERI : R/W; bitpos: [0]; default: 1; @@ -651,7 +653,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_ANA_PERI_S 7 /** LP_TEE_LP_IO_CTRL_REG register - * lp_io read/write control register + * LP_GPIO and LP_IO_MUX read/write control register */ #define LP_TEE_LP_IO_CTRL_REG (DR_REG_LP_TEE_BASE + 0x2c) /** LP_TEE_READ_TEE_LP_IO : R/W; bitpos: [0]; default: 1; @@ -728,7 +730,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_IO_S 7 /** LP_TEE_LP_TEE_CTRL_REG register - * lp_tee read/write control register + * LP_TEE read/write control register */ #define LP_TEE_LP_TEE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x34) /** LP_TEE_READ_TEE_LP_TEE : R/W; bitpos: [0]; default: 1; @@ -805,7 +807,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_TEE_S 7 /** LP_TEE_UART_CTRL_REG register - * uart read/write control register + * LP_UART read/write control register */ #define LP_TEE_UART_CTRL_REG (DR_REG_LP_TEE_BASE + 0x38) /** LP_TEE_READ_TEE_UART : R/W; bitpos: [0]; default: 1; @@ -882,7 +884,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_UART_S 7 /** LP_TEE_I2C_EXT_CTRL_REG register - * i2c_ext read/write control register + * LP_I2C read/write control register */ #define LP_TEE_I2C_EXT_CTRL_REG (DR_REG_LP_TEE_BASE + 0x40) /** LP_TEE_READ_TEE_I2C_EXT : R/W; bitpos: [0]; default: 1; @@ -959,7 +961,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_I2C_EXT_S 7 /** LP_TEE_I2C_ANA_MST_CTRL_REG register - * i2c_ana_mst read/write control register + * I2C_ANA_MST read/write control register */ #define LP_TEE_I2C_ANA_MST_CTRL_REG (DR_REG_LP_TEE_BASE + 0x44) /** LP_TEE_READ_TEE_I2C_ANA_MST : R/W; bitpos: [0]; default: 1; @@ -1035,85 +1037,8 @@ extern "C" { #define LP_TEE_WRITE_REE2_I2C_ANA_MST_V 0x00000001U #define LP_TEE_WRITE_REE2_I2C_ANA_MST_S 7 -/** LP_TEE_HUK_CTRL_REG register - * huk read/write control register - */ -#define LP_TEE_HUK_CTRL_REG (DR_REG_LP_TEE_BASE + 0x48) -/** LP_TEE_READ_TEE_HUK : R/W; bitpos: [0]; default: 1; - * Configures huk registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define LP_TEE_READ_TEE_HUK (BIT(0)) -#define LP_TEE_READ_TEE_HUK_M (LP_TEE_READ_TEE_HUK_V << LP_TEE_READ_TEE_HUK_S) -#define LP_TEE_READ_TEE_HUK_V 0x00000001U -#define LP_TEE_READ_TEE_HUK_S 0 -/** LP_TEE_READ_REE0_HUK : R/W; bitpos: [1]; default: 0; - * Configures huk registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define LP_TEE_READ_REE0_HUK (BIT(1)) -#define LP_TEE_READ_REE0_HUK_M (LP_TEE_READ_REE0_HUK_V << LP_TEE_READ_REE0_HUK_S) -#define LP_TEE_READ_REE0_HUK_V 0x00000001U -#define LP_TEE_READ_REE0_HUK_S 1 -/** LP_TEE_READ_REE1_HUK : R/W; bitpos: [2]; default: 0; - * Configures huk registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define LP_TEE_READ_REE1_HUK (BIT(2)) -#define LP_TEE_READ_REE1_HUK_M (LP_TEE_READ_REE1_HUK_V << LP_TEE_READ_REE1_HUK_S) -#define LP_TEE_READ_REE1_HUK_V 0x00000001U -#define LP_TEE_READ_REE1_HUK_S 2 -/** LP_TEE_READ_REE2_HUK : R/W; bitpos: [3]; default: 0; - * Configures huk registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define LP_TEE_READ_REE2_HUK (BIT(3)) -#define LP_TEE_READ_REE2_HUK_M (LP_TEE_READ_REE2_HUK_V << LP_TEE_READ_REE2_HUK_S) -#define LP_TEE_READ_REE2_HUK_V 0x00000001U -#define LP_TEE_READ_REE2_HUK_S 3 -/** LP_TEE_WRITE_TEE_HUK : R/W; bitpos: [4]; default: 1; - * Configures huk registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define LP_TEE_WRITE_TEE_HUK (BIT(4)) -#define LP_TEE_WRITE_TEE_HUK_M (LP_TEE_WRITE_TEE_HUK_V << LP_TEE_WRITE_TEE_HUK_S) -#define LP_TEE_WRITE_TEE_HUK_V 0x00000001U -#define LP_TEE_WRITE_TEE_HUK_S 4 -/** LP_TEE_WRITE_REE0_HUK : R/W; bitpos: [5]; default: 0; - * Configures huk registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define LP_TEE_WRITE_REE0_HUK (BIT(5)) -#define LP_TEE_WRITE_REE0_HUK_M (LP_TEE_WRITE_REE0_HUK_V << LP_TEE_WRITE_REE0_HUK_S) -#define LP_TEE_WRITE_REE0_HUK_V 0x00000001U -#define LP_TEE_WRITE_REE0_HUK_S 5 -/** LP_TEE_WRITE_REE1_HUK : R/W; bitpos: [6]; default: 0; - * Configures huk registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define LP_TEE_WRITE_REE1_HUK (BIT(6)) -#define LP_TEE_WRITE_REE1_HUK_M (LP_TEE_WRITE_REE1_HUK_V << LP_TEE_WRITE_REE1_HUK_S) -#define LP_TEE_WRITE_REE1_HUK_V 0x00000001U -#define LP_TEE_WRITE_REE1_HUK_S 6 -/** LP_TEE_WRITE_REE2_HUK : R/W; bitpos: [7]; default: 0; - * Configures huk registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define LP_TEE_WRITE_REE2_HUK (BIT(7)) -#define LP_TEE_WRITE_REE2_HUK_M (LP_TEE_WRITE_REE2_HUK_V << LP_TEE_WRITE_REE2_HUK_S) -#define LP_TEE_WRITE_REE2_HUK_V 0x00000001U -#define LP_TEE_WRITE_REE2_HUK_S 7 - /** LP_TEE_LP_APM_CTRL_REG register - * lp_apm read/write control register + * LP_APM read/write control register */ #define LP_TEE_LP_APM_CTRL_REG (DR_REG_LP_TEE_BASE + 0x4c) /** LP_TEE_READ_TEE_LP_APM : R/W; bitpos: [0]; default: 1; @@ -1190,14 +1115,14 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_APM_S 7 /** LP_TEE_FORCE_ACC_HP_REG register - * Force access to hpmem configuration register + * Force access to HP SRAM configuration register */ #define LP_TEE_FORCE_ACC_HP_REG (DR_REG_LP_TEE_BASE + 0x90) /** LP_TEE_FORCE_ACC_HPMEM_EN : R/W; bitpos: [0]; default: 0; - * Configures whether to allow LP CPU to force access to HP_MEM regardless of + * Configures whether to allow LP CPU to forcibly access HP SRAM regardless of * permission management. - * 0: disable force access HP_MEM - * 1: enable force access HP_MEM + * 0: Disable force access to HP SRAM + * 1: Enable force access to HP SRAM */ #define LP_TEE_FORCE_ACC_HPMEM_EN (BIT(0)) #define LP_TEE_FORCE_ACC_HPMEM_EN_M (LP_TEE_FORCE_ACC_HPMEM_EN_V << LP_TEE_FORCE_ACC_HPMEM_EN_S) @@ -1205,13 +1130,13 @@ extern "C" { #define LP_TEE_FORCE_ACC_HPMEM_EN_S 0 /** LP_TEE_BUS_ERR_CONF_REG register - * Clock gating register + * Error message return configuration register */ #define LP_TEE_BUS_ERR_CONF_REG (DR_REG_LP_TEE_BASE + 0xf0) /** LP_TEE_BUS_ERR_RESP_EN : R/W; bitpos: [0]; default: 0; - * Configures whether return error response to cpu when access blocked - * 0: disable error response - * 1: enable error response + * Configures whether to return error message to CPU when access is blocked. + * 0: Disable + * 1: Enable */ #define LP_TEE_BUS_ERR_RESP_EN (BIT(0)) #define LP_TEE_BUS_ERR_RESP_EN_M (LP_TEE_BUS_ERR_RESP_EN_V << LP_TEE_BUS_ERR_RESP_EN_S) @@ -1224,8 +1149,8 @@ extern "C" { #define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0xf8) /** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ #define LP_TEE_CLK_EN (BIT(0)) #define LP_TEE_CLK_EN_M (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S) @@ -1237,7 +1162,7 @@ extern "C" { */ #define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc) /** LP_TEE_DATE : R/W; bitpos: [27:0]; default: 2363416; - * Version control register + * Version control register. */ #define LP_TEE_DATE 0x0FFFFFFFU #define LP_TEE_DATE_M (LP_TEE_DATE_V << LP_TEE_DATE_S) diff --git a/components/soc/esp32c5/register/soc/lp_tee_struct.h b/components/soc/esp32c5/register/soc/lp_tee_struct.h index 8158b54d22..e344cec804 100644 --- a/components/soc/esp32c5/register/soc/lp_tee_struct.h +++ b/components/soc/esp32c5/register/soc/lp_tee_struct.h @@ -10,22 +10,24 @@ extern "C" { #endif -/** Group: Tee mode control register */ +/** Group: Configuration Registers */ /** Type of m0_mode_ctrl register - * TEE mode control register + * Security mode configuration register */ typedef union { struct { /** m0_mode : R/W; bitpos: [1:0]; default: 3; - * Configures M0 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for LP CPU. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ uint32_t m0_mode:2; /** m0_lock : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures to lock the value of LP_TEE_M0_MODE. + * 0: Do not lock + * 1: Lock */ uint32_t m0_lock:1; uint32_t reserved_3:29; @@ -34,9 +36,9 @@ typedef union { } lp_tee_m0_mode_ctrl_reg_t; -/** Group: read write control register */ +/** Group: Peripheral Read/Write Control Register */ /** Type of efuse_ctrl register - * efuse read/write control register + * eFuse read/write control register */ typedef union { struct { @@ -94,7 +96,7 @@ typedef union { } lp_tee_efuse_ctrl_reg_t; /** Type of pmu_ctrl register - * pmu read/write control register + * PMU read/write control register */ typedef union { struct { @@ -152,7 +154,7 @@ typedef union { } lp_tee_pmu_ctrl_reg_t; /** Type of clkrst_ctrl register - * clkrst read/write control register + * LP_CLKRST read/write control register */ typedef union { struct { @@ -210,7 +212,7 @@ typedef union { } lp_tee_clkrst_ctrl_reg_t; /** Type of lp_aon_ctrl_ctrl register - * lp_aon_ctrl read/write control register + * LP_AON read/write control register */ typedef union { struct { @@ -268,7 +270,7 @@ typedef union { } lp_tee_lp_aon_ctrl_ctrl_reg_t; /** Type of lp_timer_ctrl register - * lp_timer read/write control register + * LP_TIMER read/write control register */ typedef union { struct { @@ -326,7 +328,7 @@ typedef union { } lp_tee_lp_timer_ctrl_reg_t; /** Type of lp_wdt_ctrl register - * lp_wdt read/write control register + * LP_WDT read/write control register */ typedef union { struct { @@ -384,7 +386,7 @@ typedef union { } lp_tee_lp_wdt_ctrl_reg_t; /** Type of lp_peri_ctrl register - * lp_peri read/write control register + * LPPERI read/write control register */ typedef union { struct { @@ -442,7 +444,7 @@ typedef union { } lp_tee_lp_peri_ctrl_reg_t; /** Type of lp_ana_peri_ctrl register - * lp_ana_peri read/write control register + * LP_ANA_PERI read/write control register */ typedef union { struct { @@ -500,7 +502,7 @@ typedef union { } lp_tee_lp_ana_peri_ctrl_reg_t; /** Type of lp_io_ctrl register - * lp_io read/write control register + * LP_GPIO and LP_IO_MUX read/write control register */ typedef union { struct { @@ -558,7 +560,7 @@ typedef union { } lp_tee_lp_io_ctrl_reg_t; /** Type of lp_tee_ctrl register - * lp_tee read/write control register + * LP_TEE read/write control register */ typedef union { struct { @@ -616,7 +618,7 @@ typedef union { } lp_tee_lp_tee_ctrl_reg_t; /** Type of uart_ctrl register - * uart read/write control register + * LP_UART read/write control register */ typedef union { struct { @@ -674,7 +676,7 @@ typedef union { } lp_tee_uart_ctrl_reg_t; /** Type of i2c_ext_ctrl register - * i2c_ext read/write control register + * LP_I2C read/write control register */ typedef union { struct { @@ -732,7 +734,7 @@ typedef union { } lp_tee_i2c_ext_ctrl_reg_t; /** Type of i2c_ana_mst_ctrl register - * i2c_ana_mst read/write control register + * I2C_ANA_MST read/write control register */ typedef union { struct { @@ -789,66 +791,8 @@ typedef union { uint32_t val; } lp_tee_i2c_ana_mst_ctrl_reg_t; -/** Type of huk_ctrl register - * huk read/write control register - */ -typedef union { - struct { - /** read_tee_huk : R/W; bitpos: [0]; default: 1; - * Configures huk registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_huk:1; - /** read_ree0_huk : R/W; bitpos: [1]; default: 0; - * Configures huk registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_huk:1; - /** read_ree1_huk : R/W; bitpos: [2]; default: 0; - * Configures huk registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_huk:1; - /** read_ree2_huk : R/W; bitpos: [3]; default: 0; - * Configures huk registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_huk:1; - /** write_tee_huk : R/W; bitpos: [4]; default: 1; - * Configures huk registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_huk:1; - /** write_ree0_huk : R/W; bitpos: [5]; default: 0; - * Configures huk registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_huk:1; - /** write_ree1_huk : R/W; bitpos: [6]; default: 0; - * Configures huk registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_huk:1; - /** write_ree2_huk : R/W; bitpos: [7]; default: 0; - * Configures huk registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_huk:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} lp_tee_huk_ctrl_reg_t; - /** Type of lp_apm_ctrl register - * lp_apm read/write control register + * LP_APM read/write control register */ typedef union { struct { @@ -905,18 +849,16 @@ typedef union { uint32_t val; } lp_tee_lp_apm_ctrl_reg_t; - -/** Group: Force access to hpmem configuration register */ /** Type of force_acc_hp register - * Force access to hpmem configuration register + * Force access to HP SRAM configuration register */ typedef union { struct { /** force_acc_hpmem_en : R/W; bitpos: [0]; default: 0; - * Configures whether to allow LP CPU to force access to HP_MEM regardless of + * Configures whether to allow LP CPU to forcibly access HP SRAM regardless of * permission management. - * 0: disable force access HP_MEM - * 1: enable force access HP_MEM + * 0: Disable force access to HP SRAM + * 1: Enable force access to HP SRAM */ uint32_t force_acc_hpmem_en:1; uint32_t reserved_1:31; @@ -924,17 +866,15 @@ typedef union { uint32_t val; } lp_tee_force_acc_hp_reg_t; - -/** Group: config register */ /** Type of bus_err_conf register - * Clock gating register + * Error message return configuration register */ typedef union { struct { /** bus_err_resp_en : R/W; bitpos: [0]; default: 0; - * Configures whether return error response to cpu when access blocked - * 0: disable error response - * 1: enable error response + * Configures whether to return error message to CPU when access is blocked. + * 0: Disable + * 1: Enable */ uint32_t bus_err_resp_en:1; uint32_t reserved_1:31; @@ -943,7 +883,7 @@ typedef union { } lp_tee_bus_err_conf_reg_t; -/** Group: clock gating register */ +/** Group: Clock Gating Registers */ /** Type of clock_gate register * Clock gating register */ @@ -951,8 +891,8 @@ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -961,14 +901,14 @@ typedef union { } lp_tee_clock_gate_reg_t; -/** Group: Version control register */ +/** Group: Version Control Registers */ /** Type of date register * Version control register */ typedef union { struct { /** date : R/W; bitpos: [27:0]; default: 2363416; - * Version control register + * Version control register. */ uint32_t date:28; uint32_t reserved_28:4; @@ -995,7 +935,7 @@ typedef struct { uint32_t reserved_03c; volatile lp_tee_i2c_ext_ctrl_reg_t i2c_ext_ctrl; volatile lp_tee_i2c_ana_mst_ctrl_reg_t i2c_ana_mst_ctrl; - volatile lp_tee_huk_ctrl_reg_t huk_ctrl; + uint32_t reserved_048; volatile lp_tee_lp_apm_ctrl_reg_t lp_apm_ctrl; uint32_t reserved_050[16]; volatile lp_tee_force_acc_hp_reg_t force_acc_hp; diff --git a/components/soc/esp32c5/register/soc/tee_reg.h b/components/soc/esp32c5/register/soc/tee_reg.h index 48caf26c3d..398d4bc235 100644 --- a/components/soc/esp32c5/register/soc/tee_reg.h +++ b/components/soc/esp32c5/register/soc/tee_reg.h @@ -12,22 +12,24 @@ extern "C" { #endif /** TEE_M0_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M0_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x0) /** TEE_M0_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M0 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 0. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M0_MODE 0x00000003U #define TEE_M0_MODE_M (TEE_M0_MODE_V << TEE_M0_MODE_S) #define TEE_M0_MODE_V 0x00000003U #define TEE_M0_MODE_S 0 /** TEE_M0_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M0_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M0_LOCK (BIT(2)) #define TEE_M0_LOCK_M (TEE_M0_LOCK_V << TEE_M0_LOCK_S) @@ -35,22 +37,24 @@ extern "C" { #define TEE_M0_LOCK_S 2 /** TEE_M1_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M1_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4) /** TEE_M1_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M1 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 1. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M1_MODE 0x00000003U #define TEE_M1_MODE_M (TEE_M1_MODE_V << TEE_M1_MODE_S) #define TEE_M1_MODE_V 0x00000003U #define TEE_M1_MODE_S 0 /** TEE_M1_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M1_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M1_LOCK (BIT(2)) #define TEE_M1_LOCK_M (TEE_M1_LOCK_V << TEE_M1_LOCK_S) @@ -58,22 +62,24 @@ extern "C" { #define TEE_M1_LOCK_S 2 /** TEE_M2_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M2_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x8) /** TEE_M2_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M2 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 2. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M2_MODE 0x00000003U #define TEE_M2_MODE_M (TEE_M2_MODE_V << TEE_M2_MODE_S) #define TEE_M2_MODE_V 0x00000003U #define TEE_M2_MODE_S 0 /** TEE_M2_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M2_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M2_LOCK (BIT(2)) #define TEE_M2_LOCK_M (TEE_M2_LOCK_V << TEE_M2_LOCK_S) @@ -81,22 +87,24 @@ extern "C" { #define TEE_M2_LOCK_S 2 /** TEE_M3_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M3_MODE_CTRL_REG (DR_REG_TEE_BASE + 0xc) /** TEE_M3_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M3 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 3. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M3_MODE 0x00000003U #define TEE_M3_MODE_M (TEE_M3_MODE_V << TEE_M3_MODE_S) #define TEE_M3_MODE_V 0x00000003U #define TEE_M3_MODE_S 0 /** TEE_M3_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M3_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M3_LOCK (BIT(2)) #define TEE_M3_LOCK_M (TEE_M3_LOCK_V << TEE_M3_LOCK_S) @@ -104,22 +112,24 @@ extern "C" { #define TEE_M3_LOCK_S 2 /** TEE_M4_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M4_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x10) /** TEE_M4_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M4 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 4. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M4_MODE 0x00000003U #define TEE_M4_MODE_M (TEE_M4_MODE_V << TEE_M4_MODE_S) #define TEE_M4_MODE_V 0x00000003U #define TEE_M4_MODE_S 0 /** TEE_M4_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M4_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M4_LOCK (BIT(2)) #define TEE_M4_LOCK_M (TEE_M4_LOCK_V << TEE_M4_LOCK_S) @@ -127,22 +137,24 @@ extern "C" { #define TEE_M4_LOCK_S 2 /** TEE_M5_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M5_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x14) /** TEE_M5_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M5 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 5. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M5_MODE 0x00000003U #define TEE_M5_MODE_M (TEE_M5_MODE_V << TEE_M5_MODE_S) #define TEE_M5_MODE_V 0x00000003U #define TEE_M5_MODE_S 0 /** TEE_M5_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M5_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M5_LOCK (BIT(2)) #define TEE_M5_LOCK_M (TEE_M5_LOCK_V << TEE_M5_LOCK_S) @@ -150,22 +162,24 @@ extern "C" { #define TEE_M5_LOCK_S 2 /** TEE_M6_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M6_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x18) /** TEE_M6_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M6 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 6. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M6_MODE 0x00000003U #define TEE_M6_MODE_M (TEE_M6_MODE_V << TEE_M6_MODE_S) #define TEE_M6_MODE_V 0x00000003U #define TEE_M6_MODE_S 0 /** TEE_M6_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M6_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M6_LOCK (BIT(2)) #define TEE_M6_LOCK_M (TEE_M6_LOCK_V << TEE_M6_LOCK_S) @@ -173,22 +187,24 @@ extern "C" { #define TEE_M6_LOCK_S 2 /** TEE_M7_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M7_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x1c) /** TEE_M7_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M7 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 7. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M7_MODE 0x00000003U #define TEE_M7_MODE_M (TEE_M7_MODE_V << TEE_M7_MODE_S) #define TEE_M7_MODE_V 0x00000003U #define TEE_M7_MODE_S 0 /** TEE_M7_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M7_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M7_LOCK (BIT(2)) #define TEE_M7_LOCK_M (TEE_M7_LOCK_V << TEE_M7_LOCK_S) @@ -196,22 +212,24 @@ extern "C" { #define TEE_M7_LOCK_S 2 /** TEE_M8_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M8_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x20) /** TEE_M8_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M8 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 8. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M8_MODE 0x00000003U #define TEE_M8_MODE_M (TEE_M8_MODE_V << TEE_M8_MODE_S) #define TEE_M8_MODE_V 0x00000003U #define TEE_M8_MODE_S 0 /** TEE_M8_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M8_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M8_LOCK (BIT(2)) #define TEE_M8_LOCK_M (TEE_M8_LOCK_V << TEE_M8_LOCK_S) @@ -219,22 +237,24 @@ extern "C" { #define TEE_M8_LOCK_S 2 /** TEE_M9_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M9_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x24) /** TEE_M9_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M9 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 9. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M9_MODE 0x00000003U #define TEE_M9_MODE_M (TEE_M9_MODE_V << TEE_M9_MODE_S) #define TEE_M9_MODE_V 0x00000003U #define TEE_M9_MODE_S 0 /** TEE_M9_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M9_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M9_LOCK (BIT(2)) #define TEE_M9_LOCK_M (TEE_M9_LOCK_V << TEE_M9_LOCK_S) @@ -242,22 +262,24 @@ extern "C" { #define TEE_M9_LOCK_S 2 /** TEE_M10_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M10_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x28) /** TEE_M10_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M10 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 10. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M10_MODE 0x00000003U #define TEE_M10_MODE_M (TEE_M10_MODE_V << TEE_M10_MODE_S) #define TEE_M10_MODE_V 0x00000003U #define TEE_M10_MODE_S 0 /** TEE_M10_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M10_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M10_LOCK (BIT(2)) #define TEE_M10_LOCK_M (TEE_M10_LOCK_V << TEE_M10_LOCK_S) @@ -265,22 +287,24 @@ extern "C" { #define TEE_M10_LOCK_S 2 /** TEE_M11_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M11_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x2c) /** TEE_M11_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M11 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 11. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M11_MODE 0x00000003U #define TEE_M11_MODE_M (TEE_M11_MODE_V << TEE_M11_MODE_S) #define TEE_M11_MODE_V 0x00000003U #define TEE_M11_MODE_S 0 /** TEE_M11_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M11_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M11_LOCK (BIT(2)) #define TEE_M11_LOCK_M (TEE_M11_LOCK_V << TEE_M11_LOCK_S) @@ -288,22 +312,24 @@ extern "C" { #define TEE_M11_LOCK_S 2 /** TEE_M12_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M12_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x30) /** TEE_M12_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M12 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 12. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M12_MODE 0x00000003U #define TEE_M12_MODE_M (TEE_M12_MODE_V << TEE_M12_MODE_S) #define TEE_M12_MODE_V 0x00000003U #define TEE_M12_MODE_S 0 /** TEE_M12_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M12_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M12_LOCK (BIT(2)) #define TEE_M12_LOCK_M (TEE_M12_LOCK_V << TEE_M12_LOCK_S) @@ -311,22 +337,24 @@ extern "C" { #define TEE_M12_LOCK_S 2 /** TEE_M13_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M13_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x34) /** TEE_M13_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M13 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 13. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M13_MODE 0x00000003U #define TEE_M13_MODE_M (TEE_M13_MODE_V << TEE_M13_MODE_S) #define TEE_M13_MODE_V 0x00000003U #define TEE_M13_MODE_S 0 /** TEE_M13_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M13_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M13_LOCK (BIT(2)) #define TEE_M13_LOCK_M (TEE_M13_LOCK_V << TEE_M13_LOCK_S) @@ -334,22 +362,24 @@ extern "C" { #define TEE_M13_LOCK_S 2 /** TEE_M14_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M14_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x38) /** TEE_M14_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M14 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 14. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M14_MODE 0x00000003U #define TEE_M14_MODE_M (TEE_M14_MODE_V << TEE_M14_MODE_S) #define TEE_M14_MODE_V 0x00000003U #define TEE_M14_MODE_S 0 /** TEE_M14_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M14_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M14_LOCK (BIT(2)) #define TEE_M14_LOCK_M (TEE_M14_LOCK_V << TEE_M14_LOCK_S) @@ -357,22 +387,24 @@ extern "C" { #define TEE_M14_LOCK_S 2 /** TEE_M15_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M15_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x3c) /** TEE_M15_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M15 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 15. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M15_MODE 0x00000003U #define TEE_M15_MODE_M (TEE_M15_MODE_V << TEE_M15_MODE_S) #define TEE_M15_MODE_V 0x00000003U #define TEE_M15_MODE_S 0 /** TEE_M15_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M15_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M15_LOCK (BIT(2)) #define TEE_M15_LOCK_M (TEE_M15_LOCK_V << TEE_M15_LOCK_S) @@ -380,22 +412,24 @@ extern "C" { #define TEE_M15_LOCK_S 2 /** TEE_M16_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M16_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x40) /** TEE_M16_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M16 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 16. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M16_MODE 0x00000003U #define TEE_M16_MODE_M (TEE_M16_MODE_V << TEE_M16_MODE_S) #define TEE_M16_MODE_V 0x00000003U #define TEE_M16_MODE_S 0 /** TEE_M16_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M16_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M16_LOCK (BIT(2)) #define TEE_M16_LOCK_M (TEE_M16_LOCK_V << TEE_M16_LOCK_S) @@ -403,22 +437,24 @@ extern "C" { #define TEE_M16_LOCK_S 2 /** TEE_M17_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M17_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x44) /** TEE_M17_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M17 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 17. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M17_MODE 0x00000003U #define TEE_M17_MODE_M (TEE_M17_MODE_V << TEE_M17_MODE_S) #define TEE_M17_MODE_V 0x00000003U #define TEE_M17_MODE_S 0 /** TEE_M17_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M17_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M17_LOCK (BIT(2)) #define TEE_M17_LOCK_M (TEE_M17_LOCK_V << TEE_M17_LOCK_S) @@ -426,22 +462,24 @@ extern "C" { #define TEE_M17_LOCK_S 2 /** TEE_M18_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M18_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x48) /** TEE_M18_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M18 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 18. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M18_MODE 0x00000003U #define TEE_M18_MODE_M (TEE_M18_MODE_V << TEE_M18_MODE_S) #define TEE_M18_MODE_V 0x00000003U #define TEE_M18_MODE_S 0 /** TEE_M18_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M18_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M18_LOCK (BIT(2)) #define TEE_M18_LOCK_M (TEE_M18_LOCK_V << TEE_M18_LOCK_S) @@ -449,22 +487,24 @@ extern "C" { #define TEE_M18_LOCK_S 2 /** TEE_M19_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M19_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4c) /** TEE_M19_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M19 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 19. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M19_MODE 0x00000003U #define TEE_M19_MODE_M (TEE_M19_MODE_V << TEE_M19_MODE_S) #define TEE_M19_MODE_V 0x00000003U #define TEE_M19_MODE_S 0 /** TEE_M19_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M19_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M19_LOCK (BIT(2)) #define TEE_M19_LOCK_M (TEE_M19_LOCK_V << TEE_M19_LOCK_S) @@ -472,22 +512,24 @@ extern "C" { #define TEE_M19_LOCK_S 2 /** TEE_M20_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M20_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x50) /** TEE_M20_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M20 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 20. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M20_MODE 0x00000003U #define TEE_M20_MODE_M (TEE_M20_MODE_V << TEE_M20_MODE_S) #define TEE_M20_MODE_V 0x00000003U #define TEE_M20_MODE_S 0 /** TEE_M20_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M20_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M20_LOCK (BIT(2)) #define TEE_M20_LOCK_M (TEE_M20_LOCK_V << TEE_M20_LOCK_S) @@ -495,22 +537,24 @@ extern "C" { #define TEE_M20_LOCK_S 2 /** TEE_M21_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M21_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x54) /** TEE_M21_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M21 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 21. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M21_MODE 0x00000003U #define TEE_M21_MODE_M (TEE_M21_MODE_V << TEE_M21_MODE_S) #define TEE_M21_MODE_V 0x00000003U #define TEE_M21_MODE_S 0 /** TEE_M21_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M21_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M21_LOCK (BIT(2)) #define TEE_M21_LOCK_M (TEE_M21_LOCK_V << TEE_M21_LOCK_S) @@ -518,22 +562,24 @@ extern "C" { #define TEE_M21_LOCK_S 2 /** TEE_M22_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M22_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x58) /** TEE_M22_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M22 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 22. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M22_MODE 0x00000003U #define TEE_M22_MODE_M (TEE_M22_MODE_V << TEE_M22_MODE_S) #define TEE_M22_MODE_V 0x00000003U #define TEE_M22_MODE_S 0 /** TEE_M22_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M22_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M22_LOCK (BIT(2)) #define TEE_M22_LOCK_M (TEE_M22_LOCK_V << TEE_M22_LOCK_S) @@ -541,22 +587,24 @@ extern "C" { #define TEE_M22_LOCK_S 2 /** TEE_M23_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M23_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x5c) /** TEE_M23_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M23 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 23. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M23_MODE 0x00000003U #define TEE_M23_MODE_M (TEE_M23_MODE_V << TEE_M23_MODE_S) #define TEE_M23_MODE_V 0x00000003U #define TEE_M23_MODE_S 0 /** TEE_M23_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M23_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M23_LOCK (BIT(2)) #define TEE_M23_LOCK_M (TEE_M23_LOCK_V << TEE_M23_LOCK_S) @@ -564,22 +612,24 @@ extern "C" { #define TEE_M23_LOCK_S 2 /** TEE_M24_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M24_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x60) /** TEE_M24_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M24 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 24. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M24_MODE 0x00000003U #define TEE_M24_MODE_M (TEE_M24_MODE_V << TEE_M24_MODE_S) #define TEE_M24_MODE_V 0x00000003U #define TEE_M24_MODE_S 0 /** TEE_M24_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M24_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M24_LOCK (BIT(2)) #define TEE_M24_LOCK_M (TEE_M24_LOCK_V << TEE_M24_LOCK_S) @@ -587,22 +637,24 @@ extern "C" { #define TEE_M24_LOCK_S 2 /** TEE_M25_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M25_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x64) /** TEE_M25_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M25 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 25. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M25_MODE 0x00000003U #define TEE_M25_MODE_M (TEE_M25_MODE_V << TEE_M25_MODE_S) #define TEE_M25_MODE_V 0x00000003U #define TEE_M25_MODE_S 0 /** TEE_M25_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M25_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M25_LOCK (BIT(2)) #define TEE_M25_LOCK_M (TEE_M25_LOCK_V << TEE_M25_LOCK_S) @@ -610,22 +662,24 @@ extern "C" { #define TEE_M25_LOCK_S 2 /** TEE_M26_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M26_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x68) /** TEE_M26_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M26 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 26. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M26_MODE 0x00000003U #define TEE_M26_MODE_M (TEE_M26_MODE_V << TEE_M26_MODE_S) #define TEE_M26_MODE_V 0x00000003U #define TEE_M26_MODE_S 0 /** TEE_M26_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M26_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M26_LOCK (BIT(2)) #define TEE_M26_LOCK_M (TEE_M26_LOCK_V << TEE_M26_LOCK_S) @@ -633,22 +687,24 @@ extern "C" { #define TEE_M26_LOCK_S 2 /** TEE_M27_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M27_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x6c) /** TEE_M27_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M27 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 27. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M27_MODE 0x00000003U #define TEE_M27_MODE_M (TEE_M27_MODE_V << TEE_M27_MODE_S) #define TEE_M27_MODE_V 0x00000003U #define TEE_M27_MODE_S 0 /** TEE_M27_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M27_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M27_LOCK (BIT(2)) #define TEE_M27_LOCK_M (TEE_M27_LOCK_V << TEE_M27_LOCK_S) @@ -656,22 +712,24 @@ extern "C" { #define TEE_M27_LOCK_S 2 /** TEE_M28_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M28_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x70) /** TEE_M28_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M28 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 28. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M28_MODE 0x00000003U #define TEE_M28_MODE_M (TEE_M28_MODE_V << TEE_M28_MODE_S) #define TEE_M28_MODE_V 0x00000003U #define TEE_M28_MODE_S 0 /** TEE_M28_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M28_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M28_LOCK (BIT(2)) #define TEE_M28_LOCK_M (TEE_M28_LOCK_V << TEE_M28_LOCK_S) @@ -679,22 +737,24 @@ extern "C" { #define TEE_M28_LOCK_S 2 /** TEE_M29_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M29_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x74) /** TEE_M29_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M29 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 29. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M29_MODE 0x00000003U #define TEE_M29_MODE_M (TEE_M29_MODE_V << TEE_M29_MODE_S) #define TEE_M29_MODE_V 0x00000003U #define TEE_M29_MODE_S 0 /** TEE_M29_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M29_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M29_LOCK (BIT(2)) #define TEE_M29_LOCK_M (TEE_M29_LOCK_V << TEE_M29_LOCK_S) @@ -702,22 +762,24 @@ extern "C" { #define TEE_M29_LOCK_S 2 /** TEE_M30_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M30_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x78) /** TEE_M30_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M30 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 30. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M30_MODE 0x00000003U #define TEE_M30_MODE_M (TEE_M30_MODE_V << TEE_M30_MODE_S) #define TEE_M30_MODE_V 0x00000003U #define TEE_M30_MODE_S 0 /** TEE_M30_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M30_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M30_LOCK (BIT(2)) #define TEE_M30_LOCK_M (TEE_M30_LOCK_V << TEE_M30_LOCK_S) @@ -725,22 +787,24 @@ extern "C" { #define TEE_M30_LOCK_S 2 /** TEE_M31_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M31_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x7c) /** TEE_M31_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M31 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 31. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M31_MODE 0x00000003U #define TEE_M31_MODE_M (TEE_M31_MODE_V << TEE_M31_MODE_S) #define TEE_M31_MODE_V 0x00000003U #define TEE_M31_MODE_S 0 /** TEE_M31_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M31_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M31_LOCK (BIT(2)) #define TEE_M31_LOCK_M (TEE_M31_LOCK_V << TEE_M31_LOCK_S) @@ -748,7 +812,7 @@ extern "C" { #define TEE_M31_LOCK_S 2 /** TEE_UART0_CTRL_REG register - * uart0 read/write control register + * UART0 read/write control register */ #define TEE_UART0_CTRL_REG (DR_REG_TEE_BASE + 0x88) /** TEE_READ_TEE_UART0 : R/W; bitpos: [0]; default: 1; @@ -825,7 +889,7 @@ extern "C" { #define TEE_WRITE_REE2_UART0_S 7 /** TEE_UART1_CTRL_REG register - * uart1 read/write control register + * UART1 read/write control register */ #define TEE_UART1_CTRL_REG (DR_REG_TEE_BASE + 0x8c) /** TEE_READ_TEE_UART1 : R/W; bitpos: [0]; default: 1; @@ -902,7 +966,7 @@ extern "C" { #define TEE_WRITE_REE2_UART1_S 7 /** TEE_UHCI0_CTRL_REG register - * uhci0 read/write control register + * UHCI read/write control register */ #define TEE_UHCI0_CTRL_REG (DR_REG_TEE_BASE + 0x90) /** TEE_READ_TEE_UHCI0 : R/W; bitpos: [0]; default: 1; @@ -979,7 +1043,7 @@ extern "C" { #define TEE_WRITE_REE2_UHCI0_S 7 /** TEE_I2C_EXT0_CTRL_REG register - * i2c_ext0 read/write control register + * I2C read/write control register */ #define TEE_I2C_EXT0_CTRL_REG (DR_REG_TEE_BASE + 0x94) /** TEE_READ_TEE_I2C_EXT0 : R/W; bitpos: [0]; default: 1; @@ -1056,7 +1120,7 @@ extern "C" { #define TEE_WRITE_REE2_I2C_EXT0_S 7 /** TEE_I2S_CTRL_REG register - * i2s read/write control register + * I2S read/write control register */ #define TEE_I2S_CTRL_REG (DR_REG_TEE_BASE + 0x9c) /** TEE_READ_TEE_I2S : R/W; bitpos: [0]; default: 1; @@ -1133,7 +1197,7 @@ extern "C" { #define TEE_WRITE_REE2_I2S_S 7 /** TEE_PARL_IO_CTRL_REG register - * parl_io read/write control register + * PARL_IO read/write control register */ #define TEE_PARL_IO_CTRL_REG (DR_REG_TEE_BASE + 0xa0) /** TEE_READ_TEE_PARL_IO : R/W; bitpos: [0]; default: 1; @@ -1210,7 +1274,7 @@ extern "C" { #define TEE_WRITE_REE2_PARL_IO_S 7 /** TEE_PWM_CTRL_REG register - * pwm read/write control register + * MCPWM read/write control register */ #define TEE_PWM_CTRL_REG (DR_REG_TEE_BASE + 0xa4) /** TEE_READ_TEE_PWM : R/W; bitpos: [0]; default: 1; @@ -1287,7 +1351,7 @@ extern "C" { #define TEE_WRITE_REE2_PWM_S 7 /** TEE_LEDC_CTRL_REG register - * ledc read/write control register + * LEDC read/write control register */ #define TEE_LEDC_CTRL_REG (DR_REG_TEE_BASE + 0xac) /** TEE_READ_TEE_LEDC : R/W; bitpos: [0]; default: 1; @@ -1363,162 +1427,162 @@ extern "C" { #define TEE_WRITE_REE2_LEDC_V 0x00000001U #define TEE_WRITE_REE2_LEDC_S 7 -/** TEE_CAN0_CTRL_REG register - * can read/write control register +/** TEE_TWAI0_CTRL_REG register + * TWAI0 read/write control register */ -#define TEE_CAN0_CTRL_REG (DR_REG_TEE_BASE + 0xb0) -/** TEE_READ_TEE_CAN0 : R/W; bitpos: [0]; default: 1; +#define TEE_TWAI0_CTRL_REG (DR_REG_TEE_BASE + 0xb0) +/** TEE_READ_TEE_TWAI0 : R/W; bitpos: [0]; default: 1; * Configures can0 registers read permission in tee mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_TEE_CAN0 (BIT(0)) -#define TEE_READ_TEE_CAN0_M (TEE_READ_TEE_CAN0_V << TEE_READ_TEE_CAN0_S) -#define TEE_READ_TEE_CAN0_V 0x00000001U -#define TEE_READ_TEE_CAN0_S 0 -/** TEE_READ_REE0_CAN0 : R/W; bitpos: [1]; default: 0; +#define TEE_READ_TEE_TWAI0 (BIT(0)) +#define TEE_READ_TEE_TWAI0_M (TEE_READ_TEE_TWAI0_V << TEE_READ_TEE_TWAI0_S) +#define TEE_READ_TEE_TWAI0_V 0x00000001U +#define TEE_READ_TEE_TWAI0_S 0 +/** TEE_READ_REE0_TWAI0 : R/W; bitpos: [1]; default: 0; * Configures can0 registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE0_CAN0 (BIT(1)) -#define TEE_READ_REE0_CAN0_M (TEE_READ_REE0_CAN0_V << TEE_READ_REE0_CAN0_S) -#define TEE_READ_REE0_CAN0_V 0x00000001U -#define TEE_READ_REE0_CAN0_S 1 -/** TEE_READ_REE1_CAN0 : R/W; bitpos: [2]; default: 0; +#define TEE_READ_REE0_TWAI0 (BIT(1)) +#define TEE_READ_REE0_TWAI0_M (TEE_READ_REE0_TWAI0_V << TEE_READ_REE0_TWAI0_S) +#define TEE_READ_REE0_TWAI0_V 0x00000001U +#define TEE_READ_REE0_TWAI0_S 1 +/** TEE_READ_REE1_TWAI0 : R/W; bitpos: [2]; default: 0; * Configures can0 registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE1_CAN0 (BIT(2)) -#define TEE_READ_REE1_CAN0_M (TEE_READ_REE1_CAN0_V << TEE_READ_REE1_CAN0_S) -#define TEE_READ_REE1_CAN0_V 0x00000001U -#define TEE_READ_REE1_CAN0_S 2 -/** TEE_READ_REE2_CAN0 : R/W; bitpos: [3]; default: 0; +#define TEE_READ_REE1_TWAI0 (BIT(2)) +#define TEE_READ_REE1_TWAI0_M (TEE_READ_REE1_TWAI0_V << TEE_READ_REE1_TWAI0_S) +#define TEE_READ_REE1_TWAI0_V 0x00000001U +#define TEE_READ_REE1_TWAI0_S 2 +/** TEE_READ_REE2_TWAI0 : R/W; bitpos: [3]; default: 0; * Configures can0 registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE2_CAN0 (BIT(3)) -#define TEE_READ_REE2_CAN0_M (TEE_READ_REE2_CAN0_V << TEE_READ_REE2_CAN0_S) -#define TEE_READ_REE2_CAN0_V 0x00000001U -#define TEE_READ_REE2_CAN0_S 3 -/** TEE_WRITE_TEE_CAN0 : R/W; bitpos: [4]; default: 1; +#define TEE_READ_REE2_TWAI0 (BIT(3)) +#define TEE_READ_REE2_TWAI0_M (TEE_READ_REE2_TWAI0_V << TEE_READ_REE2_TWAI0_S) +#define TEE_READ_REE2_TWAI0_V 0x00000001U +#define TEE_READ_REE2_TWAI0_S 3 +/** TEE_WRITE_TEE_TWAI0 : R/W; bitpos: [4]; default: 1; * Configures can0 registers write permission in tee mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_TEE_CAN0 (BIT(4)) -#define TEE_WRITE_TEE_CAN0_M (TEE_WRITE_TEE_CAN0_V << TEE_WRITE_TEE_CAN0_S) -#define TEE_WRITE_TEE_CAN0_V 0x00000001U -#define TEE_WRITE_TEE_CAN0_S 4 -/** TEE_WRITE_REE0_CAN0 : R/W; bitpos: [5]; default: 0; +#define TEE_WRITE_TEE_TWAI0 (BIT(4)) +#define TEE_WRITE_TEE_TWAI0_M (TEE_WRITE_TEE_TWAI0_V << TEE_WRITE_TEE_TWAI0_S) +#define TEE_WRITE_TEE_TWAI0_V 0x00000001U +#define TEE_WRITE_TEE_TWAI0_S 4 +/** TEE_WRITE_REE0_TWAI0 : R/W; bitpos: [5]; default: 0; * Configures can0 registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE0_CAN0 (BIT(5)) -#define TEE_WRITE_REE0_CAN0_M (TEE_WRITE_REE0_CAN0_V << TEE_WRITE_REE0_CAN0_S) -#define TEE_WRITE_REE0_CAN0_V 0x00000001U -#define TEE_WRITE_REE0_CAN0_S 5 -/** TEE_WRITE_REE1_CAN0 : R/W; bitpos: [6]; default: 0; +#define TEE_WRITE_REE0_TWAI0 (BIT(5)) +#define TEE_WRITE_REE0_TWAI0_M (TEE_WRITE_REE0_TWAI0_V << TEE_WRITE_REE0_TWAI0_S) +#define TEE_WRITE_REE0_TWAI0_V 0x00000001U +#define TEE_WRITE_REE0_TWAI0_S 5 +/** TEE_WRITE_REE1_TWAI0 : R/W; bitpos: [6]; default: 0; * Configures can0 registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE1_CAN0 (BIT(6)) -#define TEE_WRITE_REE1_CAN0_M (TEE_WRITE_REE1_CAN0_V << TEE_WRITE_REE1_CAN0_S) -#define TEE_WRITE_REE1_CAN0_V 0x00000001U -#define TEE_WRITE_REE1_CAN0_S 6 -/** TEE_WRITE_REE2_CAN0 : R/W; bitpos: [7]; default: 0; +#define TEE_WRITE_REE1_TWAI0 (BIT(6)) +#define TEE_WRITE_REE1_TWAI0_M (TEE_WRITE_REE1_TWAI0_V << TEE_WRITE_REE1_TWAI0_S) +#define TEE_WRITE_REE1_TWAI0_V 0x00000001U +#define TEE_WRITE_REE1_TWAI0_S 6 +/** TEE_WRITE_REE2_TWAI0 : R/W; bitpos: [7]; default: 0; * Configures can0 registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE2_CAN0 (BIT(7)) -#define TEE_WRITE_REE2_CAN0_M (TEE_WRITE_REE2_CAN0_V << TEE_WRITE_REE2_CAN0_S) -#define TEE_WRITE_REE2_CAN0_V 0x00000001U -#define TEE_WRITE_REE2_CAN0_S 7 +#define TEE_WRITE_REE2_TWAI0 (BIT(7)) +#define TEE_WRITE_REE2_TWAI0_M (TEE_WRITE_REE2_TWAI0_V << TEE_WRITE_REE2_TWAI0_S) +#define TEE_WRITE_REE2_TWAI0_V 0x00000001U +#define TEE_WRITE_REE2_TWAI0_S 7 -/** TEE_USB_DEVICE_CTRL_REG register - * usb_device read/write control register +/** TEE_USB_SERIAL_JTAG_CTRL_REG register + * USB_SERIAL_JTAG read/write control register */ -#define TEE_USB_DEVICE_CTRL_REG (DR_REG_TEE_BASE + 0xb4) -/** TEE_READ_TEE_USB_DEVICE : R/W; bitpos: [0]; default: 1; +#define TEE_USB_SERIAL_JTAG_CTRL_REG (DR_REG_TEE_BASE + 0xb4) +/** TEE_READ_TEE_USB_SERIAL_JTAG : R/W; bitpos: [0]; default: 1; * Configures usb_device registers read permission in tee mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_TEE_USB_DEVICE (BIT(0)) -#define TEE_READ_TEE_USB_DEVICE_M (TEE_READ_TEE_USB_DEVICE_V << TEE_READ_TEE_USB_DEVICE_S) -#define TEE_READ_TEE_USB_DEVICE_V 0x00000001U -#define TEE_READ_TEE_USB_DEVICE_S 0 -/** TEE_READ_REE0_USB_DEVICE : R/W; bitpos: [1]; default: 0; +#define TEE_READ_TEE_USB_SERIAL_JTAG (BIT(0)) +#define TEE_READ_TEE_USB_SERIAL_JTAG_M (TEE_READ_TEE_USB_SERIAL_JTAG_V << TEE_READ_TEE_USB_SERIAL_JTAG_S) +#define TEE_READ_TEE_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_READ_TEE_USB_SERIAL_JTAG_S 0 +/** TEE_READ_REE0_USB_SERIAL_JTAG : R/W; bitpos: [1]; default: 0; * Configures usb_device registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE0_USB_DEVICE (BIT(1)) -#define TEE_READ_REE0_USB_DEVICE_M (TEE_READ_REE0_USB_DEVICE_V << TEE_READ_REE0_USB_DEVICE_S) -#define TEE_READ_REE0_USB_DEVICE_V 0x00000001U -#define TEE_READ_REE0_USB_DEVICE_S 1 -/** TEE_READ_REE1_USB_DEVICE : R/W; bitpos: [2]; default: 0; +#define TEE_READ_REE0_USB_SERIAL_JTAG (BIT(1)) +#define TEE_READ_REE0_USB_SERIAL_JTAG_M (TEE_READ_REE0_USB_SERIAL_JTAG_V << TEE_READ_REE0_USB_SERIAL_JTAG_S) +#define TEE_READ_REE0_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_READ_REE0_USB_SERIAL_JTAG_S 1 +/** TEE_READ_REE1_USB_SERIAL_JTAG : R/W; bitpos: [2]; default: 0; * Configures usb_device registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE1_USB_DEVICE (BIT(2)) -#define TEE_READ_REE1_USB_DEVICE_M (TEE_READ_REE1_USB_DEVICE_V << TEE_READ_REE1_USB_DEVICE_S) -#define TEE_READ_REE1_USB_DEVICE_V 0x00000001U -#define TEE_READ_REE1_USB_DEVICE_S 2 -/** TEE_READ_REE2_USB_DEVICE : R/W; bitpos: [3]; default: 0; +#define TEE_READ_REE1_USB_SERIAL_JTAG (BIT(2)) +#define TEE_READ_REE1_USB_SERIAL_JTAG_M (TEE_READ_REE1_USB_SERIAL_JTAG_V << TEE_READ_REE1_USB_SERIAL_JTAG_S) +#define TEE_READ_REE1_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_READ_REE1_USB_SERIAL_JTAG_S 2 +/** TEE_READ_REE2_USB_SERIAL_JTAG : R/W; bitpos: [3]; default: 0; * Configures usb_device registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE2_USB_DEVICE (BIT(3)) -#define TEE_READ_REE2_USB_DEVICE_M (TEE_READ_REE2_USB_DEVICE_V << TEE_READ_REE2_USB_DEVICE_S) -#define TEE_READ_REE2_USB_DEVICE_V 0x00000001U -#define TEE_READ_REE2_USB_DEVICE_S 3 -/** TEE_WRITE_TEE_USB_DEVICE : R/W; bitpos: [4]; default: 1; +#define TEE_READ_REE2_USB_SERIAL_JTAG (BIT(3)) +#define TEE_READ_REE2_USB_SERIAL_JTAG_M (TEE_READ_REE2_USB_SERIAL_JTAG_V << TEE_READ_REE2_USB_SERIAL_JTAG_S) +#define TEE_READ_REE2_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_READ_REE2_USB_SERIAL_JTAG_S 3 +/** TEE_WRITE_TEE_USB_SERIAL_JTAG : R/W; bitpos: [4]; default: 1; * Configures usb_device registers write permission in tee mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_TEE_USB_DEVICE (BIT(4)) -#define TEE_WRITE_TEE_USB_DEVICE_M (TEE_WRITE_TEE_USB_DEVICE_V << TEE_WRITE_TEE_USB_DEVICE_S) -#define TEE_WRITE_TEE_USB_DEVICE_V 0x00000001U -#define TEE_WRITE_TEE_USB_DEVICE_S 4 -/** TEE_WRITE_REE0_USB_DEVICE : R/W; bitpos: [5]; default: 0; +#define TEE_WRITE_TEE_USB_SERIAL_JTAG (BIT(4)) +#define TEE_WRITE_TEE_USB_SERIAL_JTAG_M (TEE_WRITE_TEE_USB_SERIAL_JTAG_V << TEE_WRITE_TEE_USB_SERIAL_JTAG_S) +#define TEE_WRITE_TEE_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_WRITE_TEE_USB_SERIAL_JTAG_S 4 +/** TEE_WRITE_REE0_USB_SERIAL_JTAG : R/W; bitpos: [5]; default: 0; * Configures usb_device registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE0_USB_DEVICE (BIT(5)) -#define TEE_WRITE_REE0_USB_DEVICE_M (TEE_WRITE_REE0_USB_DEVICE_V << TEE_WRITE_REE0_USB_DEVICE_S) -#define TEE_WRITE_REE0_USB_DEVICE_V 0x00000001U -#define TEE_WRITE_REE0_USB_DEVICE_S 5 -/** TEE_WRITE_REE1_USB_DEVICE : R/W; bitpos: [6]; default: 0; +#define TEE_WRITE_REE0_USB_SERIAL_JTAG (BIT(5)) +#define TEE_WRITE_REE0_USB_SERIAL_JTAG_M (TEE_WRITE_REE0_USB_SERIAL_JTAG_V << TEE_WRITE_REE0_USB_SERIAL_JTAG_S) +#define TEE_WRITE_REE0_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_WRITE_REE0_USB_SERIAL_JTAG_S 5 +/** TEE_WRITE_REE1_USB_SERIAL_JTAG : R/W; bitpos: [6]; default: 0; * Configures usb_device registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE1_USB_DEVICE (BIT(6)) -#define TEE_WRITE_REE1_USB_DEVICE_M (TEE_WRITE_REE1_USB_DEVICE_V << TEE_WRITE_REE1_USB_DEVICE_S) -#define TEE_WRITE_REE1_USB_DEVICE_V 0x00000001U -#define TEE_WRITE_REE1_USB_DEVICE_S 6 -/** TEE_WRITE_REE2_USB_DEVICE : R/W; bitpos: [7]; default: 0; +#define TEE_WRITE_REE1_USB_SERIAL_JTAG (BIT(6)) +#define TEE_WRITE_REE1_USB_SERIAL_JTAG_M (TEE_WRITE_REE1_USB_SERIAL_JTAG_V << TEE_WRITE_REE1_USB_SERIAL_JTAG_S) +#define TEE_WRITE_REE1_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_WRITE_REE1_USB_SERIAL_JTAG_S 6 +/** TEE_WRITE_REE2_USB_SERIAL_JTAG : R/W; bitpos: [7]; default: 0; * Configures usb_device registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE2_USB_DEVICE (BIT(7)) -#define TEE_WRITE_REE2_USB_DEVICE_M (TEE_WRITE_REE2_USB_DEVICE_V << TEE_WRITE_REE2_USB_DEVICE_S) -#define TEE_WRITE_REE2_USB_DEVICE_V 0x00000001U -#define TEE_WRITE_REE2_USB_DEVICE_S 7 +#define TEE_WRITE_REE2_USB_SERIAL_JTAG (BIT(7)) +#define TEE_WRITE_REE2_USB_SERIAL_JTAG_M (TEE_WRITE_REE2_USB_SERIAL_JTAG_V << TEE_WRITE_REE2_USB_SERIAL_JTAG_S) +#define TEE_WRITE_REE2_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_WRITE_REE2_USB_SERIAL_JTAG_S 7 /** TEE_RMT_CTRL_REG register - * rmt read/write control register + * RMT read/write control register */ #define TEE_RMT_CTRL_REG (DR_REG_TEE_BASE + 0xb8) /** TEE_READ_TEE_RMT : R/W; bitpos: [0]; default: 1; @@ -1595,7 +1659,7 @@ extern "C" { #define TEE_WRITE_REE2_RMT_S 7 /** TEE_GDMA_CTRL_REG register - * gdma read/write control register + * GDMA read/write control register */ #define TEE_GDMA_CTRL_REG (DR_REG_TEE_BASE + 0xbc) /** TEE_READ_TEE_GDMA : R/W; bitpos: [0]; default: 1; @@ -1671,85 +1735,8 @@ extern "C" { #define TEE_WRITE_REE2_GDMA_V 0x00000001U #define TEE_WRITE_REE2_GDMA_S 7 -/** TEE_REGDMA_CTRL_REG register - * regdma read/write control register - */ -#define TEE_REGDMA_CTRL_REG (DR_REG_TEE_BASE + 0xc0) -/** TEE_READ_TEE_REGDMA : R/W; bitpos: [0]; default: 1; - * Configures regdma registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_REGDMA (BIT(0)) -#define TEE_READ_TEE_REGDMA_M (TEE_READ_TEE_REGDMA_V << TEE_READ_TEE_REGDMA_S) -#define TEE_READ_TEE_REGDMA_V 0x00000001U -#define TEE_READ_TEE_REGDMA_S 0 -/** TEE_READ_REE0_REGDMA : R/W; bitpos: [1]; default: 0; - * Configures regdma registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_REGDMA (BIT(1)) -#define TEE_READ_REE0_REGDMA_M (TEE_READ_REE0_REGDMA_V << TEE_READ_REE0_REGDMA_S) -#define TEE_READ_REE0_REGDMA_V 0x00000001U -#define TEE_READ_REE0_REGDMA_S 1 -/** TEE_READ_REE1_REGDMA : R/W; bitpos: [2]; default: 0; - * Configures regdma registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_REGDMA (BIT(2)) -#define TEE_READ_REE1_REGDMA_M (TEE_READ_REE1_REGDMA_V << TEE_READ_REE1_REGDMA_S) -#define TEE_READ_REE1_REGDMA_V 0x00000001U -#define TEE_READ_REE1_REGDMA_S 2 -/** TEE_READ_REE2_REGDMA : R/W; bitpos: [3]; default: 0; - * Configures regdma registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_REGDMA (BIT(3)) -#define TEE_READ_REE2_REGDMA_M (TEE_READ_REE2_REGDMA_V << TEE_READ_REE2_REGDMA_S) -#define TEE_READ_REE2_REGDMA_V 0x00000001U -#define TEE_READ_REE2_REGDMA_S 3 -/** TEE_WRITE_TEE_REGDMA : R/W; bitpos: [4]; default: 1; - * Configures regdma registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_REGDMA (BIT(4)) -#define TEE_WRITE_TEE_REGDMA_M (TEE_WRITE_TEE_REGDMA_V << TEE_WRITE_TEE_REGDMA_S) -#define TEE_WRITE_TEE_REGDMA_V 0x00000001U -#define TEE_WRITE_TEE_REGDMA_S 4 -/** TEE_WRITE_REE0_REGDMA : R/W; bitpos: [5]; default: 0; - * Configures regdma registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_REGDMA (BIT(5)) -#define TEE_WRITE_REE0_REGDMA_M (TEE_WRITE_REE0_REGDMA_V << TEE_WRITE_REE0_REGDMA_S) -#define TEE_WRITE_REE0_REGDMA_V 0x00000001U -#define TEE_WRITE_REE0_REGDMA_S 5 -/** TEE_WRITE_REE1_REGDMA : R/W; bitpos: [6]; default: 0; - * Configures regdma registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_REGDMA (BIT(6)) -#define TEE_WRITE_REE1_REGDMA_M (TEE_WRITE_REE1_REGDMA_V << TEE_WRITE_REE1_REGDMA_S) -#define TEE_WRITE_REE1_REGDMA_V 0x00000001U -#define TEE_WRITE_REE1_REGDMA_S 6 -/** TEE_WRITE_REE2_REGDMA : R/W; bitpos: [7]; default: 0; - * Configures regdma registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_REGDMA (BIT(7)) -#define TEE_WRITE_REE2_REGDMA_M (TEE_WRITE_REE2_REGDMA_V << TEE_WRITE_REE2_REGDMA_S) -#define TEE_WRITE_REE2_REGDMA_V 0x00000001U -#define TEE_WRITE_REE2_REGDMA_S 7 - /** TEE_ETM_CTRL_REG register - * etm read/write control register + * SOC_ETM read/write control register */ #define TEE_ETM_CTRL_REG (DR_REG_TEE_BASE + 0xc4) /** TEE_READ_TEE_ETM : R/W; bitpos: [0]; default: 1; @@ -1826,7 +1813,7 @@ extern "C" { #define TEE_WRITE_REE2_ETM_S 7 /** TEE_INTMTX_CTRL_REG register - * intmtx read/write control register + * INTMTX read/write control register */ #define TEE_INTMTX_CTRL_REG (DR_REG_TEE_BASE + 0xc8) /** TEE_READ_TEE_INTMTX_CORE : R/W; bitpos: [0]; default: 1; @@ -1903,7 +1890,7 @@ extern "C" { #define TEE_WRITE_REE2_INTMTX_CORE_S 7 /** TEE_APB_ADC_CTRL_REG register - * apb_adc read/write control register + * SAR ADC read/write control register */ #define TEE_APB_ADC_CTRL_REG (DR_REG_TEE_BASE + 0xd0) /** TEE_READ_TEE_APB_ADC : R/W; bitpos: [0]; default: 1; @@ -1980,7 +1967,7 @@ extern "C" { #define TEE_WRITE_REE2_APB_ADC_S 7 /** TEE_TIMERGROUP0_CTRL_REG register - * timergroup0 read/write control register + * TIMG0 read/write control register */ #define TEE_TIMERGROUP0_CTRL_REG (DR_REG_TEE_BASE + 0xd4) /** TEE_READ_TEE_TIMERGROUP0 : R/W; bitpos: [0]; default: 1; @@ -2057,7 +2044,7 @@ extern "C" { #define TEE_WRITE_REE2_TIMERGROUP0_S 7 /** TEE_TIMERGROUP1_CTRL_REG register - * timergroup1 read/write control register + * TIMG1 read/write control register */ #define TEE_TIMERGROUP1_CTRL_REG (DR_REG_TEE_BASE + 0xd8) /** TEE_READ_TEE_TIMERGROUP1 : R/W; bitpos: [0]; default: 1; @@ -2134,7 +2121,7 @@ extern "C" { #define TEE_WRITE_REE2_TIMERGROUP1_S 7 /** TEE_SYSTIMER_CTRL_REG register - * systimer read/write control register + * SYSTIMER read/write control register */ #define TEE_SYSTIMER_CTRL_REG (DR_REG_TEE_BASE + 0xdc) /** TEE_READ_TEE_SYSTIMER : R/W; bitpos: [0]; default: 1; @@ -2210,162 +2197,8 @@ extern "C" { #define TEE_WRITE_REE2_SYSTIMER_V 0x00000001U #define TEE_WRITE_REE2_SYSTIMER_S 7 -/** TEE_MISC_CTRL_REG register - * misc read/write control register - */ -#define TEE_MISC_CTRL_REG (DR_REG_TEE_BASE + 0xe0) -/** TEE_READ_TEE_MISC : R/W; bitpos: [0]; default: 1; - * Configures misc registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_MISC (BIT(0)) -#define TEE_READ_TEE_MISC_M (TEE_READ_TEE_MISC_V << TEE_READ_TEE_MISC_S) -#define TEE_READ_TEE_MISC_V 0x00000001U -#define TEE_READ_TEE_MISC_S 0 -/** TEE_READ_REE0_MISC : R/W; bitpos: [1]; default: 0; - * Configures misc registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_MISC (BIT(1)) -#define TEE_READ_REE0_MISC_M (TEE_READ_REE0_MISC_V << TEE_READ_REE0_MISC_S) -#define TEE_READ_REE0_MISC_V 0x00000001U -#define TEE_READ_REE0_MISC_S 1 -/** TEE_READ_REE1_MISC : R/W; bitpos: [2]; default: 0; - * Configures misc registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_MISC (BIT(2)) -#define TEE_READ_REE1_MISC_M (TEE_READ_REE1_MISC_V << TEE_READ_REE1_MISC_S) -#define TEE_READ_REE1_MISC_V 0x00000001U -#define TEE_READ_REE1_MISC_S 2 -/** TEE_READ_REE2_MISC : R/W; bitpos: [3]; default: 0; - * Configures misc registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_MISC (BIT(3)) -#define TEE_READ_REE2_MISC_M (TEE_READ_REE2_MISC_V << TEE_READ_REE2_MISC_S) -#define TEE_READ_REE2_MISC_V 0x00000001U -#define TEE_READ_REE2_MISC_S 3 -/** TEE_WRITE_TEE_MISC : R/W; bitpos: [4]; default: 1; - * Configures misc registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_MISC (BIT(4)) -#define TEE_WRITE_TEE_MISC_M (TEE_WRITE_TEE_MISC_V << TEE_WRITE_TEE_MISC_S) -#define TEE_WRITE_TEE_MISC_V 0x00000001U -#define TEE_WRITE_TEE_MISC_S 4 -/** TEE_WRITE_REE0_MISC : R/W; bitpos: [5]; default: 0; - * Configures misc registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_MISC (BIT(5)) -#define TEE_WRITE_REE0_MISC_M (TEE_WRITE_REE0_MISC_V << TEE_WRITE_REE0_MISC_S) -#define TEE_WRITE_REE0_MISC_V 0x00000001U -#define TEE_WRITE_REE0_MISC_S 5 -/** TEE_WRITE_REE1_MISC : R/W; bitpos: [6]; default: 0; - * Configures misc registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_MISC (BIT(6)) -#define TEE_WRITE_REE1_MISC_M (TEE_WRITE_REE1_MISC_V << TEE_WRITE_REE1_MISC_S) -#define TEE_WRITE_REE1_MISC_V 0x00000001U -#define TEE_WRITE_REE1_MISC_S 6 -/** TEE_WRITE_REE2_MISC : R/W; bitpos: [7]; default: 0; - * Configures misc registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_MISC (BIT(7)) -#define TEE_WRITE_REE2_MISC_M (TEE_WRITE_REE2_MISC_V << TEE_WRITE_REE2_MISC_S) -#define TEE_WRITE_REE2_MISC_V 0x00000001U -#define TEE_WRITE_REE2_MISC_S 7 - -/** TEE_PVT_MONITOR_CTRL_REG register - * pvt_monitor read/write control register - */ -#define TEE_PVT_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0xf0) -/** TEE_READ_TEE_PVT_MONITOR : R/W; bitpos: [0]; default: 1; - * Configures pvt_monitor registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_PVT_MONITOR (BIT(0)) -#define TEE_READ_TEE_PVT_MONITOR_M (TEE_READ_TEE_PVT_MONITOR_V << TEE_READ_TEE_PVT_MONITOR_S) -#define TEE_READ_TEE_PVT_MONITOR_V 0x00000001U -#define TEE_READ_TEE_PVT_MONITOR_S 0 -/** TEE_READ_REE0_PVT_MONITOR : R/W; bitpos: [1]; default: 0; - * Configures pvt_monitor registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_PVT_MONITOR (BIT(1)) -#define TEE_READ_REE0_PVT_MONITOR_M (TEE_READ_REE0_PVT_MONITOR_V << TEE_READ_REE0_PVT_MONITOR_S) -#define TEE_READ_REE0_PVT_MONITOR_V 0x00000001U -#define TEE_READ_REE0_PVT_MONITOR_S 1 -/** TEE_READ_REE1_PVT_MONITOR : R/W; bitpos: [2]; default: 0; - * Configures pvt_monitor registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_PVT_MONITOR (BIT(2)) -#define TEE_READ_REE1_PVT_MONITOR_M (TEE_READ_REE1_PVT_MONITOR_V << TEE_READ_REE1_PVT_MONITOR_S) -#define TEE_READ_REE1_PVT_MONITOR_V 0x00000001U -#define TEE_READ_REE1_PVT_MONITOR_S 2 -/** TEE_READ_REE2_PVT_MONITOR : R/W; bitpos: [3]; default: 0; - * Configures pvt_monitor registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_PVT_MONITOR (BIT(3)) -#define TEE_READ_REE2_PVT_MONITOR_M (TEE_READ_REE2_PVT_MONITOR_V << TEE_READ_REE2_PVT_MONITOR_S) -#define TEE_READ_REE2_PVT_MONITOR_V 0x00000001U -#define TEE_READ_REE2_PVT_MONITOR_S 3 -/** TEE_WRITE_TEE_PVT_MONITOR : R/W; bitpos: [4]; default: 1; - * Configures pvt_monitor registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_PVT_MONITOR (BIT(4)) -#define TEE_WRITE_TEE_PVT_MONITOR_M (TEE_WRITE_TEE_PVT_MONITOR_V << TEE_WRITE_TEE_PVT_MONITOR_S) -#define TEE_WRITE_TEE_PVT_MONITOR_V 0x00000001U -#define TEE_WRITE_TEE_PVT_MONITOR_S 4 -/** TEE_WRITE_REE0_PVT_MONITOR : R/W; bitpos: [5]; default: 0; - * Configures pvt_monitor registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_PVT_MONITOR (BIT(5)) -#define TEE_WRITE_REE0_PVT_MONITOR_M (TEE_WRITE_REE0_PVT_MONITOR_V << TEE_WRITE_REE0_PVT_MONITOR_S) -#define TEE_WRITE_REE0_PVT_MONITOR_V 0x00000001U -#define TEE_WRITE_REE0_PVT_MONITOR_S 5 -/** TEE_WRITE_REE1_PVT_MONITOR : R/W; bitpos: [6]; default: 0; - * Configures pvt_monitor registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_PVT_MONITOR (BIT(6)) -#define TEE_WRITE_REE1_PVT_MONITOR_M (TEE_WRITE_REE1_PVT_MONITOR_V << TEE_WRITE_REE1_PVT_MONITOR_S) -#define TEE_WRITE_REE1_PVT_MONITOR_V 0x00000001U -#define TEE_WRITE_REE1_PVT_MONITOR_S 6 -/** TEE_WRITE_REE2_PVT_MONITOR : R/W; bitpos: [7]; default: 0; - * Configures pvt_monitor registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_PVT_MONITOR (BIT(7)) -#define TEE_WRITE_REE2_PVT_MONITOR_M (TEE_WRITE_REE2_PVT_MONITOR_V << TEE_WRITE_REE2_PVT_MONITOR_S) -#define TEE_WRITE_REE2_PVT_MONITOR_V 0x00000001U -#define TEE_WRITE_REE2_PVT_MONITOR_S 7 - /** TEE_PCNT_CTRL_REG register - * pcnt read/write control register + * PCNT read/write control register */ #define TEE_PCNT_CTRL_REG (DR_REG_TEE_BASE + 0xf4) /** TEE_READ_TEE_PCNT : R/W; bitpos: [0]; default: 1; @@ -2442,7 +2275,7 @@ extern "C" { #define TEE_WRITE_REE2_PCNT_S 7 /** TEE_IOMUX_CTRL_REG register - * iomux read/write control register + * IO MUX read/write control register */ #define TEE_IOMUX_CTRL_REG (DR_REG_TEE_BASE + 0xf8) /** TEE_READ_TEE_IOMUX : R/W; bitpos: [0]; default: 1; @@ -2519,7 +2352,7 @@ extern "C" { #define TEE_WRITE_REE2_IOMUX_S 7 /** TEE_PSRAM_MEM_MONITOR_CTRL_REG register - * psram_mem_monitor read/write control register + * PSRAM_MEM_MONITOR read/write control register */ #define TEE_PSRAM_MEM_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0xfc) /** TEE_READ_TEE_PSRAM_MEM_MONITOR : R/W; bitpos: [0]; default: 1; @@ -2596,7 +2429,7 @@ extern "C" { #define TEE_WRITE_REE2_PSRAM_MEM_MONITOR_S 7 /** TEE_MEM_ACS_MONITOR_CTRL_REG register - * mem_acs_monitor read/write control register + * TCM_MEM_MONITOR read/write control register */ #define TEE_MEM_ACS_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0x100) /** TEE_READ_TEE_MEM_ACS_MONITOR : R/W; bitpos: [0]; default: 1; @@ -2673,7 +2506,7 @@ extern "C" { #define TEE_WRITE_REE2_MEM_ACS_MONITOR_S 7 /** TEE_HP_SYSTEM_REG_CTRL_REG register - * hp_system_reg read/write control register + * HP_SYSREG read/write control register */ #define TEE_HP_SYSTEM_REG_CTRL_REG (DR_REG_TEE_BASE + 0x104) /** TEE_READ_TEE_HP_SYSTEM_REG : R/W; bitpos: [0]; default: 1; @@ -2750,7 +2583,7 @@ extern "C" { #define TEE_WRITE_REE2_HP_SYSTEM_REG_S 7 /** TEE_PCR_REG_CTRL_REG register - * pcr_reg read/write control register + * PCR read/write control register */ #define TEE_PCR_REG_CTRL_REG (DR_REG_TEE_BASE + 0x108) /** TEE_READ_TEE_PCR_REG : R/W; bitpos: [0]; default: 1; @@ -2827,7 +2660,7 @@ extern "C" { #define TEE_WRITE_REE2_PCR_REG_S 7 /** TEE_MSPI_CTRL_REG register - * mspi read/write control register + * SPI01 read/write control register */ #define TEE_MSPI_CTRL_REG (DR_REG_TEE_BASE + 0x10c) /** TEE_READ_TEE_MSPI : R/W; bitpos: [0]; default: 1; @@ -2904,7 +2737,7 @@ extern "C" { #define TEE_WRITE_REE2_MSPI_S 7 /** TEE_HP_APM_CTRL_REG register - * hp_apm read/write control register + * HP_APM and LP_APM0 read/write control register */ #define TEE_HP_APM_CTRL_REG (DR_REG_TEE_BASE + 0x110) /** TEE_READ_TEE_HP_APM : R/W; bitpos: [0]; default: 1; @@ -2981,7 +2814,7 @@ extern "C" { #define TEE_WRITE_REE2_HP_APM_S 7 /** TEE_CPU_APM_CTRL_REG register - * cpu_apm read/write control register + * CPU_APM_REG read/write control register */ #define TEE_CPU_APM_CTRL_REG (DR_REG_TEE_BASE + 0x114) /** TEE_READ_TEE_CPU_APM : R/W; bitpos: [0]; default: 1; @@ -3058,7 +2891,7 @@ extern "C" { #define TEE_WRITE_REE2_CPU_APM_S 7 /** TEE_TEE_CTRL_REG register - * tee read/write control register + * TEE read/write control register */ #define TEE_TEE_CTRL_REG (DR_REG_TEE_BASE + 0x118) /** TEE_READ_TEE_TEE : R/W; bitpos: [0]; default: 1; @@ -3135,7 +2968,8 @@ extern "C" { #define TEE_WRITE_REE2_TEE_S 7 /** TEE_CRYPT_CTRL_REG register - * crypt read/write control register + * CRYPT read/write control register, including security peripherals from AES to ECDSA + * address range */ #define TEE_CRYPT_CTRL_REG (DR_REG_TEE_BASE + 0x11c) /** TEE_READ_TEE_CRYPT : R/W; bitpos: [0]; default: 1; @@ -3212,7 +3046,7 @@ extern "C" { #define TEE_WRITE_REE2_CRYPT_S 7 /** TEE_TRACE_CTRL_REG register - * trace read/write control register + * TRACE read/write control register */ #define TEE_TRACE_CTRL_REG (DR_REG_TEE_BASE + 0x120) /** TEE_READ_TEE_TRACE : R/W; bitpos: [0]; default: 1; @@ -3289,7 +3123,7 @@ extern "C" { #define TEE_WRITE_REE2_TRACE_S 7 /** TEE_CPU_BUS_MONITOR_CTRL_REG register - * cpu_bus_monitor read/write control register + * BUS_MONITOR read/write control register */ #define TEE_CPU_BUS_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0x128) /** TEE_READ_TEE_CPU_BUS_MONITOR : R/W; bitpos: [0]; default: 1; @@ -3366,7 +3200,7 @@ extern "C" { #define TEE_WRITE_REE2_CPU_BUS_MONITOR_S 7 /** TEE_INTPRI_REG_CTRL_REG register - * intpri_reg read/write control register + * INTPRI_REG read/write control register */ #define TEE_INTPRI_REG_CTRL_REG (DR_REG_TEE_BASE + 0x12c) /** TEE_READ_TEE_INTPRI_REG : R/W; bitpos: [0]; default: 1; @@ -3442,239 +3276,85 @@ extern "C" { #define TEE_WRITE_REE2_INTPRI_REG_V 0x00000001U #define TEE_WRITE_REE2_INTPRI_REG_S 7 -/** TEE_CACHE_CFG_CTRL_REG register - * cache_cfg read/write control register +/** TEE_TWAI1_CTRL_REG register + * TWAI1 read/write control register */ -#define TEE_CACHE_CFG_CTRL_REG (DR_REG_TEE_BASE + 0x130) -/** TEE_READ_TEE_CACHE_CFG : R/W; bitpos: [0]; default: 1; - * Configures cache_cfg registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_CACHE_CFG (BIT(0)) -#define TEE_READ_TEE_CACHE_CFG_M (TEE_READ_TEE_CACHE_CFG_V << TEE_READ_TEE_CACHE_CFG_S) -#define TEE_READ_TEE_CACHE_CFG_V 0x00000001U -#define TEE_READ_TEE_CACHE_CFG_S 0 -/** TEE_READ_REE0_CACHE_CFG : R/W; bitpos: [1]; default: 0; - * Configures cache_cfg registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_CACHE_CFG (BIT(1)) -#define TEE_READ_REE0_CACHE_CFG_M (TEE_READ_REE0_CACHE_CFG_V << TEE_READ_REE0_CACHE_CFG_S) -#define TEE_READ_REE0_CACHE_CFG_V 0x00000001U -#define TEE_READ_REE0_CACHE_CFG_S 1 -/** TEE_READ_REE1_CACHE_CFG : R/W; bitpos: [2]; default: 0; - * Configures cache_cfg registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_CACHE_CFG (BIT(2)) -#define TEE_READ_REE1_CACHE_CFG_M (TEE_READ_REE1_CACHE_CFG_V << TEE_READ_REE1_CACHE_CFG_S) -#define TEE_READ_REE1_CACHE_CFG_V 0x00000001U -#define TEE_READ_REE1_CACHE_CFG_S 2 -/** TEE_READ_REE2_CACHE_CFG : R/W; bitpos: [3]; default: 0; - * Configures cache_cfg registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_CACHE_CFG (BIT(3)) -#define TEE_READ_REE2_CACHE_CFG_M (TEE_READ_REE2_CACHE_CFG_V << TEE_READ_REE2_CACHE_CFG_S) -#define TEE_READ_REE2_CACHE_CFG_V 0x00000001U -#define TEE_READ_REE2_CACHE_CFG_S 3 -/** TEE_WRITE_TEE_CACHE_CFG : R/W; bitpos: [4]; default: 1; - * Configures cache_cfg registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_CACHE_CFG (BIT(4)) -#define TEE_WRITE_TEE_CACHE_CFG_M (TEE_WRITE_TEE_CACHE_CFG_V << TEE_WRITE_TEE_CACHE_CFG_S) -#define TEE_WRITE_TEE_CACHE_CFG_V 0x00000001U -#define TEE_WRITE_TEE_CACHE_CFG_S 4 -/** TEE_WRITE_REE0_CACHE_CFG : R/W; bitpos: [5]; default: 0; - * Configures cache_cfg registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_CACHE_CFG (BIT(5)) -#define TEE_WRITE_REE0_CACHE_CFG_M (TEE_WRITE_REE0_CACHE_CFG_V << TEE_WRITE_REE0_CACHE_CFG_S) -#define TEE_WRITE_REE0_CACHE_CFG_V 0x00000001U -#define TEE_WRITE_REE0_CACHE_CFG_S 5 -/** TEE_WRITE_REE1_CACHE_CFG : R/W; bitpos: [6]; default: 0; - * Configures cache_cfg registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_CACHE_CFG (BIT(6)) -#define TEE_WRITE_REE1_CACHE_CFG_M (TEE_WRITE_REE1_CACHE_CFG_V << TEE_WRITE_REE1_CACHE_CFG_S) -#define TEE_WRITE_REE1_CACHE_CFG_V 0x00000001U -#define TEE_WRITE_REE1_CACHE_CFG_S 6 -/** TEE_WRITE_REE2_CACHE_CFG : R/W; bitpos: [7]; default: 0; - * Configures cache_cfg registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_CACHE_CFG (BIT(7)) -#define TEE_WRITE_REE2_CACHE_CFG_M (TEE_WRITE_REE2_CACHE_CFG_V << TEE_WRITE_REE2_CACHE_CFG_S) -#define TEE_WRITE_REE2_CACHE_CFG_V 0x00000001U -#define TEE_WRITE_REE2_CACHE_CFG_S 7 - -/** TEE_MODEM_CTRL_REG register - * modem read/write control register - */ -#define TEE_MODEM_CTRL_REG (DR_REG_TEE_BASE + 0x134) -/** TEE_READ_TEE_MODEM : R/W; bitpos: [0]; default: 1; - * Configures modem registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_MODEM (BIT(0)) -#define TEE_READ_TEE_MODEM_M (TEE_READ_TEE_MODEM_V << TEE_READ_TEE_MODEM_S) -#define TEE_READ_TEE_MODEM_V 0x00000001U -#define TEE_READ_TEE_MODEM_S 0 -/** TEE_READ_REE0_MODEM : R/W; bitpos: [1]; default: 0; - * Configures modem registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_MODEM (BIT(1)) -#define TEE_READ_REE0_MODEM_M (TEE_READ_REE0_MODEM_V << TEE_READ_REE0_MODEM_S) -#define TEE_READ_REE0_MODEM_V 0x00000001U -#define TEE_READ_REE0_MODEM_S 1 -/** TEE_READ_REE1_MODEM : R/W; bitpos: [2]; default: 0; - * Configures modem registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_MODEM (BIT(2)) -#define TEE_READ_REE1_MODEM_M (TEE_READ_REE1_MODEM_V << TEE_READ_REE1_MODEM_S) -#define TEE_READ_REE1_MODEM_V 0x00000001U -#define TEE_READ_REE1_MODEM_S 2 -/** TEE_READ_REE2_MODEM : R/W; bitpos: [3]; default: 0; - * Configures modem registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_MODEM (BIT(3)) -#define TEE_READ_REE2_MODEM_M (TEE_READ_REE2_MODEM_V << TEE_READ_REE2_MODEM_S) -#define TEE_READ_REE2_MODEM_V 0x00000001U -#define TEE_READ_REE2_MODEM_S 3 -/** TEE_WRITE_TEE_MODEM : R/W; bitpos: [4]; default: 1; - * Configures modem registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_MODEM (BIT(4)) -#define TEE_WRITE_TEE_MODEM_M (TEE_WRITE_TEE_MODEM_V << TEE_WRITE_TEE_MODEM_S) -#define TEE_WRITE_TEE_MODEM_V 0x00000001U -#define TEE_WRITE_TEE_MODEM_S 4 -/** TEE_WRITE_REE0_MODEM : R/W; bitpos: [5]; default: 0; - * Configures modem registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_MODEM (BIT(5)) -#define TEE_WRITE_REE0_MODEM_M (TEE_WRITE_REE0_MODEM_V << TEE_WRITE_REE0_MODEM_S) -#define TEE_WRITE_REE0_MODEM_V 0x00000001U -#define TEE_WRITE_REE0_MODEM_S 5 -/** TEE_WRITE_REE1_MODEM : R/W; bitpos: [6]; default: 0; - * Configures modem registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_MODEM (BIT(6)) -#define TEE_WRITE_REE1_MODEM_M (TEE_WRITE_REE1_MODEM_V << TEE_WRITE_REE1_MODEM_S) -#define TEE_WRITE_REE1_MODEM_V 0x00000001U -#define TEE_WRITE_REE1_MODEM_S 6 -/** TEE_WRITE_REE2_MODEM : R/W; bitpos: [7]; default: 0; - * Configures modem registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_MODEM (BIT(7)) -#define TEE_WRITE_REE2_MODEM_M (TEE_WRITE_REE2_MODEM_V << TEE_WRITE_REE2_MODEM_S) -#define TEE_WRITE_REE2_MODEM_V 0x00000001U -#define TEE_WRITE_REE2_MODEM_S 7 - -/** TEE_CAN1_CTRL_REG register - * can1 read/write control register - */ -#define TEE_CAN1_CTRL_REG (DR_REG_TEE_BASE + 0x138) -/** TEE_READ_TEE_CAN1 : R/W; bitpos: [0]; default: 1; +#define TEE_TWAI1_CTRL_REG (DR_REG_TEE_BASE + 0x138) +/** TEE_READ_TEE_TWAI1 : R/W; bitpos: [0]; default: 1; * Configures can1 registers read permission in tee mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_TEE_CAN1 (BIT(0)) -#define TEE_READ_TEE_CAN1_M (TEE_READ_TEE_CAN1_V << TEE_READ_TEE_CAN1_S) -#define TEE_READ_TEE_CAN1_V 0x00000001U -#define TEE_READ_TEE_CAN1_S 0 -/** TEE_READ_REE0_CAN1 : R/W; bitpos: [1]; default: 0; +#define TEE_READ_TEE_TWAI1 (BIT(0)) +#define TEE_READ_TEE_TWAI1_M (TEE_READ_TEE_TWAI1_V << TEE_READ_TEE_TWAI1_S) +#define TEE_READ_TEE_TWAI1_V 0x00000001U +#define TEE_READ_TEE_TWAI1_S 0 +/** TEE_READ_REE0_TWAI1 : R/W; bitpos: [1]; default: 0; * Configures can1 registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE0_CAN1 (BIT(1)) -#define TEE_READ_REE0_CAN1_M (TEE_READ_REE0_CAN1_V << TEE_READ_REE0_CAN1_S) -#define TEE_READ_REE0_CAN1_V 0x00000001U -#define TEE_READ_REE0_CAN1_S 1 -/** TEE_READ_REE1_CAN1 : R/W; bitpos: [2]; default: 0; +#define TEE_READ_REE0_TWAI1 (BIT(1)) +#define TEE_READ_REE0_TWAI1_M (TEE_READ_REE0_TWAI1_V << TEE_READ_REE0_TWAI1_S) +#define TEE_READ_REE0_TWAI1_V 0x00000001U +#define TEE_READ_REE0_TWAI1_S 1 +/** TEE_READ_REE1_TWAI1 : R/W; bitpos: [2]; default: 0; * Configures can1 registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE1_CAN1 (BIT(2)) -#define TEE_READ_REE1_CAN1_M (TEE_READ_REE1_CAN1_V << TEE_READ_REE1_CAN1_S) -#define TEE_READ_REE1_CAN1_V 0x00000001U -#define TEE_READ_REE1_CAN1_S 2 -/** TEE_READ_REE2_CAN1 : R/W; bitpos: [3]; default: 0; +#define TEE_READ_REE1_TWAI1 (BIT(2)) +#define TEE_READ_REE1_TWAI1_M (TEE_READ_REE1_TWAI1_V << TEE_READ_REE1_TWAI1_S) +#define TEE_READ_REE1_TWAI1_V 0x00000001U +#define TEE_READ_REE1_TWAI1_S 2 +/** TEE_READ_REE2_TWAI1 : R/W; bitpos: [3]; default: 0; * Configures can1 registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE2_CAN1 (BIT(3)) -#define TEE_READ_REE2_CAN1_M (TEE_READ_REE2_CAN1_V << TEE_READ_REE2_CAN1_S) -#define TEE_READ_REE2_CAN1_V 0x00000001U -#define TEE_READ_REE2_CAN1_S 3 -/** TEE_WRITE_TEE_CAN1 : R/W; bitpos: [4]; default: 1; +#define TEE_READ_REE2_TWAI1 (BIT(3)) +#define TEE_READ_REE2_TWAI1_M (TEE_READ_REE2_TWAI1_V << TEE_READ_REE2_TWAI1_S) +#define TEE_READ_REE2_TWAI1_V 0x00000001U +#define TEE_READ_REE2_TWAI1_S 3 +/** TEE_WRITE_TEE_TWAI1 : R/W; bitpos: [4]; default: 1; * Configures can1 registers write permission in tee mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_TEE_CAN1 (BIT(4)) -#define TEE_WRITE_TEE_CAN1_M (TEE_WRITE_TEE_CAN1_V << TEE_WRITE_TEE_CAN1_S) -#define TEE_WRITE_TEE_CAN1_V 0x00000001U -#define TEE_WRITE_TEE_CAN1_S 4 -/** TEE_WRITE_REE0_CAN1 : R/W; bitpos: [5]; default: 0; +#define TEE_WRITE_TEE_TWAI1 (BIT(4)) +#define TEE_WRITE_TEE_TWAI1_M (TEE_WRITE_TEE_TWAI1_V << TEE_WRITE_TEE_TWAI1_S) +#define TEE_WRITE_TEE_TWAI1_V 0x00000001U +#define TEE_WRITE_TEE_TWAI1_S 4 +/** TEE_WRITE_REE0_TWAI1 : R/W; bitpos: [5]; default: 0; * Configures can1 registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE0_CAN1 (BIT(5)) -#define TEE_WRITE_REE0_CAN1_M (TEE_WRITE_REE0_CAN1_V << TEE_WRITE_REE0_CAN1_S) -#define TEE_WRITE_REE0_CAN1_V 0x00000001U -#define TEE_WRITE_REE0_CAN1_S 5 -/** TEE_WRITE_REE1_CAN1 : R/W; bitpos: [6]; default: 0; +#define TEE_WRITE_REE0_TWAI1 (BIT(5)) +#define TEE_WRITE_REE0_TWAI1_M (TEE_WRITE_REE0_TWAI1_V << TEE_WRITE_REE0_TWAI1_S) +#define TEE_WRITE_REE0_TWAI1_V 0x00000001U +#define TEE_WRITE_REE0_TWAI1_S 5 +/** TEE_WRITE_REE1_TWAI1 : R/W; bitpos: [6]; default: 0; * Configures can1 registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE1_CAN1 (BIT(6)) -#define TEE_WRITE_REE1_CAN1_M (TEE_WRITE_REE1_CAN1_V << TEE_WRITE_REE1_CAN1_S) -#define TEE_WRITE_REE1_CAN1_V 0x00000001U -#define TEE_WRITE_REE1_CAN1_S 6 -/** TEE_WRITE_REE2_CAN1 : R/W; bitpos: [7]; default: 0; +#define TEE_WRITE_REE1_TWAI1 (BIT(6)) +#define TEE_WRITE_REE1_TWAI1_M (TEE_WRITE_REE1_TWAI1_V << TEE_WRITE_REE1_TWAI1_S) +#define TEE_WRITE_REE1_TWAI1_V 0x00000001U +#define TEE_WRITE_REE1_TWAI1_S 6 +/** TEE_WRITE_REE2_TWAI1 : R/W; bitpos: [7]; default: 0; * Configures can1 registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE2_CAN1 (BIT(7)) -#define TEE_WRITE_REE2_CAN1_M (TEE_WRITE_REE2_CAN1_V << TEE_WRITE_REE2_CAN1_S) -#define TEE_WRITE_REE2_CAN1_V 0x00000001U -#define TEE_WRITE_REE2_CAN1_S 7 +#define TEE_WRITE_REE2_TWAI1 (BIT(7)) +#define TEE_WRITE_REE2_TWAI1_M (TEE_WRITE_REE2_TWAI1_V << TEE_WRITE_REE2_TWAI1_S) +#define TEE_WRITE_REE2_TWAI1_V 0x00000001U +#define TEE_WRITE_REE2_TWAI1_S 7 /** TEE_SPI2_CTRL_REG register - * spi2 read/write control register + * SPI2 read/write control register */ #define TEE_SPI2_CTRL_REG (DR_REG_TEE_BASE + 0x13c) /** TEE_READ_TEE_SPI2 : R/W; bitpos: [0]; default: 1; @@ -3751,7 +3431,7 @@ extern "C" { #define TEE_WRITE_REE2_SPI2_S 7 /** TEE_BS_CTRL_REG register - * bs read/write control register + * BITSCRAMBLER read/write control register */ #define TEE_BS_CTRL_REG (DR_REG_TEE_BASE + 0x140) /** TEE_READ_TEE_BS : R/W; bitpos: [0]; default: 1; @@ -3827,399 +3507,14 @@ extern "C" { #define TEE_WRITE_REE2_BS_V 0x00000001U #define TEE_WRITE_REE2_BS_S 7 -/** TEE_KM_CTRL_REG register - * km read/write control register - */ -#define TEE_KM_CTRL_REG (DR_REG_TEE_BASE + 0x144) -/** TEE_READ_TEE_KM : R/W; bitpos: [0]; default: 1; - * Configures km registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_KM (BIT(0)) -#define TEE_READ_TEE_KM_M (TEE_READ_TEE_KM_V << TEE_READ_TEE_KM_S) -#define TEE_READ_TEE_KM_V 0x00000001U -#define TEE_READ_TEE_KM_S 0 -/** TEE_READ_REE0_KM : R/W; bitpos: [1]; default: 0; - * Configures km registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_KM (BIT(1)) -#define TEE_READ_REE0_KM_M (TEE_READ_REE0_KM_V << TEE_READ_REE0_KM_S) -#define TEE_READ_REE0_KM_V 0x00000001U -#define TEE_READ_REE0_KM_S 1 -/** TEE_READ_REE1_KM : R/W; bitpos: [2]; default: 0; - * Configures km registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_KM (BIT(2)) -#define TEE_READ_REE1_KM_M (TEE_READ_REE1_KM_V << TEE_READ_REE1_KM_S) -#define TEE_READ_REE1_KM_V 0x00000001U -#define TEE_READ_REE1_KM_S 2 -/** TEE_READ_REE2_KM : R/W; bitpos: [3]; default: 0; - * Configures km registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_KM (BIT(3)) -#define TEE_READ_REE2_KM_M (TEE_READ_REE2_KM_V << TEE_READ_REE2_KM_S) -#define TEE_READ_REE2_KM_V 0x00000001U -#define TEE_READ_REE2_KM_S 3 -/** TEE_WRITE_TEE_KM : R/W; bitpos: [4]; default: 1; - * Configures km registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_KM (BIT(4)) -#define TEE_WRITE_TEE_KM_M (TEE_WRITE_TEE_KM_V << TEE_WRITE_TEE_KM_S) -#define TEE_WRITE_TEE_KM_V 0x00000001U -#define TEE_WRITE_TEE_KM_S 4 -/** TEE_WRITE_REE0_KM : R/W; bitpos: [5]; default: 0; - * Configures km registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_KM (BIT(5)) -#define TEE_WRITE_REE0_KM_M (TEE_WRITE_REE0_KM_V << TEE_WRITE_REE0_KM_S) -#define TEE_WRITE_REE0_KM_V 0x00000001U -#define TEE_WRITE_REE0_KM_S 5 -/** TEE_WRITE_REE1_KM : R/W; bitpos: [6]; default: 0; - * Configures km registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_KM (BIT(6)) -#define TEE_WRITE_REE1_KM_M (TEE_WRITE_REE1_KM_V << TEE_WRITE_REE1_KM_S) -#define TEE_WRITE_REE1_KM_V 0x00000001U -#define TEE_WRITE_REE1_KM_S 6 -/** TEE_WRITE_REE2_KM : R/W; bitpos: [7]; default: 0; - * Configures km registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_KM (BIT(7)) -#define TEE_WRITE_REE2_KM_M (TEE_WRITE_REE2_KM_V << TEE_WRITE_REE2_KM_S) -#define TEE_WRITE_REE2_KM_V 0x00000001U -#define TEE_WRITE_REE2_KM_S 7 - -/** TEE_MODEM_PWR_CTRL_REG register - * modem_pwr read/write control register - */ -#define TEE_MODEM_PWR_CTRL_REG (DR_REG_TEE_BASE + 0x148) -/** TEE_READ_TEE_MODEM_PWR : R/W; bitpos: [0]; default: 1; - * Configures modem_pwr registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_MODEM_PWR (BIT(0)) -#define TEE_READ_TEE_MODEM_PWR_M (TEE_READ_TEE_MODEM_PWR_V << TEE_READ_TEE_MODEM_PWR_S) -#define TEE_READ_TEE_MODEM_PWR_V 0x00000001U -#define TEE_READ_TEE_MODEM_PWR_S 0 -/** TEE_READ_REE0_MODEM_PWR : R/W; bitpos: [1]; default: 0; - * Configures modem_pwr registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_MODEM_PWR (BIT(1)) -#define TEE_READ_REE0_MODEM_PWR_M (TEE_READ_REE0_MODEM_PWR_V << TEE_READ_REE0_MODEM_PWR_S) -#define TEE_READ_REE0_MODEM_PWR_V 0x00000001U -#define TEE_READ_REE0_MODEM_PWR_S 1 -/** TEE_READ_REE1_MODEM_PWR : R/W; bitpos: [2]; default: 0; - * Configures modem_pwr registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_MODEM_PWR (BIT(2)) -#define TEE_READ_REE1_MODEM_PWR_M (TEE_READ_REE1_MODEM_PWR_V << TEE_READ_REE1_MODEM_PWR_S) -#define TEE_READ_REE1_MODEM_PWR_V 0x00000001U -#define TEE_READ_REE1_MODEM_PWR_S 2 -/** TEE_READ_REE2_MODEM_PWR : R/W; bitpos: [3]; default: 0; - * Configures modem_pwr registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_MODEM_PWR (BIT(3)) -#define TEE_READ_REE2_MODEM_PWR_M (TEE_READ_REE2_MODEM_PWR_V << TEE_READ_REE2_MODEM_PWR_S) -#define TEE_READ_REE2_MODEM_PWR_V 0x00000001U -#define TEE_READ_REE2_MODEM_PWR_S 3 -/** TEE_WRITE_TEE_MODEM_PWR : R/W; bitpos: [4]; default: 1; - * Configures modem_pwr registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_MODEM_PWR (BIT(4)) -#define TEE_WRITE_TEE_MODEM_PWR_M (TEE_WRITE_TEE_MODEM_PWR_V << TEE_WRITE_TEE_MODEM_PWR_S) -#define TEE_WRITE_TEE_MODEM_PWR_V 0x00000001U -#define TEE_WRITE_TEE_MODEM_PWR_S 4 -/** TEE_WRITE_REE0_MODEM_PWR : R/W; bitpos: [5]; default: 0; - * Configures modem_pwr registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_MODEM_PWR (BIT(5)) -#define TEE_WRITE_REE0_MODEM_PWR_M (TEE_WRITE_REE0_MODEM_PWR_V << TEE_WRITE_REE0_MODEM_PWR_S) -#define TEE_WRITE_REE0_MODEM_PWR_V 0x00000001U -#define TEE_WRITE_REE0_MODEM_PWR_S 5 -/** TEE_WRITE_REE1_MODEM_PWR : R/W; bitpos: [6]; default: 0; - * Configures modem_pwr registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_MODEM_PWR (BIT(6)) -#define TEE_WRITE_REE1_MODEM_PWR_M (TEE_WRITE_REE1_MODEM_PWR_V << TEE_WRITE_REE1_MODEM_PWR_S) -#define TEE_WRITE_REE1_MODEM_PWR_V 0x00000001U -#define TEE_WRITE_REE1_MODEM_PWR_S 6 -/** TEE_WRITE_REE2_MODEM_PWR : R/W; bitpos: [7]; default: 0; - * Configures modem_pwr registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_MODEM_PWR (BIT(7)) -#define TEE_WRITE_REE2_MODEM_PWR_M (TEE_WRITE_REE2_MODEM_PWR_V << TEE_WRITE_REE2_MODEM_PWR_S) -#define TEE_WRITE_REE2_MODEM_PWR_V 0x00000001U -#define TEE_WRITE_REE2_MODEM_PWR_S 7 - -/** TEE_HINF_CTRL_REG register - * hinf read/write control register - */ -#define TEE_HINF_CTRL_REG (DR_REG_TEE_BASE + 0x14c) -/** TEE_READ_TEE_HINF : R/W; bitpos: [0]; default: 1; - * Configures hinf registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_HINF (BIT(0)) -#define TEE_READ_TEE_HINF_M (TEE_READ_TEE_HINF_V << TEE_READ_TEE_HINF_S) -#define TEE_READ_TEE_HINF_V 0x00000001U -#define TEE_READ_TEE_HINF_S 0 -/** TEE_READ_REE0_HINF : R/W; bitpos: [1]; default: 0; - * Configures hinf registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_HINF (BIT(1)) -#define TEE_READ_REE0_HINF_M (TEE_READ_REE0_HINF_V << TEE_READ_REE0_HINF_S) -#define TEE_READ_REE0_HINF_V 0x00000001U -#define TEE_READ_REE0_HINF_S 1 -/** TEE_READ_REE1_HINF : R/W; bitpos: [2]; default: 0; - * Configures hinf registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_HINF (BIT(2)) -#define TEE_READ_REE1_HINF_M (TEE_READ_REE1_HINF_V << TEE_READ_REE1_HINF_S) -#define TEE_READ_REE1_HINF_V 0x00000001U -#define TEE_READ_REE1_HINF_S 2 -/** TEE_READ_REE2_HINF : R/W; bitpos: [3]; default: 0; - * Configures hinf registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_HINF (BIT(3)) -#define TEE_READ_REE2_HINF_M (TEE_READ_REE2_HINF_V << TEE_READ_REE2_HINF_S) -#define TEE_READ_REE2_HINF_V 0x00000001U -#define TEE_READ_REE2_HINF_S 3 -/** TEE_WRITE_TEE_HINF : R/W; bitpos: [4]; default: 1; - * Configures hinf registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_HINF (BIT(4)) -#define TEE_WRITE_TEE_HINF_M (TEE_WRITE_TEE_HINF_V << TEE_WRITE_TEE_HINF_S) -#define TEE_WRITE_TEE_HINF_V 0x00000001U -#define TEE_WRITE_TEE_HINF_S 4 -/** TEE_WRITE_REE0_HINF : R/W; bitpos: [5]; default: 0; - * Configures hinf registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_HINF (BIT(5)) -#define TEE_WRITE_REE0_HINF_M (TEE_WRITE_REE0_HINF_V << TEE_WRITE_REE0_HINF_S) -#define TEE_WRITE_REE0_HINF_V 0x00000001U -#define TEE_WRITE_REE0_HINF_S 5 -/** TEE_WRITE_REE1_HINF : R/W; bitpos: [6]; default: 0; - * Configures hinf registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_HINF (BIT(6)) -#define TEE_WRITE_REE1_HINF_M (TEE_WRITE_REE1_HINF_V << TEE_WRITE_REE1_HINF_S) -#define TEE_WRITE_REE1_HINF_V 0x00000001U -#define TEE_WRITE_REE1_HINF_S 6 -/** TEE_WRITE_REE2_HINF : R/W; bitpos: [7]; default: 0; - * Configures hinf registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_HINF (BIT(7)) -#define TEE_WRITE_REE2_HINF_M (TEE_WRITE_REE2_HINF_V << TEE_WRITE_REE2_HINF_S) -#define TEE_WRITE_REE2_HINF_V 0x00000001U -#define TEE_WRITE_REE2_HINF_S 7 - -/** TEE_SLC_CTRL_REG register - * slc read/write control register - */ -#define TEE_SLC_CTRL_REG (DR_REG_TEE_BASE + 0x150) -/** TEE_READ_TEE_SLC : R/W; bitpos: [0]; default: 1; - * Configures slc registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_SLC (BIT(0)) -#define TEE_READ_TEE_SLC_M (TEE_READ_TEE_SLC_V << TEE_READ_TEE_SLC_S) -#define TEE_READ_TEE_SLC_V 0x00000001U -#define TEE_READ_TEE_SLC_S 0 -/** TEE_READ_REE0_SLC : R/W; bitpos: [1]; default: 0; - * Configures slc registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_SLC (BIT(1)) -#define TEE_READ_REE0_SLC_M (TEE_READ_REE0_SLC_V << TEE_READ_REE0_SLC_S) -#define TEE_READ_REE0_SLC_V 0x00000001U -#define TEE_READ_REE0_SLC_S 1 -/** TEE_READ_REE1_SLC : R/W; bitpos: [2]; default: 0; - * Configures slc registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_SLC (BIT(2)) -#define TEE_READ_REE1_SLC_M (TEE_READ_REE1_SLC_V << TEE_READ_REE1_SLC_S) -#define TEE_READ_REE1_SLC_V 0x00000001U -#define TEE_READ_REE1_SLC_S 2 -/** TEE_READ_REE2_SLC : R/W; bitpos: [3]; default: 0; - * Configures slc registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_SLC (BIT(3)) -#define TEE_READ_REE2_SLC_M (TEE_READ_REE2_SLC_V << TEE_READ_REE2_SLC_S) -#define TEE_READ_REE2_SLC_V 0x00000001U -#define TEE_READ_REE2_SLC_S 3 -/** TEE_WRITE_TEE_SLC : R/W; bitpos: [4]; default: 1; - * Configures slc registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_SLC (BIT(4)) -#define TEE_WRITE_TEE_SLC_M (TEE_WRITE_TEE_SLC_V << TEE_WRITE_TEE_SLC_S) -#define TEE_WRITE_TEE_SLC_V 0x00000001U -#define TEE_WRITE_TEE_SLC_S 4 -/** TEE_WRITE_REE0_SLC : R/W; bitpos: [5]; default: 0; - * Configures slc registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_SLC (BIT(5)) -#define TEE_WRITE_REE0_SLC_M (TEE_WRITE_REE0_SLC_V << TEE_WRITE_REE0_SLC_S) -#define TEE_WRITE_REE0_SLC_V 0x00000001U -#define TEE_WRITE_REE0_SLC_S 5 -/** TEE_WRITE_REE1_SLC : R/W; bitpos: [6]; default: 0; - * Configures slc registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_SLC (BIT(6)) -#define TEE_WRITE_REE1_SLC_M (TEE_WRITE_REE1_SLC_V << TEE_WRITE_REE1_SLC_S) -#define TEE_WRITE_REE1_SLC_V 0x00000001U -#define TEE_WRITE_REE1_SLC_S 6 -/** TEE_WRITE_REE2_SLC : R/W; bitpos: [7]; default: 0; - * Configures slc registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_SLC (BIT(7)) -#define TEE_WRITE_REE2_SLC_M (TEE_WRITE_REE2_SLC_V << TEE_WRITE_REE2_SLC_S) -#define TEE_WRITE_REE2_SLC_V 0x00000001U -#define TEE_WRITE_REE2_SLC_S 7 - -/** TEE_SLC_HOST_CTRL_REG register - * slc_host read/write control register - */ -#define TEE_SLC_HOST_CTRL_REG (DR_REG_TEE_BASE + 0x158) -/** TEE_READ_TEE_SLC_HOST : R/W; bitpos: [0]; default: 1; - * Configures slc_host registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_SLC_HOST (BIT(0)) -#define TEE_READ_TEE_SLC_HOST_M (TEE_READ_TEE_SLC_HOST_V << TEE_READ_TEE_SLC_HOST_S) -#define TEE_READ_TEE_SLC_HOST_V 0x00000001U -#define TEE_READ_TEE_SLC_HOST_S 0 -/** TEE_READ_REE0_SLC_HOST : R/W; bitpos: [1]; default: 0; - * Configures slc_host registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_SLC_HOST (BIT(1)) -#define TEE_READ_REE0_SLC_HOST_M (TEE_READ_REE0_SLC_HOST_V << TEE_READ_REE0_SLC_HOST_S) -#define TEE_READ_REE0_SLC_HOST_V 0x00000001U -#define TEE_READ_REE0_SLC_HOST_S 1 -/** TEE_READ_REE1_SLC_HOST : R/W; bitpos: [2]; default: 0; - * Configures slc_host registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_SLC_HOST (BIT(2)) -#define TEE_READ_REE1_SLC_HOST_M (TEE_READ_REE1_SLC_HOST_V << TEE_READ_REE1_SLC_HOST_S) -#define TEE_READ_REE1_SLC_HOST_V 0x00000001U -#define TEE_READ_REE1_SLC_HOST_S 2 -/** TEE_READ_REE2_SLC_HOST : R/W; bitpos: [3]; default: 0; - * Configures slc_host registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_SLC_HOST (BIT(3)) -#define TEE_READ_REE2_SLC_HOST_M (TEE_READ_REE2_SLC_HOST_V << TEE_READ_REE2_SLC_HOST_S) -#define TEE_READ_REE2_SLC_HOST_V 0x00000001U -#define TEE_READ_REE2_SLC_HOST_S 3 -/** TEE_WRITE_TEE_SLC_HOST : R/W; bitpos: [4]; default: 1; - * Configures slc_host registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_SLC_HOST (BIT(4)) -#define TEE_WRITE_TEE_SLC_HOST_M (TEE_WRITE_TEE_SLC_HOST_V << TEE_WRITE_TEE_SLC_HOST_S) -#define TEE_WRITE_TEE_SLC_HOST_V 0x00000001U -#define TEE_WRITE_TEE_SLC_HOST_S 4 -/** TEE_WRITE_REE0_SLC_HOST : R/W; bitpos: [5]; default: 0; - * Configures slc_host registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_SLC_HOST (BIT(5)) -#define TEE_WRITE_REE0_SLC_HOST_M (TEE_WRITE_REE0_SLC_HOST_V << TEE_WRITE_REE0_SLC_HOST_S) -#define TEE_WRITE_REE0_SLC_HOST_V 0x00000001U -#define TEE_WRITE_REE0_SLC_HOST_S 5 -/** TEE_WRITE_REE1_SLC_HOST : R/W; bitpos: [6]; default: 0; - * Configures slc_host registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_SLC_HOST (BIT(6)) -#define TEE_WRITE_REE1_SLC_HOST_M (TEE_WRITE_REE1_SLC_HOST_V << TEE_WRITE_REE1_SLC_HOST_S) -#define TEE_WRITE_REE1_SLC_HOST_V 0x00000001U -#define TEE_WRITE_REE1_SLC_HOST_S 6 -/** TEE_WRITE_REE2_SLC_HOST : R/W; bitpos: [7]; default: 0; - * Configures slc_host registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_SLC_HOST (BIT(7)) -#define TEE_WRITE_REE2_SLC_HOST_M (TEE_WRITE_REE2_SLC_HOST_V << TEE_WRITE_REE2_SLC_HOST_S) -#define TEE_WRITE_REE2_SLC_HOST_V 0x00000001U -#define TEE_WRITE_REE2_SLC_HOST_S 7 - /** TEE_BUS_ERR_CONF_REG register - * Clock gating register + * Error message return configuration register */ #define TEE_BUS_ERR_CONF_REG (DR_REG_TEE_BASE + 0xff0) /** TEE_BUS_ERR_RESP_EN : R/W; bitpos: [0]; default: 0; - * Configures whether return error response to cpu when access blocked - * 0: disable error response - * 1: enable error response + * Configures whether to return error message to CPU when access is blocked. + * 0: Disable + * 1: Enable */ #define TEE_BUS_ERR_RESP_EN (BIT(0)) #define TEE_BUS_ERR_RESP_EN_M (TEE_BUS_ERR_RESP_EN_V << TEE_BUS_ERR_RESP_EN_S) @@ -4232,8 +3527,8 @@ extern "C" { #define TEE_CLOCK_GATE_REG (DR_REG_TEE_BASE + 0xff8) /** TEE_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ #define TEE_CLK_EN (BIT(0)) #define TEE_CLK_EN_M (TEE_CLK_EN_V << TEE_CLK_EN_S) @@ -4245,7 +3540,7 @@ extern "C" { */ #define TEE_DATE_REG (DR_REG_TEE_BASE + 0xffc) /** TEE_DATE : R/W; bitpos: [27:0]; default: 37773824; - * Version control register + * Version control register. */ #define TEE_DATE 0x0FFFFFFFU #define TEE_DATE_M (TEE_DATE_V << TEE_DATE_S) diff --git a/components/soc/esp32c5/register/soc/tee_struct.h b/components/soc/esp32c5/register/soc/tee_struct.h index 13f9c99d53..23e99d2768 100644 --- a/components/soc/esp32c5/register/soc/tee_struct.h +++ b/components/soc/esp32c5/register/soc/tee_struct.h @@ -10,22 +10,24 @@ extern "C" { #endif -/** Group: Tee mode control register */ +/** Group: Configuration Registers */ /** Type of mn_mode_ctrl register - * TEE mode control register + * Security mode configuration register */ typedef union { struct { /** mn_mode : R/W; bitpos: [1:0]; default: 0; - * Configures Mn security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master n. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ uint32_t mn_mode:2; /** mn_lock : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_Mn_MODE. + * 0: Do not lock + * 1: Lock */ uint32_t mn_lock:1; uint32_t reserved_3:29; @@ -34,9 +36,9 @@ typedef union { } tee_mn_mode_ctrl_reg_t; -/** Group: read write control register */ +/** Group: Peripheral Read/Write Control Registers */ /** Type of uart0_ctrl register - * uart0 read/write control register + * UART0 read/write control register */ typedef union { struct { @@ -94,7 +96,7 @@ typedef union { } tee_uart0_ctrl_reg_t; /** Type of uart1_ctrl register - * uart1 read/write control register + * UART1 read/write control register */ typedef union { struct { @@ -152,7 +154,7 @@ typedef union { } tee_uart1_ctrl_reg_t; /** Type of uhci0_ctrl register - * uhci0 read/write control register + * UHCI read/write control register */ typedef union { struct { @@ -210,7 +212,7 @@ typedef union { } tee_uhci0_ctrl_reg_t; /** Type of i2c_ext0_ctrl register - * i2c_ext0 read/write control register + * I2C read/write control register */ typedef union { struct { @@ -268,7 +270,7 @@ typedef union { } tee_i2c_ext0_ctrl_reg_t; /** Type of i2s_ctrl register - * i2s read/write control register + * I2S read/write control register */ typedef union { struct { @@ -326,7 +328,7 @@ typedef union { } tee_i2s_ctrl_reg_t; /** Type of parl_io_ctrl register - * parl_io read/write control register + * PARL_IO read/write control register */ typedef union { struct { @@ -384,7 +386,7 @@ typedef union { } tee_parl_io_ctrl_reg_t; /** Type of pwm_ctrl register - * pwm read/write control register + * MCPWM read/write control register */ typedef union { struct { @@ -442,7 +444,7 @@ typedef union { } tee_pwm_ctrl_reg_t; /** Type of ledc_ctrl register - * ledc read/write control register + * LEDC read/write control register */ typedef union { struct { @@ -499,124 +501,124 @@ typedef union { uint32_t val; } tee_ledc_ctrl_reg_t; -/** Type of can0_ctrl register - * can read/write control register +/** Type of twai0_ctrl register + * TWAI0 read/write control register */ typedef union { struct { - /** read_tee_can0 : R/W; bitpos: [0]; default: 1; + /** read_tee_twai0 : R/W; bitpos: [0]; default: 1; * Configures can0 registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t read_tee_can0:1; - /** read_ree0_can0 : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_twai0:1; + /** read_ree0_twai0 : R/W; bitpos: [1]; default: 0; * Configures can0 registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree0_can0:1; - /** read_ree1_can0 : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_twai0:1; + /** read_ree1_twai0 : R/W; bitpos: [2]; default: 0; * Configures can0 registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree1_can0:1; - /** read_ree2_can0 : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_twai0:1; + /** read_ree2_twai0 : R/W; bitpos: [3]; default: 0; * Configures can0 registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree2_can0:1; - /** write_tee_can0 : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_twai0:1; + /** write_tee_twai0 : R/W; bitpos: [4]; default: 1; * Configures can0 registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t write_tee_can0:1; - /** write_ree0_can0 : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_twai0:1; + /** write_ree0_twai0 : R/W; bitpos: [5]; default: 0; * Configures can0 registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree0_can0:1; - /** write_ree1_can0 : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_twai0:1; + /** write_ree1_twai0 : R/W; bitpos: [6]; default: 0; * Configures can0 registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree1_can0:1; - /** write_ree2_can0 : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_twai0:1; + /** write_ree2_twai0 : R/W; bitpos: [7]; default: 0; * Configures can0 registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree2_can0:1; + uint32_t write_ree2_twai0:1; uint32_t reserved_8:24; }; uint32_t val; -} tee_can0_ctrl_reg_t; +} tee_twai0_ctrl_reg_t; -/** Type of usb_device_ctrl register - * usb_device read/write control register +/** Type of usb_serial_jtag_ctrl register + * USB_SERIAL_JTAG read/write control register */ typedef union { struct { - /** read_tee_usb_device : R/W; bitpos: [0]; default: 1; + /** read_tee_usb_serial_jtag : R/W; bitpos: [0]; default: 1; * Configures usb_device registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t read_tee_usb_device:1; - /** read_ree0_usb_device : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_usb_serial_jtag:1; + /** read_ree0_usb_serial_jtag : R/W; bitpos: [1]; default: 0; * Configures usb_device registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree0_usb_device:1; - /** read_ree1_usb_device : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_usb_serial_jtag:1; + /** read_ree1_usb_serial_jtag : R/W; bitpos: [2]; default: 0; * Configures usb_device registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree1_usb_device:1; - /** read_ree2_usb_device : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_usb_serial_jtag:1; + /** read_ree2_usb_serial_jtag : R/W; bitpos: [3]; default: 0; * Configures usb_device registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree2_usb_device:1; - /** write_tee_usb_device : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_usb_serial_jtag:1; + /** write_tee_usb_serial_jtag : R/W; bitpos: [4]; default: 1; * Configures usb_device registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t write_tee_usb_device:1; - /** write_ree0_usb_device : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_usb_serial_jtag:1; + /** write_ree0_usb_serial_jtag : R/W; bitpos: [5]; default: 0; * Configures usb_device registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree0_usb_device:1; - /** write_ree1_usb_device : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_usb_serial_jtag:1; + /** write_ree1_usb_serial_jtag : R/W; bitpos: [6]; default: 0; * Configures usb_device registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree1_usb_device:1; - /** write_ree2_usb_device : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_usb_serial_jtag:1; + /** write_ree2_usb_serial_jtag : R/W; bitpos: [7]; default: 0; * Configures usb_device registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree2_usb_device:1; + uint32_t write_ree2_usb_serial_jtag:1; uint32_t reserved_8:24; }; uint32_t val; -} tee_usb_device_ctrl_reg_t; +} tee_usb_serial_jtag_ctrl_reg_t; /** Type of rmt_ctrl register - * rmt read/write control register + * RMT read/write control register */ typedef union { struct { @@ -674,7 +676,7 @@ typedef union { } tee_rmt_ctrl_reg_t; /** Type of gdma_ctrl register - * gdma read/write control register + * GDMA read/write control register */ typedef union { struct { @@ -731,66 +733,8 @@ typedef union { uint32_t val; } tee_gdma_ctrl_reg_t; -/** Type of regdma_ctrl register - * regdma read/write control register - */ -typedef union { - struct { - /** read_tee_regdma : R/W; bitpos: [0]; default: 1; - * Configures regdma registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_regdma:1; - /** read_ree0_regdma : R/W; bitpos: [1]; default: 0; - * Configures regdma registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_regdma:1; - /** read_ree1_regdma : R/W; bitpos: [2]; default: 0; - * Configures regdma registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_regdma:1; - /** read_ree2_regdma : R/W; bitpos: [3]; default: 0; - * Configures regdma registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_regdma:1; - /** write_tee_regdma : R/W; bitpos: [4]; default: 1; - * Configures regdma registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_regdma:1; - /** write_ree0_regdma : R/W; bitpos: [5]; default: 0; - * Configures regdma registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_regdma:1; - /** write_ree1_regdma : R/W; bitpos: [6]; default: 0; - * Configures regdma registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_regdma:1; - /** write_ree2_regdma : R/W; bitpos: [7]; default: 0; - * Configures regdma registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_regdma:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_regdma_ctrl_reg_t; - /** Type of etm_ctrl register - * etm read/write control register + * SOC_ETM read/write control register */ typedef union { struct { @@ -848,7 +792,7 @@ typedef union { } tee_etm_ctrl_reg_t; /** Type of intmtx_ctrl register - * intmtx read/write control register + * INTMTX read/write control register */ typedef union { struct { @@ -906,7 +850,7 @@ typedef union { } tee_intmtx_ctrl_reg_t; /** Type of apb_adc_ctrl register - * apb_adc read/write control register + * SAR ADC read/write control register */ typedef union { struct { @@ -964,7 +908,7 @@ typedef union { } tee_apb_adc_ctrl_reg_t; /** Type of timergroup0_ctrl register - * timergroup0 read/write control register + * TIMG0 read/write control register */ typedef union { struct { @@ -1022,7 +966,7 @@ typedef union { } tee_timergroup0_ctrl_reg_t; /** Type of timergroup1_ctrl register - * timergroup1 read/write control register + * TIMG1 read/write control register */ typedef union { struct { @@ -1080,7 +1024,7 @@ typedef union { } tee_timergroup1_ctrl_reg_t; /** Type of systimer_ctrl register - * systimer read/write control register + * SYSTIMER read/write control register */ typedef union { struct { @@ -1137,124 +1081,8 @@ typedef union { uint32_t val; } tee_systimer_ctrl_reg_t; -/** Type of misc_ctrl register - * misc read/write control register - */ -typedef union { - struct { - /** read_tee_misc : R/W; bitpos: [0]; default: 1; - * Configures misc registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_misc:1; - /** read_ree0_misc : R/W; bitpos: [1]; default: 0; - * Configures misc registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_misc:1; - /** read_ree1_misc : R/W; bitpos: [2]; default: 0; - * Configures misc registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_misc:1; - /** read_ree2_misc : R/W; bitpos: [3]; default: 0; - * Configures misc registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_misc:1; - /** write_tee_misc : R/W; bitpos: [4]; default: 1; - * Configures misc registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_misc:1; - /** write_ree0_misc : R/W; bitpos: [5]; default: 0; - * Configures misc registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_misc:1; - /** write_ree1_misc : R/W; bitpos: [6]; default: 0; - * Configures misc registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_misc:1; - /** write_ree2_misc : R/W; bitpos: [7]; default: 0; - * Configures misc registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_misc:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_misc_ctrl_reg_t; - -/** Type of pvt_monitor_ctrl register - * pvt_monitor read/write control register - */ -typedef union { - struct { - /** read_tee_pvt_monitor : R/W; bitpos: [0]; default: 1; - * Configures pvt_monitor registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_pvt_monitor:1; - /** read_ree0_pvt_monitor : R/W; bitpos: [1]; default: 0; - * Configures pvt_monitor registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_pvt_monitor:1; - /** read_ree1_pvt_monitor : R/W; bitpos: [2]; default: 0; - * Configures pvt_monitor registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_pvt_monitor:1; - /** read_ree2_pvt_monitor : R/W; bitpos: [3]; default: 0; - * Configures pvt_monitor registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_pvt_monitor:1; - /** write_tee_pvt_monitor : R/W; bitpos: [4]; default: 1; - * Configures pvt_monitor registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_pvt_monitor:1; - /** write_ree0_pvt_monitor : R/W; bitpos: [5]; default: 0; - * Configures pvt_monitor registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_pvt_monitor:1; - /** write_ree1_pvt_monitor : R/W; bitpos: [6]; default: 0; - * Configures pvt_monitor registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_pvt_monitor:1; - /** write_ree2_pvt_monitor : R/W; bitpos: [7]; default: 0; - * Configures pvt_monitor registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_pvt_monitor:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_pvt_monitor_ctrl_reg_t; - /** Type of pcnt_ctrl register - * pcnt read/write control register + * PCNT read/write control register */ typedef union { struct { @@ -1312,7 +1140,7 @@ typedef union { } tee_pcnt_ctrl_reg_t; /** Type of iomux_ctrl register - * iomux read/write control register + * IO MUX read/write control register */ typedef union { struct { @@ -1370,7 +1198,7 @@ typedef union { } tee_iomux_ctrl_reg_t; /** Type of psram_mem_monitor_ctrl register - * psram_mem_monitor read/write control register + * PSRAM_MEM_MONITOR read/write control register */ typedef union { struct { @@ -1428,7 +1256,7 @@ typedef union { } tee_psram_mem_monitor_ctrl_reg_t; /** Type of mem_acs_monitor_ctrl register - * mem_acs_monitor read/write control register + * TCM_MEM_MONITOR read/write control register */ typedef union { struct { @@ -1486,7 +1314,7 @@ typedef union { } tee_mem_acs_monitor_ctrl_reg_t; /** Type of hp_system_reg_ctrl register - * hp_system_reg read/write control register + * HP_SYSREG read/write control register */ typedef union { struct { @@ -1544,7 +1372,7 @@ typedef union { } tee_hp_system_reg_ctrl_reg_t; /** Type of pcr_reg_ctrl register - * pcr_reg read/write control register + * PCR read/write control register */ typedef union { struct { @@ -1602,7 +1430,7 @@ typedef union { } tee_pcr_reg_ctrl_reg_t; /** Type of mspi_ctrl register - * mspi read/write control register + * SPI01 read/write control register */ typedef union { struct { @@ -1660,7 +1488,7 @@ typedef union { } tee_mspi_ctrl_reg_t; /** Type of hp_apm_ctrl register - * hp_apm read/write control register + * HP_APM and LP_APM0 read/write control register */ typedef union { struct { @@ -1718,7 +1546,7 @@ typedef union { } tee_hp_apm_ctrl_reg_t; /** Type of cpu_apm_ctrl register - * cpu_apm read/write control register + * CPU_APM_REG read/write control register */ typedef union { struct { @@ -1776,7 +1604,7 @@ typedef union { } tee_cpu_apm_ctrl_reg_t; /** Type of tee_ctrl register - * tee read/write control register + * TEE read/write control register */ typedef union { struct { @@ -1834,7 +1662,8 @@ typedef union { } tee_tee_ctrl_reg_t; /** Type of crypt_ctrl register - * crypt read/write control register + * CRYPT read/write control register, including security peripherals from AES to ECDSA + * address range */ typedef union { struct { @@ -1892,7 +1721,7 @@ typedef union { } tee_crypt_ctrl_reg_t; /** Type of trace_ctrl register - * trace read/write control register + * TRACE read/write control register */ typedef union { struct { @@ -1950,7 +1779,7 @@ typedef union { } tee_trace_ctrl_reg_t; /** Type of cpu_bus_monitor_ctrl register - * cpu_bus_monitor read/write control register + * BUS_MONITOR read/write control register */ typedef union { struct { @@ -2008,7 +1837,7 @@ typedef union { } tee_cpu_bus_monitor_ctrl_reg_t; /** Type of intpri_reg_ctrl register - * intpri_reg read/write control register + * INTPRI_REG read/write control register */ typedef union { struct { @@ -2065,182 +1894,66 @@ typedef union { uint32_t val; } tee_intpri_reg_ctrl_reg_t; -/** Type of cache_cfg_ctrl register - * cache_cfg read/write control register +/** Type of twai1_ctrl register + * TWAI1 read/write control register */ typedef union { struct { - /** read_tee_cache_cfg : R/W; bitpos: [0]; default: 1; - * Configures cache_cfg registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_cache_cfg:1; - /** read_ree0_cache_cfg : R/W; bitpos: [1]; default: 0; - * Configures cache_cfg registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_cache_cfg:1; - /** read_ree1_cache_cfg : R/W; bitpos: [2]; default: 0; - * Configures cache_cfg registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_cache_cfg:1; - /** read_ree2_cache_cfg : R/W; bitpos: [3]; default: 0; - * Configures cache_cfg registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_cache_cfg:1; - /** write_tee_cache_cfg : R/W; bitpos: [4]; default: 1; - * Configures cache_cfg registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_cache_cfg:1; - /** write_ree0_cache_cfg : R/W; bitpos: [5]; default: 0; - * Configures cache_cfg registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_cache_cfg:1; - /** write_ree1_cache_cfg : R/W; bitpos: [6]; default: 0; - * Configures cache_cfg registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_cache_cfg:1; - /** write_ree2_cache_cfg : R/W; bitpos: [7]; default: 0; - * Configures cache_cfg registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_cache_cfg:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_cache_cfg_ctrl_reg_t; - -/** Type of modem_ctrl register - * modem read/write control register - */ -typedef union { - struct { - /** read_tee_modem : R/W; bitpos: [0]; default: 1; - * Configures modem registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_modem:1; - /** read_ree0_modem : R/W; bitpos: [1]; default: 0; - * Configures modem registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_modem:1; - /** read_ree1_modem : R/W; bitpos: [2]; default: 0; - * Configures modem registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_modem:1; - /** read_ree2_modem : R/W; bitpos: [3]; default: 0; - * Configures modem registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_modem:1; - /** write_tee_modem : R/W; bitpos: [4]; default: 1; - * Configures modem registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_modem:1; - /** write_ree0_modem : R/W; bitpos: [5]; default: 0; - * Configures modem registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_modem:1; - /** write_ree1_modem : R/W; bitpos: [6]; default: 0; - * Configures modem registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_modem:1; - /** write_ree2_modem : R/W; bitpos: [7]; default: 0; - * Configures modem registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_modem:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_modem_ctrl_reg_t; - -/** Type of can1_ctrl register - * can1 read/write control register - */ -typedef union { - struct { - /** read_tee_can1 : R/W; bitpos: [0]; default: 1; + /** read_tee_twai1 : R/W; bitpos: [0]; default: 1; * Configures can1 registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t read_tee_can1:1; - /** read_ree0_can1 : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_twai1:1; + /** read_ree0_twai1 : R/W; bitpos: [1]; default: 0; * Configures can1 registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree0_can1:1; - /** read_ree1_can1 : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_twai1:1; + /** read_ree1_twai1 : R/W; bitpos: [2]; default: 0; * Configures can1 registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree1_can1:1; - /** read_ree2_can1 : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_twai1:1; + /** read_ree2_twai1 : R/W; bitpos: [3]; default: 0; * Configures can1 registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree2_can1:1; - /** write_tee_can1 : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_twai1:1; + /** write_tee_twai1 : R/W; bitpos: [4]; default: 1; * Configures can1 registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t write_tee_can1:1; - /** write_ree0_can1 : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_twai1:1; + /** write_ree0_twai1 : R/W; bitpos: [5]; default: 0; * Configures can1 registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree0_can1:1; - /** write_ree1_can1 : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_twai1:1; + /** write_ree1_twai1 : R/W; bitpos: [6]; default: 0; * Configures can1 registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree1_can1:1; - /** write_ree2_can1 : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_twai1:1; + /** write_ree2_twai1 : R/W; bitpos: [7]; default: 0; * Configures can1 registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree2_can1:1; + uint32_t write_ree2_twai1:1; uint32_t reserved_8:24; }; uint32_t val; -} tee_can1_ctrl_reg_t; +} tee_twai1_ctrl_reg_t; /** Type of spi2_ctrl register - * spi2 read/write control register + * SPI2 read/write control register */ typedef union { struct { @@ -2298,7 +2011,7 @@ typedef union { } tee_spi2_ctrl_reg_t; /** Type of bs_ctrl register - * bs read/write control register + * BITSCRAMBLER read/write control register */ typedef union { struct { @@ -2355,307 +2068,15 @@ typedef union { uint32_t val; } tee_bs_ctrl_reg_t; -/** Type of km_ctrl register - * km read/write control register - */ -typedef union { - struct { - /** read_tee_km : R/W; bitpos: [0]; default: 1; - * Configures km registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_km:1; - /** read_ree0_km : R/W; bitpos: [1]; default: 0; - * Configures km registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_km:1; - /** read_ree1_km : R/W; bitpos: [2]; default: 0; - * Configures km registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_km:1; - /** read_ree2_km : R/W; bitpos: [3]; default: 0; - * Configures km registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_km:1; - /** write_tee_km : R/W; bitpos: [4]; default: 1; - * Configures km registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_km:1; - /** write_ree0_km : R/W; bitpos: [5]; default: 0; - * Configures km registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_km:1; - /** write_ree1_km : R/W; bitpos: [6]; default: 0; - * Configures km registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_km:1; - /** write_ree2_km : R/W; bitpos: [7]; default: 0; - * Configures km registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_km:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_km_ctrl_reg_t; - -/** Type of modem_pwr_ctrl register - * modem_pwr read/write control register - */ -typedef union { - struct { - /** read_tee_modem_pwr : R/W; bitpos: [0]; default: 1; - * Configures modem_pwr registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_modem_pwr:1; - /** read_ree0_modem_pwr : R/W; bitpos: [1]; default: 0; - * Configures modem_pwr registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_modem_pwr:1; - /** read_ree1_modem_pwr : R/W; bitpos: [2]; default: 0; - * Configures modem_pwr registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_modem_pwr:1; - /** read_ree2_modem_pwr : R/W; bitpos: [3]; default: 0; - * Configures modem_pwr registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_modem_pwr:1; - /** write_tee_modem_pwr : R/W; bitpos: [4]; default: 1; - * Configures modem_pwr registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_modem_pwr:1; - /** write_ree0_modem_pwr : R/W; bitpos: [5]; default: 0; - * Configures modem_pwr registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_modem_pwr:1; - /** write_ree1_modem_pwr : R/W; bitpos: [6]; default: 0; - * Configures modem_pwr registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_modem_pwr:1; - /** write_ree2_modem_pwr : R/W; bitpos: [7]; default: 0; - * Configures modem_pwr registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_modem_pwr:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_modem_pwr_ctrl_reg_t; - -/** Type of hinf_ctrl register - * hinf read/write control register - */ -typedef union { - struct { - /** read_tee_hinf : R/W; bitpos: [0]; default: 1; - * Configures hinf registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_hinf:1; - /** read_ree0_hinf : R/W; bitpos: [1]; default: 0; - * Configures hinf registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_hinf:1; - /** read_ree1_hinf : R/W; bitpos: [2]; default: 0; - * Configures hinf registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_hinf:1; - /** read_ree2_hinf : R/W; bitpos: [3]; default: 0; - * Configures hinf registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_hinf:1; - /** write_tee_hinf : R/W; bitpos: [4]; default: 1; - * Configures hinf registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_hinf:1; - /** write_ree0_hinf : R/W; bitpos: [5]; default: 0; - * Configures hinf registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_hinf:1; - /** write_ree1_hinf : R/W; bitpos: [6]; default: 0; - * Configures hinf registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_hinf:1; - /** write_ree2_hinf : R/W; bitpos: [7]; default: 0; - * Configures hinf registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_hinf:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_hinf_ctrl_reg_t; - -/** Type of slc_ctrl register - * slc read/write control register - */ -typedef union { - struct { - /** read_tee_slc : R/W; bitpos: [0]; default: 1; - * Configures slc registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_slc:1; - /** read_ree0_slc : R/W; bitpos: [1]; default: 0; - * Configures slc registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_slc:1; - /** read_ree1_slc : R/W; bitpos: [2]; default: 0; - * Configures slc registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_slc:1; - /** read_ree2_slc : R/W; bitpos: [3]; default: 0; - * Configures slc registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_slc:1; - /** write_tee_slc : R/W; bitpos: [4]; default: 1; - * Configures slc registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_slc:1; - /** write_ree0_slc : R/W; bitpos: [5]; default: 0; - * Configures slc registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_slc:1; - /** write_ree1_slc : R/W; bitpos: [6]; default: 0; - * Configures slc registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_slc:1; - /** write_ree2_slc : R/W; bitpos: [7]; default: 0; - * Configures slc registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_slc:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_slc_ctrl_reg_t; - -/** Type of slc_host_ctrl register - * slc_host read/write control register - */ -typedef union { - struct { - /** read_tee_slc_host : R/W; bitpos: [0]; default: 1; - * Configures slc_host registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_slc_host:1; - /** read_ree0_slc_host : R/W; bitpos: [1]; default: 0; - * Configures slc_host registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_slc_host:1; - /** read_ree1_slc_host : R/W; bitpos: [2]; default: 0; - * Configures slc_host registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_slc_host:1; - /** read_ree2_slc_host : R/W; bitpos: [3]; default: 0; - * Configures slc_host registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_slc_host:1; - /** write_tee_slc_host : R/W; bitpos: [4]; default: 1; - * Configures slc_host registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_slc_host:1; - /** write_ree0_slc_host : R/W; bitpos: [5]; default: 0; - * Configures slc_host registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_slc_host:1; - /** write_ree1_slc_host : R/W; bitpos: [6]; default: 0; - * Configures slc_host registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_slc_host:1; - /** write_ree2_slc_host : R/W; bitpos: [7]; default: 0; - * Configures slc_host registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_slc_host:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_slc_host_ctrl_reg_t; - - -/** Group: config register */ /** Type of bus_err_conf register - * Clock gating register + * Error message return configuration register */ typedef union { struct { /** bus_err_resp_en : R/W; bitpos: [0]; default: 0; - * Configures whether return error response to cpu when access blocked - * 0: disable error response - * 1: enable error response + * Configures whether to return error message to CPU when access is blocked. + * 0: Disable + * 1: Enable */ uint32_t bus_err_resp_en:1; uint32_t reserved_1:31; @@ -2672,8 +2093,8 @@ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -2682,14 +2103,14 @@ typedef union { } tee_clock_gate_reg_t; -/** Group: Version control register */ +/** Group: Version Control Registers */ /** Type of date register * Version control register */ typedef union { struct { /** date : R/W; bitpos: [27:0]; default: 37773824; - * Version control register + * Version control register. */ uint32_t date:28; uint32_t reserved_28:4; @@ -2711,11 +2132,11 @@ typedef struct { volatile tee_pwm_ctrl_reg_t pwm_ctrl; uint32_t reserved_0a8; volatile tee_ledc_ctrl_reg_t ledc_ctrl; - volatile tee_can0_ctrl_reg_t can0_ctrl; - volatile tee_usb_device_ctrl_reg_t usb_device_ctrl; + volatile tee_twai0_ctrl_reg_t twai0_ctrl; + volatile tee_usb_serial_jtag_ctrl_reg_t usb_serial_jtag_ctrl; volatile tee_rmt_ctrl_reg_t rmt_ctrl; volatile tee_gdma_ctrl_reg_t gdma_ctrl; - volatile tee_regdma_ctrl_reg_t regdma_ctrl; + uint32_t reserved_0c0; volatile tee_etm_ctrl_reg_t etm_ctrl; volatile tee_intmtx_ctrl_reg_t intmtx_ctrl; uint32_t reserved_0cc; @@ -2723,9 +2144,7 @@ typedef struct { volatile tee_timergroup0_ctrl_reg_t timergroup0_ctrl; volatile tee_timergroup1_ctrl_reg_t timergroup1_ctrl; volatile tee_systimer_ctrl_reg_t systimer_ctrl; - volatile tee_misc_ctrl_reg_t misc_ctrl; - uint32_t reserved_0e4[3]; - volatile tee_pvt_monitor_ctrl_reg_t pvt_monitor_ctrl; + uint32_t reserved_0e0[5]; volatile tee_pcnt_ctrl_reg_t pcnt_ctrl; volatile tee_iomux_ctrl_reg_t iomux_ctrl; volatile tee_psram_mem_monitor_ctrl_reg_t psram_mem_monitor_ctrl; @@ -2741,18 +2160,11 @@ typedef struct { uint32_t reserved_124; volatile tee_cpu_bus_monitor_ctrl_reg_t cpu_bus_monitor_ctrl; volatile tee_intpri_reg_ctrl_reg_t intpri_reg_ctrl; - volatile tee_cache_cfg_ctrl_reg_t cache_cfg_ctrl; - volatile tee_modem_ctrl_reg_t modem_ctrl; - volatile tee_can1_ctrl_reg_t can1_ctrl; + uint32_t reserved_130[2]; + volatile tee_twai1_ctrl_reg_t twai1_ctrl; volatile tee_spi2_ctrl_reg_t spi2_ctrl; volatile tee_bs_ctrl_reg_t bs_ctrl; - volatile tee_km_ctrl_reg_t km_ctrl; - volatile tee_modem_pwr_ctrl_reg_t modem_pwr_ctrl; - volatile tee_hinf_ctrl_reg_t hinf_ctrl; - volatile tee_slc_ctrl_reg_t slc_ctrl; - uint32_t reserved_154; - volatile tee_slc_host_ctrl_reg_t slc_host_ctrl; - uint32_t reserved_15c[933]; + uint32_t reserved_144[939]; volatile tee_bus_err_conf_reg_t bus_err_conf; uint32_t reserved_ff4; volatile tee_clock_gate_reg_t clock_gate; From 0a93309a89ec5539f942b153c6232df78c56b968 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Fri, 23 May 2025 14:33:55 +0800 Subject: [PATCH 3/3] change(cache): update cache soc headers of c61 --- .../hal/esp32c61/include/hal/cache_ll.h | 8 +- .../soc/esp32c61/register/soc/cache_reg.h | 5635 +---------------- .../soc/esp32c61/register/soc/cache_struct.h | 5263 ++------------- 3 files changed, 791 insertions(+), 10115 deletions(-) diff --git a/components/hal/esp32c61/include/hal/cache_ll.h b/components/hal/esp32c61/include/hal/cache_ll.h index b636530415..965c7627f9 100644 --- a/components/hal/esp32c61/include/hal/cache_ll.h +++ b/components/hal/esp32c61/include/hal/cache_ll.h @@ -246,11 +246,11 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); uint32_t ibus_mask = 0; - ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_ICACHE_SHUT_IBUS0 : 0); + ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0); REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask); uint32_t dbus_mask = 0; - dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0); + dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0); REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask); } @@ -268,11 +268,11 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); uint32_t ibus_mask = 0; - ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_ICACHE_SHUT_IBUS0 : 0); + ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0); REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask); uint32_t dbus_mask = 0; - dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0); + dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0); REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask); } diff --git a/components/soc/esp32c61/register/soc/cache_reg.h b/components/soc/esp32c61/register/soc/cache_reg.h index d0e294a28c..3235f2dc32 100644 --- a/components/soc/esp32c61/register/soc/cache_reg.h +++ b/components/soc/esp32c61/register/soc/cache_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,504 +11,61 @@ extern "C" { #endif -/** CACHE_L1_ICACHE_CTRL_REG register - * L1 instruction Cache(L1-ICache) control register - */ -#define CACHE_L1_ICACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x0) -/** CACHE_L1_ICACHE_SHUT_IBUS0 : R/W; bitpos: [0]; default: 0; - * The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable - */ -#define CACHE_L1_ICACHE_SHUT_IBUS0 (BIT(0)) -#define CACHE_L1_ICACHE_SHUT_IBUS0_M (CACHE_L1_ICACHE_SHUT_IBUS0_V << CACHE_L1_ICACHE_SHUT_IBUS0_S) -#define CACHE_L1_ICACHE_SHUT_IBUS0_V 0x00000001U -#define CACHE_L1_ICACHE_SHUT_IBUS0_S 0 -/** CACHE_L1_ICACHE_SHUT_IBUS1 : R/W; bitpos: [1]; default: 0; - * The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable - */ -#define CACHE_L1_ICACHE_SHUT_IBUS1 (BIT(1)) -#define CACHE_L1_ICACHE_SHUT_IBUS1_M (CACHE_L1_ICACHE_SHUT_IBUS1_V << CACHE_L1_ICACHE_SHUT_IBUS1_S) -#define CACHE_L1_ICACHE_SHUT_IBUS1_V 0x00000001U -#define CACHE_L1_ICACHE_SHUT_IBUS1_S 1 -/** CACHE_L1_ICACHE_SHUT_IBUS2 : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE_SHUT_IBUS2 (BIT(2)) -#define CACHE_L1_ICACHE_SHUT_IBUS2_M (CACHE_L1_ICACHE_SHUT_IBUS2_V << CACHE_L1_ICACHE_SHUT_IBUS2_S) -#define CACHE_L1_ICACHE_SHUT_IBUS2_V 0x00000001U -#define CACHE_L1_ICACHE_SHUT_IBUS2_S 2 -/** CACHE_L1_ICACHE_SHUT_IBUS3 : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE_SHUT_IBUS3 (BIT(3)) -#define CACHE_L1_ICACHE_SHUT_IBUS3_M (CACHE_L1_ICACHE_SHUT_IBUS3_V << CACHE_L1_ICACHE_SHUT_IBUS3_S) -#define CACHE_L1_ICACHE_SHUT_IBUS3_V 0x00000001U -#define CACHE_L1_ICACHE_SHUT_IBUS3_S 3 -/** CACHE_L1_ICACHE_UNDEF_OP : R/W; bitpos: [15:8]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE_UNDEF_OP 0x000000FFU -#define CACHE_L1_ICACHE_UNDEF_OP_M (CACHE_L1_ICACHE_UNDEF_OP_V << CACHE_L1_ICACHE_UNDEF_OP_S) -#define CACHE_L1_ICACHE_UNDEF_OP_V 0x000000FFU -#define CACHE_L1_ICACHE_UNDEF_OP_S 8 - /** CACHE_L1_CACHE_CTRL_REG register - * L1 data Cache(L1-Cache) control register + * L1 data cache (L1 cache) control register */ #define CACHE_L1_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x4) /** CACHE_L1_CACHE_SHUT_BUS0 : R/W; bitpos: [0]; default: 0; - * The bit is used to disable core0 bus0 access L1-Cache, 0: enable, 1: disable + * Configures whether to disable BUS0 to access the L1 cache. + * 0: Enable + * 1: Disable */ #define CACHE_L1_CACHE_SHUT_BUS0 (BIT(0)) #define CACHE_L1_CACHE_SHUT_BUS0_M (CACHE_L1_CACHE_SHUT_BUS0_V << CACHE_L1_CACHE_SHUT_BUS0_S) #define CACHE_L1_CACHE_SHUT_BUS0_V 0x00000001U #define CACHE_L1_CACHE_SHUT_BUS0_S 0 /** CACHE_L1_CACHE_SHUT_BUS1 : R/W; bitpos: [1]; default: 0; - * The bit is used to disable core0 bus1 access L1-Cache, 0: enable, 1: disable + * Configures whether to disable BUS1 to access the L1 cache. + * 0: Enable + * 1: Disable */ #define CACHE_L1_CACHE_SHUT_BUS1 (BIT(1)) #define CACHE_L1_CACHE_SHUT_BUS1_M (CACHE_L1_CACHE_SHUT_BUS1_V << CACHE_L1_CACHE_SHUT_BUS1_S) #define CACHE_L1_CACHE_SHUT_BUS1_V 0x00000001U #define CACHE_L1_CACHE_SHUT_BUS1_S 1 -/** CACHE_L1_CACHE_SHUT_DBUS2 : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_CACHE_SHUT_DBUS2 (BIT(2)) -#define CACHE_L1_CACHE_SHUT_DBUS2_M (CACHE_L1_CACHE_SHUT_DBUS2_V << CACHE_L1_CACHE_SHUT_DBUS2_S) -#define CACHE_L1_CACHE_SHUT_DBUS2_V 0x00000001U -#define CACHE_L1_CACHE_SHUT_DBUS2_S 2 -/** CACHE_L1_CACHE_SHUT_DBUS3 : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_CACHE_SHUT_DBUS3 (BIT(3)) -#define CACHE_L1_CACHE_SHUT_DBUS3_M (CACHE_L1_CACHE_SHUT_DBUS3_V << CACHE_L1_CACHE_SHUT_DBUS3_S) -#define CACHE_L1_CACHE_SHUT_DBUS3_V 0x00000001U -#define CACHE_L1_CACHE_SHUT_DBUS3_S 3 -/** CACHE_L1_CACHE_SHUT_DMA : HRO; bitpos: [4]; default: 0; - * The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable - */ -#define CACHE_L1_CACHE_SHUT_DMA (BIT(4)) -#define CACHE_L1_CACHE_SHUT_DMA_M (CACHE_L1_CACHE_SHUT_DMA_V << CACHE_L1_CACHE_SHUT_DMA_S) -#define CACHE_L1_CACHE_SHUT_DMA_V 0x00000001U -#define CACHE_L1_CACHE_SHUT_DMA_S 4 -/** CACHE_L1_CACHE_UNDEF_OP : R/W; bitpos: [15:8]; default: 0; - * Reserved - */ -#define CACHE_L1_CACHE_UNDEF_OP 0x000000FFU -#define CACHE_L1_CACHE_UNDEF_OP_M (CACHE_L1_CACHE_UNDEF_OP_V << CACHE_L1_CACHE_UNDEF_OP_S) -#define CACHE_L1_CACHE_UNDEF_OP_V 0x000000FFU -#define CACHE_L1_CACHE_UNDEF_OP_S 8 - -/** CACHE_L1_BYPASS_CACHE_CONF_REG register - * Bypass Cache configure register - */ -#define CACHE_L1_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x8) -/** CACHE_BYPASS_L1_ICACHE0_EN : HRO; bitpos: [0]; default: 0; - * The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass. - */ -#define CACHE_BYPASS_L1_ICACHE0_EN (BIT(0)) -#define CACHE_BYPASS_L1_ICACHE0_EN_M (CACHE_BYPASS_L1_ICACHE0_EN_V << CACHE_BYPASS_L1_ICACHE0_EN_S) -#define CACHE_BYPASS_L1_ICACHE0_EN_V 0x00000001U -#define CACHE_BYPASS_L1_ICACHE0_EN_S 0 -/** CACHE_BYPASS_L1_ICACHE1_EN : HRO; bitpos: [1]; default: 0; - * The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass. - */ -#define CACHE_BYPASS_L1_ICACHE1_EN (BIT(1)) -#define CACHE_BYPASS_L1_ICACHE1_EN_M (CACHE_BYPASS_L1_ICACHE1_EN_V << CACHE_BYPASS_L1_ICACHE1_EN_S) -#define CACHE_BYPASS_L1_ICACHE1_EN_V 0x00000001U -#define CACHE_BYPASS_L1_ICACHE1_EN_S 1 -/** CACHE_BYPASS_L1_ICACHE2_EN : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_BYPASS_L1_ICACHE2_EN (BIT(2)) -#define CACHE_BYPASS_L1_ICACHE2_EN_M (CACHE_BYPASS_L1_ICACHE2_EN_V << CACHE_BYPASS_L1_ICACHE2_EN_S) -#define CACHE_BYPASS_L1_ICACHE2_EN_V 0x00000001U -#define CACHE_BYPASS_L1_ICACHE2_EN_S 2 -/** CACHE_BYPASS_L1_ICACHE3_EN : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_BYPASS_L1_ICACHE3_EN (BIT(3)) -#define CACHE_BYPASS_L1_ICACHE3_EN_M (CACHE_BYPASS_L1_ICACHE3_EN_V << CACHE_BYPASS_L1_ICACHE3_EN_S) -#define CACHE_BYPASS_L1_ICACHE3_EN_V 0x00000001U -#define CACHE_BYPASS_L1_ICACHE3_EN_S 3 -/** CACHE_BYPASS_L1_DCACHE_EN : HRO; bitpos: [4]; default: 0; - * The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass. - */ -#define CACHE_BYPASS_L1_DCACHE_EN (BIT(4)) -#define CACHE_BYPASS_L1_DCACHE_EN_M (CACHE_BYPASS_L1_DCACHE_EN_V << CACHE_BYPASS_L1_DCACHE_EN_S) -#define CACHE_BYPASS_L1_DCACHE_EN_V 0x00000001U -#define CACHE_BYPASS_L1_DCACHE_EN_S 4 - -/** CACHE_L1_CACHE_ATOMIC_CONF_REG register - * L1 Cache atomic feature configure register - */ -#define CACHE_L1_CACHE_ATOMIC_CONF_REG (DR_REG_CACHE_BASE + 0xc) -/** CACHE_L1_CACHE_ATOMIC_EN : HRO; bitpos: [0]; default: 0; - * The bit is used to enable atomic feature on L1-Cache when multiple cores access - * L1-Cache. 1: disable, 1: enable. - */ -#define CACHE_L1_CACHE_ATOMIC_EN (BIT(0)) -#define CACHE_L1_CACHE_ATOMIC_EN_M (CACHE_L1_CACHE_ATOMIC_EN_V << CACHE_L1_CACHE_ATOMIC_EN_S) -#define CACHE_L1_CACHE_ATOMIC_EN_V 0x00000001U -#define CACHE_L1_CACHE_ATOMIC_EN_S 0 - -/** CACHE_L1_ICACHE_CACHESIZE_CONF_REG register - * L1 instruction Cache CacheSize mode configure register - */ -#define CACHE_L1_ICACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x10) -/** CACHE_L1_ICACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0; - * The field is used to configure cachesize of L1-ICache as 256 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_256 (BIT(0)) -#define CACHE_L1_ICACHE_CACHESIZE_256_M (CACHE_L1_ICACHE_CACHESIZE_256_V << CACHE_L1_ICACHE_CACHESIZE_256_S) -#define CACHE_L1_ICACHE_CACHESIZE_256_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_256_S 0 -/** CACHE_L1_ICACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0; - * The field is used to configure cachesize of L1-ICache as 512 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_512 (BIT(1)) -#define CACHE_L1_ICACHE_CACHESIZE_512_M (CACHE_L1_ICACHE_CACHESIZE_512_V << CACHE_L1_ICACHE_CACHESIZE_512_S) -#define CACHE_L1_ICACHE_CACHESIZE_512_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_512_S 1 -/** CACHE_L1_ICACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0; - * The field is used to configure cachesize of L1-ICache as 1k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_1K (BIT(2)) -#define CACHE_L1_ICACHE_CACHESIZE_1K_M (CACHE_L1_ICACHE_CACHESIZE_1K_V << CACHE_L1_ICACHE_CACHESIZE_1K_S) -#define CACHE_L1_ICACHE_CACHESIZE_1K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_1K_S 2 -/** CACHE_L1_ICACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0; - * The field is used to configure cachesize of L1-ICache as 2k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_2K (BIT(3)) -#define CACHE_L1_ICACHE_CACHESIZE_2K_M (CACHE_L1_ICACHE_CACHESIZE_2K_V << CACHE_L1_ICACHE_CACHESIZE_2K_S) -#define CACHE_L1_ICACHE_CACHESIZE_2K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_2K_S 3 -/** CACHE_L1_ICACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0; - * The field is used to configure cachesize of L1-ICache as 4k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_4K (BIT(4)) -#define CACHE_L1_ICACHE_CACHESIZE_4K_M (CACHE_L1_ICACHE_CACHESIZE_4K_V << CACHE_L1_ICACHE_CACHESIZE_4K_S) -#define CACHE_L1_ICACHE_CACHESIZE_4K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_4K_S 4 -/** CACHE_L1_ICACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0; - * The field is used to configure cachesize of L1-ICache as 8k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_8K (BIT(5)) -#define CACHE_L1_ICACHE_CACHESIZE_8K_M (CACHE_L1_ICACHE_CACHESIZE_8K_V << CACHE_L1_ICACHE_CACHESIZE_8K_S) -#define CACHE_L1_ICACHE_CACHESIZE_8K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_8K_S 5 -/** CACHE_L1_ICACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0; - * The field is used to configure cachesize of L1-ICache as 16k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_16K (BIT(6)) -#define CACHE_L1_ICACHE_CACHESIZE_16K_M (CACHE_L1_ICACHE_CACHESIZE_16K_V << CACHE_L1_ICACHE_CACHESIZE_16K_S) -#define CACHE_L1_ICACHE_CACHESIZE_16K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_16K_S 6 -/** CACHE_L1_ICACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0; - * The field is used to configure cachesize of L1-ICache as 32k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_32K (BIT(7)) -#define CACHE_L1_ICACHE_CACHESIZE_32K_M (CACHE_L1_ICACHE_CACHESIZE_32K_V << CACHE_L1_ICACHE_CACHESIZE_32K_S) -#define CACHE_L1_ICACHE_CACHESIZE_32K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_32K_S 7 -/** CACHE_L1_ICACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0; - * The field is used to configure cachesize of L1-ICache as 64k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_64K (BIT(8)) -#define CACHE_L1_ICACHE_CACHESIZE_64K_M (CACHE_L1_ICACHE_CACHESIZE_64K_V << CACHE_L1_ICACHE_CACHESIZE_64K_S) -#define CACHE_L1_ICACHE_CACHESIZE_64K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_64K_S 8 -/** CACHE_L1_ICACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0; - * The field is used to configure cachesize of L1-ICache as 128k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_128K (BIT(9)) -#define CACHE_L1_ICACHE_CACHESIZE_128K_M (CACHE_L1_ICACHE_CACHESIZE_128K_V << CACHE_L1_ICACHE_CACHESIZE_128K_S) -#define CACHE_L1_ICACHE_CACHESIZE_128K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_128K_S 9 -/** CACHE_L1_ICACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0; - * The field is used to configure cachesize of L1-ICache as 256k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_256K (BIT(10)) -#define CACHE_L1_ICACHE_CACHESIZE_256K_M (CACHE_L1_ICACHE_CACHESIZE_256K_V << CACHE_L1_ICACHE_CACHESIZE_256K_S) -#define CACHE_L1_ICACHE_CACHESIZE_256K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_256K_S 10 -/** CACHE_L1_ICACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0; - * The field is used to configure cachesize of L1-ICache as 512k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_512K (BIT(11)) -#define CACHE_L1_ICACHE_CACHESIZE_512K_M (CACHE_L1_ICACHE_CACHESIZE_512K_V << CACHE_L1_ICACHE_CACHESIZE_512K_S) -#define CACHE_L1_ICACHE_CACHESIZE_512K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_512K_S 11 -/** CACHE_L1_ICACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0; - * The field is used to configure cachesize of L1-ICache as 1024k bytes. This field - * and all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_1024K (BIT(12)) -#define CACHE_L1_ICACHE_CACHESIZE_1024K_M (CACHE_L1_ICACHE_CACHESIZE_1024K_V << CACHE_L1_ICACHE_CACHESIZE_1024K_S) -#define CACHE_L1_ICACHE_CACHESIZE_1024K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_1024K_S 12 - -/** CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG register - * L1 instruction Cache BlockSize mode configure register - */ -#define CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x14) -/** CACHE_L1_ICACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0; - * The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all - * other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_BLOCKSIZE_8 (BIT(0)) -#define CACHE_L1_ICACHE_BLOCKSIZE_8_M (CACHE_L1_ICACHE_BLOCKSIZE_8_V << CACHE_L1_ICACHE_BLOCKSIZE_8_S) -#define CACHE_L1_ICACHE_BLOCKSIZE_8_V 0x00000001U -#define CACHE_L1_ICACHE_BLOCKSIZE_8_S 0 -/** CACHE_L1_ICACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0; - * The field is used to configureblocksize of L1-ICache as 16 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_BLOCKSIZE_16 (BIT(1)) -#define CACHE_L1_ICACHE_BLOCKSIZE_16_M (CACHE_L1_ICACHE_BLOCKSIZE_16_V << CACHE_L1_ICACHE_BLOCKSIZE_16_S) -#define CACHE_L1_ICACHE_BLOCKSIZE_16_V 0x00000001U -#define CACHE_L1_ICACHE_BLOCKSIZE_16_S 1 -/** CACHE_L1_ICACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0; - * The field is used to configureblocksize of L1-ICache as 32 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_BLOCKSIZE_32 (BIT(2)) -#define CACHE_L1_ICACHE_BLOCKSIZE_32_M (CACHE_L1_ICACHE_BLOCKSIZE_32_V << CACHE_L1_ICACHE_BLOCKSIZE_32_S) -#define CACHE_L1_ICACHE_BLOCKSIZE_32_V 0x00000001U -#define CACHE_L1_ICACHE_BLOCKSIZE_32_S 2 -/** CACHE_L1_ICACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0; - * The field is used to configureblocksize of L1-ICache as 64 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_BLOCKSIZE_64 (BIT(3)) -#define CACHE_L1_ICACHE_BLOCKSIZE_64_M (CACHE_L1_ICACHE_BLOCKSIZE_64_V << CACHE_L1_ICACHE_BLOCKSIZE_64_S) -#define CACHE_L1_ICACHE_BLOCKSIZE_64_V 0x00000001U -#define CACHE_L1_ICACHE_BLOCKSIZE_64_S 3 -/** CACHE_L1_ICACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0; - * The field is used to configureblocksize of L1-ICache as 128 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_BLOCKSIZE_128 (BIT(4)) -#define CACHE_L1_ICACHE_BLOCKSIZE_128_M (CACHE_L1_ICACHE_BLOCKSIZE_128_V << CACHE_L1_ICACHE_BLOCKSIZE_128_S) -#define CACHE_L1_ICACHE_BLOCKSIZE_128_V 0x00000001U -#define CACHE_L1_ICACHE_BLOCKSIZE_128_S 4 -/** CACHE_L1_ICACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0; - * The field is used to configureblocksize of L1-ICache as 256 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_BLOCKSIZE_256 (BIT(5)) -#define CACHE_L1_ICACHE_BLOCKSIZE_256_M (CACHE_L1_ICACHE_BLOCKSIZE_256_V << CACHE_L1_ICACHE_BLOCKSIZE_256_S) -#define CACHE_L1_ICACHE_BLOCKSIZE_256_V 0x00000001U -#define CACHE_L1_ICACHE_BLOCKSIZE_256_S 5 /** CACHE_L1_CACHE_CACHESIZE_CONF_REG register - * L1 data Cache CacheSize mode configure register + * Cache cache size register */ #define CACHE_L1_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x18) -/** CACHE_L1_CACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0; - * The field is used to configure cachesize of L1-DCache as 256 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_256 (BIT(0)) -#define CACHE_L1_CACHE_CACHESIZE_256_M (CACHE_L1_CACHE_CACHESIZE_256_V << CACHE_L1_CACHE_CACHESIZE_256_S) -#define CACHE_L1_CACHE_CACHESIZE_256_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_256_S 0 -/** CACHE_L1_CACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0; - * The field is used to configure cachesize of L1-DCache as 512 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_512 (BIT(1)) -#define CACHE_L1_CACHE_CACHESIZE_512_M (CACHE_L1_CACHE_CACHESIZE_512_V << CACHE_L1_CACHE_CACHESIZE_512_S) -#define CACHE_L1_CACHE_CACHESIZE_512_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_512_S 1 -/** CACHE_L1_CACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0; - * The field is used to configure cachesize of L1-DCache as 1k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_1K (BIT(2)) -#define CACHE_L1_CACHE_CACHESIZE_1K_M (CACHE_L1_CACHE_CACHESIZE_1K_V << CACHE_L1_CACHE_CACHESIZE_1K_S) -#define CACHE_L1_CACHE_CACHESIZE_1K_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_1K_S 2 -/** CACHE_L1_CACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0; - * The field is used to configure cachesize of L1-DCache as 2k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_2K (BIT(3)) -#define CACHE_L1_CACHE_CACHESIZE_2K_M (CACHE_L1_CACHE_CACHESIZE_2K_V << CACHE_L1_CACHE_CACHESIZE_2K_S) -#define CACHE_L1_CACHE_CACHESIZE_2K_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_2K_S 3 -/** CACHE_L1_CACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0; - * The field is used to configure cachesize of L1-DCache as 4k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_4K (BIT(4)) -#define CACHE_L1_CACHE_CACHESIZE_4K_M (CACHE_L1_CACHE_CACHESIZE_4K_V << CACHE_L1_CACHE_CACHESIZE_4K_S) -#define CACHE_L1_CACHE_CACHESIZE_4K_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_4K_S 4 -/** CACHE_L1_CACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0; - * The field is used to configure cachesize of L1-DCache as 8k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_8K (BIT(5)) -#define CACHE_L1_CACHE_CACHESIZE_8K_M (CACHE_L1_CACHE_CACHESIZE_8K_V << CACHE_L1_CACHE_CACHESIZE_8K_S) -#define CACHE_L1_CACHE_CACHESIZE_8K_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_8K_S 5 -/** CACHE_L1_CACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0; - * The field is used to configure cachesize of L1-DCache as 16k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_16K (BIT(6)) -#define CACHE_L1_CACHE_CACHESIZE_16K_M (CACHE_L1_CACHE_CACHESIZE_16K_V << CACHE_L1_CACHE_CACHESIZE_16K_S) -#define CACHE_L1_CACHE_CACHESIZE_16K_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_16K_S 6 -/** CACHE_L1_CACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 1; - * The field is used to configure cachesize of L1-DCache as 32k bytes. This field and - * all other fields within this register is onehot. +/** CACHE_L1_CACHE_CACHESIZE_32K : RO; bitpos: [7]; default: 1; + * Indicates that cache size is 32 KB. */ #define CACHE_L1_CACHE_CACHESIZE_32K (BIT(7)) #define CACHE_L1_CACHE_CACHESIZE_32K_M (CACHE_L1_CACHE_CACHESIZE_32K_V << CACHE_L1_CACHE_CACHESIZE_32K_S) #define CACHE_L1_CACHE_CACHESIZE_32K_V 0x00000001U #define CACHE_L1_CACHE_CACHESIZE_32K_S 7 -/** CACHE_L1_CACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0; - * The field is used to configure cachesize of L1-DCache as 64k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_64K (BIT(8)) -#define CACHE_L1_CACHE_CACHESIZE_64K_M (CACHE_L1_CACHE_CACHESIZE_64K_V << CACHE_L1_CACHE_CACHESIZE_64K_S) -#define CACHE_L1_CACHE_CACHESIZE_64K_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_64K_S 8 -/** CACHE_L1_CACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0; - * The field is used to configure cachesize of L1-DCache as 128k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_128K (BIT(9)) -#define CACHE_L1_CACHE_CACHESIZE_128K_M (CACHE_L1_CACHE_CACHESIZE_128K_V << CACHE_L1_CACHE_CACHESIZE_128K_S) -#define CACHE_L1_CACHE_CACHESIZE_128K_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_128K_S 9 -/** CACHE_L1_CACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0; - * The field is used to configure cachesize of L1-DCache as 256k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_256K (BIT(10)) -#define CACHE_L1_CACHE_CACHESIZE_256K_M (CACHE_L1_CACHE_CACHESIZE_256K_V << CACHE_L1_CACHE_CACHESIZE_256K_S) -#define CACHE_L1_CACHE_CACHESIZE_256K_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_256K_S 10 -/** CACHE_L1_CACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0; - * The field is used to configure cachesize of L1-DCache as 512k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_512K (BIT(11)) -#define CACHE_L1_CACHE_CACHESIZE_512K_M (CACHE_L1_CACHE_CACHESIZE_512K_V << CACHE_L1_CACHE_CACHESIZE_512K_S) -#define CACHE_L1_CACHE_CACHESIZE_512K_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_512K_S 11 -/** CACHE_L1_CACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0; - * The field is used to configure cachesize of L1-DCache as 1024k bytes. This field - * and all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_1024K (BIT(12)) -#define CACHE_L1_CACHE_CACHESIZE_1024K_M (CACHE_L1_CACHE_CACHESIZE_1024K_V << CACHE_L1_CACHE_CACHESIZE_1024K_S) -#define CACHE_L1_CACHE_CACHESIZE_1024K_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_1024K_S 12 /** CACHE_L1_CACHE_BLOCKSIZE_CONF_REG register - * L1 data Cache BlockSize mode configure register + * Cache block size register */ #define CACHE_L1_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x1c) -/** CACHE_L1_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0; - * The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all - * other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_BLOCKSIZE_8 (BIT(0)) -#define CACHE_L1_CACHE_BLOCKSIZE_8_M (CACHE_L1_CACHE_BLOCKSIZE_8_V << CACHE_L1_CACHE_BLOCKSIZE_8_S) -#define CACHE_L1_CACHE_BLOCKSIZE_8_V 0x00000001U -#define CACHE_L1_CACHE_BLOCKSIZE_8_S 0 -/** CACHE_L1_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0; - * The field is used to configureblocksize of L1-DCache as 16 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_BLOCKSIZE_16 (BIT(1)) -#define CACHE_L1_CACHE_BLOCKSIZE_16_M (CACHE_L1_CACHE_BLOCKSIZE_16_V << CACHE_L1_CACHE_BLOCKSIZE_16_S) -#define CACHE_L1_CACHE_BLOCKSIZE_16_V 0x00000001U -#define CACHE_L1_CACHE_BLOCKSIZE_16_S 1 -/** CACHE_L1_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 1; - * The field is used to configureblocksize of L1-DCache as 32 bytes. This field and - * all other fields within this register is onehot. +/** CACHE_L1_CACHE_BLOCKSIZE_32 : RO; bitpos: [2]; default: 1; + * Indicates that the cache block size is 32 bytes. */ #define CACHE_L1_CACHE_BLOCKSIZE_32 (BIT(2)) #define CACHE_L1_CACHE_BLOCKSIZE_32_M (CACHE_L1_CACHE_BLOCKSIZE_32_V << CACHE_L1_CACHE_BLOCKSIZE_32_S) #define CACHE_L1_CACHE_BLOCKSIZE_32_V 0x00000001U #define CACHE_L1_CACHE_BLOCKSIZE_32_S 2 -/** CACHE_L1_CACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0; - * The field is used to configureblocksize of L1-DCache as 64 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_BLOCKSIZE_64 (BIT(3)) -#define CACHE_L1_CACHE_BLOCKSIZE_64_M (CACHE_L1_CACHE_BLOCKSIZE_64_V << CACHE_L1_CACHE_BLOCKSIZE_64_S) -#define CACHE_L1_CACHE_BLOCKSIZE_64_V 0x00000001U -#define CACHE_L1_CACHE_BLOCKSIZE_64_S 3 -/** CACHE_L1_CACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0; - * The field is used to configureblocksize of L1-DCache as 128 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_BLOCKSIZE_128 (BIT(4)) -#define CACHE_L1_CACHE_BLOCKSIZE_128_M (CACHE_L1_CACHE_BLOCKSIZE_128_V << CACHE_L1_CACHE_BLOCKSIZE_128_S) -#define CACHE_L1_CACHE_BLOCKSIZE_128_V 0x00000001U -#define CACHE_L1_CACHE_BLOCKSIZE_128_S 4 -/** CACHE_L1_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0; - * The field is used to configureblocksize of L1-DCache as 256 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_BLOCKSIZE_256 (BIT(5)) -#define CACHE_L1_CACHE_BLOCKSIZE_256_M (CACHE_L1_CACHE_BLOCKSIZE_256_V << CACHE_L1_CACHE_BLOCKSIZE_256_S) -#define CACHE_L1_CACHE_BLOCKSIZE_256_V 0x00000001U -#define CACHE_L1_CACHE_BLOCKSIZE_256_S 5 /** CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG register - * Cache wrap around control register + * Cache critical word first control register */ #define CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x20) -/** CACHE_L1_ICACHE0_WRAP : HRO; bitpos: [0]; default: 0; - * Set this bit as 1 to enable L1-ICache0 wrap around mode. - */ -#define CACHE_L1_ICACHE0_WRAP (BIT(0)) -#define CACHE_L1_ICACHE0_WRAP_M (CACHE_L1_ICACHE0_WRAP_V << CACHE_L1_ICACHE0_WRAP_S) -#define CACHE_L1_ICACHE0_WRAP_V 0x00000001U -#define CACHE_L1_ICACHE0_WRAP_S 0 -/** CACHE_L1_ICACHE1_WRAP : HRO; bitpos: [1]; default: 0; - * Set this bit as 1 to enable L1-ICache1 wrap around mode. - */ -#define CACHE_L1_ICACHE1_WRAP (BIT(1)) -#define CACHE_L1_ICACHE1_WRAP_M (CACHE_L1_ICACHE1_WRAP_V << CACHE_L1_ICACHE1_WRAP_S) -#define CACHE_L1_ICACHE1_WRAP_V 0x00000001U -#define CACHE_L1_ICACHE1_WRAP_S 1 -/** CACHE_L1_ICACHE2_WRAP : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_WRAP (BIT(2)) -#define CACHE_L1_ICACHE2_WRAP_M (CACHE_L1_ICACHE2_WRAP_V << CACHE_L1_ICACHE2_WRAP_S) -#define CACHE_L1_ICACHE2_WRAP_V 0x00000001U -#define CACHE_L1_ICACHE2_WRAP_S 2 -/** CACHE_L1_ICACHE3_WRAP : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_WRAP (BIT(3)) -#define CACHE_L1_ICACHE3_WRAP_M (CACHE_L1_ICACHE3_WRAP_V << CACHE_L1_ICACHE3_WRAP_S) -#define CACHE_L1_ICACHE3_WRAP_V 0x00000001U -#define CACHE_L1_ICACHE3_WRAP_S 3 /** CACHE_L1_CACHE_WRAP : R/W; bitpos: [4]; default: 0; - * Set this bit as 1 to enable L1-DCache wrap around mode. + * Configures whether to enable the critical word first mode for the L1 cache. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_WRAP (BIT(4)) #define CACHE_L1_CACHE_WRAP_M (CACHE_L1_CACHE_WRAP_V << CACHE_L1_CACHE_WRAP_S) @@ -519,36 +76,10 @@ extern "C" { * Cache wrap around control register */ #define CACHE_L1_CACHE_MISS_ACCESS_CTRL_REG (DR_REG_CACHE_BASE + 0x24) -/** CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS : HRO; bitpos: [0]; default: 0; - * Set this bit as 1 to disable early restart of L1-ICache0 - */ -#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS (BIT(0)) -#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_M (CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_S) -#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_V 0x00000001U -#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_S 0 -/** CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS : HRO; bitpos: [1]; default: 0; - * Set this bit as 1 to disable early restart of L1-ICache1 - */ -#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS (BIT(1)) -#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_M (CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_S) -#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_V 0x00000001U -#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_S 1 -/** CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS (BIT(2)) -#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_M (CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_S) -#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_V 0x00000001U -#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_S 2 -/** CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS (BIT(3)) -#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_M (CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_S) -#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_V 0x00000001U -#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_S 3 /** CACHE_L1_CACHE_MISS_DISABLE_ACCESS : R/W; bitpos: [4]; default: 0; - * Set this bit as 1 to disable early restart of L1-DCache + * Configures whether to disable early restart function. + * 0: Enable + * 1: Disable */ #define CACHE_L1_CACHE_MISS_DISABLE_ACCESS (BIT(4)) #define CACHE_L1_CACHE_MISS_DISABLE_ACCESS_M (CACHE_L1_CACHE_MISS_DISABLE_ACCESS_V << CACHE_L1_CACHE_MISS_DISABLE_ACCESS_S) @@ -556,118 +87,32 @@ extern "C" { #define CACHE_L1_CACHE_MISS_DISABLE_ACCESS_S 4 /** CACHE_L1_CACHE_FREEZE_CTRL_REG register - * Cache Freeze control register + * Cache freeze control register */ #define CACHE_L1_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x28) -/** CACHE_L1_ICACHE0_FREEZE_EN : HRO; bitpos: [0]; default: 0; - * The bit is used to enable freeze operation on L1-ICache0. It can be cleared by - * software. - */ -#define CACHE_L1_ICACHE0_FREEZE_EN (BIT(0)) -#define CACHE_L1_ICACHE0_FREEZE_EN_M (CACHE_L1_ICACHE0_FREEZE_EN_V << CACHE_L1_ICACHE0_FREEZE_EN_S) -#define CACHE_L1_ICACHE0_FREEZE_EN_V 0x00000001U -#define CACHE_L1_ICACHE0_FREEZE_EN_S 0 -/** CACHE_L1_ICACHE0_FREEZE_MODE : HRO; bitpos: [1]; default: 0; - * The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. - */ -#define CACHE_L1_ICACHE0_FREEZE_MODE (BIT(1)) -#define CACHE_L1_ICACHE0_FREEZE_MODE_M (CACHE_L1_ICACHE0_FREEZE_MODE_V << CACHE_L1_ICACHE0_FREEZE_MODE_S) -#define CACHE_L1_ICACHE0_FREEZE_MODE_V 0x00000001U -#define CACHE_L1_ICACHE0_FREEZE_MODE_S 1 -/** CACHE_L1_ICACHE0_FREEZE_DONE : RO; bitpos: [2]; default: 0; - * The bit is used to indicate whether freeze operation on L1-ICache0 is finished or - * not. 0: not finished. 1: finished. - */ -#define CACHE_L1_ICACHE0_FREEZE_DONE (BIT(2)) -#define CACHE_L1_ICACHE0_FREEZE_DONE_M (CACHE_L1_ICACHE0_FREEZE_DONE_V << CACHE_L1_ICACHE0_FREEZE_DONE_S) -#define CACHE_L1_ICACHE0_FREEZE_DONE_V 0x00000001U -#define CACHE_L1_ICACHE0_FREEZE_DONE_S 2 -/** CACHE_L1_ICACHE1_FREEZE_EN : HRO; bitpos: [4]; default: 0; - * The bit is used to enable freeze operation on L1-ICache1. It can be cleared by - * software. - */ -#define CACHE_L1_ICACHE1_FREEZE_EN (BIT(4)) -#define CACHE_L1_ICACHE1_FREEZE_EN_M (CACHE_L1_ICACHE1_FREEZE_EN_V << CACHE_L1_ICACHE1_FREEZE_EN_S) -#define CACHE_L1_ICACHE1_FREEZE_EN_V 0x00000001U -#define CACHE_L1_ICACHE1_FREEZE_EN_S 4 -/** CACHE_L1_ICACHE1_FREEZE_MODE : HRO; bitpos: [5]; default: 0; - * The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. - */ -#define CACHE_L1_ICACHE1_FREEZE_MODE (BIT(5)) -#define CACHE_L1_ICACHE1_FREEZE_MODE_M (CACHE_L1_ICACHE1_FREEZE_MODE_V << CACHE_L1_ICACHE1_FREEZE_MODE_S) -#define CACHE_L1_ICACHE1_FREEZE_MODE_V 0x00000001U -#define CACHE_L1_ICACHE1_FREEZE_MODE_S 5 -/** CACHE_L1_ICACHE1_FREEZE_DONE : RO; bitpos: [6]; default: 0; - * The bit is used to indicate whether freeze operation on L1-ICache1 is finished or - * not. 0: not finished. 1: finished. - */ -#define CACHE_L1_ICACHE1_FREEZE_DONE (BIT(6)) -#define CACHE_L1_ICACHE1_FREEZE_DONE_M (CACHE_L1_ICACHE1_FREEZE_DONE_V << CACHE_L1_ICACHE1_FREEZE_DONE_S) -#define CACHE_L1_ICACHE1_FREEZE_DONE_V 0x00000001U -#define CACHE_L1_ICACHE1_FREEZE_DONE_S 6 -/** CACHE_L1_ICACHE2_FREEZE_EN : HRO; bitpos: [8]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_FREEZE_EN (BIT(8)) -#define CACHE_L1_ICACHE2_FREEZE_EN_M (CACHE_L1_ICACHE2_FREEZE_EN_V << CACHE_L1_ICACHE2_FREEZE_EN_S) -#define CACHE_L1_ICACHE2_FREEZE_EN_V 0x00000001U -#define CACHE_L1_ICACHE2_FREEZE_EN_S 8 -/** CACHE_L1_ICACHE2_FREEZE_MODE : HRO; bitpos: [9]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_FREEZE_MODE (BIT(9)) -#define CACHE_L1_ICACHE2_FREEZE_MODE_M (CACHE_L1_ICACHE2_FREEZE_MODE_V << CACHE_L1_ICACHE2_FREEZE_MODE_S) -#define CACHE_L1_ICACHE2_FREEZE_MODE_V 0x00000001U -#define CACHE_L1_ICACHE2_FREEZE_MODE_S 9 -/** CACHE_L1_ICACHE2_FREEZE_DONE : RO; bitpos: [10]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_FREEZE_DONE (BIT(10)) -#define CACHE_L1_ICACHE2_FREEZE_DONE_M (CACHE_L1_ICACHE2_FREEZE_DONE_V << CACHE_L1_ICACHE2_FREEZE_DONE_S) -#define CACHE_L1_ICACHE2_FREEZE_DONE_V 0x00000001U -#define CACHE_L1_ICACHE2_FREEZE_DONE_S 10 -/** CACHE_L1_ICACHE3_FREEZE_EN : HRO; bitpos: [12]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_FREEZE_EN (BIT(12)) -#define CACHE_L1_ICACHE3_FREEZE_EN_M (CACHE_L1_ICACHE3_FREEZE_EN_V << CACHE_L1_ICACHE3_FREEZE_EN_S) -#define CACHE_L1_ICACHE3_FREEZE_EN_V 0x00000001U -#define CACHE_L1_ICACHE3_FREEZE_EN_S 12 -/** CACHE_L1_ICACHE3_FREEZE_MODE : HRO; bitpos: [13]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_FREEZE_MODE (BIT(13)) -#define CACHE_L1_ICACHE3_FREEZE_MODE_M (CACHE_L1_ICACHE3_FREEZE_MODE_V << CACHE_L1_ICACHE3_FREEZE_MODE_S) -#define CACHE_L1_ICACHE3_FREEZE_MODE_V 0x00000001U -#define CACHE_L1_ICACHE3_FREEZE_MODE_S 13 -/** CACHE_L1_ICACHE3_FREEZE_DONE : RO; bitpos: [14]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_FREEZE_DONE (BIT(14)) -#define CACHE_L1_ICACHE3_FREEZE_DONE_M (CACHE_L1_ICACHE3_FREEZE_DONE_V << CACHE_L1_ICACHE3_FREEZE_DONE_S) -#define CACHE_L1_ICACHE3_FREEZE_DONE_V 0x00000001U -#define CACHE_L1_ICACHE3_FREEZE_DONE_S 14 /** CACHE_L1_CACHE_FREEZE_EN : R/W; bitpos: [16]; default: 0; - * The bit is used to enable freeze operation on L1-Cache. It can be cleared by + * Configures whether to enable freeze operation in the L1 cache. It can be cleared by * software. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_FREEZE_EN (BIT(16)) #define CACHE_L1_CACHE_FREEZE_EN_M (CACHE_L1_CACHE_FREEZE_EN_V << CACHE_L1_CACHE_FREEZE_EN_S) #define CACHE_L1_CACHE_FREEZE_EN_V 0x00000001U #define CACHE_L1_CACHE_FREEZE_EN_S 16 /** CACHE_L1_CACHE_FREEZE_MODE : R/W; bitpos: [17]; default: 0; - * The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. + * Configures the freeze mode in the L1 cache. + * 0: Assert busy if a cache miss occurs + * 1: Assert hit if a cache miss occurs */ #define CACHE_L1_CACHE_FREEZE_MODE (BIT(17)) #define CACHE_L1_CACHE_FREEZE_MODE_M (CACHE_L1_CACHE_FREEZE_MODE_V << CACHE_L1_CACHE_FREEZE_MODE_S) #define CACHE_L1_CACHE_FREEZE_MODE_V 0x00000001U #define CACHE_L1_CACHE_FREEZE_MODE_S 17 /** CACHE_L1_CACHE_FREEZE_DONE : RO; bitpos: [18]; default: 0; - * The bit is used to indicate whether freeze operation on L1-Cache is finished or - * not. 0: not finished. 1: finished. + * Represents whether the freeze operation in L1 cache is finished. + * 0: Not finished + * 1: Finished */ #define CACHE_L1_CACHE_FREEZE_DONE (BIT(18)) #define CACHE_L1_CACHE_FREEZE_DONE_M (CACHE_L1_CACHE_FREEZE_DONE_V << CACHE_L1_CACHE_FREEZE_DONE_S) @@ -675,80 +120,23 @@ extern "C" { #define CACHE_L1_CACHE_FREEZE_DONE_S 18 /** CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG register - * Cache data memory access configure register + * Cache data memory access configuration register */ #define CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x2c) -/** CACHE_L1_ICACHE0_DATA_MEM_RD_EN : HRO; bitpos: [0]; default: 0; - * The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: - * enable. - */ -#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN (BIT(0)) -#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_M (CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S) -#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V 0x00000001U -#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S 0 -/** CACHE_L1_ICACHE0_DATA_MEM_WR_EN : HRO; bitpos: [1]; default: 0; - * The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, - * 1: enable. - */ -#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN (BIT(1)) -#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_M (CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S) -#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V 0x00000001U -#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S 1 -/** CACHE_L1_ICACHE1_DATA_MEM_RD_EN : HRO; bitpos: [4]; default: 0; - * The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: - * enable. - */ -#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN (BIT(4)) -#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_M (CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S) -#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V 0x00000001U -#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S 4 -/** CACHE_L1_ICACHE1_DATA_MEM_WR_EN : HRO; bitpos: [5]; default: 0; - * The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, - * 1: enable. - */ -#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN (BIT(5)) -#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_M (CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S) -#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V 0x00000001U -#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S 5 -/** CACHE_L1_ICACHE2_DATA_MEM_RD_EN : HRO; bitpos: [8]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN (BIT(8)) -#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_M (CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S) -#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V 0x00000001U -#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S 8 -/** CACHE_L1_ICACHE2_DATA_MEM_WR_EN : HRO; bitpos: [9]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN (BIT(9)) -#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_M (CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S) -#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V 0x00000001U -#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S 9 -/** CACHE_L1_ICACHE3_DATA_MEM_RD_EN : HRO; bitpos: [12]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN (BIT(12)) -#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_M (CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S) -#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V 0x00000001U -#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S 12 -/** CACHE_L1_ICACHE3_DATA_MEM_WR_EN : HRO; bitpos: [13]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN (BIT(13)) -#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_M (CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S) -#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V 0x00000001U -#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S 13 /** CACHE_L1_CACHE_DATA_MEM_RD_EN : R/W; bitpos: [16]; default: 0; - * The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: - * enable. + * Configures whether to enable the configuration bus to read the L1 cache data memory. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_DATA_MEM_RD_EN (BIT(16)) #define CACHE_L1_CACHE_DATA_MEM_RD_EN_M (CACHE_L1_CACHE_DATA_MEM_RD_EN_V << CACHE_L1_CACHE_DATA_MEM_RD_EN_S) #define CACHE_L1_CACHE_DATA_MEM_RD_EN_V 0x00000001U #define CACHE_L1_CACHE_DATA_MEM_RD_EN_S 16 /** CACHE_L1_CACHE_DATA_MEM_WR_EN : R/W; bitpos: [17]; default: 0; - * The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: - * enable. + * Configures whether to enable the configuration bus to write the L1 cache data + * memory. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_DATA_MEM_WR_EN (BIT(17)) #define CACHE_L1_CACHE_DATA_MEM_WR_EN_M (CACHE_L1_CACHE_DATA_MEM_WR_EN_V << CACHE_L1_CACHE_DATA_MEM_WR_EN_S) @@ -756,445 +144,94 @@ extern "C" { #define CACHE_L1_CACHE_DATA_MEM_WR_EN_S 17 /** CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG register - * Cache tag memory access configure register + * Cache tag memory access configuration register */ #define CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x30) -/** CACHE_L1_ICACHE0_TAG_MEM_RD_EN : HRO; bitpos: [0]; default: 0; - * The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: - * enable. - */ -#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN (BIT(0)) -#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_M (CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S) -#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V 0x00000001U -#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S 0 -/** CACHE_L1_ICACHE0_TAG_MEM_WR_EN : HRO; bitpos: [1]; default: 0; - * The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: - * enable. - */ -#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN (BIT(1)) -#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_M (CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S) -#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V 0x00000001U -#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S 1 -/** CACHE_L1_ICACHE1_TAG_MEM_RD_EN : HRO; bitpos: [4]; default: 0; - * The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: - * enable. - */ -#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN (BIT(4)) -#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_M (CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S) -#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V 0x00000001U -#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S 4 -/** CACHE_L1_ICACHE1_TAG_MEM_WR_EN : HRO; bitpos: [5]; default: 0; - * The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: - * enable. - */ -#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN (BIT(5)) -#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_M (CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S) -#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V 0x00000001U -#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S 5 -/** CACHE_L1_ICACHE2_TAG_MEM_RD_EN : HRO; bitpos: [8]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN (BIT(8)) -#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_M (CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S) -#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V 0x00000001U -#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S 8 -/** CACHE_L1_ICACHE2_TAG_MEM_WR_EN : HRO; bitpos: [9]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN (BIT(9)) -#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_M (CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S) -#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V 0x00000001U -#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S 9 -/** CACHE_L1_ICACHE3_TAG_MEM_RD_EN : HRO; bitpos: [12]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN (BIT(12)) -#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_M (CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S) -#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V 0x00000001U -#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S 12 -/** CACHE_L1_ICACHE3_TAG_MEM_WR_EN : HRO; bitpos: [13]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN (BIT(13)) -#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_M (CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S) -#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V 0x00000001U -#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S 13 /** CACHE_L1_CACHE_TAG_MEM_RD_EN : R/W; bitpos: [16]; default: 0; - * The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: - * enable. + * Configures whether to enable the configuration bus to read the L1 cache tag memory. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_TAG_MEM_RD_EN (BIT(16)) #define CACHE_L1_CACHE_TAG_MEM_RD_EN_M (CACHE_L1_CACHE_TAG_MEM_RD_EN_V << CACHE_L1_CACHE_TAG_MEM_RD_EN_S) #define CACHE_L1_CACHE_TAG_MEM_RD_EN_V 0x00000001U #define CACHE_L1_CACHE_TAG_MEM_RD_EN_S 16 /** CACHE_L1_CACHE_TAG_MEM_WR_EN : R/W; bitpos: [17]; default: 0; - * The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1: - * enable. + * Configures whether to enable the configuration bus to write the L1 cache tag memory. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_TAG_MEM_WR_EN (BIT(17)) #define CACHE_L1_CACHE_TAG_MEM_WR_EN_M (CACHE_L1_CACHE_TAG_MEM_WR_EN_V << CACHE_L1_CACHE_TAG_MEM_WR_EN_S) #define CACHE_L1_CACHE_TAG_MEM_WR_EN_V 0x00000001U #define CACHE_L1_CACHE_TAG_MEM_WR_EN_S 17 -/** CACHE_L1_ICACHE0_PRELOCK_CONF_REG register - * L1 instruction Cache 0 prelock configure register - */ -#define CACHE_L1_ICACHE0_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x34) -/** CACHE_L1_ICACHE0_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-ICache0. - */ -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN (BIT(0)) -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_M (CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S) -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V 0x00000001U -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S 0 -/** CACHE_L1_ICACHE0_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-ICache0. - */ -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN (BIT(1)) -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_M (CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S) -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V 0x00000001U -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S 1 -/** CACHE_L1_ICACHE0_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 icache0 prelock. - */ -#define CACHE_L1_ICACHE0_PRELOCK_RGID 0x0000000FU -#define CACHE_L1_ICACHE0_PRELOCK_RGID_M (CACHE_L1_ICACHE0_PRELOCK_RGID_V << CACHE_L1_ICACHE0_PRELOCK_RGID_S) -#define CACHE_L1_ICACHE0_PRELOCK_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE0_PRELOCK_RGID_S 2 - -/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG register - * L1 instruction Cache 0 prelock section0 address configure register - */ -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x38) -/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG - */ -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_M (CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S) -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S 0 - -/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG register - * L1 instruction Cache 0 prelock section1 address configure register - */ -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x3c) -/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG - */ -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_M (CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S) -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S 0 - -/** CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG register - * L1 instruction Cache 0 prelock section size configure register - */ -#define CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x40) -/** CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG - */ -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_M (CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S) -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S 0 -/** CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG - */ -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_M (CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S) -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S 16 - -/** CACHE_L1_ICACHE1_PRELOCK_CONF_REG register - * L1 instruction Cache 1 prelock configure register - */ -#define CACHE_L1_ICACHE1_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x44) -/** CACHE_L1_ICACHE1_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-ICache1. - */ -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN (BIT(0)) -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_M (CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S) -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V 0x00000001U -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S 0 -/** CACHE_L1_ICACHE1_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-ICache1. - */ -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN (BIT(1)) -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_M (CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S) -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V 0x00000001U -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S 1 -/** CACHE_L1_ICACHE1_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 icache1 prelock. - */ -#define CACHE_L1_ICACHE1_PRELOCK_RGID 0x0000000FU -#define CACHE_L1_ICACHE1_PRELOCK_RGID_M (CACHE_L1_ICACHE1_PRELOCK_RGID_V << CACHE_L1_ICACHE1_PRELOCK_RGID_S) -#define CACHE_L1_ICACHE1_PRELOCK_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE1_PRELOCK_RGID_S 2 - -/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG register - * L1 instruction Cache 1 prelock section0 address configure register - */ -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x48) -/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG - */ -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_M (CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S) -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S 0 - -/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG register - * L1 instruction Cache 1 prelock section1 address configure register - */ -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x4c) -/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG - */ -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_M (CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S) -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S 0 - -/** CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG register - * L1 instruction Cache 1 prelock section size configure register - */ -#define CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x50) -/** CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG - */ -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_M (CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S) -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S 0 -/** CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG - */ -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_M (CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S) -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S 16 - -/** CACHE_L1_ICACHE2_PRELOCK_CONF_REG register - * L1 instruction Cache 2 prelock configure register - */ -#define CACHE_L1_ICACHE2_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x54) -/** CACHE_L1_ICACHE2_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-ICache2. - */ -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN (BIT(0)) -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_M (CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S) -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V 0x00000001U -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S 0 -/** CACHE_L1_ICACHE2_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-ICache2. - */ -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN (BIT(1)) -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_M (CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S) -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V 0x00000001U -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S 1 -/** CACHE_L1_ICACHE2_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 icache2 prelock. - */ -#define CACHE_L1_ICACHE2_PRELOCK_RGID 0x0000000FU -#define CACHE_L1_ICACHE2_PRELOCK_RGID_M (CACHE_L1_ICACHE2_PRELOCK_RGID_V << CACHE_L1_ICACHE2_PRELOCK_RGID_S) -#define CACHE_L1_ICACHE2_PRELOCK_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE2_PRELOCK_RGID_S 2 - -/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG register - * L1 instruction Cache 2 prelock section0 address configure register - */ -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x58) -/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG - */ -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_M (CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S) -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S 0 - -/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG register - * L1 instruction Cache 2 prelock section1 address configure register - */ -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x5c) -/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG - */ -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_M (CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S) -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S 0 - -/** CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG register - * L1 instruction Cache 2 prelock section size configure register - */ -#define CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x60) -/** CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG - */ -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_M (CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S) -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S 0 -/** CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG - */ -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_M (CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S) -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S 16 - -/** CACHE_L1_ICACHE3_PRELOCK_CONF_REG register - * L1 instruction Cache 3 prelock configure register - */ -#define CACHE_L1_ICACHE3_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x64) -/** CACHE_L1_ICACHE3_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-ICache3. - */ -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN (BIT(0)) -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_M (CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S) -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V 0x00000001U -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S 0 -/** CACHE_L1_ICACHE3_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-ICache3. - */ -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN (BIT(1)) -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_M (CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S) -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V 0x00000001U -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S 1 -/** CACHE_L1_ICACHE3_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 icache3 prelock. - */ -#define CACHE_L1_ICACHE3_PRELOCK_RGID 0x0000000FU -#define CACHE_L1_ICACHE3_PRELOCK_RGID_M (CACHE_L1_ICACHE3_PRELOCK_RGID_V << CACHE_L1_ICACHE3_PRELOCK_RGID_S) -#define CACHE_L1_ICACHE3_PRELOCK_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE3_PRELOCK_RGID_S 2 - -/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG register - * L1 instruction Cache 3 prelock section0 address configure register - */ -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x68) -/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG - */ -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_M (CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S) -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S 0 - -/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG register - * L1 instruction Cache 3 prelock section1 address configure register - */ -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x6c) -/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG - */ -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_M (CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S) -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S 0 - -/** CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG register - * L1 instruction Cache 3 prelock section size configure register - */ -#define CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x70) -/** CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG - */ -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_M (CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S) -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S 0 -/** CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG - */ -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_M (CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S) -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S 16 - /** CACHE_L1_CACHE_PRELOCK_CONF_REG register * L1 Cache prelock configure register */ #define CACHE_L1_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x74) /** CACHE_L1_CACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-Cache. + * Configures whether to enable the prelocking function in Section 0 of the L1 cache. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_PRELOCK_SCT0_EN (BIT(0)) #define CACHE_L1_CACHE_PRELOCK_SCT0_EN_M (CACHE_L1_CACHE_PRELOCK_SCT0_EN_V << CACHE_L1_CACHE_PRELOCK_SCT0_EN_S) #define CACHE_L1_CACHE_PRELOCK_SCT0_EN_V 0x00000001U #define CACHE_L1_CACHE_PRELOCK_SCT0_EN_S 0 /** CACHE_L1_CACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-Cache. + * Configures whether to enable the prelocking function in Section 1 of the L1 cache. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_PRELOCK_SCT1_EN (BIT(1)) #define CACHE_L1_CACHE_PRELOCK_SCT1_EN_M (CACHE_L1_CACHE_PRELOCK_SCT1_EN_V << CACHE_L1_CACHE_PRELOCK_SCT1_EN_S) #define CACHE_L1_CACHE_PRELOCK_SCT1_EN_V 0x00000001U #define CACHE_L1_CACHE_PRELOCK_SCT1_EN_S 1 -/** CACHE_L1_CACHE_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 cache prelock. - */ -#define CACHE_L1_CACHE_PRELOCK_RGID 0x0000000FU -#define CACHE_L1_CACHE_PRELOCK_RGID_M (CACHE_L1_CACHE_PRELOCK_RGID_V << CACHE_L1_CACHE_PRELOCK_RGID_S) -#define CACHE_L1_CACHE_PRELOCK_RGID_V 0x0000000FU -#define CACHE_L1_CACHE_PRELOCK_RGID_S 2 /** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG register - * L1 Cache prelock section0 address configure register + * L1 cache prelocking Section 0 address configuration register */ #define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x78) /** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_SIZE_REG + * Configures the starting virtual address of Section 0 for prelocking in the L1 + * cache. This field should be configured together with + * CACHE_L1_CACHE_PRELOCK_SCT0_SIZE. */ #define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFFU #define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_M (CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S) #define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU #define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S 0 -/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG register - * L1 Cache prelock section1 address configure register +/** CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_REG register + * L1 cache prelocking Section 1 address configuration register */ -#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x7c) +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x7c) /** CACHE_L1_CACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_SIZE_REG + * Configures the starting virtual address of Section 1 for prelocking in the L1 + * cache. This field should be configured together with + * CACHE_L1_CACHE_PRELOCK_SCT1_SIZE. */ #define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFFU #define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_M (CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S) #define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU #define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S 0 -/** CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG register - * L1 Cache prelock section size configure register +/** CACHE_L1_CACHE_PRELOCK_SCT_SIZE_REG register + * L1 cache prelocking section size configuration register */ -#define CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x80) +#define CACHE_L1_CACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x80) /** CACHE_L1_CACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG + * Configures the size of Section 0 for prelocking in the L1 cache. This field should + * be configured together with CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG. */ #define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE 0x00003FFFU #define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_M (CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S) #define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V 0x00003FFFU #define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S 0 /** CACHE_L1_CACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG + * Configures the size of Section 1 for prelocking in the L1 cache. This field should + * be configured together with CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_REG. */ #define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE 0x00003FFFU #define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_M (CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S) @@ -1202,48 +239,48 @@ extern "C" { #define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S 16 /** CACHE_LOCK_CTRL_REG register - * Lock-class (manual lock) operation control register + * Locking operation control register */ #define CACHE_LOCK_CTRL_REG (DR_REG_CACHE_BASE + 0x84) /** CACHE_LOCK_ENA : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable lock operation. It will be cleared by hardware after lock - * operation done + * Configures whether to enable lock operation. It will be cleared by hardware after + * the lock operation is done. + * 0: Disable + * 1: Enable */ #define CACHE_LOCK_ENA (BIT(0)) #define CACHE_LOCK_ENA_M (CACHE_LOCK_ENA_V << CACHE_LOCK_ENA_S) #define CACHE_LOCK_ENA_V 0x00000001U #define CACHE_LOCK_ENA_S 0 /** CACHE_UNLOCK_ENA : R/W/SC; bitpos: [1]; default: 0; - * The bit is used to enable unlock operation. It will be cleared by hardware after - * unlock operation done + * Configures whether to enable unlock operation. It will be cleared by hardware after + * the unlock operation is done. + * 0: Disable + * 1: Enable */ #define CACHE_UNLOCK_ENA (BIT(1)) #define CACHE_UNLOCK_ENA_M (CACHE_UNLOCK_ENA_V << CACHE_UNLOCK_ENA_S) #define CACHE_UNLOCK_ENA_V 0x00000001U #define CACHE_UNLOCK_ENA_S 1 /** CACHE_LOCK_DONE : RO; bitpos: [2]; default: 1; - * The bit is used to indicate whether unlock/lock operation is finished or not. 0: - * not finished. 1: finished. + * Represents whether the unlock or the lock operation is finished. + * 0: Not finished + * 1: Finished */ #define CACHE_LOCK_DONE (BIT(2)) #define CACHE_LOCK_DONE_M (CACHE_LOCK_DONE_V << CACHE_LOCK_DONE_S) #define CACHE_LOCK_DONE_V 0x00000001U #define CACHE_LOCK_DONE_S 2 -/** CACHE_LOCK_RGID : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of cache lock/unlock. - */ -#define CACHE_LOCK_RGID 0x0000000FU -#define CACHE_LOCK_RGID_M (CACHE_LOCK_RGID_V << CACHE_LOCK_RGID_S) -#define CACHE_LOCK_RGID_V 0x0000000FU -#define CACHE_LOCK_RGID_S 3 /** CACHE_LOCK_MAP_REG register - * Lock (manual lock) map configure register + * Locking map configuration register */ #define CACHE_LOCK_MAP_REG (DR_REG_CACHE_BASE + 0x88) /** CACHE_LOCK_MAP : R/W; bitpos: [5:0]; default: 0; - * Those bits are used to indicate which caches in the two-level cache structure will - * apply this lock/unlock operation. [4]: L1-Cache + * Configures which level of cache in the two-level cache structure to perform the + * locking or the unlocking operation. + * Bit 4: Write 1 to this bit to select the L1 cache + * Other bits: reserved */ #define CACHE_LOCK_MAP 0x0000003FU #define CACHE_LOCK_MAP_M (CACHE_LOCK_MAP_V << CACHE_LOCK_MAP_S) @@ -1251,12 +288,12 @@ extern "C" { #define CACHE_LOCK_MAP_S 0 /** CACHE_LOCK_ADDR_REG register - * Lock (manual lock) address configure register + * Locking address configuration register */ #define CACHE_LOCK_ADDR_REG (DR_REG_CACHE_BASE + 0x8c) /** CACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the lock/unlock operation, - * which should be used together with CACHE_LOCK_SIZE_REG + * Configures the starting virtual address for the locking or unlocking operation. + * This field should be configured together with CACHE_LOCK_SIZE_REG. */ #define CACHE_LOCK_ADDR 0xFFFFFFFFU #define CACHE_LOCK_ADDR_M (CACHE_LOCK_ADDR_V << CACHE_LOCK_ADDR_S) @@ -1264,12 +301,12 @@ extern "C" { #define CACHE_LOCK_ADDR_S 0 /** CACHE_LOCK_SIZE_REG register - * Lock (manual lock) size configure register + * Locking size configuration register */ #define CACHE_LOCK_SIZE_REG (DR_REG_CACHE_BASE + 0x90) /** CACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0; - * Those bits are used to configure the size of the lock/unlock operation, which - * should be used together with CACHE_LOCK_ADDR_REG + * Configures the size for the locking or unlocking operation. This field should be + * configured together with CACHE_LOCK_ADDR_REG. */ #define CACHE_LOCK_SIZE 0x0000FFFFU #define CACHE_LOCK_SIZE_M (CACHE_LOCK_SIZE_V << CACHE_LOCK_SIZE_S) @@ -1277,73 +314,68 @@ extern "C" { #define CACHE_LOCK_SIZE_S 0 /** CACHE_SYNC_CTRL_REG register - * Sync-class operation control register + * Sync operation control register */ #define CACHE_SYNC_CTRL_REG (DR_REG_CACHE_BASE + 0x94) -/** CACHE_INVALIDATE_ENA : R/W/SC; bitpos: [0]; default: 1; - * The bit is used to enable invalidate operation. It will be cleared by hardware - * after invalidate operation done. Note that this bit and the other sync-bits - * (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that - * is, those bits can not be set to 1 at the same time. +/** CACHE_INVALIDATE_ENA : RW; bitpos: [0]; default: 1; + * Configures whether to enable the invalidatation operation. Hardware will clear it + * once the operation has finished. + * 0: Disable + * 1: Enable */ #define CACHE_INVALIDATE_ENA (BIT(0)) #define CACHE_INVALIDATE_ENA_M (CACHE_INVALIDATE_ENA_V << CACHE_INVALIDATE_ENA_S) #define CACHE_INVALIDATE_ENA_V 0x00000001U #define CACHE_INVALIDATE_ENA_S 0 /** CACHE_CLEAN_ENA : R/W/SC; bitpos: [1]; default: 0; - * The bit is used to enable clean operation. It will be cleared by hardware after - * clean operation done. Note that this bit and the other sync-bits (invalidate_ena, - * writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those - * bits can not be set to 1 at the same time. + * Configures whether to enable the clean operation. Hardware will clear it once the + * operation has finished. + * 0: Disable + * 1: Enable */ #define CACHE_CLEAN_ENA (BIT(1)) #define CACHE_CLEAN_ENA_M (CACHE_CLEAN_ENA_V << CACHE_CLEAN_ENA_S) #define CACHE_CLEAN_ENA_V 0x00000001U #define CACHE_CLEAN_ENA_S 1 /** CACHE_WRITEBACK_ENA : R/W/SC; bitpos: [2]; default: 0; - * The bit is used to enable writeback operation. It will be cleared by hardware after - * writeback operation done. Note that this bit and the other sync-bits - * (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that - * is, those bits can not be set to 1 at the same time. + * Configures whether to enable the write-back operation. Hardware will clear it once + * the operation has finished. + * 0: Disable + * 1: Enable */ #define CACHE_WRITEBACK_ENA (BIT(2)) #define CACHE_WRITEBACK_ENA_M (CACHE_WRITEBACK_ENA_V << CACHE_WRITEBACK_ENA_S) #define CACHE_WRITEBACK_ENA_V 0x00000001U #define CACHE_WRITEBACK_ENA_S 2 /** CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC; bitpos: [3]; default: 0; - * The bit is used to enable writeback-invalidate operation. It will be cleared by - * hardware after writeback-invalidate operation done. Note that this bit and the - * other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, - * that is, those bits can not be set to 1 at the same time. + * Configures whether to enable the write-back invalidation operation. Hardware will + * clear it once the operation has finished. + * 0: Disable + * 1: Enable */ #define CACHE_WRITEBACK_INVALIDATE_ENA (BIT(3)) #define CACHE_WRITEBACK_INVALIDATE_ENA_M (CACHE_WRITEBACK_INVALIDATE_ENA_V << CACHE_WRITEBACK_INVALIDATE_ENA_S) #define CACHE_WRITEBACK_INVALIDATE_ENA_V 0x00000001U #define CACHE_WRITEBACK_INVALIDATE_ENA_S 3 /** CACHE_SYNC_DONE : RO; bitpos: [4]; default: 0; - * The bit is used to indicate whether sync operation (invalidate, clean, writeback, - * writeback_invalidate) is finished or not. 0: not finished. 1: finished. + * Represents whether the synchronization operation is finished. + * 0: Not finished + * 1: Finished */ #define CACHE_SYNC_DONE (BIT(4)) #define CACHE_SYNC_DONE_M (CACHE_SYNC_DONE_V << CACHE_SYNC_DONE_S) #define CACHE_SYNC_DONE_V 0x00000001U #define CACHE_SYNC_DONE_S 4 -/** CACHE_SYNC_RGID : HRO; bitpos: [8:5]; default: 0; - * The bit is used to set the gid of cache sync operation (invalidate, clean, - * writeback, writeback_invalidate) - */ -#define CACHE_SYNC_RGID 0x0000000FU -#define CACHE_SYNC_RGID_M (CACHE_SYNC_RGID_V << CACHE_SYNC_RGID_S) -#define CACHE_SYNC_RGID_V 0x0000000FU -#define CACHE_SYNC_RGID_S 5 /** CACHE_SYNC_MAP_REG register - * Sync map configure register + * Sync map configuration register */ #define CACHE_SYNC_MAP_REG (DR_REG_CACHE_BASE + 0x98) /** CACHE_SYNC_MAP : R/W; bitpos: [5:0]; default: 63; - * Those bits are used to indicate which caches in the two-level cache structure will - * apply the sync operation. [4]: L1-Cache + * Configures which caches in the two-level cache structure will apply the sync + * operation. + * Bit 4: Write 1 to this bit to select the L1 cache + * Other bits: Reserved */ #define CACHE_SYNC_MAP 0x0000003FU #define CACHE_SYNC_MAP_M (CACHE_SYNC_MAP_V << CACHE_SYNC_MAP_S) @@ -1351,12 +383,12 @@ extern "C" { #define CACHE_SYNC_MAP_S 0 /** CACHE_SYNC_ADDR_REG register - * Sync address configure register + * Sync address configuration register */ #define CACHE_SYNC_ADDR_REG (DR_REG_CACHE_BASE + 0x9c) /** CACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the sync operation, which - * should be used together with CACHE_SYNC_SIZE_REG + * Configures the starting virtual address for the synchronization operation. This + * field should be configured together with CACHE_SYNC_SIZE_REG. */ #define CACHE_SYNC_ADDR 0xFFFFFFFFU #define CACHE_SYNC_ADDR_M (CACHE_SYNC_ADDR_V << CACHE_SYNC_ADDR_S) @@ -1364,862 +396,148 @@ extern "C" { #define CACHE_SYNC_ADDR_S 0 /** CACHE_SYNC_SIZE_REG register - * Sync size configure register + * Sync size configuration register */ #define CACHE_SYNC_SIZE_REG (DR_REG_CACHE_BASE + 0xa0) /** CACHE_SYNC_SIZE : R/W; bitpos: [24:0]; default: 0; - * Those bits are used to configure the size of the sync operation, which should be - * used together with CACHE_SYNC_ADDR_REG + * Configures the size for the synchronization operation. This field should be + * configured together with CACHE_SYNC_ADDR_REG. */ #define CACHE_SYNC_SIZE 0x01FFFFFFU #define CACHE_SYNC_SIZE_M (CACHE_SYNC_SIZE_V << CACHE_SYNC_SIZE_S) #define CACHE_SYNC_SIZE_V 0x01FFFFFFU #define CACHE_SYNC_SIZE_S 0 -/** CACHE_L1_ICACHE0_PRELOAD_CTRL_REG register - * L1 instruction Cache 0 preload-operation control register - */ -#define CACHE_L1_ICACHE0_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xa4) -/** CACHE_L1_ICACHE0_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-ICache0. It will be cleared by - * hardware automatically after preload operation is done. - */ -#define CACHE_L1_ICACHE0_PRELOAD_ENA (BIT(0)) -#define CACHE_L1_ICACHE0_PRELOAD_ENA_M (CACHE_L1_ICACHE0_PRELOAD_ENA_V << CACHE_L1_ICACHE0_PRELOAD_ENA_S) -#define CACHE_L1_ICACHE0_PRELOAD_ENA_V 0x00000001U -#define CACHE_L1_ICACHE0_PRELOAD_ENA_S 0 -/** CACHE_L1_ICACHE0_PRELOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ -#define CACHE_L1_ICACHE0_PRELOAD_DONE (BIT(1)) -#define CACHE_L1_ICACHE0_PRELOAD_DONE_M (CACHE_L1_ICACHE0_PRELOAD_DONE_V << CACHE_L1_ICACHE0_PRELOAD_DONE_S) -#define CACHE_L1_ICACHE0_PRELOAD_DONE_V 0x00000001U -#define CACHE_L1_ICACHE0_PRELOAD_DONE_S 1 -/** CACHE_L1_ICACHE0_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ -#define CACHE_L1_ICACHE0_PRELOAD_ORDER (BIT(2)) -#define CACHE_L1_ICACHE0_PRELOAD_ORDER_M (CACHE_L1_ICACHE0_PRELOAD_ORDER_V << CACHE_L1_ICACHE0_PRELOAD_ORDER_S) -#define CACHE_L1_ICACHE0_PRELOAD_ORDER_V 0x00000001U -#define CACHE_L1_ICACHE0_PRELOAD_ORDER_S 2 -/** CACHE_L1_ICACHE0_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 icache0 preload. - */ -#define CACHE_L1_ICACHE0_PRELOAD_RGID 0x0000000FU -#define CACHE_L1_ICACHE0_PRELOAD_RGID_M (CACHE_L1_ICACHE0_PRELOAD_RGID_V << CACHE_L1_ICACHE0_PRELOAD_RGID_S) -#define CACHE_L1_ICACHE0_PRELOAD_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE0_PRELOAD_RGID_S 3 - -/** CACHE_L1_ICACHE0_PRELOAD_ADDR_REG register - * L1 instruction Cache 0 preload address configure register - */ -#define CACHE_L1_ICACHE0_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xa8) -/** CACHE_L1_ICACHE0_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L1-ICache0, which - * should be used together with L1_ICACHE0_PRELOAD_SIZE_REG - */ -#define CACHE_L1_ICACHE0_PRELOAD_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_PRELOAD_ADDR_M (CACHE_L1_ICACHE0_PRELOAD_ADDR_V << CACHE_L1_ICACHE0_PRELOAD_ADDR_S) -#define CACHE_L1_ICACHE0_PRELOAD_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_PRELOAD_ADDR_S 0 - -/** CACHE_L1_ICACHE0_PRELOAD_SIZE_REG register - * L1 instruction Cache 0 preload size configure register - */ -#define CACHE_L1_ICACHE0_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xac) -/** CACHE_L1_ICACHE0_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG - */ -#define CACHE_L1_ICACHE0_PRELOAD_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE0_PRELOAD_SIZE_M (CACHE_L1_ICACHE0_PRELOAD_SIZE_V << CACHE_L1_ICACHE0_PRELOAD_SIZE_S) -#define CACHE_L1_ICACHE0_PRELOAD_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE0_PRELOAD_SIZE_S 0 - -/** CACHE_L1_ICACHE1_PRELOAD_CTRL_REG register - * L1 instruction Cache 1 preload-operation control register - */ -#define CACHE_L1_ICACHE1_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xb0) -/** CACHE_L1_ICACHE1_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-ICache1. It will be cleared by - * hardware automatically after preload operation is done. - */ -#define CACHE_L1_ICACHE1_PRELOAD_ENA (BIT(0)) -#define CACHE_L1_ICACHE1_PRELOAD_ENA_M (CACHE_L1_ICACHE1_PRELOAD_ENA_V << CACHE_L1_ICACHE1_PRELOAD_ENA_S) -#define CACHE_L1_ICACHE1_PRELOAD_ENA_V 0x00000001U -#define CACHE_L1_ICACHE1_PRELOAD_ENA_S 0 -/** CACHE_L1_ICACHE1_PRELOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ -#define CACHE_L1_ICACHE1_PRELOAD_DONE (BIT(1)) -#define CACHE_L1_ICACHE1_PRELOAD_DONE_M (CACHE_L1_ICACHE1_PRELOAD_DONE_V << CACHE_L1_ICACHE1_PRELOAD_DONE_S) -#define CACHE_L1_ICACHE1_PRELOAD_DONE_V 0x00000001U -#define CACHE_L1_ICACHE1_PRELOAD_DONE_S 1 -/** CACHE_L1_ICACHE1_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ -#define CACHE_L1_ICACHE1_PRELOAD_ORDER (BIT(2)) -#define CACHE_L1_ICACHE1_PRELOAD_ORDER_M (CACHE_L1_ICACHE1_PRELOAD_ORDER_V << CACHE_L1_ICACHE1_PRELOAD_ORDER_S) -#define CACHE_L1_ICACHE1_PRELOAD_ORDER_V 0x00000001U -#define CACHE_L1_ICACHE1_PRELOAD_ORDER_S 2 -/** CACHE_L1_ICACHE1_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 icache1 preload. - */ -#define CACHE_L1_ICACHE1_PRELOAD_RGID 0x0000000FU -#define CACHE_L1_ICACHE1_PRELOAD_RGID_M (CACHE_L1_ICACHE1_PRELOAD_RGID_V << CACHE_L1_ICACHE1_PRELOAD_RGID_S) -#define CACHE_L1_ICACHE1_PRELOAD_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE1_PRELOAD_RGID_S 3 - -/** CACHE_L1_ICACHE1_PRELOAD_ADDR_REG register - * L1 instruction Cache 1 preload address configure register - */ -#define CACHE_L1_ICACHE1_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xb4) -/** CACHE_L1_ICACHE1_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L1-ICache1, which - * should be used together with L1_ICACHE1_PRELOAD_SIZE_REG - */ -#define CACHE_L1_ICACHE1_PRELOAD_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_PRELOAD_ADDR_M (CACHE_L1_ICACHE1_PRELOAD_ADDR_V << CACHE_L1_ICACHE1_PRELOAD_ADDR_S) -#define CACHE_L1_ICACHE1_PRELOAD_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_PRELOAD_ADDR_S 0 - -/** CACHE_L1_ICACHE1_PRELOAD_SIZE_REG register - * L1 instruction Cache 1 preload size configure register - */ -#define CACHE_L1_ICACHE1_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xb8) -/** CACHE_L1_ICACHE1_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG - */ -#define CACHE_L1_ICACHE1_PRELOAD_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE1_PRELOAD_SIZE_M (CACHE_L1_ICACHE1_PRELOAD_SIZE_V << CACHE_L1_ICACHE1_PRELOAD_SIZE_S) -#define CACHE_L1_ICACHE1_PRELOAD_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE1_PRELOAD_SIZE_S 0 - -/** CACHE_L1_ICACHE2_PRELOAD_CTRL_REG register - * L1 instruction Cache 2 preload-operation control register - */ -#define CACHE_L1_ICACHE2_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xbc) -/** CACHE_L1_ICACHE2_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-ICache2. It will be cleared by - * hardware automatically after preload operation is done. - */ -#define CACHE_L1_ICACHE2_PRELOAD_ENA (BIT(0)) -#define CACHE_L1_ICACHE2_PRELOAD_ENA_M (CACHE_L1_ICACHE2_PRELOAD_ENA_V << CACHE_L1_ICACHE2_PRELOAD_ENA_S) -#define CACHE_L1_ICACHE2_PRELOAD_ENA_V 0x00000001U -#define CACHE_L1_ICACHE2_PRELOAD_ENA_S 0 -/** CACHE_L1_ICACHE2_PRELOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ -#define CACHE_L1_ICACHE2_PRELOAD_DONE (BIT(1)) -#define CACHE_L1_ICACHE2_PRELOAD_DONE_M (CACHE_L1_ICACHE2_PRELOAD_DONE_V << CACHE_L1_ICACHE2_PRELOAD_DONE_S) -#define CACHE_L1_ICACHE2_PRELOAD_DONE_V 0x00000001U -#define CACHE_L1_ICACHE2_PRELOAD_DONE_S 1 -/** CACHE_L1_ICACHE2_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ -#define CACHE_L1_ICACHE2_PRELOAD_ORDER (BIT(2)) -#define CACHE_L1_ICACHE2_PRELOAD_ORDER_M (CACHE_L1_ICACHE2_PRELOAD_ORDER_V << CACHE_L1_ICACHE2_PRELOAD_ORDER_S) -#define CACHE_L1_ICACHE2_PRELOAD_ORDER_V 0x00000001U -#define CACHE_L1_ICACHE2_PRELOAD_ORDER_S 2 -/** CACHE_L1_ICACHE2_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 icache2 preload. - */ -#define CACHE_L1_ICACHE2_PRELOAD_RGID 0x0000000FU -#define CACHE_L1_ICACHE2_PRELOAD_RGID_M (CACHE_L1_ICACHE2_PRELOAD_RGID_V << CACHE_L1_ICACHE2_PRELOAD_RGID_S) -#define CACHE_L1_ICACHE2_PRELOAD_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE2_PRELOAD_RGID_S 3 - -/** CACHE_L1_ICACHE2_PRELOAD_ADDR_REG register - * L1 instruction Cache 2 preload address configure register - */ -#define CACHE_L1_ICACHE2_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xc0) -/** CACHE_L1_ICACHE2_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L1-ICache2, which - * should be used together with L1_ICACHE2_PRELOAD_SIZE_REG - */ -#define CACHE_L1_ICACHE2_PRELOAD_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_PRELOAD_ADDR_M (CACHE_L1_ICACHE2_PRELOAD_ADDR_V << CACHE_L1_ICACHE2_PRELOAD_ADDR_S) -#define CACHE_L1_ICACHE2_PRELOAD_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_PRELOAD_ADDR_S 0 - -/** CACHE_L1_ICACHE2_PRELOAD_SIZE_REG register - * L1 instruction Cache 2 preload size configure register - */ -#define CACHE_L1_ICACHE2_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xc4) -/** CACHE_L1_ICACHE2_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG - */ -#define CACHE_L1_ICACHE2_PRELOAD_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE2_PRELOAD_SIZE_M (CACHE_L1_ICACHE2_PRELOAD_SIZE_V << CACHE_L1_ICACHE2_PRELOAD_SIZE_S) -#define CACHE_L1_ICACHE2_PRELOAD_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE2_PRELOAD_SIZE_S 0 - -/** CACHE_L1_ICACHE3_PRELOAD_CTRL_REG register - * L1 instruction Cache 3 preload-operation control register - */ -#define CACHE_L1_ICACHE3_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xc8) -/** CACHE_L1_ICACHE3_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-ICache3. It will be cleared by - * hardware automatically after preload operation is done. - */ -#define CACHE_L1_ICACHE3_PRELOAD_ENA (BIT(0)) -#define CACHE_L1_ICACHE3_PRELOAD_ENA_M (CACHE_L1_ICACHE3_PRELOAD_ENA_V << CACHE_L1_ICACHE3_PRELOAD_ENA_S) -#define CACHE_L1_ICACHE3_PRELOAD_ENA_V 0x00000001U -#define CACHE_L1_ICACHE3_PRELOAD_ENA_S 0 -/** CACHE_L1_ICACHE3_PRELOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ -#define CACHE_L1_ICACHE3_PRELOAD_DONE (BIT(1)) -#define CACHE_L1_ICACHE3_PRELOAD_DONE_M (CACHE_L1_ICACHE3_PRELOAD_DONE_V << CACHE_L1_ICACHE3_PRELOAD_DONE_S) -#define CACHE_L1_ICACHE3_PRELOAD_DONE_V 0x00000001U -#define CACHE_L1_ICACHE3_PRELOAD_DONE_S 1 -/** CACHE_L1_ICACHE3_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ -#define CACHE_L1_ICACHE3_PRELOAD_ORDER (BIT(2)) -#define CACHE_L1_ICACHE3_PRELOAD_ORDER_M (CACHE_L1_ICACHE3_PRELOAD_ORDER_V << CACHE_L1_ICACHE3_PRELOAD_ORDER_S) -#define CACHE_L1_ICACHE3_PRELOAD_ORDER_V 0x00000001U -#define CACHE_L1_ICACHE3_PRELOAD_ORDER_S 2 -/** CACHE_L1_ICACHE3_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 icache3 preload. - */ -#define CACHE_L1_ICACHE3_PRELOAD_RGID 0x0000000FU -#define CACHE_L1_ICACHE3_PRELOAD_RGID_M (CACHE_L1_ICACHE3_PRELOAD_RGID_V << CACHE_L1_ICACHE3_PRELOAD_RGID_S) -#define CACHE_L1_ICACHE3_PRELOAD_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE3_PRELOAD_RGID_S 3 - -/** CACHE_L1_ICACHE3_PRELOAD_ADDR_REG register - * L1 instruction Cache 3 preload address configure register - */ -#define CACHE_L1_ICACHE3_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xcc) -/** CACHE_L1_ICACHE3_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L1-ICache3, which - * should be used together with L1_ICACHE3_PRELOAD_SIZE_REG - */ -#define CACHE_L1_ICACHE3_PRELOAD_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_PRELOAD_ADDR_M (CACHE_L1_ICACHE3_PRELOAD_ADDR_V << CACHE_L1_ICACHE3_PRELOAD_ADDR_S) -#define CACHE_L1_ICACHE3_PRELOAD_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_PRELOAD_ADDR_S 0 - -/** CACHE_L1_ICACHE3_PRELOAD_SIZE_REG register - * L1 instruction Cache 3 preload size configure register - */ -#define CACHE_L1_ICACHE3_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xd0) -/** CACHE_L1_ICACHE3_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG - */ -#define CACHE_L1_ICACHE3_PRELOAD_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE3_PRELOAD_SIZE_M (CACHE_L1_ICACHE3_PRELOAD_SIZE_V << CACHE_L1_ICACHE3_PRELOAD_SIZE_S) -#define CACHE_L1_ICACHE3_PRELOAD_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE3_PRELOAD_SIZE_S 0 - /** CACHE_L1_CACHE_PRELOAD_CTRL_REG register - * L1 Cache preload-operation control register + * L1 cache preloading operation control register */ #define CACHE_L1_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xd4) /** CACHE_L1_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-Cache. It will be cleared by - * hardware automatically after preload operation is done. + * Configures whether to enable the preloading operation in the L1 cache. It will be + * cleared by hardware automatically after the preloading operation is done. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_PRELOAD_ENA (BIT(0)) #define CACHE_L1_CACHE_PRELOAD_ENA_M (CACHE_L1_CACHE_PRELOAD_ENA_V << CACHE_L1_CACHE_PRELOAD_ENA_S) #define CACHE_L1_CACHE_PRELOAD_ENA_V 0x00000001U #define CACHE_L1_CACHE_PRELOAD_ENA_S 0 /** CACHE_L1_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. + * Represents whether the preloading operation is finished. + * 0: Not finished + * 1: Finished */ #define CACHE_L1_CACHE_PRELOAD_DONE (BIT(1)) #define CACHE_L1_CACHE_PRELOAD_DONE_M (CACHE_L1_CACHE_PRELOAD_DONE_V << CACHE_L1_CACHE_PRELOAD_DONE_S) #define CACHE_L1_CACHE_PRELOAD_DONE_V 0x00000001U #define CACHE_L1_CACHE_PRELOAD_DONE_S 1 /** CACHE_L1_CACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. + * Configures the direction of the preloading operation. + * 0: Ascending + * 1: Descending */ #define CACHE_L1_CACHE_PRELOAD_ORDER (BIT(2)) #define CACHE_L1_CACHE_PRELOAD_ORDER_M (CACHE_L1_CACHE_PRELOAD_ORDER_V << CACHE_L1_CACHE_PRELOAD_ORDER_S) #define CACHE_L1_CACHE_PRELOAD_ORDER_V 0x00000001U #define CACHE_L1_CACHE_PRELOAD_ORDER_S 2 -/** CACHE_L1_CACHE_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 cache preload. - */ -#define CACHE_L1_CACHE_PRELOAD_RGID 0x0000000FU -#define CACHE_L1_CACHE_PRELOAD_RGID_M (CACHE_L1_CACHE_PRELOAD_RGID_V << CACHE_L1_CACHE_PRELOAD_RGID_S) -#define CACHE_L1_CACHE_PRELOAD_RGID_V 0x0000000FU -#define CACHE_L1_CACHE_PRELOAD_RGID_S 3 -/** CACHE_L1_DCACHE_PRELOAD_ADDR_REG register - * L1 Cache preload address configure register +/** CACHE_L1_CACHE_PRELOAD_ADDR_REG register + * L1 cache preloading address configuration register */ -#define CACHE_L1_DCACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xd8) +#define CACHE_L1_CACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xd8) /** CACHE_L1_CACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L1-Cache, which - * should be used together with L1_CACHE_PRELOAD_SIZE_REG + * Configures the starting virtual address for the preloading operation in the L1 + * cache. This field should be configured together with + * CACHE_L1_CACHE_PRELOAD_SIZE_REG. */ #define CACHE_L1_CACHE_PRELOAD_ADDR 0xFFFFFFFFU #define CACHE_L1_CACHE_PRELOAD_ADDR_M (CACHE_L1_CACHE_PRELOAD_ADDR_V << CACHE_L1_CACHE_PRELOAD_ADDR_S) #define CACHE_L1_CACHE_PRELOAD_ADDR_V 0xFFFFFFFFU #define CACHE_L1_CACHE_PRELOAD_ADDR_S 0 -/** CACHE_L1_DCACHE_PRELOAD_SIZE_REG register - * L1 Cache preload size configure register +/** CACHE_L1_CACHE_PRELOAD_SIZE_REG register + * L1 cache preloading size configuration register */ -#define CACHE_L1_DCACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xdc) +#define CACHE_L1_CACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xdc) /** CACHE_L1_CACHE_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG + * Configures the size of Section 0 for the preloading operation in the L1 cache. This + * field should be configured together with CACHE_L1_CACHE_PRELOAD_ADDR_REG. */ #define CACHE_L1_CACHE_PRELOAD_SIZE 0x00003FFFU #define CACHE_L1_CACHE_PRELOAD_SIZE_M (CACHE_L1_CACHE_PRELOAD_SIZE_V << CACHE_L1_CACHE_PRELOAD_SIZE_S) #define CACHE_L1_CACHE_PRELOAD_SIZE_V 0x00003FFFU #define CACHE_L1_CACHE_PRELOAD_SIZE_S 0 -/** CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG register - * L1 instruction Cache 0 autoload-operation control register - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xe0) -/** CACHE_L1_ICACHE0_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, - * 0: disable. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_ENA (BIT(0)) -#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_M (CACHE_L1_ICACHE0_AUTOLOAD_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_ENA_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_V 0x00000001U -#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_S 0 -/** CACHE_L1_ICACHE0_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-ICache0 is finished or - * not. 0: not finished. 1: finished. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_DONE (BIT(1)) -#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_M (CACHE_L1_ICACHE0_AUTOLOAD_DONE_V << CACHE_L1_ICACHE0_AUTOLOAD_DONE_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_V 0x00000001U -#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_S 1 -/** CACHE_L1_ICACHE0_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-ICache0. 0: - * ascending. 1: descending. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER (BIT(2)) -#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_M (CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V 0x00000001U -#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S 2 -/** CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-ICache0. - * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE 0x00000003U -#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V 0x00000003U -#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S 3 -/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-ICache0. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA (BIT(8)) -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V 0x00000001U -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S 8 -/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-ICache0. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA (BIT(9)) -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V 0x00000001U -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S 9 -/** CACHE_L1_ICACHE0_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0; - * The bit is used to set the gid of l1 icache0 autoload. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_RGID 0x0000000FU -#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_M (CACHE_L1_ICACHE0_AUTOLOAD_RGID_V << CACHE_L1_ICACHE0_AUTOLOAD_RGID_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_S 10 - -/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG register - * L1 instruction Cache 0 autoload section 0 address configure register - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xe4) -/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L1-ICache0. Note that it should be used together with - * L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S 0 - -/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG register - * L1 instruction Cache 0 autoload section 0 size configure register - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0xe8) -/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-ICache0. Note that it should be used together with - * L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE 0x0FFFFFFFU -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V 0x0FFFFFFFU -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S 0 - -/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG register - * L1 instruction Cache 0 autoload section 1 address configure register - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0xec) -/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L1-ICache0. Note that it should be used together with - * L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S 0 - -/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG register - * L1 instruction Cache 0 autoload section 1 size configure register - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0xf0) -/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L1-ICache0. Note that it should be used together with - * L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE 0x0FFFFFFFU -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V 0x0FFFFFFFU -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S 0 - -/** CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG register - * L1 instruction Cache 1 autoload-operation control register - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xf4) -/** CACHE_L1_ICACHE1_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, - * 0: disable. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_ENA (BIT(0)) -#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_M (CACHE_L1_ICACHE1_AUTOLOAD_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_ENA_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_V 0x00000001U -#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_S 0 -/** CACHE_L1_ICACHE1_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-ICache1 is finished or - * not. 0: not finished. 1: finished. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_DONE (BIT(1)) -#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_M (CACHE_L1_ICACHE1_AUTOLOAD_DONE_V << CACHE_L1_ICACHE1_AUTOLOAD_DONE_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_V 0x00000001U -#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_S 1 -/** CACHE_L1_ICACHE1_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-ICache1. 0: - * ascending. 1: descending. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER (BIT(2)) -#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_M (CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V 0x00000001U -#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S 2 -/** CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-ICache1. - * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE 0x00000003U -#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V 0x00000003U -#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S 3 -/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-ICache1. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA (BIT(8)) -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V 0x00000001U -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S 8 -/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-ICache1. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA (BIT(9)) -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V 0x00000001U -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S 9 -/** CACHE_L1_ICACHE1_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0; - * The bit is used to set the gid of l1 icache1 autoload. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_RGID 0x0000000FU -#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_M (CACHE_L1_ICACHE1_AUTOLOAD_RGID_V << CACHE_L1_ICACHE1_AUTOLOAD_RGID_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_S 10 - -/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG register - * L1 instruction Cache 1 autoload section 0 address configure register - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xf8) -/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L1-ICache1. Note that it should be used together with - * L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S 0 - -/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG register - * L1 instruction Cache 1 autoload section 0 size configure register - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0xfc) -/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-ICache1. Note that it should be used together with - * L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE 0x0FFFFFFFU -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V 0x0FFFFFFFU -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S 0 - -/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG register - * L1 instruction Cache 1 autoload section 1 address configure register - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x100) -/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L1-ICache1. Note that it should be used together with - * L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S 0 - -/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG register - * L1 instruction Cache 1 autoload section 1 size configure register - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x104) -/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L1-ICache1. Note that it should be used together with - * L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE 0x0FFFFFFFU -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V 0x0FFFFFFFU -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S 0 - -/** CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG register - * L1 instruction Cache 2 autoload-operation control register - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x108) -/** CACHE_L1_ICACHE2_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, - * 0: disable. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_ENA (BIT(0)) -#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_M (CACHE_L1_ICACHE2_AUTOLOAD_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_ENA_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_V 0x00000001U -#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_S 0 -/** CACHE_L1_ICACHE2_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-ICache2 is finished or - * not. 0: not finished. 1: finished. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_DONE (BIT(1)) -#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_M (CACHE_L1_ICACHE2_AUTOLOAD_DONE_V << CACHE_L1_ICACHE2_AUTOLOAD_DONE_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_V 0x00000001U -#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_S 1 -/** CACHE_L1_ICACHE2_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-ICache2. 0: - * ascending. 1: descending. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER (BIT(2)) -#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_M (CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V 0x00000001U -#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S 2 -/** CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-ICache2. - * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE 0x00000003U -#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V 0x00000003U -#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S 3 -/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-ICache2. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA (BIT(8)) -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V 0x00000001U -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S 8 -/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-ICache2. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA (BIT(9)) -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V 0x00000001U -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S 9 -/** CACHE_L1_ICACHE2_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0; - * The bit is used to set the gid of l1 icache2 autoload. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_RGID 0x0000000FU -#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_M (CACHE_L1_ICACHE2_AUTOLOAD_RGID_V << CACHE_L1_ICACHE2_AUTOLOAD_RGID_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_S 10 - -/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG register - * L1 instruction Cache 2 autoload section 0 address configure register - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x10c) -/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L1-ICache2. Note that it should be used together with - * L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S 0 - -/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG register - * L1 instruction Cache 2 autoload section 0 size configure register - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x110) -/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-ICache2. Note that it should be used together with - * L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE 0x0FFFFFFFU -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V 0x0FFFFFFFU -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S 0 - -/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG register - * L1 instruction Cache 2 autoload section 1 address configure register - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x114) -/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L1-ICache2. Note that it should be used together with - * L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S 0 - -/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG register - * L1 instruction Cache 2 autoload section 1 size configure register - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x118) -/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L1-ICache2. Note that it should be used together with - * L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE 0x0FFFFFFFU -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V 0x0FFFFFFFU -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S 0 - -/** CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG register - * L1 instruction Cache 3 autoload-operation control register - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x11c) -/** CACHE_L1_ICACHE3_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, - * 0: disable. - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_ENA (BIT(0)) -#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_M (CACHE_L1_ICACHE3_AUTOLOAD_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_ENA_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_V 0x00000001U -#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_S 0 -/** CACHE_L1_ICACHE3_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-ICache3 is finished or - * not. 0: not finished. 1: finished. - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_DONE (BIT(1)) -#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_M (CACHE_L1_ICACHE3_AUTOLOAD_DONE_V << CACHE_L1_ICACHE3_AUTOLOAD_DONE_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_V 0x00000001U -#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_S 1 -/** CACHE_L1_ICACHE3_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-ICache3. 0: - * ascending. 1: descending. - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER (BIT(2)) -#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_M (CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V 0x00000001U -#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S 2 -/** CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-ICache3. - * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE 0x00000003U -#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V 0x00000003U -#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S 3 -/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-ICache3. - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA (BIT(8)) -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V 0x00000001U -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S 8 -/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-ICache3. - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA (BIT(9)) -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V 0x00000001U -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S 9 -/** CACHE_L1_ICACHE3_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0; - * The bit is used to set the gid of l1 icache3 autoload. - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_RGID 0x0000000FU -#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_M (CACHE_L1_ICACHE3_AUTOLOAD_RGID_V << CACHE_L1_ICACHE3_AUTOLOAD_RGID_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_S 10 - -/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG register - * L1 instruction Cache 3 autoload section 0 address configure register - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x120) -/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L1-ICache3. Note that it should be used together with - * L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S 0 - -/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG register - * L1 instruction Cache 3 autoload section 0 size configure register - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x124) -/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-ICache3. Note that it should be used together with - * L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE 0x0FFFFFFFU -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V 0x0FFFFFFFU -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S 0 - -/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG register - * L1 instruction Cache 3 autoload section 1 address configure register - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x128) -/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L1-ICache3. Note that it should be used together with - * L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S 0 - -/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG register - * L1 instruction Cache 3 autoload section 1 size configure register - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x12c) -/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE 0x0FFFFFFFU -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V 0x0FFFFFFFU -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S 0 - /** CACHE_L1_CACHE_AUTOLOAD_CTRL_REG register - * L1 Cache autoload-operation control register + * L1 cache autoloading operation control register */ #define CACHE_L1_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x130) /** CACHE_L1_CACHE_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-Cache. 1: enable, - * 0: disable. + * Configures whether to enable the autoloading operation in the L1 cache. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_AUTOLOAD_ENA (BIT(0)) #define CACHE_L1_CACHE_AUTOLOAD_ENA_M (CACHE_L1_CACHE_AUTOLOAD_ENA_V << CACHE_L1_CACHE_AUTOLOAD_ENA_S) #define CACHE_L1_CACHE_AUTOLOAD_ENA_V 0x00000001U #define CACHE_L1_CACHE_AUTOLOAD_ENA_S 0 /** CACHE_L1_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-Cache is finished or - * not. 0: not finished. 1: finished. + * Represents whether the autoloading operation in the L1 cache is finished. + * 0: Not finished + * 1: Finished */ #define CACHE_L1_CACHE_AUTOLOAD_DONE (BIT(1)) #define CACHE_L1_CACHE_AUTOLOAD_DONE_M (CACHE_L1_CACHE_AUTOLOAD_DONE_V << CACHE_L1_CACHE_AUTOLOAD_DONE_S) #define CACHE_L1_CACHE_AUTOLOAD_DONE_V 0x00000001U #define CACHE_L1_CACHE_AUTOLOAD_DONE_S 1 /** CACHE_L1_CACHE_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-Cache. 0: - * ascending. 1: descending. + * Configures the direction of the autoloading operation in the L1 cache. + * 0: Ascending + * 1: Descending */ #define CACHE_L1_CACHE_AUTOLOAD_ORDER (BIT(2)) #define CACHE_L1_CACHE_AUTOLOAD_ORDER_M (CACHE_L1_CACHE_AUTOLOAD_ORDER_V << CACHE_L1_CACHE_AUTOLOAD_ORDER_S) #define CACHE_L1_CACHE_AUTOLOAD_ORDER_V 0x00000001U #define CACHE_L1_CACHE_AUTOLOAD_ORDER_S 2 /** CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3: - * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + * Configures the trigger mode of the autoloading operation in the L1 cache. + * 0/3: Triggered by misses + * 1: Triggered by hits + * 2: Triggered by misses or hits */ #define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE 0x00000003U #define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S) #define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V 0x00000003U #define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S 3 /** CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-Cache. + * Configures whether to enable Section 0 for the autoloading operation in the L1 + * cache. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA (BIT(8)) #define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_M (CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S) #define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V 0x00000001U #define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S 8 /** CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-Cache. + * Configures whether to enable Section 1 for the autoloading operation in the L1 + * cache. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA (BIT(9)) #define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_M (CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S) #define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V 0x00000001U #define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S 9 -/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA : HRO; bitpos: [10]; default: 0; - * The bit is used to enable the third section for autoload operation on L1-Cache. - */ -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA (BIT(10)) -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_M (CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_S) -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_V 0x00000001U -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_S 10 -/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA : HRO; bitpos: [11]; default: 0; - * The bit is used to enable the fourth section for autoload operation on L1-Cache. - */ -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA (BIT(11)) -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_M (CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_S) -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_V 0x00000001U -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_S 11 -/** CACHE_L1_CACHE_AUTOLOAD_RGID : HRO; bitpos: [15:12]; default: 0; - * The bit is used to set the gid of l1 cache autoload. - */ -#define CACHE_L1_CACHE_AUTOLOAD_RGID 0x0000000FU -#define CACHE_L1_CACHE_AUTOLOAD_RGID_M (CACHE_L1_CACHE_AUTOLOAD_RGID_V << CACHE_L1_CACHE_AUTOLOAD_RGID_S) -#define CACHE_L1_CACHE_AUTOLOAD_RGID_V 0x0000000FU -#define CACHE_L1_CACHE_AUTOLOAD_RGID_S 12 /** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG register - * L1 Cache autoload section 0 address configure register + * L1 cache autoloading Section 0 address configuration register */ #define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x134) /** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA. + * Configures the starting virtual address of Section 0 for the autoloading operation + * in the L1 cache. Note that it should be used together with + * CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE and CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA. */ #define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU #define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S) @@ -2227,13 +545,13 @@ extern "C" { #define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S 0 /** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG register - * L1 Cache autoload section 0 size configure register + * L1 cache autoloading Section 0 size configuration register */ #define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x138) /** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [24:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA. + * Configures the size of Section 0 for the autoloading operation in the L1 cache. + * Note that it should be used together with CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR and + * CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA. */ #define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE 0x01FFFFFFU #define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S) @@ -2241,13 +559,13 @@ extern "C" { #define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S 0 /** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG register - * L1 Cache autoload section 1 address configure register + * L1 cache autoloading Section 1 address configuration register */ #define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x13c) /** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA. + * Configures the starting virtual address of Section 1 for the autoloading operation + * in the L1 cache. Note that it should be used together with + * CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE and CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA. */ #define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU #define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S) @@ -2255,378 +573,104 @@ extern "C" { #define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S 0 /** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG register - * L1 Cache autoload section 1 size configure register + * L1 cache autoloading Section 1 size configuration register */ #define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x140) /** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [24:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA. + * Configures the size of Section 1 for the autoloading operation in the L1 cache. + * Note that it should be used together with CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR and + * CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA. */ #define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE 0x01FFFFFFU #define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S) #define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V 0x01FFFFFFU #define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S 0 -/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_REG register - * L1 Cache autoload section 2 address configure register - */ -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x144) -/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the third section for - * autoload operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA. - */ -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR 0xFFFFFFFFU -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_M (CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S) -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S 0 - -/** CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_REG register - * L1 Cache autoload section 2 size configure register - */ -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x148) -/** CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE : HRO; bitpos: [24:0]; default: 0; - * Those bits are used to configure the size of the third section for autoload - * operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA. - */ -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE 0x01FFFFFFU -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_M (CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S) -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V 0x01FFFFFFU -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S 0 - -/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_REG register - * L1 Cache autoload section 1 address configure register - */ -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x14c) -/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the fourth section for - * autoload operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA. - */ -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR 0xFFFFFFFFU -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_M (CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S) -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S 0 - -/** CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_REG register - * L1 Cache autoload section 1 size configure register - */ -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x150) -/** CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE : HRO; bitpos: [24:0]; default: 0; - * Those bits are used to configure the size of the fourth section for autoload - * operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA. - */ -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE 0x01FFFFFFU -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_M (CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S) -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V 0x01FFFFFFU -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S 0 - /** CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG register - * Cache Access Counter Interrupt enable register + * Cache access counter interrupt enable register */ #define CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x154) -/** CACHE_L1_IBUS0_OVF_INT_ENA : HRO; bitpos: [0]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L1-ICache0 due to bus0 accesses L1-ICache0. - */ -#define CACHE_L1_IBUS0_OVF_INT_ENA (BIT(0)) -#define CACHE_L1_IBUS0_OVF_INT_ENA_M (CACHE_L1_IBUS0_OVF_INT_ENA_V << CACHE_L1_IBUS0_OVF_INT_ENA_S) -#define CACHE_L1_IBUS0_OVF_INT_ENA_V 0x00000001U -#define CACHE_L1_IBUS0_OVF_INT_ENA_S 0 -/** CACHE_L1_IBUS1_OVF_INT_ENA : HRO; bitpos: [1]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L1-ICache1 due to bus1 accesses L1-ICache1. - */ -#define CACHE_L1_IBUS1_OVF_INT_ENA (BIT(1)) -#define CACHE_L1_IBUS1_OVF_INT_ENA_M (CACHE_L1_IBUS1_OVF_INT_ENA_V << CACHE_L1_IBUS1_OVF_INT_ENA_S) -#define CACHE_L1_IBUS1_OVF_INT_ENA_V 0x00000001U -#define CACHE_L1_IBUS1_OVF_INT_ENA_S 1 -/** CACHE_L1_IBUS2_OVF_INT_ENA : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_IBUS2_OVF_INT_ENA (BIT(2)) -#define CACHE_L1_IBUS2_OVF_INT_ENA_M (CACHE_L1_IBUS2_OVF_INT_ENA_V << CACHE_L1_IBUS2_OVF_INT_ENA_S) -#define CACHE_L1_IBUS2_OVF_INT_ENA_V 0x00000001U -#define CACHE_L1_IBUS2_OVF_INT_ENA_S 2 -/** CACHE_L1_IBUS3_OVF_INT_ENA : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_IBUS3_OVF_INT_ENA (BIT(3)) -#define CACHE_L1_IBUS3_OVF_INT_ENA_M (CACHE_L1_IBUS3_OVF_INT_ENA_V << CACHE_L1_IBUS3_OVF_INT_ENA_S) -#define CACHE_L1_IBUS3_OVF_INT_ENA_V 0x00000001U -#define CACHE_L1_IBUS3_OVF_INT_ENA_S 3 /** CACHE_L1_BUS0_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L1-DCache due to bus0 accesses L1-DCache. + * Write 1 to enable L1_BUS0_OVF_INT. */ #define CACHE_L1_BUS0_OVF_INT_ENA (BIT(4)) #define CACHE_L1_BUS0_OVF_INT_ENA_M (CACHE_L1_BUS0_OVF_INT_ENA_V << CACHE_L1_BUS0_OVF_INT_ENA_S) #define CACHE_L1_BUS0_OVF_INT_ENA_V 0x00000001U #define CACHE_L1_BUS0_OVF_INT_ENA_S 4 /** CACHE_L1_BUS1_OVF_INT_ENA : R/W; bitpos: [5]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L1-DCache due to bus1 accesses L1-DCache. + * Write 1 to enable L1_BUS1_OVF_INT. */ #define CACHE_L1_BUS1_OVF_INT_ENA (BIT(5)) #define CACHE_L1_BUS1_OVF_INT_ENA_M (CACHE_L1_BUS1_OVF_INT_ENA_V << CACHE_L1_BUS1_OVF_INT_ENA_S) #define CACHE_L1_BUS1_OVF_INT_ENA_V 0x00000001U #define CACHE_L1_BUS1_OVF_INT_ENA_S 5 -/** CACHE_L1_DBUS2_OVF_INT_ENA : HRO; bitpos: [6]; default: 0; - * Reserved - */ -#define CACHE_L1_DBUS2_OVF_INT_ENA (BIT(6)) -#define CACHE_L1_DBUS2_OVF_INT_ENA_M (CACHE_L1_DBUS2_OVF_INT_ENA_V << CACHE_L1_DBUS2_OVF_INT_ENA_S) -#define CACHE_L1_DBUS2_OVF_INT_ENA_V 0x00000001U -#define CACHE_L1_DBUS2_OVF_INT_ENA_S 6 -/** CACHE_L1_DBUS3_OVF_INT_ENA : HRO; bitpos: [7]; default: 0; - * Reserved - */ -#define CACHE_L1_DBUS3_OVF_INT_ENA (BIT(7)) -#define CACHE_L1_DBUS3_OVF_INT_ENA_M (CACHE_L1_DBUS3_OVF_INT_ENA_V << CACHE_L1_DBUS3_OVF_INT_ENA_S) -#define CACHE_L1_DBUS3_OVF_INT_ENA_V 0x00000001U -#define CACHE_L1_DBUS3_OVF_INT_ENA_S 7 /** CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG register - * Cache Access Counter Interrupt clear register + * Cache access counter interrupt clear register */ #define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x158) -/** CACHE_L1_IBUS0_OVF_INT_CLR : HRO; bitpos: [0]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due - * to bus0 accesses L1-ICache0. - */ -#define CACHE_L1_IBUS0_OVF_INT_CLR (BIT(0)) -#define CACHE_L1_IBUS0_OVF_INT_CLR_M (CACHE_L1_IBUS0_OVF_INT_CLR_V << CACHE_L1_IBUS0_OVF_INT_CLR_S) -#define CACHE_L1_IBUS0_OVF_INT_CLR_V 0x00000001U -#define CACHE_L1_IBUS0_OVF_INT_CLR_S 0 -/** CACHE_L1_IBUS1_OVF_INT_CLR : HRO; bitpos: [1]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due - * to bus1 accesses L1-ICache1. - */ -#define CACHE_L1_IBUS1_OVF_INT_CLR (BIT(1)) -#define CACHE_L1_IBUS1_OVF_INT_CLR_M (CACHE_L1_IBUS1_OVF_INT_CLR_V << CACHE_L1_IBUS1_OVF_INT_CLR_S) -#define CACHE_L1_IBUS1_OVF_INT_CLR_V 0x00000001U -#define CACHE_L1_IBUS1_OVF_INT_CLR_S 1 -/** CACHE_L1_IBUS2_OVF_INT_CLR : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_IBUS2_OVF_INT_CLR (BIT(2)) -#define CACHE_L1_IBUS2_OVF_INT_CLR_M (CACHE_L1_IBUS2_OVF_INT_CLR_V << CACHE_L1_IBUS2_OVF_INT_CLR_S) -#define CACHE_L1_IBUS2_OVF_INT_CLR_V 0x00000001U -#define CACHE_L1_IBUS2_OVF_INT_CLR_S 2 -/** CACHE_L1_IBUS3_OVF_INT_CLR : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_IBUS3_OVF_INT_CLR (BIT(3)) -#define CACHE_L1_IBUS3_OVF_INT_CLR_M (CACHE_L1_IBUS3_OVF_INT_CLR_V << CACHE_L1_IBUS3_OVF_INT_CLR_S) -#define CACHE_L1_IBUS3_OVF_INT_CLR_V 0x00000001U -#define CACHE_L1_IBUS3_OVF_INT_CLR_S 3 /** CACHE_L1_BUS0_OVF_INT_CLR : WT; bitpos: [4]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L1-DCache due - * to bus0 accesses L1-DCache. + * Write 1 to clear L1_BUS0_OVF_INT. */ #define CACHE_L1_BUS0_OVF_INT_CLR (BIT(4)) #define CACHE_L1_BUS0_OVF_INT_CLR_M (CACHE_L1_BUS0_OVF_INT_CLR_V << CACHE_L1_BUS0_OVF_INT_CLR_S) #define CACHE_L1_BUS0_OVF_INT_CLR_V 0x00000001U #define CACHE_L1_BUS0_OVF_INT_CLR_S 4 /** CACHE_L1_BUS1_OVF_INT_CLR : WT; bitpos: [5]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L1-DCache due - * to bus1 accesses L1-DCache. + * Write 1 to clear L1_BUS1_OVF_INT. */ #define CACHE_L1_BUS1_OVF_INT_CLR (BIT(5)) #define CACHE_L1_BUS1_OVF_INT_CLR_M (CACHE_L1_BUS1_OVF_INT_CLR_V << CACHE_L1_BUS1_OVF_INT_CLR_S) #define CACHE_L1_BUS1_OVF_INT_CLR_V 0x00000001U #define CACHE_L1_BUS1_OVF_INT_CLR_S 5 -/** CACHE_L1_DBUS2_OVF_INT_CLR : R/W; bitpos: [6]; default: 0; - * Reserved - */ -#define CACHE_L1_DBUS2_OVF_INT_CLR (BIT(6)) -#define CACHE_L1_DBUS2_OVF_INT_CLR_M (CACHE_L1_DBUS2_OVF_INT_CLR_V << CACHE_L1_DBUS2_OVF_INT_CLR_S) -#define CACHE_L1_DBUS2_OVF_INT_CLR_V 0x00000001U -#define CACHE_L1_DBUS2_OVF_INT_CLR_S 6 -/** CACHE_L1_DBUS3_OVF_INT_CLR : R/W; bitpos: [7]; default: 0; - * Reserved - */ -#define CACHE_L1_DBUS3_OVF_INT_CLR (BIT(7)) -#define CACHE_L1_DBUS3_OVF_INT_CLR_M (CACHE_L1_DBUS3_OVF_INT_CLR_V << CACHE_L1_DBUS3_OVF_INT_CLR_S) -#define CACHE_L1_DBUS3_OVF_INT_CLR_V 0x00000001U -#define CACHE_L1_DBUS3_OVF_INT_CLR_S 7 /** CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG register - * Cache Access Counter Interrupt raw register + * Cache access counter interrupt raw register */ #define CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x15c) -/** CACHE_L1_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 - * due to bus0 accesses L1-ICache0. - */ -#define CACHE_L1_IBUS0_OVF_INT_RAW (BIT(0)) -#define CACHE_L1_IBUS0_OVF_INT_RAW_M (CACHE_L1_IBUS0_OVF_INT_RAW_V << CACHE_L1_IBUS0_OVF_INT_RAW_S) -#define CACHE_L1_IBUS0_OVF_INT_RAW_V 0x00000001U -#define CACHE_L1_IBUS0_OVF_INT_RAW_S 0 -/** CACHE_L1_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 - * due to bus1 accesses L1-ICache1. - */ -#define CACHE_L1_IBUS1_OVF_INT_RAW (BIT(1)) -#define CACHE_L1_IBUS1_OVF_INT_RAW_M (CACHE_L1_IBUS1_OVF_INT_RAW_V << CACHE_L1_IBUS1_OVF_INT_RAW_S) -#define CACHE_L1_IBUS1_OVF_INT_RAW_V 0x00000001U -#define CACHE_L1_IBUS1_OVF_INT_RAW_S 1 -/** CACHE_L1_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 - * due to bus2 accesses L1-ICache2. - */ -#define CACHE_L1_IBUS2_OVF_INT_RAW (BIT(2)) -#define CACHE_L1_IBUS2_OVF_INT_RAW_M (CACHE_L1_IBUS2_OVF_INT_RAW_V << CACHE_L1_IBUS2_OVF_INT_RAW_S) -#define CACHE_L1_IBUS2_OVF_INT_RAW_V 0x00000001U -#define CACHE_L1_IBUS2_OVF_INT_RAW_S 2 -/** CACHE_L1_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 - * due to bus3 accesses L1-ICache3. - */ -#define CACHE_L1_IBUS3_OVF_INT_RAW (BIT(3)) -#define CACHE_L1_IBUS3_OVF_INT_RAW_M (CACHE_L1_IBUS3_OVF_INT_RAW_V << CACHE_L1_IBUS3_OVF_INT_RAW_S) -#define CACHE_L1_IBUS3_OVF_INT_RAW_V 0x00000001U -#define CACHE_L1_IBUS3_OVF_INT_RAW_S 3 /** CACHE_L1_BUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache - * due to bus0 accesses L1-DCache. + * The raw interrupt status of L1_BUS0_OVF_INT. */ #define CACHE_L1_BUS0_OVF_INT_RAW (BIT(4)) #define CACHE_L1_BUS0_OVF_INT_RAW_M (CACHE_L1_BUS0_OVF_INT_RAW_V << CACHE_L1_BUS0_OVF_INT_RAW_S) #define CACHE_L1_BUS0_OVF_INT_RAW_V 0x00000001U #define CACHE_L1_BUS0_OVF_INT_RAW_S 4 /** CACHE_L1_BUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache - * due to bus1 accesses L1-DCache. + * The raw interrupt status of L1_BUS1_OVF_INT. */ #define CACHE_L1_BUS1_OVF_INT_RAW (BIT(5)) #define CACHE_L1_BUS1_OVF_INT_RAW_M (CACHE_L1_BUS1_OVF_INT_RAW_V << CACHE_L1_BUS1_OVF_INT_RAW_S) #define CACHE_L1_BUS1_OVF_INT_RAW_V 0x00000001U #define CACHE_L1_BUS1_OVF_INT_RAW_S 5 -/** CACHE_L1_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache - * due to bus2 accesses L1-DCache. - */ -#define CACHE_L1_DBUS2_OVF_INT_RAW (BIT(6)) -#define CACHE_L1_DBUS2_OVF_INT_RAW_M (CACHE_L1_DBUS2_OVF_INT_RAW_V << CACHE_L1_DBUS2_OVF_INT_RAW_S) -#define CACHE_L1_DBUS2_OVF_INT_RAW_V 0x00000001U -#define CACHE_L1_DBUS2_OVF_INT_RAW_S 6 -/** CACHE_L1_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache - * due to bus3 accesses L1-DCache. - */ -#define CACHE_L1_DBUS3_OVF_INT_RAW (BIT(7)) -#define CACHE_L1_DBUS3_OVF_INT_RAW_M (CACHE_L1_DBUS3_OVF_INT_RAW_V << CACHE_L1_DBUS3_OVF_INT_RAW_S) -#define CACHE_L1_DBUS3_OVF_INT_RAW_V 0x00000001U -#define CACHE_L1_DBUS3_OVF_INT_RAW_S 7 /** CACHE_L1_CACHE_ACS_CNT_INT_ST_REG register - * Cache Access Counter Interrupt status register + * Cache access counter interrupt status register */ #define CACHE_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x160) -/** CACHE_L1_IBUS0_OVF_INT_ST : HRO; bitpos: [0]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L1-ICache0 due to bus0 accesses L1-ICache0. - */ -#define CACHE_L1_IBUS0_OVF_INT_ST (BIT(0)) -#define CACHE_L1_IBUS0_OVF_INT_ST_M (CACHE_L1_IBUS0_OVF_INT_ST_V << CACHE_L1_IBUS0_OVF_INT_ST_S) -#define CACHE_L1_IBUS0_OVF_INT_ST_V 0x00000001U -#define CACHE_L1_IBUS0_OVF_INT_ST_S 0 -/** CACHE_L1_IBUS1_OVF_INT_ST : RO; bitpos: [1]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L1-ICache1 due to bus1 accesses L1-ICache1. - */ -#define CACHE_L1_IBUS1_OVF_INT_ST (BIT(1)) -#define CACHE_L1_IBUS1_OVF_INT_ST_M (CACHE_L1_IBUS1_OVF_INT_ST_V << CACHE_L1_IBUS1_OVF_INT_ST_S) -#define CACHE_L1_IBUS1_OVF_INT_ST_V 0x00000001U -#define CACHE_L1_IBUS1_OVF_INT_ST_S 1 -/** CACHE_L1_IBUS2_OVF_INT_ST : RO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_IBUS2_OVF_INT_ST (BIT(2)) -#define CACHE_L1_IBUS2_OVF_INT_ST_M (CACHE_L1_IBUS2_OVF_INT_ST_V << CACHE_L1_IBUS2_OVF_INT_ST_S) -#define CACHE_L1_IBUS2_OVF_INT_ST_V 0x00000001U -#define CACHE_L1_IBUS2_OVF_INT_ST_S 2 -/** CACHE_L1_IBUS3_OVF_INT_ST : RO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_IBUS3_OVF_INT_ST (BIT(3)) -#define CACHE_L1_IBUS3_OVF_INT_ST_M (CACHE_L1_IBUS3_OVF_INT_ST_V << CACHE_L1_IBUS3_OVF_INT_ST_S) -#define CACHE_L1_IBUS3_OVF_INT_ST_V 0x00000001U -#define CACHE_L1_IBUS3_OVF_INT_ST_S 3 /** CACHE_L1_BUS0_OVF_INT_ST : RO; bitpos: [4]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L1-DCache due to bus0 accesses L1-DCache. + * The masked interrupt status of L1_BUS0_OVF_INT. */ #define CACHE_L1_BUS0_OVF_INT_ST (BIT(4)) #define CACHE_L1_BUS0_OVF_INT_ST_M (CACHE_L1_BUS0_OVF_INT_ST_V << CACHE_L1_BUS0_OVF_INT_ST_S) #define CACHE_L1_BUS0_OVF_INT_ST_V 0x00000001U #define CACHE_L1_BUS0_OVF_INT_ST_S 4 /** CACHE_L1_BUS1_OVF_INT_ST : RO; bitpos: [5]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L1-DCache due to bus1 accesses L1-DCache. + * The masked interrupt status of L1_BUS1_OVF_INT. */ #define CACHE_L1_BUS1_OVF_INT_ST (BIT(5)) #define CACHE_L1_BUS1_OVF_INT_ST_M (CACHE_L1_BUS1_OVF_INT_ST_V << CACHE_L1_BUS1_OVF_INT_ST_S) #define CACHE_L1_BUS1_OVF_INT_ST_V 0x00000001U #define CACHE_L1_BUS1_OVF_INT_ST_S 5 -/** CACHE_L1_DBUS2_OVF_INT_ST : RO; bitpos: [6]; default: 0; - * Reserved - */ -#define CACHE_L1_DBUS2_OVF_INT_ST (BIT(6)) -#define CACHE_L1_DBUS2_OVF_INT_ST_M (CACHE_L1_DBUS2_OVF_INT_ST_V << CACHE_L1_DBUS2_OVF_INT_ST_S) -#define CACHE_L1_DBUS2_OVF_INT_ST_V 0x00000001U -#define CACHE_L1_DBUS2_OVF_INT_ST_S 6 -/** CACHE_L1_DBUS3_OVF_INT_ST : RO; bitpos: [7]; default: 0; - * Reserved - */ -#define CACHE_L1_DBUS3_OVF_INT_ST (BIT(7)) -#define CACHE_L1_DBUS3_OVF_INT_ST_M (CACHE_L1_DBUS3_OVF_INT_ST_V << CACHE_L1_DBUS3_OVF_INT_ST_S) -#define CACHE_L1_DBUS3_OVF_INT_ST_V 0x00000001U -#define CACHE_L1_DBUS3_OVF_INT_ST_S 7 /** CACHE_L1_CACHE_ACS_FAIL_CTRL_REG register - * Cache Access Fail Configuration register + * Cache access failed interrupt configuration register */ #define CACHE_L1_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x164) -/** CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE : HRO; bitpos: [0]; default: 0; - * The bit is used to configure l1 icache0 access fail check mode. 0: the access fail - * is not propagated to the request, 1: the access fail is propagated to the request - */ -#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE (BIT(0)) -#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_M (CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_S) -#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_V 0x00000001U -#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_S 0 -/** CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE : HRO; bitpos: [1]; default: 0; - * The bit is used to configure l1 icache1 access fail check mode. 0: the access fail - * is not propagated to the request, 1: the access fail is propagated to the request - */ -#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE (BIT(1)) -#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_M (CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_S) -#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_V 0x00000001U -#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_S 1 -/** CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE : HRO; bitpos: [2]; default: 0; - * The bit is used to configure l1 icache2 access fail check mode. 0: the access fail - * is not propagated to the request, 1: the access fail is propagated to the request - */ -#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE (BIT(2)) -#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_M (CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_S) -#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_V 0x00000001U -#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_S 2 -/** CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE : HRO; bitpos: [3]; default: 0; - * The bit is used to configure l1 icache3 access fail check mode. 0: the access fail - * is not propagated to the request, 1: the access fail is propagated to the request - */ -#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE (BIT(3)) -#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_M (CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_S) -#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_V 0x00000001U -#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_S 3 /** CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE : R/W; bitpos: [4]; default: 0; - * The bit is used to configure l1 cache access fail check mode. 0: the access fail is - * not propagated to the request, 1: the access fail is propagated to the request + * Configures whether to pass the exception of cache accessing lower-level memory to + * the upper-level device. + * 0: Do not pass to the upper-level device + * 1: Pass to the upper-level device */ #define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE (BIT(4)) #define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_M (CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_S) @@ -2634,42 +678,11 @@ extern "C" { #define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_S 4 /** CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG register - * Cache Access Fail Interrupt enable register + * Cache access failed interrupt enable register */ #define CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x168) -/** CACHE_L1_ICACHE0_FAIL_INT_ENA : HRO; bitpos: [0]; default: 0; - * The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to - * cpu accesses L1-ICache0. - */ -#define CACHE_L1_ICACHE0_FAIL_INT_ENA (BIT(0)) -#define CACHE_L1_ICACHE0_FAIL_INT_ENA_M (CACHE_L1_ICACHE0_FAIL_INT_ENA_V << CACHE_L1_ICACHE0_FAIL_INT_ENA_S) -#define CACHE_L1_ICACHE0_FAIL_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE0_FAIL_INT_ENA_S 0 -/** CACHE_L1_ICACHE1_FAIL_INT_ENA : HRO; bitpos: [1]; default: 0; - * The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to - * cpu accesses L1-ICache1. - */ -#define CACHE_L1_ICACHE1_FAIL_INT_ENA (BIT(1)) -#define CACHE_L1_ICACHE1_FAIL_INT_ENA_M (CACHE_L1_ICACHE1_FAIL_INT_ENA_V << CACHE_L1_ICACHE1_FAIL_INT_ENA_S) -#define CACHE_L1_ICACHE1_FAIL_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE1_FAIL_INT_ENA_S 1 -/** CACHE_L1_ICACHE2_FAIL_INT_ENA : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_FAIL_INT_ENA (BIT(2)) -#define CACHE_L1_ICACHE2_FAIL_INT_ENA_M (CACHE_L1_ICACHE2_FAIL_INT_ENA_V << CACHE_L1_ICACHE2_FAIL_INT_ENA_S) -#define CACHE_L1_ICACHE2_FAIL_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE2_FAIL_INT_ENA_S 2 -/** CACHE_L1_ICACHE3_FAIL_INT_ENA : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_FAIL_INT_ENA (BIT(3)) -#define CACHE_L1_ICACHE3_FAIL_INT_ENA_M (CACHE_L1_ICACHE3_FAIL_INT_ENA_V << CACHE_L1_ICACHE3_FAIL_INT_ENA_S) -#define CACHE_L1_ICACHE3_FAIL_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE3_FAIL_INT_ENA_S 3 /** CACHE_L1_CACHE_FAIL_INT_ENA : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt of access fail that occurs in L1-DCache due to - * cpu accesses L1-DCache. + * Write 1 to enable L1_CACHE_FAIL_INT. */ #define CACHE_L1_CACHE_FAIL_INT_ENA (BIT(4)) #define CACHE_L1_CACHE_FAIL_INT_ENA_M (CACHE_L1_CACHE_FAIL_INT_ENA_V << CACHE_L1_CACHE_FAIL_INT_ENA_S) @@ -2677,42 +690,11 @@ extern "C" { #define CACHE_L1_CACHE_FAIL_INT_ENA_S 4 /** CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG register - * L1-Cache Access Fail Interrupt clear register + * L1 cache access failed interrupt clear register */ #define CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x16c) -/** CACHE_L1_ICACHE0_FAIL_INT_CLR : WT; bitpos: [0]; default: 0; - * The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to - * cpu accesses L1-ICache0. - */ -#define CACHE_L1_ICACHE0_FAIL_INT_CLR (BIT(0)) -#define CACHE_L1_ICACHE0_FAIL_INT_CLR_M (CACHE_L1_ICACHE0_FAIL_INT_CLR_V << CACHE_L1_ICACHE0_FAIL_INT_CLR_S) -#define CACHE_L1_ICACHE0_FAIL_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE0_FAIL_INT_CLR_S 0 -/** CACHE_L1_ICACHE1_FAIL_INT_CLR : WT; bitpos: [1]; default: 0; - * The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to - * cpu accesses L1-ICache1. - */ -#define CACHE_L1_ICACHE1_FAIL_INT_CLR (BIT(1)) -#define CACHE_L1_ICACHE1_FAIL_INT_CLR_M (CACHE_L1_ICACHE1_FAIL_INT_CLR_V << CACHE_L1_ICACHE1_FAIL_INT_CLR_S) -#define CACHE_L1_ICACHE1_FAIL_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE1_FAIL_INT_CLR_S 1 -/** CACHE_L1_ICACHE2_FAIL_INT_CLR : WT; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_FAIL_INT_CLR (BIT(2)) -#define CACHE_L1_ICACHE2_FAIL_INT_CLR_M (CACHE_L1_ICACHE2_FAIL_INT_CLR_V << CACHE_L1_ICACHE2_FAIL_INT_CLR_S) -#define CACHE_L1_ICACHE2_FAIL_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE2_FAIL_INT_CLR_S 2 -/** CACHE_L1_ICACHE3_FAIL_INT_CLR : WT; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_FAIL_INT_CLR (BIT(3)) -#define CACHE_L1_ICACHE3_FAIL_INT_CLR_M (CACHE_L1_ICACHE3_FAIL_INT_CLR_V << CACHE_L1_ICACHE3_FAIL_INT_CLR_S) -#define CACHE_L1_ICACHE3_FAIL_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE3_FAIL_INT_CLR_S 3 /** CACHE_L1_CACHE_FAIL_INT_CLR : WT; bitpos: [4]; default: 0; - * The bit is used to clear interrupt of access fail that occurs in L1-DCache due to - * cpu accesses L1-DCache. + * Write 1 to clear L1_CACHE_FAIL_INT. */ #define CACHE_L1_CACHE_FAIL_INT_CLR (BIT(4)) #define CACHE_L1_CACHE_FAIL_INT_CLR_M (CACHE_L1_CACHE_FAIL_INT_CLR_V << CACHE_L1_CACHE_FAIL_INT_CLR_S) @@ -2720,39 +702,11 @@ extern "C" { #define CACHE_L1_CACHE_FAIL_INT_CLR_S 4 /** CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG register - * Cache Access Fail Interrupt raw register + * Cache access failed interrupt raw register */ #define CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x170) -/** CACHE_L1_ICACHE0_FAIL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-ICache0. - */ -#define CACHE_L1_ICACHE0_FAIL_INT_RAW (BIT(0)) -#define CACHE_L1_ICACHE0_FAIL_INT_RAW_M (CACHE_L1_ICACHE0_FAIL_INT_RAW_V << CACHE_L1_ICACHE0_FAIL_INT_RAW_S) -#define CACHE_L1_ICACHE0_FAIL_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE0_FAIL_INT_RAW_S 0 -/** CACHE_L1_ICACHE1_FAIL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-ICache1. - */ -#define CACHE_L1_ICACHE1_FAIL_INT_RAW (BIT(1)) -#define CACHE_L1_ICACHE1_FAIL_INT_RAW_M (CACHE_L1_ICACHE1_FAIL_INT_RAW_V << CACHE_L1_ICACHE1_FAIL_INT_RAW_S) -#define CACHE_L1_ICACHE1_FAIL_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE1_FAIL_INT_RAW_S 1 -/** CACHE_L1_ICACHE2_FAIL_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-ICache2. - */ -#define CACHE_L1_ICACHE2_FAIL_INT_RAW (BIT(2)) -#define CACHE_L1_ICACHE2_FAIL_INT_RAW_M (CACHE_L1_ICACHE2_FAIL_INT_RAW_V << CACHE_L1_ICACHE2_FAIL_INT_RAW_S) -#define CACHE_L1_ICACHE2_FAIL_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE2_FAIL_INT_RAW_S 2 -/** CACHE_L1_ICACHE3_FAIL_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-ICache3. - */ -#define CACHE_L1_ICACHE3_FAIL_INT_RAW (BIT(3)) -#define CACHE_L1_ICACHE3_FAIL_INT_RAW_M (CACHE_L1_ICACHE3_FAIL_INT_RAW_V << CACHE_L1_ICACHE3_FAIL_INT_RAW_S) -#define CACHE_L1_ICACHE3_FAIL_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE3_FAIL_INT_RAW_S 3 /** CACHE_L1_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-DCache. + * The raw interrupt status of L1_CACHE_FAIL_INT. */ #define CACHE_L1_CACHE_FAIL_INT_RAW (BIT(4)) #define CACHE_L1_CACHE_FAIL_INT_RAW_M (CACHE_L1_CACHE_FAIL_INT_RAW_V << CACHE_L1_CACHE_FAIL_INT_RAW_S) @@ -2760,42 +714,11 @@ extern "C" { #define CACHE_L1_CACHE_FAIL_INT_RAW_S 4 /** CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG register - * Cache Access Fail Interrupt status register + * Cache access failed interrupt status register */ #define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x174) -/** CACHE_L1_ICACHE0_FAIL_INT_ST : RO; bitpos: [0]; default: 0; - * The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due - * to cpu accesses L1-ICache. - */ -#define CACHE_L1_ICACHE0_FAIL_INT_ST (BIT(0)) -#define CACHE_L1_ICACHE0_FAIL_INT_ST_M (CACHE_L1_ICACHE0_FAIL_INT_ST_V << CACHE_L1_ICACHE0_FAIL_INT_ST_S) -#define CACHE_L1_ICACHE0_FAIL_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE0_FAIL_INT_ST_S 0 -/** CACHE_L1_ICACHE1_FAIL_INT_ST : RO; bitpos: [1]; default: 0; - * The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due - * to cpu accesses L1-ICache. - */ -#define CACHE_L1_ICACHE1_FAIL_INT_ST (BIT(1)) -#define CACHE_L1_ICACHE1_FAIL_INT_ST_M (CACHE_L1_ICACHE1_FAIL_INT_ST_V << CACHE_L1_ICACHE1_FAIL_INT_ST_S) -#define CACHE_L1_ICACHE1_FAIL_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE1_FAIL_INT_ST_S 1 -/** CACHE_L1_ICACHE2_FAIL_INT_ST : RO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_FAIL_INT_ST (BIT(2)) -#define CACHE_L1_ICACHE2_FAIL_INT_ST_M (CACHE_L1_ICACHE2_FAIL_INT_ST_V << CACHE_L1_ICACHE2_FAIL_INT_ST_S) -#define CACHE_L1_ICACHE2_FAIL_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE2_FAIL_INT_ST_S 2 -/** CACHE_L1_ICACHE3_FAIL_INT_ST : RO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_FAIL_INT_ST (BIT(3)) -#define CACHE_L1_ICACHE3_FAIL_INT_ST_M (CACHE_L1_ICACHE3_FAIL_INT_ST_V << CACHE_L1_ICACHE3_FAIL_INT_ST_S) -#define CACHE_L1_ICACHE3_FAIL_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE3_FAIL_INT_ST_S 3 /** CACHE_L1_CACHE_FAIL_INT_ST : RO; bitpos: [4]; default: 0; - * The bit indicates the interrupt status of access fail that occurs in L1-DCache due - * to cpu accesses L1-DCache. + * The masked interrupt status of L1_CACHE_FAIL_INT. */ #define CACHE_L1_CACHE_FAIL_INT_ST (BIT(4)) #define CACHE_L1_CACHE_FAIL_INT_ST_M (CACHE_L1_CACHE_FAIL_INT_ST_V << CACHE_L1_CACHE_FAIL_INT_ST_S) @@ -2803,324 +726,52 @@ extern "C" { #define CACHE_L1_CACHE_FAIL_INT_ST_S 4 /** CACHE_L1_CACHE_ACS_CNT_CTRL_REG register - * Cache Access Counter enable and clear register + * Cache access counter enable and clear register */ #define CACHE_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x178) -/** CACHE_L1_IBUS0_CNT_ENA : HRO; bitpos: [0]; default: 0; - * The bit is used to enable ibus0 counter in L1-ICache0. - */ -#define CACHE_L1_IBUS0_CNT_ENA (BIT(0)) -#define CACHE_L1_IBUS0_CNT_ENA_M (CACHE_L1_IBUS0_CNT_ENA_V << CACHE_L1_IBUS0_CNT_ENA_S) -#define CACHE_L1_IBUS0_CNT_ENA_V 0x00000001U -#define CACHE_L1_IBUS0_CNT_ENA_S 0 -/** CACHE_L1_IBUS1_CNT_ENA : HRO; bitpos: [1]; default: 0; - * The bit is used to enable ibus1 counter in L1-ICache1. - */ -#define CACHE_L1_IBUS1_CNT_ENA (BIT(1)) -#define CACHE_L1_IBUS1_CNT_ENA_M (CACHE_L1_IBUS1_CNT_ENA_V << CACHE_L1_IBUS1_CNT_ENA_S) -#define CACHE_L1_IBUS1_CNT_ENA_V 0x00000001U -#define CACHE_L1_IBUS1_CNT_ENA_S 1 -/** CACHE_L1_IBUS2_CNT_ENA : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_IBUS2_CNT_ENA (BIT(2)) -#define CACHE_L1_IBUS2_CNT_ENA_M (CACHE_L1_IBUS2_CNT_ENA_V << CACHE_L1_IBUS2_CNT_ENA_S) -#define CACHE_L1_IBUS2_CNT_ENA_V 0x00000001U -#define CACHE_L1_IBUS2_CNT_ENA_S 2 -/** CACHE_L1_IBUS3_CNT_ENA : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_IBUS3_CNT_ENA (BIT(3)) -#define CACHE_L1_IBUS3_CNT_ENA_M (CACHE_L1_IBUS3_CNT_ENA_V << CACHE_L1_IBUS3_CNT_ENA_S) -#define CACHE_L1_IBUS3_CNT_ENA_V 0x00000001U -#define CACHE_L1_IBUS3_CNT_ENA_S 3 /** CACHE_L1_BUS0_CNT_ENA : R/W; bitpos: [4]; default: 0; - * The bit is used to enable dbus0 counter in L1-DCache. + * Configures whether to enable the BUS0 counters in the L1 cache. + * 0: Disable + * 1: Enable */ #define CACHE_L1_BUS0_CNT_ENA (BIT(4)) #define CACHE_L1_BUS0_CNT_ENA_M (CACHE_L1_BUS0_CNT_ENA_V << CACHE_L1_BUS0_CNT_ENA_S) #define CACHE_L1_BUS0_CNT_ENA_V 0x00000001U #define CACHE_L1_BUS0_CNT_ENA_S 4 /** CACHE_L1_BUS1_CNT_ENA : R/W; bitpos: [5]; default: 0; - * The bit is used to enable dbus1 counter in L1-DCache. + * Configures whether to enable the BUS1 counters in the L1 cache. + * 0: Disable + * 1: Enable */ #define CACHE_L1_BUS1_CNT_ENA (BIT(5)) #define CACHE_L1_BUS1_CNT_ENA_M (CACHE_L1_BUS1_CNT_ENA_V << CACHE_L1_BUS1_CNT_ENA_S) #define CACHE_L1_BUS1_CNT_ENA_V 0x00000001U #define CACHE_L1_BUS1_CNT_ENA_S 5 -/** CACHE_L1_DBUS2_CNT_ENA : HRO; bitpos: [6]; default: 0; - * Reserved - */ -#define CACHE_L1_DBUS2_CNT_ENA (BIT(6)) -#define CACHE_L1_DBUS2_CNT_ENA_M (CACHE_L1_DBUS2_CNT_ENA_V << CACHE_L1_DBUS2_CNT_ENA_S) -#define CACHE_L1_DBUS2_CNT_ENA_V 0x00000001U -#define CACHE_L1_DBUS2_CNT_ENA_S 6 -/** CACHE_L1_DBUS3_CNT_ENA : HRO; bitpos: [7]; default: 0; - * Reserved - */ -#define CACHE_L1_DBUS3_CNT_ENA (BIT(7)) -#define CACHE_L1_DBUS3_CNT_ENA_M (CACHE_L1_DBUS3_CNT_ENA_V << CACHE_L1_DBUS3_CNT_ENA_S) -#define CACHE_L1_DBUS3_CNT_ENA_V 0x00000001U -#define CACHE_L1_DBUS3_CNT_ENA_S 7 -/** CACHE_L1_IBUS0_CNT_CLR : WT; bitpos: [16]; default: 0; - * The bit is used to clear ibus0 counter in L1-ICache0. - */ -#define CACHE_L1_IBUS0_CNT_CLR (BIT(16)) -#define CACHE_L1_IBUS0_CNT_CLR_M (CACHE_L1_IBUS0_CNT_CLR_V << CACHE_L1_IBUS0_CNT_CLR_S) -#define CACHE_L1_IBUS0_CNT_CLR_V 0x00000001U -#define CACHE_L1_IBUS0_CNT_CLR_S 16 -/** CACHE_L1_IBUS1_CNT_CLR : WT; bitpos: [17]; default: 0; - * The bit is used to clear ibus1 counter in L1-ICache1. - */ -#define CACHE_L1_IBUS1_CNT_CLR (BIT(17)) -#define CACHE_L1_IBUS1_CNT_CLR_M (CACHE_L1_IBUS1_CNT_CLR_V << CACHE_L1_IBUS1_CNT_CLR_S) -#define CACHE_L1_IBUS1_CNT_CLR_V 0x00000001U -#define CACHE_L1_IBUS1_CNT_CLR_S 17 -/** CACHE_L1_IBUS2_CNT_CLR : WT; bitpos: [18]; default: 0; - * Reserved - */ -#define CACHE_L1_IBUS2_CNT_CLR (BIT(18)) -#define CACHE_L1_IBUS2_CNT_CLR_M (CACHE_L1_IBUS2_CNT_CLR_V << CACHE_L1_IBUS2_CNT_CLR_S) -#define CACHE_L1_IBUS2_CNT_CLR_V 0x00000001U -#define CACHE_L1_IBUS2_CNT_CLR_S 18 -/** CACHE_L1_IBUS3_CNT_CLR : WT; bitpos: [19]; default: 0; - * Reserved - */ -#define CACHE_L1_IBUS3_CNT_CLR (BIT(19)) -#define CACHE_L1_IBUS3_CNT_CLR_M (CACHE_L1_IBUS3_CNT_CLR_V << CACHE_L1_IBUS3_CNT_CLR_S) -#define CACHE_L1_IBUS3_CNT_CLR_V 0x00000001U -#define CACHE_L1_IBUS3_CNT_CLR_S 19 /** CACHE_L1_BUS0_CNT_CLR : WT; bitpos: [20]; default: 0; - * The bit is used to clear dbus0 counter in L1-DCache. + * Configures whether to clear the BUS0 counters in the L1 cache. + * 0: Not clear + * 1: Clear */ #define CACHE_L1_BUS0_CNT_CLR (BIT(20)) #define CACHE_L1_BUS0_CNT_CLR_M (CACHE_L1_BUS0_CNT_CLR_V << CACHE_L1_BUS0_CNT_CLR_S) #define CACHE_L1_BUS0_CNT_CLR_V 0x00000001U #define CACHE_L1_BUS0_CNT_CLR_S 20 /** CACHE_L1_BUS1_CNT_CLR : WT; bitpos: [21]; default: 0; - * The bit is used to clear dbus1 counter in L1-DCache. + * Configures whether to clear the BUS1 counters in the L1 cache. + * 0: Not clear + * 1: Clear */ #define CACHE_L1_BUS1_CNT_CLR (BIT(21)) #define CACHE_L1_BUS1_CNT_CLR_M (CACHE_L1_BUS1_CNT_CLR_V << CACHE_L1_BUS1_CNT_CLR_S) #define CACHE_L1_BUS1_CNT_CLR_V 0x00000001U #define CACHE_L1_BUS1_CNT_CLR_S 21 -/** CACHE_L1_DBUS2_CNT_CLR : HRO; bitpos: [22]; default: 0; - * Reserved - */ -#define CACHE_L1_DBUS2_CNT_CLR (BIT(22)) -#define CACHE_L1_DBUS2_CNT_CLR_M (CACHE_L1_DBUS2_CNT_CLR_V << CACHE_L1_DBUS2_CNT_CLR_S) -#define CACHE_L1_DBUS2_CNT_CLR_V 0x00000001U -#define CACHE_L1_DBUS2_CNT_CLR_S 22 -/** CACHE_L1_DBUS3_CNT_CLR : HRO; bitpos: [23]; default: 0; - * Reserved - */ -#define CACHE_L1_DBUS3_CNT_CLR (BIT(23)) -#define CACHE_L1_DBUS3_CNT_CLR_M (CACHE_L1_DBUS3_CNT_CLR_V << CACHE_L1_DBUS3_CNT_CLR_S) -#define CACHE_L1_DBUS3_CNT_CLR_V 0x00000001U -#define CACHE_L1_DBUS3_CNT_CLR_S 23 - -/** CACHE_L1_IBUS0_ACS_HIT_CNT_REG register - * L1-ICache bus0 Hit-Access Counter register - */ -#define CACHE_L1_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x17c) -/** CACHE_L1_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus0 accesses L1-ICache0. - */ -#define CACHE_L1_IBUS0_HIT_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS0_HIT_CNT_M (CACHE_L1_IBUS0_HIT_CNT_V << CACHE_L1_IBUS0_HIT_CNT_S) -#define CACHE_L1_IBUS0_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS0_HIT_CNT_S 0 - -/** CACHE_L1_IBUS0_ACS_MISS_CNT_REG register - * L1-ICache bus0 Miss-Access Counter register - */ -#define CACHE_L1_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x180) -/** CACHE_L1_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus0 accesses L1-ICache0. - */ -#define CACHE_L1_IBUS0_MISS_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS0_MISS_CNT_M (CACHE_L1_IBUS0_MISS_CNT_V << CACHE_L1_IBUS0_MISS_CNT_S) -#define CACHE_L1_IBUS0_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS0_MISS_CNT_S 0 - -/** CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG register - * L1-ICache bus0 Conflict-Access Counter register - */ -#define CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x184) -/** CACHE_L1_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus0 accesses L1-ICache0. - */ -#define CACHE_L1_IBUS0_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS0_CONFLICT_CNT_M (CACHE_L1_IBUS0_CONFLICT_CNT_V << CACHE_L1_IBUS0_CONFLICT_CNT_S) -#define CACHE_L1_IBUS0_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS0_CONFLICT_CNT_S 0 - -/** CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG register - * L1-ICache bus0 Next-Level-Access Counter register - */ -#define CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x188) -/** CACHE_L1_IBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-ICache accesses L2-Cache due to - * bus0 accessing L1-ICache0. - */ -#define CACHE_L1_IBUS0_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_M (CACHE_L1_IBUS0_NXTLVL_RD_CNT_V << CACHE_L1_IBUS0_NXTLVL_RD_CNT_S) -#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_S 0 - -/** CACHE_L1_IBUS1_ACS_HIT_CNT_REG register - * L1-ICache bus1 Hit-Access Counter register - */ -#define CACHE_L1_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x18c) -/** CACHE_L1_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus1 accesses L1-ICache1. - */ -#define CACHE_L1_IBUS1_HIT_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS1_HIT_CNT_M (CACHE_L1_IBUS1_HIT_CNT_V << CACHE_L1_IBUS1_HIT_CNT_S) -#define CACHE_L1_IBUS1_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS1_HIT_CNT_S 0 - -/** CACHE_L1_IBUS1_ACS_MISS_CNT_REG register - * L1-ICache bus1 Miss-Access Counter register - */ -#define CACHE_L1_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x190) -/** CACHE_L1_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus1 accesses L1-ICache1. - */ -#define CACHE_L1_IBUS1_MISS_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS1_MISS_CNT_M (CACHE_L1_IBUS1_MISS_CNT_V << CACHE_L1_IBUS1_MISS_CNT_S) -#define CACHE_L1_IBUS1_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS1_MISS_CNT_S 0 - -/** CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG register - * L1-ICache bus1 Conflict-Access Counter register - */ -#define CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x194) -/** CACHE_L1_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus1 accesses L1-ICache1. - */ -#define CACHE_L1_IBUS1_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS1_CONFLICT_CNT_M (CACHE_L1_IBUS1_CONFLICT_CNT_V << CACHE_L1_IBUS1_CONFLICT_CNT_S) -#define CACHE_L1_IBUS1_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS1_CONFLICT_CNT_S 0 - -/** CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG register - * L1-ICache bus1 Next-Level-Access Counter register - */ -#define CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x198) -/** CACHE_L1_IBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-ICache accesses L2-Cache due to - * bus1 accessing L1-ICache1. - */ -#define CACHE_L1_IBUS1_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_M (CACHE_L1_IBUS1_NXTLVL_RD_CNT_V << CACHE_L1_IBUS1_NXTLVL_RD_CNT_S) -#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_S 0 - -/** CACHE_L1_IBUS2_ACS_HIT_CNT_REG register - * L1-ICache bus2 Hit-Access Counter register - */ -#define CACHE_L1_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x19c) -/** CACHE_L1_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus2 accesses L1-ICache2. - */ -#define CACHE_L1_IBUS2_HIT_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS2_HIT_CNT_M (CACHE_L1_IBUS2_HIT_CNT_V << CACHE_L1_IBUS2_HIT_CNT_S) -#define CACHE_L1_IBUS2_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS2_HIT_CNT_S 0 - -/** CACHE_L1_IBUS2_ACS_MISS_CNT_REG register - * L1-ICache bus2 Miss-Access Counter register - */ -#define CACHE_L1_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1a0) -/** CACHE_L1_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus2 accesses L1-ICache2. - */ -#define CACHE_L1_IBUS2_MISS_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS2_MISS_CNT_M (CACHE_L1_IBUS2_MISS_CNT_V << CACHE_L1_IBUS2_MISS_CNT_S) -#define CACHE_L1_IBUS2_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS2_MISS_CNT_S 0 - -/** CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG register - * L1-ICache bus2 Conflict-Access Counter register - */ -#define CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1a4) -/** CACHE_L1_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus2 accesses L1-ICache2. - */ -#define CACHE_L1_IBUS2_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS2_CONFLICT_CNT_M (CACHE_L1_IBUS2_CONFLICT_CNT_V << CACHE_L1_IBUS2_CONFLICT_CNT_S) -#define CACHE_L1_IBUS2_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS2_CONFLICT_CNT_S 0 - -/** CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_REG register - * L1-ICache bus2 Next-Level-Access Counter register - */ -#define CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1a8) -/** CACHE_L1_IBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-ICache accesses L2-Cache due to - * bus2 accessing L1-ICache2. - */ -#define CACHE_L1_IBUS2_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_M (CACHE_L1_IBUS2_NXTLVL_RD_CNT_V << CACHE_L1_IBUS2_NXTLVL_RD_CNT_S) -#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_S 0 - -/** CACHE_L1_IBUS3_ACS_HIT_CNT_REG register - * L1-ICache bus3 Hit-Access Counter register - */ -#define CACHE_L1_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1ac) -/** CACHE_L1_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus3 accesses L1-ICache3. - */ -#define CACHE_L1_IBUS3_HIT_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS3_HIT_CNT_M (CACHE_L1_IBUS3_HIT_CNT_V << CACHE_L1_IBUS3_HIT_CNT_S) -#define CACHE_L1_IBUS3_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS3_HIT_CNT_S 0 - -/** CACHE_L1_IBUS3_ACS_MISS_CNT_REG register - * L1-ICache bus3 Miss-Access Counter register - */ -#define CACHE_L1_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1b0) -/** CACHE_L1_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus3 accesses L1-ICache3. - */ -#define CACHE_L1_IBUS3_MISS_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS3_MISS_CNT_M (CACHE_L1_IBUS3_MISS_CNT_V << CACHE_L1_IBUS3_MISS_CNT_S) -#define CACHE_L1_IBUS3_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS3_MISS_CNT_S 0 - -/** CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG register - * L1-ICache bus3 Conflict-Access Counter register - */ -#define CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1b4) -/** CACHE_L1_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus3 accesses L1-ICache3. - */ -#define CACHE_L1_IBUS3_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS3_CONFLICT_CNT_M (CACHE_L1_IBUS3_CONFLICT_CNT_V << CACHE_L1_IBUS3_CONFLICT_CNT_S) -#define CACHE_L1_IBUS3_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS3_CONFLICT_CNT_S 0 - -/** CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_REG register - * L1-ICache bus3 Next-Level-Access Counter register - */ -#define CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1b8) -/** CACHE_L1_IBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-ICache accesses L2-Cache due to - * bus3 accessing L1-ICache3. - */ -#define CACHE_L1_IBUS3_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_M (CACHE_L1_IBUS3_NXTLVL_RD_CNT_V << CACHE_L1_IBUS3_NXTLVL_RD_CNT_S) -#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_S 0 /** CACHE_L1_BUS0_ACS_HIT_CNT_REG register - * L1-Cache bus0 Hit-Access Counter register + * L1 cache BUS0 hit-access counter register */ #define CACHE_L1_BUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1bc) /** CACHE_L1_BUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus0 accesses L1-Cache. + * Represents the number of hits when BUS0 accesses the L1 cache. */ #define CACHE_L1_BUS0_HIT_CNT 0xFFFFFFFFU #define CACHE_L1_BUS0_HIT_CNT_M (CACHE_L1_BUS0_HIT_CNT_V << CACHE_L1_BUS0_HIT_CNT_S) @@ -3128,11 +779,11 @@ extern "C" { #define CACHE_L1_BUS0_HIT_CNT_S 0 /** CACHE_L1_BUS0_ACS_MISS_CNT_REG register - * L1-Cache bus0 Miss-Access Counter register + * L1 cache BUS0 missed-access counter register */ #define CACHE_L1_BUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1c0) /** CACHE_L1_BUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus0 accesses L1-Cache. + * Represents the number of misses when BUS0 accesses the L1 cache. */ #define CACHE_L1_BUS0_MISS_CNT 0xFFFFFFFFU #define CACHE_L1_BUS0_MISS_CNT_M (CACHE_L1_BUS0_MISS_CNT_V << CACHE_L1_BUS0_MISS_CNT_S) @@ -3140,36 +791,37 @@ extern "C" { #define CACHE_L1_BUS0_MISS_CNT_S 0 /** CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG register - * L1-Cache bus0 Conflict-Access Counter register + * L1 cache BUS0 conflicting-access Counter register */ #define CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1c4) -/** CACHE_L1_BUS0_CONFLICT_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus0 accesses L1-Cache. +/** CACHE_L1_BUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * Represents the number of access conflicts when BUS0 accesses the L1 cache. */ -#define CACHE_L1_BUS0_CONFLICT_RD_CNT 0xFFFFFFFFU -#define CACHE_L1_BUS0_CONFLICT_RD_CNT_M (CACHE_L1_BUS0_CONFLICT_RD_CNT_V << CACHE_L1_BUS0_CONFLICT_RD_CNT_S) -#define CACHE_L1_BUS0_CONFLICT_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L1_BUS0_CONFLICT_RD_CNT_S 0 +#define CACHE_L1_BUS0_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_CONFLICT_CNT_M (CACHE_L1_BUS0_CONFLICT_CNT_V << CACHE_L1_BUS0_CONFLICT_CNT_S) +#define CACHE_L1_BUS0_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_CONFLICT_CNT_S 0 -/** CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG register - * L1-Cache bus0 Next-Level-Access Counter register +/** CACHE_L1_BUS0_ACS_NXTLVL_RD_CNT_REG register + * L1 cache BUS0 reads the lower-level memory */ -#define CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1c8) +#define CACHE_L1_BUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1c8) /** CACHE_L1_BUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-Cache accesses L2-Cache due to - * bus0 accessing L1-Cache. + * Represents the number of times that the cache accesses its lower-level module due + * to BUS0's read access. */ #define CACHE_L1_BUS0_NXTLVL_RD_CNT 0xFFFFFFFFU #define CACHE_L1_BUS0_NXTLVL_RD_CNT_M (CACHE_L1_BUS0_NXTLVL_RD_CNT_V << CACHE_L1_BUS0_NXTLVL_RD_CNT_S) #define CACHE_L1_BUS0_NXTLVL_RD_CNT_V 0xFFFFFFFFU #define CACHE_L1_BUS0_NXTLVL_RD_CNT_S 0 -/** CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG register - * L1-DCache bus0 WB-Access Counter register +/** CACHE_L1_BUS0_ACS_NXTLVL_WR_CNT_REG register + * L1 cache BUS0 writes the lower-level memory */ -#define CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1cc) +#define CACHE_L1_BUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1cc) /** CACHE_L1_BUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when bus0 accesses L1-Cache. + * Represents the number of times that the cache accesses its lower-level module due + * to BUS0's write access. */ #define CACHE_L1_BUS0_NXTLVL_WR_CNT 0xFFFFFFFFU #define CACHE_L1_BUS0_NXTLVL_WR_CNT_M (CACHE_L1_BUS0_NXTLVL_WR_CNT_V << CACHE_L1_BUS0_NXTLVL_WR_CNT_S) @@ -3177,11 +829,11 @@ extern "C" { #define CACHE_L1_BUS0_NXTLVL_WR_CNT_S 0 /** CACHE_L1_BUS1_ACS_HIT_CNT_REG register - * L1-Cache bus1 Hit-Access Counter register + * L1 cache BUS1 hit-access counter register */ #define CACHE_L1_BUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1d0) /** CACHE_L1_BUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus1 accesses L1-Cache. + * Represents the number of hits when BUS1 accesses the L1 cache. */ #define CACHE_L1_BUS1_HIT_CNT 0xFFFFFFFFU #define CACHE_L1_BUS1_HIT_CNT_M (CACHE_L1_BUS1_HIT_CNT_V << CACHE_L1_BUS1_HIT_CNT_S) @@ -3189,11 +841,11 @@ extern "C" { #define CACHE_L1_BUS1_HIT_CNT_S 0 /** CACHE_L1_BUS1_ACS_MISS_CNT_REG register - * L1-Cache bus1 Miss-Access Counter register + * L1 cache BUS1 missed-access counter register */ #define CACHE_L1_BUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1d4) /** CACHE_L1_BUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus1 accesses L1-Cache. + * Represents the number of misses when BUS1 accesses the L1 cache. */ #define CACHE_L1_BUS1_MISS_CNT 0xFFFFFFFFU #define CACHE_L1_BUS1_MISS_CNT_M (CACHE_L1_BUS1_MISS_CNT_V << CACHE_L1_BUS1_MISS_CNT_S) @@ -3201,11 +853,11 @@ extern "C" { #define CACHE_L1_BUS1_MISS_CNT_S 0 /** CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG register - * L1-Cache bus1 Conflict-Access Counter register + * L1 cache BUS1 conflicting-access counter register */ #define CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1d8) /** CACHE_L1_BUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus1 accesses L1-Cache. + * Represents the number of access conflicts when BUS1 accesses the L1 cache. */ #define CACHE_L1_BUS1_CONFLICT_CNT 0xFFFFFFFFU #define CACHE_L1_BUS1_CONFLICT_CNT_M (CACHE_L1_BUS1_CONFLICT_CNT_V << CACHE_L1_BUS1_CONFLICT_CNT_S) @@ -3213,301 +865,63 @@ extern "C" { #define CACHE_L1_BUS1_CONFLICT_CNT_S 0 /** CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG register - * L1-DCache bus1 Next-Level-Access Counter register + * L1 cache BUS1 reads the lower-level memory */ #define CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1dc) -/** CACHE_L1_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-Cache accesses L2-Cache due to - * bus1 accessing L1-Cache. +/** CACHE_L1_BUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * Represents the number of times that the cache accesses its lower-level module due + * to BUS1's read access. */ -#define CACHE_L1_DBUS1_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_M (CACHE_L1_DBUS1_NXTLVL_RD_CNT_V << CACHE_L1_DBUS1_NXTLVL_RD_CNT_S) -#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_S 0 +#define CACHE_L1_BUS1_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS1_NXTLVL_RD_CNT_M (CACHE_L1_BUS1_NXTLVL_RD_CNT_V << CACHE_L1_BUS1_NXTLVL_RD_CNT_S) +#define CACHE_L1_BUS1_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS1_NXTLVL_RD_CNT_S 0 /** CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG register - * L1-DCache bus1 WB-Access Counter register + * L1 cache BUS1 writes the lower-level memory */ #define CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1e0) -/** CACHE_L1_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when bus1 accesses L1-Cache. +/** CACHE_L1_BUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; + * Represents the number of times that the cache accesses its lower-level module due + * to BUS1's write access. */ -#define CACHE_L1_DBUS1_NXTLVL_WR_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_M (CACHE_L1_DBUS1_NXTLVL_WR_CNT_V << CACHE_L1_DBUS1_NXTLVL_WR_CNT_S) -#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_S 0 +#define CACHE_L1_BUS1_NXTLVL_WR_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS1_NXTLVL_WR_CNT_M (CACHE_L1_BUS1_NXTLVL_WR_CNT_V << CACHE_L1_BUS1_NXTLVL_WR_CNT_S) +#define CACHE_L1_BUS1_NXTLVL_WR_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS1_NXTLVL_WR_CNT_S 0 -/** CACHE_L1_DBUS2_ACS_HIT_CNT_REG register - * L1-DCache bus2 Hit-Access Counter register +/** CACHE_L1_CACHE_ACS_FAIL_ID_ATTR_REG register + * L1 cache access failed ID and attribution recording register */ -#define CACHE_L1_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1e4) -/** CACHE_L1_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus2 accesses L1-DCache. - */ -#define CACHE_L1_DBUS2_HIT_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS2_HIT_CNT_M (CACHE_L1_DBUS2_HIT_CNT_V << CACHE_L1_DBUS2_HIT_CNT_S) -#define CACHE_L1_DBUS2_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS2_HIT_CNT_S 0 - -/** CACHE_L1_DBUS2_ACS_MISS_CNT_REG register - * L1-DCache bus2 Miss-Access Counter register - */ -#define CACHE_L1_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1e8) -/** CACHE_L1_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus2 accesses L1-DCache. - */ -#define CACHE_L1_DBUS2_MISS_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS2_MISS_CNT_M (CACHE_L1_DBUS2_MISS_CNT_V << CACHE_L1_DBUS2_MISS_CNT_S) -#define CACHE_L1_DBUS2_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS2_MISS_CNT_S 0 - -/** CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG register - * L1-DCache bus2 Conflict-Access Counter register - */ -#define CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1ec) -/** CACHE_L1_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus2 accesses L1-DCache. - */ -#define CACHE_L1_DBUS2_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS2_CONFLICT_CNT_M (CACHE_L1_DBUS2_CONFLICT_CNT_V << CACHE_L1_DBUS2_CONFLICT_CNT_S) -#define CACHE_L1_DBUS2_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS2_CONFLICT_CNT_S 0 - -/** CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_REG register - * L1-DCache bus2 Next-Level-Access Counter register - */ -#define CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1f0) -/** CACHE_L1_DBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-Cache accesses L2-Cache due to - * bus2 accessing L1-Cache. - */ -#define CACHE_L1_DBUS2_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_M (CACHE_L1_DBUS2_NXTLVL_RD_CNT_V << CACHE_L1_DBUS2_NXTLVL_RD_CNT_S) -#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_S 0 - -/** CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_REG register - * L1-DCache bus2 WB-Access Counter register - */ -#define CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1f4) -/** CACHE_L1_DBUS2_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when bus2 accesses L1-Cache. - */ -#define CACHE_L1_DBUS2_NXTLVL_WR_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_M (CACHE_L1_DBUS2_NXTLVL_WR_CNT_V << CACHE_L1_DBUS2_NXTLVL_WR_CNT_S) -#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_S 0 - -/** CACHE_L1_DBUS3_ACS_HIT_CNT_REG register - * L1-DCache bus3 Hit-Access Counter register - */ -#define CACHE_L1_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1f8) -/** CACHE_L1_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus3 accesses L1-DCache. - */ -#define CACHE_L1_DBUS3_HIT_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS3_HIT_CNT_M (CACHE_L1_DBUS3_HIT_CNT_V << CACHE_L1_DBUS3_HIT_CNT_S) -#define CACHE_L1_DBUS3_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS3_HIT_CNT_S 0 - -/** CACHE_L1_DBUS3_ACS_MISS_CNT_REG register - * L1-DCache bus3 Miss-Access Counter register - */ -#define CACHE_L1_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1fc) -/** CACHE_L1_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus3 accesses L1-DCache. - */ -#define CACHE_L1_DBUS3_MISS_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS3_MISS_CNT_M (CACHE_L1_DBUS3_MISS_CNT_V << CACHE_L1_DBUS3_MISS_CNT_S) -#define CACHE_L1_DBUS3_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS3_MISS_CNT_S 0 - -/** CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG register - * L1-DCache bus3 Conflict-Access Counter register - */ -#define CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x200) -/** CACHE_L1_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus3 accesses L1-DCache. - */ -#define CACHE_L1_DBUS3_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS3_CONFLICT_CNT_M (CACHE_L1_DBUS3_CONFLICT_CNT_V << CACHE_L1_DBUS3_CONFLICT_CNT_S) -#define CACHE_L1_DBUS3_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS3_CONFLICT_CNT_S 0 - -/** CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_REG register - * L1-DCache bus3 Next-Level-Access Counter register - */ -#define CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x204) -/** CACHE_L1_DBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-Cache accesses L2-Cache due to - * bus3 accessing L1-Cache. - */ -#define CACHE_L1_DBUS3_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_M (CACHE_L1_DBUS3_NXTLVL_RD_CNT_V << CACHE_L1_DBUS3_NXTLVL_RD_CNT_S) -#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_S 0 - -/** CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_REG register - * L1-DCache bus3 WB-Access Counter register - */ -#define CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x208) -/** CACHE_L1_DBUS3_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when bus0 accesses L1-Cache. - */ -#define CACHE_L1_DBUS3_NXTLVL_WR_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_M (CACHE_L1_DBUS3_NXTLVL_WR_CNT_V << CACHE_L1_DBUS3_NXTLVL_WR_CNT_S) -#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_S 0 - -/** CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG register - * L1-ICache0 Access Fail ID/attribution information register - */ -#define CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x20c) -/** CACHE_L1_ICACHE0_FAIL_ID : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache0 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE0_FAIL_ID 0x0000FFFFU -#define CACHE_L1_ICACHE0_FAIL_ID_M (CACHE_L1_ICACHE0_FAIL_ID_V << CACHE_L1_ICACHE0_FAIL_ID_S) -#define CACHE_L1_ICACHE0_FAIL_ID_V 0x0000FFFFU -#define CACHE_L1_ICACHE0_FAIL_ID_S 0 -/** CACHE_L1_ICACHE0_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache0 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE0_FAIL_ATTR 0x0000FFFFU -#define CACHE_L1_ICACHE0_FAIL_ATTR_M (CACHE_L1_ICACHE0_FAIL_ATTR_V << CACHE_L1_ICACHE0_FAIL_ATTR_S) -#define CACHE_L1_ICACHE0_FAIL_ATTR_V 0x0000FFFFU -#define CACHE_L1_ICACHE0_FAIL_ATTR_S 16 - -/** CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG register - * L1-ICache0 Access Fail Address information register - */ -#define CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x210) -/** CACHE_L1_ICACHE0_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache0 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE0_FAIL_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_FAIL_ADDR_M (CACHE_L1_ICACHE0_FAIL_ADDR_V << CACHE_L1_ICACHE0_FAIL_ADDR_S) -#define CACHE_L1_ICACHE0_FAIL_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_FAIL_ADDR_S 0 - -/** CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG register - * L1-ICache0 Access Fail ID/attribution information register - */ -#define CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x214) -/** CACHE_L1_ICACHE1_FAIL_ID : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache1 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE1_FAIL_ID 0x0000FFFFU -#define CACHE_L1_ICACHE1_FAIL_ID_M (CACHE_L1_ICACHE1_FAIL_ID_V << CACHE_L1_ICACHE1_FAIL_ID_S) -#define CACHE_L1_ICACHE1_FAIL_ID_V 0x0000FFFFU -#define CACHE_L1_ICACHE1_FAIL_ID_S 0 -/** CACHE_L1_ICACHE1_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache1 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE1_FAIL_ATTR 0x0000FFFFU -#define CACHE_L1_ICACHE1_FAIL_ATTR_M (CACHE_L1_ICACHE1_FAIL_ATTR_V << CACHE_L1_ICACHE1_FAIL_ATTR_S) -#define CACHE_L1_ICACHE1_FAIL_ATTR_V 0x0000FFFFU -#define CACHE_L1_ICACHE1_FAIL_ATTR_S 16 - -/** CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG register - * L1-ICache0 Access Fail Address information register - */ -#define CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x218) -/** CACHE_L1_ICACHE1_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache1 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE1_FAIL_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_FAIL_ADDR_M (CACHE_L1_ICACHE1_FAIL_ADDR_V << CACHE_L1_ICACHE1_FAIL_ADDR_S) -#define CACHE_L1_ICACHE1_FAIL_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_FAIL_ADDR_S 0 - -/** CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG register - * L1-ICache0 Access Fail ID/attribution information register - */ -#define CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x21c) -/** CACHE_L1_ICACHE2_FAIL_ID : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache2 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE2_FAIL_ID 0x0000FFFFU -#define CACHE_L1_ICACHE2_FAIL_ID_M (CACHE_L1_ICACHE2_FAIL_ID_V << CACHE_L1_ICACHE2_FAIL_ID_S) -#define CACHE_L1_ICACHE2_FAIL_ID_V 0x0000FFFFU -#define CACHE_L1_ICACHE2_FAIL_ID_S 0 -/** CACHE_L1_ICACHE2_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache2 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE2_FAIL_ATTR 0x0000FFFFU -#define CACHE_L1_ICACHE2_FAIL_ATTR_M (CACHE_L1_ICACHE2_FAIL_ATTR_V << CACHE_L1_ICACHE2_FAIL_ATTR_S) -#define CACHE_L1_ICACHE2_FAIL_ATTR_V 0x0000FFFFU -#define CACHE_L1_ICACHE2_FAIL_ATTR_S 16 - -/** CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG register - * L1-ICache0 Access Fail Address information register - */ -#define CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x220) -/** CACHE_L1_ICACHE2_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache2 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE2_FAIL_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_FAIL_ADDR_M (CACHE_L1_ICACHE2_FAIL_ADDR_V << CACHE_L1_ICACHE2_FAIL_ADDR_S) -#define CACHE_L1_ICACHE2_FAIL_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_FAIL_ADDR_S 0 - -/** CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG register - * L1-ICache0 Access Fail ID/attribution information register - */ -#define CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x224) -/** CACHE_L1_ICACHE3_FAIL_ID : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache3 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE3_FAIL_ID 0x0000FFFFU -#define CACHE_L1_ICACHE3_FAIL_ID_M (CACHE_L1_ICACHE3_FAIL_ID_V << CACHE_L1_ICACHE3_FAIL_ID_S) -#define CACHE_L1_ICACHE3_FAIL_ID_V 0x0000FFFFU -#define CACHE_L1_ICACHE3_FAIL_ID_S 0 -/** CACHE_L1_ICACHE3_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache3 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE3_FAIL_ATTR 0x0000FFFFU -#define CACHE_L1_ICACHE3_FAIL_ATTR_M (CACHE_L1_ICACHE3_FAIL_ATTR_V << CACHE_L1_ICACHE3_FAIL_ATTR_S) -#define CACHE_L1_ICACHE3_FAIL_ATTR_V 0x0000FFFFU -#define CACHE_L1_ICACHE3_FAIL_ATTR_S 16 - -/** CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG register - * L1-ICache0 Access Fail Address information register - */ -#define CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x228) -/** CACHE_L1_ICACHE3_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache3 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE3_FAIL_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_FAIL_ADDR_M (CACHE_L1_ICACHE3_FAIL_ADDR_V << CACHE_L1_ICACHE3_FAIL_ADDR_S) -#define CACHE_L1_ICACHE3_FAIL_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_FAIL_ADDR_S 0 - -/** CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG register - * L1-Cache Access Fail ID/attribution information register - */ -#define CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x22c) +#define CACHE_L1_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x22c) /** CACHE_L1_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache accesses L1-Cache. + * Represents the ID of the failed access to the L1 cache. + * Bit 4: BUS0 + * Bit 5: BUS1 + * Others: reserved */ #define CACHE_L1_CACHE_FAIL_ID 0x0000FFFFU #define CACHE_L1_CACHE_FAIL_ID_M (CACHE_L1_CACHE_FAIL_ID_V << CACHE_L1_CACHE_FAIL_ID_S) #define CACHE_L1_CACHE_FAIL_ID_V 0x0000FFFFU #define CACHE_L1_CACHE_FAIL_ID_S 0 /** CACHE_L1_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache accesses L1-Cache. + * Represents the attribute of the failed access to the L1 cache. + * Bit 0: Fetching instructions + * Bit 1: Reading data + * Bit 7: non-cacheable + * Others: reserved */ #define CACHE_L1_CACHE_FAIL_ATTR 0x0000FFFFU #define CACHE_L1_CACHE_FAIL_ATTR_M (CACHE_L1_CACHE_FAIL_ATTR_V << CACHE_L1_CACHE_FAIL_ATTR_S) #define CACHE_L1_CACHE_FAIL_ATTR_V 0x0000FFFFU #define CACHE_L1_CACHE_FAIL_ATTR_S 16 -/** CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG register - * L1-Cache Access Fail Address information register +/** CACHE_L1_CACHE_ACS_FAIL_ADDR_REG register + * L1 cache access failed address information register */ -#define CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x230) +#define CACHE_L1_CACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x230) /** CACHE_L1_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache accesses L1-Cache. + * Represents the address of the failed access to the L1 cache. */ #define CACHE_L1_CACHE_FAIL_ADDR 0xFFFFFFFFU #define CACHE_L1_CACHE_FAIL_ADDR_M (CACHE_L1_CACHE_FAIL_ADDR_V << CACHE_L1_CACHE_FAIL_ADDR_S) @@ -3515,91 +929,32 @@ extern "C" { #define CACHE_L1_CACHE_FAIL_ADDR_S 0 /** CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG register - * L1-Cache Access Fail Interrupt enable register + * Sync and preloading operation interrupt enable register */ #define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x234) -/** CACHE_L1_ICACHE0_PLD_DONE_INT_ENA : HRO; bitpos: [0]; default: 0; - * The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload - * operation is done, interrupt occurs. - */ -#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA (BIT(0)) -#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_M (CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S) -#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S 0 -/** CACHE_L1_ICACHE1_PLD_DONE_INT_ENA : HRO; bitpos: [1]; default: 0; - * The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload - * operation is done, interrupt occurs. - */ -#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA (BIT(1)) -#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_M (CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S) -#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S 1 -/** CACHE_L1_ICACHE2_PLD_DONE_INT_ENA : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA (BIT(2)) -#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_M (CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S) -#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S 2 -/** CACHE_L1_ICACHE3_PLD_DONE_INT_ENA : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA (BIT(3)) -#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_M (CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S) -#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S 3 /** CACHE_L1_CACHE_PLD_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt of L1-Cache preload-operation. If preload - * operation is done, interrupt occurs. + * Write 1 to enable L1_CACHE_PLD_DONE_INT. */ #define CACHE_L1_CACHE_PLD_DONE_INT_ENA (BIT(4)) #define CACHE_L1_CACHE_PLD_DONE_INT_ENA_M (CACHE_L1_CACHE_PLD_DONE_INT_ENA_V << CACHE_L1_CACHE_PLD_DONE_INT_ENA_S) #define CACHE_L1_CACHE_PLD_DONE_INT_ENA_V 0x00000001U #define CACHE_L1_CACHE_PLD_DONE_INT_ENA_S 4 /** CACHE_SYNC_DONE_INT_ENA : R/W; bitpos: [6]; default: 0; - * The bit is used to enable interrupt of Cache sync-operation done. + * Write 1 to enable CACHE_SYNC_DONE_INT. */ #define CACHE_SYNC_DONE_INT_ENA (BIT(6)) #define CACHE_SYNC_DONE_INT_ENA_M (CACHE_SYNC_DONE_INT_ENA_V << CACHE_SYNC_DONE_INT_ENA_S) #define CACHE_SYNC_DONE_INT_ENA_V 0x00000001U #define CACHE_SYNC_DONE_INT_ENA_S 6 -/** CACHE_L1_ICACHE0_PLD_ERR_INT_ENA : HRO; bitpos: [7]; default: 0; - * The bit is used to enable interrupt of L1-ICache0 preload-operation error. - */ -#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA (BIT(7)) -#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_M (CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S) -#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S 7 -/** CACHE_L1_ICACHE1_PLD_ERR_INT_ENA : HRO; bitpos: [8]; default: 0; - * The bit is used to enable interrupt of L1-ICache1 preload-operation error. - */ -#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA (BIT(8)) -#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_M (CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S) -#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S 8 -/** CACHE_L1_ICACHE2_PLD_ERR_INT_ENA : HRO; bitpos: [9]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA (BIT(9)) -#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_M (CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S) -#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S 9 -/** CACHE_L1_ICACHE3_PLD_ERR_INT_ENA : HRO; bitpos: [10]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA (BIT(10)) -#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_M (CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S) -#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S 10 /** CACHE_L1_CACHE_PLD_ERR_INT_ENA : R/W; bitpos: [11]; default: 0; - * The bit is used to enable interrupt of L1-Cache preload-operation error. + * Write 1 to enable CACHE_PLD_ERR_INT. */ #define CACHE_L1_CACHE_PLD_ERR_INT_ENA (BIT(11)) #define CACHE_L1_CACHE_PLD_ERR_INT_ENA_M (CACHE_L1_CACHE_PLD_ERR_INT_ENA_V << CACHE_L1_CACHE_PLD_ERR_INT_ENA_S) #define CACHE_L1_CACHE_PLD_ERR_INT_ENA_V 0x00000001U #define CACHE_L1_CACHE_PLD_ERR_INT_ENA_S 11 /** CACHE_SYNC_ERR_INT_ENA : R/W; bitpos: [13]; default: 0; - * The bit is used to enable interrupt of Cache sync-operation error. + * Write 1 to enable CACHE_SYNC_ERR_INT. */ #define CACHE_SYNC_ERR_INT_ENA (BIT(13)) #define CACHE_SYNC_ERR_INT_ENA_M (CACHE_SYNC_ERR_INT_ENA_V << CACHE_SYNC_ERR_INT_ENA_S) @@ -3607,92 +962,32 @@ extern "C" { #define CACHE_SYNC_ERR_INT_ENA_S 13 /** CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG register - * Sync Preload operation Interrupt clear register + * Sync and preloading operation interrupt clear register */ #define CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x238) -/** CACHE_L1_ICACHE0_PLD_DONE_INT_CLR : HRO; bitpos: [0]; default: 0; - * The bit is used to clear interrupt that occurs only when L1-ICache0 - * preload-operation is done. - */ -#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR (BIT(0)) -#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_M (CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S) -#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S 0 -/** CACHE_L1_ICACHE1_PLD_DONE_INT_CLR : HRO; bitpos: [1]; default: 0; - * The bit is used to clear interrupt that occurs only when L1-ICache1 - * preload-operation is done. - */ -#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR (BIT(1)) -#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_M (CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S) -#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S 1 -/** CACHE_L1_ICACHE2_PLD_DONE_INT_CLR : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR (BIT(2)) -#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_M (CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S) -#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S 2 -/** CACHE_L1_ICACHE3_PLD_DONE_INT_CLR : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR (BIT(3)) -#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_M (CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S) -#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S 3 /** CACHE_L1_CACHE_PLD_DONE_INT_CLR : WT; bitpos: [4]; default: 0; - * The bit is used to clear interrupt that occurs only when L1-Cache preload-operation - * is done. + * Write 1 to clear L1_CACHE_PLD_DONE_INT. */ #define CACHE_L1_CACHE_PLD_DONE_INT_CLR (BIT(4)) #define CACHE_L1_CACHE_PLD_DONE_INT_CLR_M (CACHE_L1_CACHE_PLD_DONE_INT_CLR_V << CACHE_L1_CACHE_PLD_DONE_INT_CLR_S) #define CACHE_L1_CACHE_PLD_DONE_INT_CLR_V 0x00000001U #define CACHE_L1_CACHE_PLD_DONE_INT_CLR_S 4 /** CACHE_SYNC_DONE_INT_CLR : WT; bitpos: [6]; default: 0; - * The bit is used to clear interrupt that occurs only when Cache sync-operation is - * done. + * Write 1 to clear CACHE_SYNC_DONE_INT. */ #define CACHE_SYNC_DONE_INT_CLR (BIT(6)) #define CACHE_SYNC_DONE_INT_CLR_M (CACHE_SYNC_DONE_INT_CLR_V << CACHE_SYNC_DONE_INT_CLR_S) #define CACHE_SYNC_DONE_INT_CLR_V 0x00000001U #define CACHE_SYNC_DONE_INT_CLR_S 6 -/** CACHE_L1_ICACHE0_PLD_ERR_INT_CLR : HRO; bitpos: [7]; default: 0; - * The bit is used to clear interrupt of L1-ICache0 preload-operation error. - */ -#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR (BIT(7)) -#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_M (CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S) -#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S 7 -/** CACHE_L1_ICACHE1_PLD_ERR_INT_CLR : HRO; bitpos: [8]; default: 0; - * The bit is used to clear interrupt of L1-ICache1 preload-operation error. - */ -#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR (BIT(8)) -#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_M (CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S) -#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S 8 -/** CACHE_L1_ICACHE2_PLD_ERR_INT_CLR : HRO; bitpos: [9]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR (BIT(9)) -#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_M (CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S) -#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S 9 -/** CACHE_L1_ICACHE3_PLD_ERR_INT_CLR : HRO; bitpos: [10]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR (BIT(10)) -#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_M (CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S) -#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S 10 /** CACHE_L1_CACHE_PLD_ERR_INT_CLR : WT; bitpos: [11]; default: 0; - * The bit is used to clear interrupt of L1-Cache preload-operation error. + * Write 1 to clear L1_CACHE_PLD_ERR_INT. */ #define CACHE_L1_CACHE_PLD_ERR_INT_CLR (BIT(11)) #define CACHE_L1_CACHE_PLD_ERR_INT_CLR_M (CACHE_L1_CACHE_PLD_ERR_INT_CLR_V << CACHE_L1_CACHE_PLD_ERR_INT_CLR_S) #define CACHE_L1_CACHE_PLD_ERR_INT_CLR_V 0x00000001U #define CACHE_L1_CACHE_PLD_ERR_INT_CLR_S 11 /** CACHE_SYNC_ERR_INT_CLR : WT; bitpos: [13]; default: 0; - * The bit is used to clear interrupt of Cache sync-operation error. + * Write 1 to clear CACHE_SYNC_ERR_INT. */ #define CACHE_SYNC_ERR_INT_CLR (BIT(13)) #define CACHE_SYNC_ERR_INT_CLR_M (CACHE_SYNC_ERR_INT_CLR_V << CACHE_SYNC_ERR_INT_CLR_S) @@ -3700,95 +995,32 @@ extern "C" { #define CACHE_SYNC_ERR_INT_CLR_S 13 /** CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG register - * Sync Preload operation Interrupt raw register + * Sync and preloading operation interrupt raw register */ #define CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x23c) -/** CACHE_L1_ICACHE0_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is - * done. - */ -#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW (BIT(0)) -#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_M (CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S) -#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S 0 -/** CACHE_L1_ICACHE1_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is - * done. - */ -#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW (BIT(1)) -#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_M (CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S) -#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S 1 -/** CACHE_L1_ICACHE2_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW (BIT(2)) -#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_M (CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S) -#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S 2 -/** CACHE_L1_ICACHE3_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW (BIT(3)) -#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_M (CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S) -#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S 3 /** CACHE_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit of the interrupt that occurs only when L1-Cache preload-operation is - * done. + * The raw interrupt status of L1_CACHE_PLD_DONE_INT. */ #define CACHE_L1_CACHE_PLD_DONE_INT_RAW (BIT(4)) #define CACHE_L1_CACHE_PLD_DONE_INT_RAW_M (CACHE_L1_CACHE_PLD_DONE_INT_RAW_V << CACHE_L1_CACHE_PLD_DONE_INT_RAW_S) #define CACHE_L1_CACHE_PLD_DONE_INT_RAW_V 0x00000001U #define CACHE_L1_CACHE_PLD_DONE_INT_RAW_S 4 /** CACHE_SYNC_DONE_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit of the interrupt that occurs only when Cache sync-operation is done. + * The raw interrupt status of CACHE_SYNC_DONE_INT. */ #define CACHE_SYNC_DONE_INT_RAW (BIT(6)) #define CACHE_SYNC_DONE_INT_RAW_M (CACHE_SYNC_DONE_INT_RAW_V << CACHE_SYNC_DONE_INT_RAW_S) #define CACHE_SYNC_DONE_INT_RAW_V 0x00000001U #define CACHE_SYNC_DONE_INT_RAW_S 6 -/** CACHE_L1_ICACHE0_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation - * error occurs. - */ -#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW (BIT(7)) -#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_M (CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S) -#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S 7 -/** CACHE_L1_ICACHE1_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation - * error occurs. - */ -#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW (BIT(8)) -#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_M (CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S) -#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S 8 -/** CACHE_L1_ICACHE2_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW (BIT(9)) -#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_M (CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S) -#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S 9 -/** CACHE_L1_ICACHE3_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW (BIT(10)) -#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_M (CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S) -#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S 10 /** CACHE_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw bit of the interrupt that occurs only when L1-Cache preload-operation error - * occurs. + * The raw interrupt status of L1_CACHE_PLD_ERR_INT. */ #define CACHE_L1_CACHE_PLD_ERR_INT_RAW (BIT(11)) #define CACHE_L1_CACHE_PLD_ERR_INT_RAW_M (CACHE_L1_CACHE_PLD_ERR_INT_RAW_V << CACHE_L1_CACHE_PLD_ERR_INT_RAW_S) #define CACHE_L1_CACHE_PLD_ERR_INT_RAW_V 0x00000001U #define CACHE_L1_CACHE_PLD_ERR_INT_RAW_S 11 /** CACHE_SYNC_ERR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * The raw bit of the interrupt that occurs only when Cache sync-operation error - * occurs. + * The raw interrupt status of CACHE_SYNC_ERR_INT. */ #define CACHE_SYNC_ERR_INT_RAW (BIT(13)) #define CACHE_SYNC_ERR_INT_RAW_M (CACHE_SYNC_ERR_INT_RAW_V << CACHE_SYNC_ERR_INT_RAW_S) @@ -3796,92 +1028,32 @@ extern "C" { #define CACHE_SYNC_ERR_INT_RAW_S 13 /** CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG register - * L1-Cache Access Fail Interrupt status register + * Sync and preloading operation interrupt status register */ #define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x240) -/** CACHE_L1_ICACHE0_PLD_DONE_INT_ST : HRO; bitpos: [0]; default: 0; - * The bit indicates the status of the interrupt that occurs only when L1-ICache0 - * preload-operation is done. - */ -#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST (BIT(0)) -#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_M (CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S) -#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S 0 -/** CACHE_L1_ICACHE1_PLD_DONE_INT_ST : HRO; bitpos: [1]; default: 0; - * The bit indicates the status of the interrupt that occurs only when L1-ICache1 - * preload-operation is done. - */ -#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST (BIT(1)) -#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_M (CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S) -#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S 1 -/** CACHE_L1_ICACHE2_PLD_DONE_INT_ST : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST (BIT(2)) -#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_M (CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S) -#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S 2 -/** CACHE_L1_ICACHE3_PLD_DONE_INT_ST : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST (BIT(3)) -#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_M (CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S) -#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S 3 /** CACHE_L1_CACHE_PLD_DONE_INT_ST : RO; bitpos: [4]; default: 0; - * The bit indicates the status of the interrupt that occurs only when L1-Cache - * preload-operation is done. + * The masked interrupt status of L1_CACHE_PLD_DONE_INT. */ #define CACHE_L1_CACHE_PLD_DONE_INT_ST (BIT(4)) #define CACHE_L1_CACHE_PLD_DONE_INT_ST_M (CACHE_L1_CACHE_PLD_DONE_INT_ST_V << CACHE_L1_CACHE_PLD_DONE_INT_ST_S) #define CACHE_L1_CACHE_PLD_DONE_INT_ST_V 0x00000001U #define CACHE_L1_CACHE_PLD_DONE_INT_ST_S 4 /** CACHE_SYNC_DONE_INT_ST : RO; bitpos: [6]; default: 0; - * The bit indicates the status of the interrupt that occurs only when Cache - * sync-operation is done. + * The masked interrupt status of CACHE_SYNC_DONE_INT. */ #define CACHE_SYNC_DONE_INT_ST (BIT(6)) #define CACHE_SYNC_DONE_INT_ST_M (CACHE_SYNC_DONE_INT_ST_V << CACHE_SYNC_DONE_INT_ST_S) #define CACHE_SYNC_DONE_INT_ST_V 0x00000001U #define CACHE_SYNC_DONE_INT_ST_S 6 -/** CACHE_L1_ICACHE0_PLD_ERR_INT_ST : HRO; bitpos: [7]; default: 0; - * The bit indicates the status of the interrupt of L1-ICache0 preload-operation error. - */ -#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST (BIT(7)) -#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_M (CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S) -#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S 7 -/** CACHE_L1_ICACHE1_PLD_ERR_INT_ST : HRO; bitpos: [8]; default: 0; - * The bit indicates the status of the interrupt of L1-ICache1 preload-operation error. - */ -#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST (BIT(8)) -#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_M (CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S) -#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S 8 -/** CACHE_L1_ICACHE2_PLD_ERR_INT_ST : HRO; bitpos: [9]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST (BIT(9)) -#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_M (CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S) -#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S 9 -/** CACHE_L1_ICACHE3_PLD_ERR_INT_ST : HRO; bitpos: [10]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST (BIT(10)) -#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_M (CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S) -#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S 10 /** CACHE_L1_CACHE_PLD_ERR_INT_ST : RO; bitpos: [11]; default: 0; - * The bit indicates the status of the interrupt of L1-Cache preload-operation error. + * The masked interrupt status of L1_CACHE_PLD_ERR_INT. */ #define CACHE_L1_CACHE_PLD_ERR_INT_ST (BIT(11)) #define CACHE_L1_CACHE_PLD_ERR_INT_ST_M (CACHE_L1_CACHE_PLD_ERR_INT_ST_V << CACHE_L1_CACHE_PLD_ERR_INT_ST_S) #define CACHE_L1_CACHE_PLD_ERR_INT_ST_V 0x00000001U #define CACHE_L1_CACHE_PLD_ERR_INT_ST_S 11 /** CACHE_SYNC_ERR_INT_ST : RO; bitpos: [13]; default: 0; - * The bit indicates the status of the interrupt of Cache sync-operation error. + * The masked interrupt status of CACHE_SYNC_ERR_INT. */ #define CACHE_SYNC_ERR_INT_ST (BIT(13)) #define CACHE_SYNC_ERR_INT_ST_M (CACHE_SYNC_ERR_INT_ST_V << CACHE_SYNC_ERR_INT_ST_S) @@ -3889,47 +1061,24 @@ extern "C" { #define CACHE_SYNC_ERR_INT_ST_S 13 /** CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG register - * Cache Sync/Preload Operation exception register + * Cache sync and preloading operation exception register */ #define CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x244) -/** CACHE_L1_ICACHE0_PLD_ERR_CODE : RO; bitpos: [1:0]; default: 0; - * The value 2 is Only available which means preload size is error in L1-ICache0. - */ -#define CACHE_L1_ICACHE0_PLD_ERR_CODE 0x00000003U -#define CACHE_L1_ICACHE0_PLD_ERR_CODE_M (CACHE_L1_ICACHE0_PLD_ERR_CODE_V << CACHE_L1_ICACHE0_PLD_ERR_CODE_S) -#define CACHE_L1_ICACHE0_PLD_ERR_CODE_V 0x00000003U -#define CACHE_L1_ICACHE0_PLD_ERR_CODE_S 0 -/** CACHE_L1_ICACHE1_PLD_ERR_CODE : RO; bitpos: [3:2]; default: 0; - * The value 2 is Only available which means preload size is error in L1-ICache1. - */ -#define CACHE_L1_ICACHE1_PLD_ERR_CODE 0x00000003U -#define CACHE_L1_ICACHE1_PLD_ERR_CODE_M (CACHE_L1_ICACHE1_PLD_ERR_CODE_V << CACHE_L1_ICACHE1_PLD_ERR_CODE_S) -#define CACHE_L1_ICACHE1_PLD_ERR_CODE_V 0x00000003U -#define CACHE_L1_ICACHE1_PLD_ERR_CODE_S 2 -/** CACHE_L1_ICACHE2_PLD_ERR_CODE : RO; bitpos: [5:4]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_PLD_ERR_CODE 0x00000003U -#define CACHE_L1_ICACHE2_PLD_ERR_CODE_M (CACHE_L1_ICACHE2_PLD_ERR_CODE_V << CACHE_L1_ICACHE2_PLD_ERR_CODE_S) -#define CACHE_L1_ICACHE2_PLD_ERR_CODE_V 0x00000003U -#define CACHE_L1_ICACHE2_PLD_ERR_CODE_S 4 -/** CACHE_L1_ICACHE3_PLD_ERR_CODE : RO; bitpos: [7:6]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_PLD_ERR_CODE 0x00000003U -#define CACHE_L1_ICACHE3_PLD_ERR_CODE_M (CACHE_L1_ICACHE3_PLD_ERR_CODE_V << CACHE_L1_ICACHE3_PLD_ERR_CODE_S) -#define CACHE_L1_ICACHE3_PLD_ERR_CODE_V 0x00000003U -#define CACHE_L1_ICACHE3_PLD_ERR_CODE_S 6 /** CACHE_L1_CACHE_PLD_ERR_CODE : RO; bitpos: [9:8]; default: 0; - * The value 2 is Only available which means preload size is error in L1-Cache. + * Represents the error code for the failed preloading operation. + * 2: The preloading size in the L1 cache is wrong + * Other values: reserved */ #define CACHE_L1_CACHE_PLD_ERR_CODE 0x00000003U #define CACHE_L1_CACHE_PLD_ERR_CODE_M (CACHE_L1_CACHE_PLD_ERR_CODE_V << CACHE_L1_CACHE_PLD_ERR_CODE_S) #define CACHE_L1_CACHE_PLD_ERR_CODE_V 0x00000003U #define CACHE_L1_CACHE_PLD_ERR_CODE_S 8 /** CACHE_SYNC_ERR_CODE : RO; bitpos: [13:12]; default: 0; - * The values 0-2 are available which means sync map, command conflict and size are - * error in Cache System. + * Represents the error code for the failed synchronization operation. + * 0: Incorrect synchronization map + * 1: Synchronization command conflict + * 2: Incorrect synchronization size + * 3: Reserved */ #define CACHE_SYNC_ERR_CODE 0x00000003U #define CACHE_SYNC_ERR_CODE_M (CACHE_SYNC_ERR_CODE_V << CACHE_SYNC_ERR_CODE_S) @@ -3937,42 +1086,15 @@ extern "C" { #define CACHE_SYNC_ERR_CODE_S 12 /** CACHE_L1_CACHE_SYNC_RST_CTRL_REG register - * Cache Sync Reset control register + * Cache sync reset control register */ #define CACHE_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x248) -/** CACHE_L1_ICACHE0_SYNC_RST : HRO; bitpos: [0]; default: 0; - * set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only - * be used to initialize sync-logic when some fatal error of sync-logic occurs. - */ -#define CACHE_L1_ICACHE0_SYNC_RST (BIT(0)) -#define CACHE_L1_ICACHE0_SYNC_RST_M (CACHE_L1_ICACHE0_SYNC_RST_V << CACHE_L1_ICACHE0_SYNC_RST_S) -#define CACHE_L1_ICACHE0_SYNC_RST_V 0x00000001U -#define CACHE_L1_ICACHE0_SYNC_RST_S 0 -/** CACHE_L1_ICACHE1_SYNC_RST : HRO; bitpos: [1]; default: 0; - * set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only - * be used to initialize sync-logic when some fatal error of sync-logic occurs. - */ -#define CACHE_L1_ICACHE1_SYNC_RST (BIT(1)) -#define CACHE_L1_ICACHE1_SYNC_RST_M (CACHE_L1_ICACHE1_SYNC_RST_V << CACHE_L1_ICACHE1_SYNC_RST_S) -#define CACHE_L1_ICACHE1_SYNC_RST_V 0x00000001U -#define CACHE_L1_ICACHE1_SYNC_RST_S 1 -/** CACHE_L1_ICACHE2_SYNC_RST : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_SYNC_RST (BIT(2)) -#define CACHE_L1_ICACHE2_SYNC_RST_M (CACHE_L1_ICACHE2_SYNC_RST_V << CACHE_L1_ICACHE2_SYNC_RST_S) -#define CACHE_L1_ICACHE2_SYNC_RST_V 0x00000001U -#define CACHE_L1_ICACHE2_SYNC_RST_S 2 -/** CACHE_L1_ICACHE3_SYNC_RST : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_SYNC_RST (BIT(3)) -#define CACHE_L1_ICACHE3_SYNC_RST_M (CACHE_L1_ICACHE3_SYNC_RST_V << CACHE_L1_ICACHE3_SYNC_RST_S) -#define CACHE_L1_ICACHE3_SYNC_RST_V 0x00000001U -#define CACHE_L1_ICACHE3_SYNC_RST_S 3 /** CACHE_L1_CACHE_SYNC_RST : R/W; bitpos: [4]; default: 0; - * set this bit to reset sync-logic inside L1-Cache. Recommend that this should only - * be used to initialize sync-logic when some fatal error of sync-logic occurs. + * Configures whether to reset the synchronization logic inside the L1 cache. + * 0: Not reset + * 1: Reset + * It is recommended that this field should only be used when a fatal error of the + * synchronization logic occurs. */ #define CACHE_L1_CACHE_SYNC_RST (BIT(4)) #define CACHE_L1_CACHE_SYNC_RST_M (CACHE_L1_CACHE_SYNC_RST_V << CACHE_L1_CACHE_SYNC_RST_S) @@ -3980,45 +1102,15 @@ extern "C" { #define CACHE_L1_CACHE_SYNC_RST_S 4 /** CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG register - * Cache Preload Reset control register + * Cache preloading reset control register */ #define CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x24c) -/** CACHE_L1_ICACHE0_PLD_RST : HRO; bitpos: [0]; default: 0; - * set this bit to reset preload-logic inside L1-ICache0. Recommend that this should - * only be used to initialize preload-logic when some fatal error of preload-logic - * occurs. - */ -#define CACHE_L1_ICACHE0_PLD_RST (BIT(0)) -#define CACHE_L1_ICACHE0_PLD_RST_M (CACHE_L1_ICACHE0_PLD_RST_V << CACHE_L1_ICACHE0_PLD_RST_S) -#define CACHE_L1_ICACHE0_PLD_RST_V 0x00000001U -#define CACHE_L1_ICACHE0_PLD_RST_S 0 -/** CACHE_L1_ICACHE1_PLD_RST : HRO; bitpos: [1]; default: 0; - * set this bit to reset preload-logic inside L1-ICache1. Recommend that this should - * only be used to initialize preload-logic when some fatal error of preload-logic - * occurs. - */ -#define CACHE_L1_ICACHE1_PLD_RST (BIT(1)) -#define CACHE_L1_ICACHE1_PLD_RST_M (CACHE_L1_ICACHE1_PLD_RST_V << CACHE_L1_ICACHE1_PLD_RST_S) -#define CACHE_L1_ICACHE1_PLD_RST_V 0x00000001U -#define CACHE_L1_ICACHE1_PLD_RST_S 1 -/** CACHE_L1_ICACHE2_PLD_RST : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_PLD_RST (BIT(2)) -#define CACHE_L1_ICACHE2_PLD_RST_M (CACHE_L1_ICACHE2_PLD_RST_V << CACHE_L1_ICACHE2_PLD_RST_S) -#define CACHE_L1_ICACHE2_PLD_RST_V 0x00000001U -#define CACHE_L1_ICACHE2_PLD_RST_S 2 -/** CACHE_L1_ICACHE3_PLD_RST : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_PLD_RST (BIT(3)) -#define CACHE_L1_ICACHE3_PLD_RST_M (CACHE_L1_ICACHE3_PLD_RST_V << CACHE_L1_ICACHE3_PLD_RST_S) -#define CACHE_L1_ICACHE3_PLD_RST_V 0x00000001U -#define CACHE_L1_ICACHE3_PLD_RST_S 3 /** CACHE_L1_CACHE_PLD_RST : R/W; bitpos: [4]; default: 0; - * set this bit to reset preload-logic inside L1-Cache. Recommend that this should - * only be used to initialize preload-logic when some fatal error of preload-logic - * occurs. + * Configures whether to reset the preloading logic inside the L1 cache. + * 0: Not reset + * 1: Reset + * It is recommended that this field should only be used when a fatal error of the + * preloading logic occurs. */ #define CACHE_L1_CACHE_PLD_RST (BIT(4)) #define CACHE_L1_CACHE_PLD_RST_M (CACHE_L1_CACHE_PLD_RST_V << CACHE_L1_CACHE_PLD_RST_S) @@ -4026,169 +1118,40 @@ extern "C" { #define CACHE_L1_CACHE_PLD_RST_S 4 /** CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register - * Cache Autoload buffer clear control register + * Cache autoloading buffer clear control register */ #define CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x250) -/** CACHE_L1_ICACHE0_ALD_BUF_CLR : HRO; bitpos: [0]; default: 0; - * set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, - * autoload will not work in L1-ICache0. This bit should not be active when autoload - * works in L1-ICache0. - */ -#define CACHE_L1_ICACHE0_ALD_BUF_CLR (BIT(0)) -#define CACHE_L1_ICACHE0_ALD_BUF_CLR_M (CACHE_L1_ICACHE0_ALD_BUF_CLR_V << CACHE_L1_ICACHE0_ALD_BUF_CLR_S) -#define CACHE_L1_ICACHE0_ALD_BUF_CLR_V 0x00000001U -#define CACHE_L1_ICACHE0_ALD_BUF_CLR_S 0 -/** CACHE_L1_ICACHE1_ALD_BUF_CLR : HRO; bitpos: [1]; default: 0; - * set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, - * autoload will not work in L1-ICache1. This bit should not be active when autoload - * works in L1-ICache1. - */ -#define CACHE_L1_ICACHE1_ALD_BUF_CLR (BIT(1)) -#define CACHE_L1_ICACHE1_ALD_BUF_CLR_M (CACHE_L1_ICACHE1_ALD_BUF_CLR_V << CACHE_L1_ICACHE1_ALD_BUF_CLR_S) -#define CACHE_L1_ICACHE1_ALD_BUF_CLR_V 0x00000001U -#define CACHE_L1_ICACHE1_ALD_BUF_CLR_S 1 -/** CACHE_L1_ICACHE2_ALD_BUF_CLR : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_ALD_BUF_CLR (BIT(2)) -#define CACHE_L1_ICACHE2_ALD_BUF_CLR_M (CACHE_L1_ICACHE2_ALD_BUF_CLR_V << CACHE_L1_ICACHE2_ALD_BUF_CLR_S) -#define CACHE_L1_ICACHE2_ALD_BUF_CLR_V 0x00000001U -#define CACHE_L1_ICACHE2_ALD_BUF_CLR_S 2 -/** CACHE_L1_ICACHE3_ALD_BUF_CLR : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_ALD_BUF_CLR (BIT(3)) -#define CACHE_L1_ICACHE3_ALD_BUF_CLR_M (CACHE_L1_ICACHE3_ALD_BUF_CLR_V << CACHE_L1_ICACHE3_ALD_BUF_CLR_S) -#define CACHE_L1_ICACHE3_ALD_BUF_CLR_V 0x00000001U -#define CACHE_L1_ICACHE3_ALD_BUF_CLR_S 3 /** CACHE_L1_CACHE_ALD_BUF_CLR : R/W; bitpos: [4]; default: 0; - * set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, - * autoload will not work in L1-Cache. This bit should not be active when autoload - * works in L1-Cache. + * Configures whether to clear the autoloading buffer inside the L1 cache. + * 0: Not clear the buffer. Recommended when autoloading of L1 cache is used. + * 1: Clear the buffer. Once set, autoloading of L1 cache will stop working. */ #define CACHE_L1_CACHE_ALD_BUF_CLR (BIT(4)) #define CACHE_L1_CACHE_ALD_BUF_CLR_M (CACHE_L1_CACHE_ALD_BUF_CLR_V << CACHE_L1_CACHE_ALD_BUF_CLR_S) #define CACHE_L1_CACHE_ALD_BUF_CLR_V 0x00000001U #define CACHE_L1_CACHE_ALD_BUF_CLR_S 4 -/** CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG register - * Unallocate request buffer clear registers - */ -#define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x254) -/** CACHE_L1_ICACHE0_UNALLOC_CLR : HRO; bitpos: [0]; default: 0; - * The bit is used to clear the unallocate request buffer of l1 icache0 where the - * unallocate request is responded but not completed. - */ -#define CACHE_L1_ICACHE0_UNALLOC_CLR (BIT(0)) -#define CACHE_L1_ICACHE0_UNALLOC_CLR_M (CACHE_L1_ICACHE0_UNALLOC_CLR_V << CACHE_L1_ICACHE0_UNALLOC_CLR_S) -#define CACHE_L1_ICACHE0_UNALLOC_CLR_V 0x00000001U -#define CACHE_L1_ICACHE0_UNALLOC_CLR_S 0 -/** CACHE_L1_ICACHE1_UNALLOC_CLR : HRO; bitpos: [1]; default: 0; - * The bit is used to clear the unallocate request buffer of l1 icache1 where the - * unallocate request is responded but not completed. - */ -#define CACHE_L1_ICACHE1_UNALLOC_CLR (BIT(1)) -#define CACHE_L1_ICACHE1_UNALLOC_CLR_M (CACHE_L1_ICACHE1_UNALLOC_CLR_V << CACHE_L1_ICACHE1_UNALLOC_CLR_S) -#define CACHE_L1_ICACHE1_UNALLOC_CLR_V 0x00000001U -#define CACHE_L1_ICACHE1_UNALLOC_CLR_S 1 -/** CACHE_L1_ICACHE2_UNALLOC_CLR : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_UNALLOC_CLR (BIT(2)) -#define CACHE_L1_ICACHE2_UNALLOC_CLR_M (CACHE_L1_ICACHE2_UNALLOC_CLR_V << CACHE_L1_ICACHE2_UNALLOC_CLR_S) -#define CACHE_L1_ICACHE2_UNALLOC_CLR_V 0x00000001U -#define CACHE_L1_ICACHE2_UNALLOC_CLR_S 2 -/** CACHE_L1_ICACHE3_UNALLOC_CLR : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_UNALLOC_CLR (BIT(3)) -#define CACHE_L1_ICACHE3_UNALLOC_CLR_M (CACHE_L1_ICACHE3_UNALLOC_CLR_V << CACHE_L1_ICACHE3_UNALLOC_CLR_S) -#define CACHE_L1_ICACHE3_UNALLOC_CLR_V 0x00000001U -#define CACHE_L1_ICACHE3_UNALLOC_CLR_S 3 -/** CACHE_L1_CACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0; - * The bit is used to clear the unallocate request buffer of l1 cache where the - * unallocate request is responded but not completed. - */ -#define CACHE_L1_CACHE_UNALLOC_CLR (BIT(4)) -#define CACHE_L1_CACHE_UNALLOC_CLR_M (CACHE_L1_CACHE_UNALLOC_CLR_V << CACHE_L1_CACHE_UNALLOC_CLR_S) -#define CACHE_L1_CACHE_UNALLOC_CLR_V 0x00000001U -#define CACHE_L1_CACHE_UNALLOC_CLR_S 4 - /** CACHE_L1_CACHE_OBJECT_CTRL_REG register - * Cache Tag and Data memory Object control register + * Cache tag and data memory object control register */ #define CACHE_L1_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x258) -/** CACHE_L1_ICACHE0_TAG_OBJECT : R/W; bitpos: [0]; default: 0; - * Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with - * the others fields inside this register. - */ -#define CACHE_L1_ICACHE0_TAG_OBJECT (BIT(0)) -#define CACHE_L1_ICACHE0_TAG_OBJECT_M (CACHE_L1_ICACHE0_TAG_OBJECT_V << CACHE_L1_ICACHE0_TAG_OBJECT_S) -#define CACHE_L1_ICACHE0_TAG_OBJECT_V 0x00000001U -#define CACHE_L1_ICACHE0_TAG_OBJECT_S 0 -/** CACHE_L1_ICACHE1_TAG_OBJECT : R/W; bitpos: [1]; default: 0; - * Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with - * the others fields inside this register. - */ -#define CACHE_L1_ICACHE1_TAG_OBJECT (BIT(1)) -#define CACHE_L1_ICACHE1_TAG_OBJECT_M (CACHE_L1_ICACHE1_TAG_OBJECT_V << CACHE_L1_ICACHE1_TAG_OBJECT_S) -#define CACHE_L1_ICACHE1_TAG_OBJECT_V 0x00000001U -#define CACHE_L1_ICACHE1_TAG_OBJECT_S 1 -/** CACHE_L1_ICACHE2_TAG_OBJECT : R/W; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_TAG_OBJECT (BIT(2)) -#define CACHE_L1_ICACHE2_TAG_OBJECT_M (CACHE_L1_ICACHE2_TAG_OBJECT_V << CACHE_L1_ICACHE2_TAG_OBJECT_S) -#define CACHE_L1_ICACHE2_TAG_OBJECT_V 0x00000001U -#define CACHE_L1_ICACHE2_TAG_OBJECT_S 2 -/** CACHE_L1_ICACHE3_TAG_OBJECT : R/W; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_TAG_OBJECT (BIT(3)) -#define CACHE_L1_ICACHE3_TAG_OBJECT_M (CACHE_L1_ICACHE3_TAG_OBJECT_V << CACHE_L1_ICACHE3_TAG_OBJECT_S) -#define CACHE_L1_ICACHE3_TAG_OBJECT_V 0x00000001U -#define CACHE_L1_ICACHE3_TAG_OBJECT_S 3 /** CACHE_L1_CACHE_TAG_OBJECT : R/W; bitpos: [4]; default: 0; - * Set this bit to set L1-Cache tag memory as object. This bit should be onehot with - * the others fields inside this register. + * Configure whether to set the L1 cache tag memory as an object. + * 0: Not set + * 1: Set + * This register uses "one-hot encoding," which means that at any time, only one field + * can be valid in conjunction with other fields. */ #define CACHE_L1_CACHE_TAG_OBJECT (BIT(4)) #define CACHE_L1_CACHE_TAG_OBJECT_M (CACHE_L1_CACHE_TAG_OBJECT_V << CACHE_L1_CACHE_TAG_OBJECT_S) #define CACHE_L1_CACHE_TAG_OBJECT_V 0x00000001U #define CACHE_L1_CACHE_TAG_OBJECT_S 4 -/** CACHE_L1_ICACHE0_MEM_OBJECT : R/W; bitpos: [6]; default: 0; - * Set this bit to set L1-ICache0 data memory as object. This bit should be onehot - * with the others fields inside this register. - */ -#define CACHE_L1_ICACHE0_MEM_OBJECT (BIT(6)) -#define CACHE_L1_ICACHE0_MEM_OBJECT_M (CACHE_L1_ICACHE0_MEM_OBJECT_V << CACHE_L1_ICACHE0_MEM_OBJECT_S) -#define CACHE_L1_ICACHE0_MEM_OBJECT_V 0x00000001U -#define CACHE_L1_ICACHE0_MEM_OBJECT_S 6 -/** CACHE_L1_ICACHE1_MEM_OBJECT : R/W; bitpos: [7]; default: 0; - * Set this bit to set L1-ICache1 data memory as object. This bit should be onehot - * with the others fields inside this register. - */ -#define CACHE_L1_ICACHE1_MEM_OBJECT (BIT(7)) -#define CACHE_L1_ICACHE1_MEM_OBJECT_M (CACHE_L1_ICACHE1_MEM_OBJECT_V << CACHE_L1_ICACHE1_MEM_OBJECT_S) -#define CACHE_L1_ICACHE1_MEM_OBJECT_V 0x00000001U -#define CACHE_L1_ICACHE1_MEM_OBJECT_S 7 -/** CACHE_L1_ICACHE2_MEM_OBJECT : R/W; bitpos: [8]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_MEM_OBJECT (BIT(8)) -#define CACHE_L1_ICACHE2_MEM_OBJECT_M (CACHE_L1_ICACHE2_MEM_OBJECT_V << CACHE_L1_ICACHE2_MEM_OBJECT_S) -#define CACHE_L1_ICACHE2_MEM_OBJECT_V 0x00000001U -#define CACHE_L1_ICACHE2_MEM_OBJECT_S 8 -/** CACHE_L1_ICACHE3_MEM_OBJECT : R/W; bitpos: [9]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_MEM_OBJECT (BIT(9)) -#define CACHE_L1_ICACHE3_MEM_OBJECT_M (CACHE_L1_ICACHE3_MEM_OBJECT_V << CACHE_L1_ICACHE3_MEM_OBJECT_S) -#define CACHE_L1_ICACHE3_MEM_OBJECT_V 0x00000001U -#define CACHE_L1_ICACHE3_MEM_OBJECT_S 9 /** CACHE_L1_CACHE_MEM_OBJECT : R/W; bitpos: [10]; default: 0; - * Set this bit to set L1-Cache data memory as object. This bit should be onehot with - * the others fields inside this register. + * Configure whether to set the L1 cache data memory as an object. + * 0: Not set + * 1: Set + * This register uses "one-hot encoding," which means that at any time, only one field + * can be valid in conjunction with other fields. */ #define CACHE_L1_CACHE_MEM_OBJECT (BIT(10)) #define CACHE_L1_CACHE_MEM_OBJECT_M (CACHE_L1_CACHE_MEM_OBJECT_V << CACHE_L1_CACHE_MEM_OBJECT_S) @@ -4196,12 +1159,15 @@ extern "C" { #define CACHE_L1_CACHE_MEM_OBJECT_S 10 /** CACHE_L1_CACHE_WAY_OBJECT_REG register - * Cache Tag and Data memory way register + * Cache tag and data memory way register */ #define CACHE_L1_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x25c) /** CACHE_L1_CACHE_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0; - * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: - * way1, 2: way2, 3: way3, ?, 7: way7. + * Configures which way in the tag memory or the data memory to access. + * 0: Way 0 + * 1: Way 1 + * 2: Way 2 + * 3: Way 3 */ #define CACHE_L1_CACHE_WAY_OBJECT 0x00000007U #define CACHE_L1_CACHE_WAY_OBJECT_M (CACHE_L1_CACHE_WAY_OBJECT_V << CACHE_L1_CACHE_WAY_OBJECT_S) @@ -4213,8 +1179,7 @@ extern "C" { */ #define CACHE_L1_CACHE_ADDR_REG (DR_REG_CACHE_BASE + 0x260) /** CACHE_L1_CACHE_ADDR : R/W; bitpos: [31:0]; default: 0; - * Those bits stores the address which will decide where inside the specified tag - * memory object will be accessed. + * Configures the virtual address inside the tag memory or data memory to access. */ #define CACHE_L1_CACHE_ADDR 0xFFFFFFFFU #define CACHE_L1_CACHE_ADDR_M (CACHE_L1_CACHE_ADDR_V << CACHE_L1_CACHE_ADDR_S) @@ -4222,1853 +1187,18 @@ extern "C" { #define CACHE_L1_CACHE_ADDR_S 0 /** CACHE_L1_CACHE_DEBUG_BUS_REG register - * Cache Tag/data memory content register + * Cache tag and data memory content register */ #define CACHE_L1_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x264) /** CACHE_L1_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 612; - * This is a constant place where we can write data to or read data from the tag/data - * memory on the specified cache. + * Configures the data to write to or the data to read from the tag memory or the data + * memory. */ #define CACHE_L1_CACHE_DEBUG_BUS 0xFFFFFFFFU #define CACHE_L1_CACHE_DEBUG_BUS_M (CACHE_L1_CACHE_DEBUG_BUS_V << CACHE_L1_CACHE_DEBUG_BUS_S) #define CACHE_L1_CACHE_DEBUG_BUS_V 0xFFFFFFFFU #define CACHE_L1_CACHE_DEBUG_BUS_S 0 -/** CACHE_LEVEL_SPLIT0_REG register - * USED TO SPLIT L1 CACHE AND L2 CACHE - */ -#define CACHE_LEVEL_SPLIT0_REG (DR_REG_CACHE_BASE + 0x268) -/** CACHE_LEVEL_SPLIT0 : HRO; bitpos: [31:0]; default: 616; - * Reserved - */ -#define CACHE_LEVEL_SPLIT0 0xFFFFFFFFU -#define CACHE_LEVEL_SPLIT0_M (CACHE_LEVEL_SPLIT0_V << CACHE_LEVEL_SPLIT0_S) -#define CACHE_LEVEL_SPLIT0_V 0xFFFFFFFFU -#define CACHE_LEVEL_SPLIT0_S 0 - -/** CACHE_L2_CACHE_CTRL_REG register - * L2 Cache(L2-Cache) control register - */ -#define CACHE_L2_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x26c) -/** CACHE_L2_CACHE_SHUT_DMA : HRO; bitpos: [4]; default: 0; - * The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable - */ -#define CACHE_L2_CACHE_SHUT_DMA (BIT(4)) -#define CACHE_L2_CACHE_SHUT_DMA_M (CACHE_L2_CACHE_SHUT_DMA_V << CACHE_L2_CACHE_SHUT_DMA_S) -#define CACHE_L2_CACHE_SHUT_DMA_V 0x00000001U -#define CACHE_L2_CACHE_SHUT_DMA_S 4 -/** CACHE_L2_CACHE_UNDEF_OP : R/W; bitpos: [15:8]; default: 0; - * Reserved - */ -#define CACHE_L2_CACHE_UNDEF_OP 0x000000FFU -#define CACHE_L2_CACHE_UNDEF_OP_M (CACHE_L2_CACHE_UNDEF_OP_V << CACHE_L2_CACHE_UNDEF_OP_S) -#define CACHE_L2_CACHE_UNDEF_OP_V 0x000000FFU -#define CACHE_L2_CACHE_UNDEF_OP_S 8 - -/** CACHE_L2_BYPASS_CACHE_CONF_REG register - * Bypass Cache configure register - */ -#define CACHE_L2_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x270) -/** CACHE_BYPASS_L2_CACHE_EN : HRO; bitpos: [5]; default: 0; - * The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass. - */ -#define CACHE_BYPASS_L2_CACHE_EN (BIT(5)) -#define CACHE_BYPASS_L2_CACHE_EN_M (CACHE_BYPASS_L2_CACHE_EN_V << CACHE_BYPASS_L2_CACHE_EN_S) -#define CACHE_BYPASS_L2_CACHE_EN_V 0x00000001U -#define CACHE_BYPASS_L2_CACHE_EN_S 5 - -/** CACHE_L2_CACHE_CACHESIZE_CONF_REG register - * L2 Cache CacheSize mode configure register - */ -#define CACHE_L2_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x274) -/** CACHE_L2_CACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0; - * The field is used to configure cachesize of L2-Cache as 256 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_256 (BIT(0)) -#define CACHE_L2_CACHE_CACHESIZE_256_M (CACHE_L2_CACHE_CACHESIZE_256_V << CACHE_L2_CACHE_CACHESIZE_256_S) -#define CACHE_L2_CACHE_CACHESIZE_256_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_256_S 0 -/** CACHE_L2_CACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0; - * The field is used to configure cachesize of L2-Cache as 512 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_512 (BIT(1)) -#define CACHE_L2_CACHE_CACHESIZE_512_M (CACHE_L2_CACHE_CACHESIZE_512_V << CACHE_L2_CACHE_CACHESIZE_512_S) -#define CACHE_L2_CACHE_CACHESIZE_512_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_512_S 1 -/** CACHE_L2_CACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0; - * The field is used to configure cachesize of L2-Cache as 1k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_1K (BIT(2)) -#define CACHE_L2_CACHE_CACHESIZE_1K_M (CACHE_L2_CACHE_CACHESIZE_1K_V << CACHE_L2_CACHE_CACHESIZE_1K_S) -#define CACHE_L2_CACHE_CACHESIZE_1K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_1K_S 2 -/** CACHE_L2_CACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0; - * The field is used to configure cachesize of L2-Cache as 2k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_2K (BIT(3)) -#define CACHE_L2_CACHE_CACHESIZE_2K_M (CACHE_L2_CACHE_CACHESIZE_2K_V << CACHE_L2_CACHE_CACHESIZE_2K_S) -#define CACHE_L2_CACHE_CACHESIZE_2K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_2K_S 3 -/** CACHE_L2_CACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0; - * The field is used to configure cachesize of L2-Cache as 4k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_4K (BIT(4)) -#define CACHE_L2_CACHE_CACHESIZE_4K_M (CACHE_L2_CACHE_CACHESIZE_4K_V << CACHE_L2_CACHE_CACHESIZE_4K_S) -#define CACHE_L2_CACHE_CACHESIZE_4K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_4K_S 4 -/** CACHE_L2_CACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0; - * The field is used to configure cachesize of L2-Cache as 8k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_8K (BIT(5)) -#define CACHE_L2_CACHE_CACHESIZE_8K_M (CACHE_L2_CACHE_CACHESIZE_8K_V << CACHE_L2_CACHE_CACHESIZE_8K_S) -#define CACHE_L2_CACHE_CACHESIZE_8K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_8K_S 5 -/** CACHE_L2_CACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0; - * The field is used to configure cachesize of L2-Cache as 16k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_16K (BIT(6)) -#define CACHE_L2_CACHE_CACHESIZE_16K_M (CACHE_L2_CACHE_CACHESIZE_16K_V << CACHE_L2_CACHE_CACHESIZE_16K_S) -#define CACHE_L2_CACHE_CACHESIZE_16K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_16K_S 6 -/** CACHE_L2_CACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0; - * The field is used to configure cachesize of L2-Cache as 32k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_32K (BIT(7)) -#define CACHE_L2_CACHE_CACHESIZE_32K_M (CACHE_L2_CACHE_CACHESIZE_32K_V << CACHE_L2_CACHE_CACHESIZE_32K_S) -#define CACHE_L2_CACHE_CACHESIZE_32K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_32K_S 7 -/** CACHE_L2_CACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0; - * The field is used to configure cachesize of L2-Cache as 64k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_64K (BIT(8)) -#define CACHE_L2_CACHE_CACHESIZE_64K_M (CACHE_L2_CACHE_CACHESIZE_64K_V << CACHE_L2_CACHE_CACHESIZE_64K_S) -#define CACHE_L2_CACHE_CACHESIZE_64K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_64K_S 8 -/** CACHE_L2_CACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0; - * The field is used to configure cachesize of L2-Cache as 128k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_128K (BIT(9)) -#define CACHE_L2_CACHE_CACHESIZE_128K_M (CACHE_L2_CACHE_CACHESIZE_128K_V << CACHE_L2_CACHE_CACHESIZE_128K_S) -#define CACHE_L2_CACHE_CACHESIZE_128K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_128K_S 9 -/** CACHE_L2_CACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0; - * The field is used to configure cachesize of L2-Cache as 256k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_256K (BIT(10)) -#define CACHE_L2_CACHE_CACHESIZE_256K_M (CACHE_L2_CACHE_CACHESIZE_256K_V << CACHE_L2_CACHE_CACHESIZE_256K_S) -#define CACHE_L2_CACHE_CACHESIZE_256K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_256K_S 10 -/** CACHE_L2_CACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0; - * The field is used to configure cachesize of L2-Cache as 512k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_512K (BIT(11)) -#define CACHE_L2_CACHE_CACHESIZE_512K_M (CACHE_L2_CACHE_CACHESIZE_512K_V << CACHE_L2_CACHE_CACHESIZE_512K_S) -#define CACHE_L2_CACHE_CACHESIZE_512K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_512K_S 11 -/** CACHE_L2_CACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0; - * The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_1024K (BIT(12)) -#define CACHE_L2_CACHE_CACHESIZE_1024K_M (CACHE_L2_CACHE_CACHESIZE_1024K_V << CACHE_L2_CACHE_CACHESIZE_1024K_S) -#define CACHE_L2_CACHE_CACHESIZE_1024K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_1024K_S 12 - -/** CACHE_L2_CACHE_BLOCKSIZE_CONF_REG register - * L2 Cache BlockSize mode configure register - */ -#define CACHE_L2_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x278) -/** CACHE_L2_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0; - * The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all - * other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_BLOCKSIZE_8 (BIT(0)) -#define CACHE_L2_CACHE_BLOCKSIZE_8_M (CACHE_L2_CACHE_BLOCKSIZE_8_V << CACHE_L2_CACHE_BLOCKSIZE_8_S) -#define CACHE_L2_CACHE_BLOCKSIZE_8_V 0x00000001U -#define CACHE_L2_CACHE_BLOCKSIZE_8_S 0 -/** CACHE_L2_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0; - * The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all - * other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_BLOCKSIZE_16 (BIT(1)) -#define CACHE_L2_CACHE_BLOCKSIZE_16_M (CACHE_L2_CACHE_BLOCKSIZE_16_V << CACHE_L2_CACHE_BLOCKSIZE_16_S) -#define CACHE_L2_CACHE_BLOCKSIZE_16_V 0x00000001U -#define CACHE_L2_CACHE_BLOCKSIZE_16_S 1 -/** CACHE_L2_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0; - * The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all - * other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_BLOCKSIZE_32 (BIT(2)) -#define CACHE_L2_CACHE_BLOCKSIZE_32_M (CACHE_L2_CACHE_BLOCKSIZE_32_V << CACHE_L2_CACHE_BLOCKSIZE_32_S) -#define CACHE_L2_CACHE_BLOCKSIZE_32_V 0x00000001U -#define CACHE_L2_CACHE_BLOCKSIZE_32_S 2 -/** CACHE_L2_CACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0; - * The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all - * other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_BLOCKSIZE_64 (BIT(3)) -#define CACHE_L2_CACHE_BLOCKSIZE_64_M (CACHE_L2_CACHE_BLOCKSIZE_64_V << CACHE_L2_CACHE_BLOCKSIZE_64_S) -#define CACHE_L2_CACHE_BLOCKSIZE_64_V 0x00000001U -#define CACHE_L2_CACHE_BLOCKSIZE_64_S 3 -/** CACHE_L2_CACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0; - * The field is used to configureblocksize of L2-Cache as 128 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_BLOCKSIZE_128 (BIT(4)) -#define CACHE_L2_CACHE_BLOCKSIZE_128_M (CACHE_L2_CACHE_BLOCKSIZE_128_V << CACHE_L2_CACHE_BLOCKSIZE_128_S) -#define CACHE_L2_CACHE_BLOCKSIZE_128_V 0x00000001U -#define CACHE_L2_CACHE_BLOCKSIZE_128_S 4 -/** CACHE_L2_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0; - * The field is used to configureblocksize of L2-Cache as 256 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_BLOCKSIZE_256 (BIT(5)) -#define CACHE_L2_CACHE_BLOCKSIZE_256_M (CACHE_L2_CACHE_BLOCKSIZE_256_V << CACHE_L2_CACHE_BLOCKSIZE_256_S) -#define CACHE_L2_CACHE_BLOCKSIZE_256_V 0x00000001U -#define CACHE_L2_CACHE_BLOCKSIZE_256_S 5 - -/** CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG register - * Cache wrap around control register - */ -#define CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x27c) -/** CACHE_L2_CACHE_WRAP : HRO; bitpos: [5]; default: 0; - * Set this bit as 1 to enable L2-Cache wrap around mode. - */ -#define CACHE_L2_CACHE_WRAP (BIT(5)) -#define CACHE_L2_CACHE_WRAP_M (CACHE_L2_CACHE_WRAP_V << CACHE_L2_CACHE_WRAP_S) -#define CACHE_L2_CACHE_WRAP_V 0x00000001U -#define CACHE_L2_CACHE_WRAP_S 5 - -/** CACHE_L2_CACHE_MISS_ACCESS_CTRL_REG register - * Cache wrap around control register - */ -#define CACHE_L2_CACHE_MISS_ACCESS_CTRL_REG (DR_REG_CACHE_BASE + 0x280) -/** CACHE_L2_CACHE_MISS_DISABLE_ACCESS : HRO; bitpos: [5]; default: 0; - * Set this bit as 1 to disable early restart of L2-Cache - */ -#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS (BIT(5)) -#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS_M (CACHE_L2_CACHE_MISS_DISABLE_ACCESS_V << CACHE_L2_CACHE_MISS_DISABLE_ACCESS_S) -#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS_V 0x00000001U -#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS_S 5 - -/** CACHE_L2_CACHE_FREEZE_CTRL_REG register - * Cache Freeze control register - */ -#define CACHE_L2_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x284) -/** CACHE_L2_CACHE_FREEZE_EN : HRO; bitpos: [20]; default: 0; - * The bit is used to enable freeze operation on L2-Cache. It can be cleared by - * software. - */ -#define CACHE_L2_CACHE_FREEZE_EN (BIT(20)) -#define CACHE_L2_CACHE_FREEZE_EN_M (CACHE_L2_CACHE_FREEZE_EN_V << CACHE_L2_CACHE_FREEZE_EN_S) -#define CACHE_L2_CACHE_FREEZE_EN_V 0x00000001U -#define CACHE_L2_CACHE_FREEZE_EN_S 20 -/** CACHE_L2_CACHE_FREEZE_MODE : HRO; bitpos: [21]; default: 0; - * The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. - */ -#define CACHE_L2_CACHE_FREEZE_MODE (BIT(21)) -#define CACHE_L2_CACHE_FREEZE_MODE_M (CACHE_L2_CACHE_FREEZE_MODE_V << CACHE_L2_CACHE_FREEZE_MODE_S) -#define CACHE_L2_CACHE_FREEZE_MODE_V 0x00000001U -#define CACHE_L2_CACHE_FREEZE_MODE_S 21 -/** CACHE_L2_CACHE_FREEZE_DONE : RO; bitpos: [22]; default: 0; - * The bit is used to indicate whether freeze operation on L2-Cache is finished or - * not. 0: not finished. 1: finished. - */ -#define CACHE_L2_CACHE_FREEZE_DONE (BIT(22)) -#define CACHE_L2_CACHE_FREEZE_DONE_M (CACHE_L2_CACHE_FREEZE_DONE_V << CACHE_L2_CACHE_FREEZE_DONE_S) -#define CACHE_L2_CACHE_FREEZE_DONE_V 0x00000001U -#define CACHE_L2_CACHE_FREEZE_DONE_S 22 - -/** CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG register - * Cache data memory access configure register - */ -#define CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x288) -/** CACHE_L2_CACHE_DATA_MEM_RD_EN : HRO; bitpos: [20]; default: 0; - * The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: - * enable. - */ -#define CACHE_L2_CACHE_DATA_MEM_RD_EN (BIT(20)) -#define CACHE_L2_CACHE_DATA_MEM_RD_EN_M (CACHE_L2_CACHE_DATA_MEM_RD_EN_V << CACHE_L2_CACHE_DATA_MEM_RD_EN_S) -#define CACHE_L2_CACHE_DATA_MEM_RD_EN_V 0x00000001U -#define CACHE_L2_CACHE_DATA_MEM_RD_EN_S 20 -/** CACHE_L2_CACHE_DATA_MEM_WR_EN : HRO; bitpos: [21]; default: 0; - * The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: - * enable. - */ -#define CACHE_L2_CACHE_DATA_MEM_WR_EN (BIT(21)) -#define CACHE_L2_CACHE_DATA_MEM_WR_EN_M (CACHE_L2_CACHE_DATA_MEM_WR_EN_V << CACHE_L2_CACHE_DATA_MEM_WR_EN_S) -#define CACHE_L2_CACHE_DATA_MEM_WR_EN_V 0x00000001U -#define CACHE_L2_CACHE_DATA_MEM_WR_EN_S 21 - -/** CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG register - * Cache tag memory access configure register - */ -#define CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x28c) -/** CACHE_L2_CACHE_TAG_MEM_RD_EN : HRO; bitpos: [20]; default: 0; - * The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: - * enable. - */ -#define CACHE_L2_CACHE_TAG_MEM_RD_EN (BIT(20)) -#define CACHE_L2_CACHE_TAG_MEM_RD_EN_M (CACHE_L2_CACHE_TAG_MEM_RD_EN_V << CACHE_L2_CACHE_TAG_MEM_RD_EN_S) -#define CACHE_L2_CACHE_TAG_MEM_RD_EN_V 0x00000001U -#define CACHE_L2_CACHE_TAG_MEM_RD_EN_S 20 -/** CACHE_L2_CACHE_TAG_MEM_WR_EN : HRO; bitpos: [21]; default: 0; - * The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: - * enable. - */ -#define CACHE_L2_CACHE_TAG_MEM_WR_EN (BIT(21)) -#define CACHE_L2_CACHE_TAG_MEM_WR_EN_M (CACHE_L2_CACHE_TAG_MEM_WR_EN_V << CACHE_L2_CACHE_TAG_MEM_WR_EN_S) -#define CACHE_L2_CACHE_TAG_MEM_WR_EN_V 0x00000001U -#define CACHE_L2_CACHE_TAG_MEM_WR_EN_S 21 - -/** CACHE_L2_CACHE_PRELOCK_CONF_REG register - * L2 Cache prelock configure register - */ -#define CACHE_L2_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x290) -/** CACHE_L2_CACHE_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L2-Cache. - */ -#define CACHE_L2_CACHE_PRELOCK_SCT0_EN (BIT(0)) -#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_M (CACHE_L2_CACHE_PRELOCK_SCT0_EN_V << CACHE_L2_CACHE_PRELOCK_SCT0_EN_S) -#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_V 0x00000001U -#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_S 0 -/** CACHE_L2_CACHE_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L2-Cache. - */ -#define CACHE_L2_CACHE_PRELOCK_SCT1_EN (BIT(1)) -#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_M (CACHE_L2_CACHE_PRELOCK_SCT1_EN_V << CACHE_L2_CACHE_PRELOCK_SCT1_EN_S) -#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_V 0x00000001U -#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_S 1 -/** CACHE_L2_CACHE_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l2 cache prelock. - */ -#define CACHE_L2_CACHE_PRELOCK_RGID 0x0000000FU -#define CACHE_L2_CACHE_PRELOCK_RGID_M (CACHE_L2_CACHE_PRELOCK_RGID_V << CACHE_L2_CACHE_PRELOCK_RGID_S) -#define CACHE_L2_CACHE_PRELOCK_RGID_V 0x0000000FU -#define CACHE_L2_CACHE_PRELOCK_RGID_S 2 - -/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG register - * L2 Cache prelock section0 address configure register - */ -#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x294) -/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG - */ -#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFFU -#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_M (CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S) -#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU -#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S 0 - -/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG register - * L2 Cache prelock section1 address configure register - */ -#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x298) -/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG - */ -#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFFU -#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_M (CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S) -#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU -#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S 0 - -/** CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG register - * L2 Cache prelock section size configure register - */ -#define CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x29c) -/** CACHE_L2_CACHE_PRELOCK_SCT0_SIZE : HRO; bitpos: [15:0]; default: 65535; - * Those bits are used to configure the size of the first section of prelock on - * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG - */ -#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE 0x0000FFFFU -#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_M (CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S) -#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V 0x0000FFFFU -#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S 0 -/** CACHE_L2_CACHE_PRELOCK_SCT1_SIZE : HRO; bitpos: [31:16]; default: 65535; - * Those bits are used to configure the size of the second section of prelock on - * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG - */ -#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE 0x0000FFFFU -#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_M (CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S) -#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V 0x0000FFFFU -#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S 16 - -/** CACHE_L2_CACHE_PRELOAD_CTRL_REG register - * L2 Cache preload-operation control register - */ -#define CACHE_L2_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2a0) -/** CACHE_L2_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L2-Cache. It will be cleared by - * hardware automatically after preload operation is done. - */ -#define CACHE_L2_CACHE_PRELOAD_ENA (BIT(0)) -#define CACHE_L2_CACHE_PRELOAD_ENA_M (CACHE_L2_CACHE_PRELOAD_ENA_V << CACHE_L2_CACHE_PRELOAD_ENA_S) -#define CACHE_L2_CACHE_PRELOAD_ENA_V 0x00000001U -#define CACHE_L2_CACHE_PRELOAD_ENA_S 0 -/** CACHE_L2_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ -#define CACHE_L2_CACHE_PRELOAD_DONE (BIT(1)) -#define CACHE_L2_CACHE_PRELOAD_DONE_M (CACHE_L2_CACHE_PRELOAD_DONE_V << CACHE_L2_CACHE_PRELOAD_DONE_S) -#define CACHE_L2_CACHE_PRELOAD_DONE_V 0x00000001U -#define CACHE_L2_CACHE_PRELOAD_DONE_S 1 -/** CACHE_L2_CACHE_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ -#define CACHE_L2_CACHE_PRELOAD_ORDER (BIT(2)) -#define CACHE_L2_CACHE_PRELOAD_ORDER_M (CACHE_L2_CACHE_PRELOAD_ORDER_V << CACHE_L2_CACHE_PRELOAD_ORDER_S) -#define CACHE_L2_CACHE_PRELOAD_ORDER_V 0x00000001U -#define CACHE_L2_CACHE_PRELOAD_ORDER_S 2 -/** CACHE_L2_CACHE_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l2 cache preload. - */ -#define CACHE_L2_CACHE_PRELOAD_RGID 0x0000000FU -#define CACHE_L2_CACHE_PRELOAD_RGID_M (CACHE_L2_CACHE_PRELOAD_RGID_V << CACHE_L2_CACHE_PRELOAD_RGID_S) -#define CACHE_L2_CACHE_PRELOAD_RGID_V 0x0000000FU -#define CACHE_L2_CACHE_PRELOAD_RGID_S 3 - -/** CACHE_L2_CACHE_PRELOAD_ADDR_REG register - * L2 Cache preload address configure register - */ -#define CACHE_L2_CACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0x2a4) -/** CACHE_L2_CACHE_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L2-Cache, which - * should be used together with L2_CACHE_PRELOAD_SIZE_REG - */ -#define CACHE_L2_CACHE_PRELOAD_ADDR 0xFFFFFFFFU -#define CACHE_L2_CACHE_PRELOAD_ADDR_M (CACHE_L2_CACHE_PRELOAD_ADDR_V << CACHE_L2_CACHE_PRELOAD_ADDR_S) -#define CACHE_L2_CACHE_PRELOAD_ADDR_V 0xFFFFFFFFU -#define CACHE_L2_CACHE_PRELOAD_ADDR_S 0 - -/** CACHE_L2_CACHE_PRELOAD_SIZE_REG register - * L2 Cache preload size configure register - */ -#define CACHE_L2_CACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0x2a8) -/** CACHE_L2_CACHE_PRELOAD_SIZE : HRO; bitpos: [15:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG - */ -#define CACHE_L2_CACHE_PRELOAD_SIZE 0x0000FFFFU -#define CACHE_L2_CACHE_PRELOAD_SIZE_M (CACHE_L2_CACHE_PRELOAD_SIZE_V << CACHE_L2_CACHE_PRELOAD_SIZE_S) -#define CACHE_L2_CACHE_PRELOAD_SIZE_V 0x0000FFFFU -#define CACHE_L2_CACHE_PRELOAD_SIZE_S 0 - -/** CACHE_L2_CACHE_AUTOLOAD_CTRL_REG register - * L2 Cache autoload-operation control register - */ -#define CACHE_L2_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2ac) -/** CACHE_L2_CACHE_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, - * 0: disable. - */ -#define CACHE_L2_CACHE_AUTOLOAD_ENA (BIT(0)) -#define CACHE_L2_CACHE_AUTOLOAD_ENA_M (CACHE_L2_CACHE_AUTOLOAD_ENA_V << CACHE_L2_CACHE_AUTOLOAD_ENA_S) -#define CACHE_L2_CACHE_AUTOLOAD_ENA_V 0x00000001U -#define CACHE_L2_CACHE_AUTOLOAD_ENA_S 0 -/** CACHE_L2_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L2-Cache is finished or - * not. 0: not finished. 1: finished. - */ -#define CACHE_L2_CACHE_AUTOLOAD_DONE (BIT(1)) -#define CACHE_L2_CACHE_AUTOLOAD_DONE_M (CACHE_L2_CACHE_AUTOLOAD_DONE_V << CACHE_L2_CACHE_AUTOLOAD_DONE_S) -#define CACHE_L2_CACHE_AUTOLOAD_DONE_V 0x00000001U -#define CACHE_L2_CACHE_AUTOLOAD_DONE_S 1 -/** CACHE_L2_CACHE_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L2-Cache. 0: - * ascending. 1: descending. - */ -#define CACHE_L2_CACHE_AUTOLOAD_ORDER (BIT(2)) -#define CACHE_L2_CACHE_AUTOLOAD_ORDER_M (CACHE_L2_CACHE_AUTOLOAD_ORDER_V << CACHE_L2_CACHE_AUTOLOAD_ORDER_S) -#define CACHE_L2_CACHE_AUTOLOAD_ORDER_V 0x00000001U -#define CACHE_L2_CACHE_AUTOLOAD_ORDER_S 2 -/** CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: - * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ -#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE 0x00000003U -#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_M (CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S) -#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V 0x00000003U -#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S 3 -/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L2-Cache. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA (BIT(8)) -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_M (CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V 0x00000001U -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S 8 -/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L2-Cache. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA (BIT(9)) -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_M (CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V 0x00000001U -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S 9 -/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA : HRO; bitpos: [10]; default: 0; - * The bit is used to enable the third section for autoload operation on L2-Cache. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA (BIT(10)) -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_M (CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V 0x00000001U -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S 10 -/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA : HRO; bitpos: [11]; default: 0; - * The bit is used to enable the fourth section for autoload operation on L2-Cache. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA (BIT(11)) -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_M (CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V 0x00000001U -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S 11 -/** CACHE_L2_CACHE_AUTOLOAD_RGID : HRO; bitpos: [15:12]; default: 0; - * The bit is used to set the gid of l2 cache autoload. - */ -#define CACHE_L2_CACHE_AUTOLOAD_RGID 0x0000000FU -#define CACHE_L2_CACHE_AUTOLOAD_RGID_M (CACHE_L2_CACHE_AUTOLOAD_RGID_V << CACHE_L2_CACHE_AUTOLOAD_RGID_S) -#define CACHE_L2_CACHE_AUTOLOAD_RGID_V 0x0000000FU -#define CACHE_L2_CACHE_AUTOLOAD_RGID_S 12 - -/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG register - * L2 Cache autoload section 0 address configure register - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x2b0) -/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_M (CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S 0 - -/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG register - * L2 Cache autoload section 0 size configure register - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x2b4) -/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE 0x0FFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_M (CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V 0x0FFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S 0 - -/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG register - * L2 Cache autoload section 1 address configure register - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x2b8) -/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_M (CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S 0 - -/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG register - * L2 Cache autoload section 1 size configure register - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x2bc) -/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE 0x0FFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_M (CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V 0x0FFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S 0 - -/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG register - * L2 Cache autoload section 2 address configure register - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x2c0) -/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the third section for - * autoload operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR 0xFFFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_M (CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V 0xFFFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S 0 - -/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG register - * L2 Cache autoload section 2 size configure register - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x2c4) -/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the third section for autoload - * operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE 0x0FFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_M (CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V 0x0FFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S 0 - -/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG register - * L2 Cache autoload section 3 address configure register - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x2c8) -/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the fourth section for - * autoload operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR 0xFFFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_M (CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V 0xFFFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S 0 - -/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG register - * L2 Cache autoload section 3 size configure register - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x2cc) -/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the fourth section for autoload - * operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE 0x0FFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_M (CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V 0x0FFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S 0 - -/** CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG register - * Cache Access Counter Interrupt enable register - */ -#define CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2d0) -/** CACHE_L2_IBUS0_OVF_INT_ENA : HRO; bitpos: [8]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L2-Cache due to bus0 accesses L2-Cache. - */ -#define CACHE_L2_IBUS0_OVF_INT_ENA (BIT(8)) -#define CACHE_L2_IBUS0_OVF_INT_ENA_M (CACHE_L2_IBUS0_OVF_INT_ENA_V << CACHE_L2_IBUS0_OVF_INT_ENA_S) -#define CACHE_L2_IBUS0_OVF_INT_ENA_V 0x00000001U -#define CACHE_L2_IBUS0_OVF_INT_ENA_S 8 -/** CACHE_L2_IBUS1_OVF_INT_ENA : HRO; bitpos: [9]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L2-Cache due to bus1 accesses L2-Cache. - */ -#define CACHE_L2_IBUS1_OVF_INT_ENA (BIT(9)) -#define CACHE_L2_IBUS1_OVF_INT_ENA_M (CACHE_L2_IBUS1_OVF_INT_ENA_V << CACHE_L2_IBUS1_OVF_INT_ENA_S) -#define CACHE_L2_IBUS1_OVF_INT_ENA_V 0x00000001U -#define CACHE_L2_IBUS1_OVF_INT_ENA_S 9 -/** CACHE_L2_IBUS2_OVF_INT_ENA : HRO; bitpos: [10]; default: 0; - * Reserved - */ -#define CACHE_L2_IBUS2_OVF_INT_ENA (BIT(10)) -#define CACHE_L2_IBUS2_OVF_INT_ENA_M (CACHE_L2_IBUS2_OVF_INT_ENA_V << CACHE_L2_IBUS2_OVF_INT_ENA_S) -#define CACHE_L2_IBUS2_OVF_INT_ENA_V 0x00000001U -#define CACHE_L2_IBUS2_OVF_INT_ENA_S 10 -/** CACHE_L2_IBUS3_OVF_INT_ENA : HRO; bitpos: [11]; default: 0; - * Reserved - */ -#define CACHE_L2_IBUS3_OVF_INT_ENA (BIT(11)) -#define CACHE_L2_IBUS3_OVF_INT_ENA_M (CACHE_L2_IBUS3_OVF_INT_ENA_V << CACHE_L2_IBUS3_OVF_INT_ENA_S) -#define CACHE_L2_IBUS3_OVF_INT_ENA_V 0x00000001U -#define CACHE_L2_IBUS3_OVF_INT_ENA_S 11 -/** CACHE_L2_DBUS0_OVF_INT_ENA : HRO; bitpos: [12]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L2-Cache due to bus0 accesses L2-Cache. - */ -#define CACHE_L2_DBUS0_OVF_INT_ENA (BIT(12)) -#define CACHE_L2_DBUS0_OVF_INT_ENA_M (CACHE_L2_DBUS0_OVF_INT_ENA_V << CACHE_L2_DBUS0_OVF_INT_ENA_S) -#define CACHE_L2_DBUS0_OVF_INT_ENA_V 0x00000001U -#define CACHE_L2_DBUS0_OVF_INT_ENA_S 12 -/** CACHE_L2_DBUS1_OVF_INT_ENA : HRO; bitpos: [13]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L2-Cache due to bus1 accesses L2-Cache. - */ -#define CACHE_L2_DBUS1_OVF_INT_ENA (BIT(13)) -#define CACHE_L2_DBUS1_OVF_INT_ENA_M (CACHE_L2_DBUS1_OVF_INT_ENA_V << CACHE_L2_DBUS1_OVF_INT_ENA_S) -#define CACHE_L2_DBUS1_OVF_INT_ENA_V 0x00000001U -#define CACHE_L2_DBUS1_OVF_INT_ENA_S 13 -/** CACHE_L2_DBUS2_OVF_INT_ENA : HRO; bitpos: [14]; default: 0; - * Reserved - */ -#define CACHE_L2_DBUS2_OVF_INT_ENA (BIT(14)) -#define CACHE_L2_DBUS2_OVF_INT_ENA_M (CACHE_L2_DBUS2_OVF_INT_ENA_V << CACHE_L2_DBUS2_OVF_INT_ENA_S) -#define CACHE_L2_DBUS2_OVF_INT_ENA_V 0x00000001U -#define CACHE_L2_DBUS2_OVF_INT_ENA_S 14 -/** CACHE_L2_DBUS3_OVF_INT_ENA : HRO; bitpos: [15]; default: 0; - * Reserved - */ -#define CACHE_L2_DBUS3_OVF_INT_ENA (BIT(15)) -#define CACHE_L2_DBUS3_OVF_INT_ENA_M (CACHE_L2_DBUS3_OVF_INT_ENA_V << CACHE_L2_DBUS3_OVF_INT_ENA_S) -#define CACHE_L2_DBUS3_OVF_INT_ENA_V 0x00000001U -#define CACHE_L2_DBUS3_OVF_INT_ENA_S 15 - -/** CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG register - * Cache Access Counter Interrupt clear register - */ -#define CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2d4) -/** CACHE_L2_IBUS0_OVF_INT_CLR : HRO; bitpos: [8]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L2-Cache due - * to bus0 accesses L2-Cache. - */ -#define CACHE_L2_IBUS0_OVF_INT_CLR (BIT(8)) -#define CACHE_L2_IBUS0_OVF_INT_CLR_M (CACHE_L2_IBUS0_OVF_INT_CLR_V << CACHE_L2_IBUS0_OVF_INT_CLR_S) -#define CACHE_L2_IBUS0_OVF_INT_CLR_V 0x00000001U -#define CACHE_L2_IBUS0_OVF_INT_CLR_S 8 -/** CACHE_L2_IBUS1_OVF_INT_CLR : HRO; bitpos: [9]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L2-Cache due - * to bus1 accesses L2-Cache. - */ -#define CACHE_L2_IBUS1_OVF_INT_CLR (BIT(9)) -#define CACHE_L2_IBUS1_OVF_INT_CLR_M (CACHE_L2_IBUS1_OVF_INT_CLR_V << CACHE_L2_IBUS1_OVF_INT_CLR_S) -#define CACHE_L2_IBUS1_OVF_INT_CLR_V 0x00000001U -#define CACHE_L2_IBUS1_OVF_INT_CLR_S 9 -/** CACHE_L2_IBUS2_OVF_INT_CLR : HRO; bitpos: [10]; default: 0; - * Reserved - */ -#define CACHE_L2_IBUS2_OVF_INT_CLR (BIT(10)) -#define CACHE_L2_IBUS2_OVF_INT_CLR_M (CACHE_L2_IBUS2_OVF_INT_CLR_V << CACHE_L2_IBUS2_OVF_INT_CLR_S) -#define CACHE_L2_IBUS2_OVF_INT_CLR_V 0x00000001U -#define CACHE_L2_IBUS2_OVF_INT_CLR_S 10 -/** CACHE_L2_IBUS3_OVF_INT_CLR : HRO; bitpos: [11]; default: 0; - * Reserved - */ -#define CACHE_L2_IBUS3_OVF_INT_CLR (BIT(11)) -#define CACHE_L2_IBUS3_OVF_INT_CLR_M (CACHE_L2_IBUS3_OVF_INT_CLR_V << CACHE_L2_IBUS3_OVF_INT_CLR_S) -#define CACHE_L2_IBUS3_OVF_INT_CLR_V 0x00000001U -#define CACHE_L2_IBUS3_OVF_INT_CLR_S 11 -/** CACHE_L2_DBUS0_OVF_INT_CLR : HRO; bitpos: [12]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L2-Cache due - * to bus0 accesses L2-Cache. - */ -#define CACHE_L2_DBUS0_OVF_INT_CLR (BIT(12)) -#define CACHE_L2_DBUS0_OVF_INT_CLR_M (CACHE_L2_DBUS0_OVF_INT_CLR_V << CACHE_L2_DBUS0_OVF_INT_CLR_S) -#define CACHE_L2_DBUS0_OVF_INT_CLR_V 0x00000001U -#define CACHE_L2_DBUS0_OVF_INT_CLR_S 12 -/** CACHE_L2_DBUS1_OVF_INT_CLR : HRO; bitpos: [13]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L2-Cache due - * to bus1 accesses L2-Cache. - */ -#define CACHE_L2_DBUS1_OVF_INT_CLR (BIT(13)) -#define CACHE_L2_DBUS1_OVF_INT_CLR_M (CACHE_L2_DBUS1_OVF_INT_CLR_V << CACHE_L2_DBUS1_OVF_INT_CLR_S) -#define CACHE_L2_DBUS1_OVF_INT_CLR_V 0x00000001U -#define CACHE_L2_DBUS1_OVF_INT_CLR_S 13 -/** CACHE_L2_DBUS2_OVF_INT_CLR : HRO; bitpos: [14]; default: 0; - * Reserved - */ -#define CACHE_L2_DBUS2_OVF_INT_CLR (BIT(14)) -#define CACHE_L2_DBUS2_OVF_INT_CLR_M (CACHE_L2_DBUS2_OVF_INT_CLR_V << CACHE_L2_DBUS2_OVF_INT_CLR_S) -#define CACHE_L2_DBUS2_OVF_INT_CLR_V 0x00000001U -#define CACHE_L2_DBUS2_OVF_INT_CLR_S 14 -/** CACHE_L2_DBUS3_OVF_INT_CLR : HRO; bitpos: [15]; default: 0; - * Reserved - */ -#define CACHE_L2_DBUS3_OVF_INT_CLR (BIT(15)) -#define CACHE_L2_DBUS3_OVF_INT_CLR_M (CACHE_L2_DBUS3_OVF_INT_CLR_V << CACHE_L2_DBUS3_OVF_INT_CLR_S) -#define CACHE_L2_DBUS3_OVF_INT_CLR_V 0x00000001U -#define CACHE_L2_DBUS3_OVF_INT_CLR_S 15 - -/** CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG register - * Cache Access Counter Interrupt raw register - */ -#define CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2d8) -/** CACHE_L2_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus0 accesses L2-ICache0. - */ -#define CACHE_L2_IBUS0_OVF_INT_RAW (BIT(8)) -#define CACHE_L2_IBUS0_OVF_INT_RAW_M (CACHE_L2_IBUS0_OVF_INT_RAW_V << CACHE_L2_IBUS0_OVF_INT_RAW_S) -#define CACHE_L2_IBUS0_OVF_INT_RAW_V 0x00000001U -#define CACHE_L2_IBUS0_OVF_INT_RAW_S 8 -/** CACHE_L2_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus1 accesses L2-ICache1. - */ -#define CACHE_L2_IBUS1_OVF_INT_RAW (BIT(9)) -#define CACHE_L2_IBUS1_OVF_INT_RAW_M (CACHE_L2_IBUS1_OVF_INT_RAW_V << CACHE_L2_IBUS1_OVF_INT_RAW_S) -#define CACHE_L2_IBUS1_OVF_INT_RAW_V 0x00000001U -#define CACHE_L2_IBUS1_OVF_INT_RAW_S 9 -/** CACHE_L2_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus2 accesses L2-ICache2. - */ -#define CACHE_L2_IBUS2_OVF_INT_RAW (BIT(10)) -#define CACHE_L2_IBUS2_OVF_INT_RAW_M (CACHE_L2_IBUS2_OVF_INT_RAW_V << CACHE_L2_IBUS2_OVF_INT_RAW_S) -#define CACHE_L2_IBUS2_OVF_INT_RAW_V 0x00000001U -#define CACHE_L2_IBUS2_OVF_INT_RAW_S 10 -/** CACHE_L2_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus3 accesses L2-ICache3. - */ -#define CACHE_L2_IBUS3_OVF_INT_RAW (BIT(11)) -#define CACHE_L2_IBUS3_OVF_INT_RAW_M (CACHE_L2_IBUS3_OVF_INT_RAW_V << CACHE_L2_IBUS3_OVF_INT_RAW_S) -#define CACHE_L2_IBUS3_OVF_INT_RAW_V 0x00000001U -#define CACHE_L2_IBUS3_OVF_INT_RAW_S 11 -/** CACHE_L2_DBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus0 accesses L2-DCache. - */ -#define CACHE_L2_DBUS0_OVF_INT_RAW (BIT(12)) -#define CACHE_L2_DBUS0_OVF_INT_RAW_M (CACHE_L2_DBUS0_OVF_INT_RAW_V << CACHE_L2_DBUS0_OVF_INT_RAW_S) -#define CACHE_L2_DBUS0_OVF_INT_RAW_V 0x00000001U -#define CACHE_L2_DBUS0_OVF_INT_RAW_S 12 -/** CACHE_L2_DBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus1 accesses L2-DCache. - */ -#define CACHE_L2_DBUS1_OVF_INT_RAW (BIT(13)) -#define CACHE_L2_DBUS1_OVF_INT_RAW_M (CACHE_L2_DBUS1_OVF_INT_RAW_V << CACHE_L2_DBUS1_OVF_INT_RAW_S) -#define CACHE_L2_DBUS1_OVF_INT_RAW_V 0x00000001U -#define CACHE_L2_DBUS1_OVF_INT_RAW_S 13 -/** CACHE_L2_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus2 accesses L2-DCache. - */ -#define CACHE_L2_DBUS2_OVF_INT_RAW (BIT(14)) -#define CACHE_L2_DBUS2_OVF_INT_RAW_M (CACHE_L2_DBUS2_OVF_INT_RAW_V << CACHE_L2_DBUS2_OVF_INT_RAW_S) -#define CACHE_L2_DBUS2_OVF_INT_RAW_V 0x00000001U -#define CACHE_L2_DBUS2_OVF_INT_RAW_S 14 -/** CACHE_L2_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus3 accesses L2-DCache. - */ -#define CACHE_L2_DBUS3_OVF_INT_RAW (BIT(15)) -#define CACHE_L2_DBUS3_OVF_INT_RAW_M (CACHE_L2_DBUS3_OVF_INT_RAW_V << CACHE_L2_DBUS3_OVF_INT_RAW_S) -#define CACHE_L2_DBUS3_OVF_INT_RAW_V 0x00000001U -#define CACHE_L2_DBUS3_OVF_INT_RAW_S 15 - -/** CACHE_L2_CACHE_ACS_CNT_INT_ST_REG register - * Cache Access Counter Interrupt status register - */ -#define CACHE_L2_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x2dc) -/** CACHE_L2_IBUS0_OVF_INT_ST : HRO; bitpos: [8]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L2-Cache due to bus0 accesses L2-Cache. - */ -#define CACHE_L2_IBUS0_OVF_INT_ST (BIT(8)) -#define CACHE_L2_IBUS0_OVF_INT_ST_M (CACHE_L2_IBUS0_OVF_INT_ST_V << CACHE_L2_IBUS0_OVF_INT_ST_S) -#define CACHE_L2_IBUS0_OVF_INT_ST_V 0x00000001U -#define CACHE_L2_IBUS0_OVF_INT_ST_S 8 -/** CACHE_L2_IBUS1_OVF_INT_ST : HRO; bitpos: [9]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L2-Cache due to bus1 accesses L2-Cache. - */ -#define CACHE_L2_IBUS1_OVF_INT_ST (BIT(9)) -#define CACHE_L2_IBUS1_OVF_INT_ST_M (CACHE_L2_IBUS1_OVF_INT_ST_V << CACHE_L2_IBUS1_OVF_INT_ST_S) -#define CACHE_L2_IBUS1_OVF_INT_ST_V 0x00000001U -#define CACHE_L2_IBUS1_OVF_INT_ST_S 9 -/** CACHE_L2_IBUS2_OVF_INT_ST : HRO; bitpos: [10]; default: 0; - * Reserved - */ -#define CACHE_L2_IBUS2_OVF_INT_ST (BIT(10)) -#define CACHE_L2_IBUS2_OVF_INT_ST_M (CACHE_L2_IBUS2_OVF_INT_ST_V << CACHE_L2_IBUS2_OVF_INT_ST_S) -#define CACHE_L2_IBUS2_OVF_INT_ST_V 0x00000001U -#define CACHE_L2_IBUS2_OVF_INT_ST_S 10 -/** CACHE_L2_IBUS3_OVF_INT_ST : HRO; bitpos: [11]; default: 0; - * Reserved - */ -#define CACHE_L2_IBUS3_OVF_INT_ST (BIT(11)) -#define CACHE_L2_IBUS3_OVF_INT_ST_M (CACHE_L2_IBUS3_OVF_INT_ST_V << CACHE_L2_IBUS3_OVF_INT_ST_S) -#define CACHE_L2_IBUS3_OVF_INT_ST_V 0x00000001U -#define CACHE_L2_IBUS3_OVF_INT_ST_S 11 -/** CACHE_L2_DBUS0_OVF_INT_ST : HRO; bitpos: [12]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L2-Cache due to bus0 accesses L2-Cache. - */ -#define CACHE_L2_DBUS0_OVF_INT_ST (BIT(12)) -#define CACHE_L2_DBUS0_OVF_INT_ST_M (CACHE_L2_DBUS0_OVF_INT_ST_V << CACHE_L2_DBUS0_OVF_INT_ST_S) -#define CACHE_L2_DBUS0_OVF_INT_ST_V 0x00000001U -#define CACHE_L2_DBUS0_OVF_INT_ST_S 12 -/** CACHE_L2_DBUS1_OVF_INT_ST : HRO; bitpos: [13]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L2-Cache due to bus1 accesses L2-Cache. - */ -#define CACHE_L2_DBUS1_OVF_INT_ST (BIT(13)) -#define CACHE_L2_DBUS1_OVF_INT_ST_M (CACHE_L2_DBUS1_OVF_INT_ST_V << CACHE_L2_DBUS1_OVF_INT_ST_S) -#define CACHE_L2_DBUS1_OVF_INT_ST_V 0x00000001U -#define CACHE_L2_DBUS1_OVF_INT_ST_S 13 -/** CACHE_L2_DBUS2_OVF_INT_ST : HRO; bitpos: [14]; default: 0; - * Reserved - */ -#define CACHE_L2_DBUS2_OVF_INT_ST (BIT(14)) -#define CACHE_L2_DBUS2_OVF_INT_ST_M (CACHE_L2_DBUS2_OVF_INT_ST_V << CACHE_L2_DBUS2_OVF_INT_ST_S) -#define CACHE_L2_DBUS2_OVF_INT_ST_V 0x00000001U -#define CACHE_L2_DBUS2_OVF_INT_ST_S 14 -/** CACHE_L2_DBUS3_OVF_INT_ST : HRO; bitpos: [15]; default: 0; - * Reserved - */ -#define CACHE_L2_DBUS3_OVF_INT_ST (BIT(15)) -#define CACHE_L2_DBUS3_OVF_INT_ST_M (CACHE_L2_DBUS3_OVF_INT_ST_V << CACHE_L2_DBUS3_OVF_INT_ST_S) -#define CACHE_L2_DBUS3_OVF_INT_ST_V 0x00000001U -#define CACHE_L2_DBUS3_OVF_INT_ST_S 15 - -/** CACHE_L2_CACHE_ACS_FAIL_CTRL_REG register - * Cache Access Fail Configuration register - */ -#define CACHE_L2_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x2e0) -/** CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE : HRO; bitpos: [0]; default: 0; - * The bit is used to configure l2 cache access fail check mode. 0: the access fail is - * not propagated to the request, 1: the access fail is propagated to the request - */ -#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE (BIT(0)) -#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_M (CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_S) -#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_V 0x00000001U -#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_S 0 - -/** CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG register - * Cache Access Fail Interrupt enable register - */ -#define CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2e4) -/** CACHE_L2_CACHE_FAIL_INT_ENA : HRO; bitpos: [5]; default: 0; - * The bit is used to enable interrupt of access fail that occurs in L2-Cache due to - * l1 cache accesses L2-Cache. - */ -#define CACHE_L2_CACHE_FAIL_INT_ENA (BIT(5)) -#define CACHE_L2_CACHE_FAIL_INT_ENA_M (CACHE_L2_CACHE_FAIL_INT_ENA_V << CACHE_L2_CACHE_FAIL_INT_ENA_S) -#define CACHE_L2_CACHE_FAIL_INT_ENA_V 0x00000001U -#define CACHE_L2_CACHE_FAIL_INT_ENA_S 5 - -/** CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG register - * L1-Cache Access Fail Interrupt clear register - */ -#define CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2e8) -/** CACHE_L2_CACHE_FAIL_INT_CLR : HRO; bitpos: [5]; default: 0; - * The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 - * cache accesses L2-Cache. - */ -#define CACHE_L2_CACHE_FAIL_INT_CLR (BIT(5)) -#define CACHE_L2_CACHE_FAIL_INT_CLR_M (CACHE_L2_CACHE_FAIL_INT_CLR_V << CACHE_L2_CACHE_FAIL_INT_CLR_S) -#define CACHE_L2_CACHE_FAIL_INT_CLR_V 0x00000001U -#define CACHE_L2_CACHE_FAIL_INT_CLR_S 5 - -/** CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG register - * Cache Access Fail Interrupt raw register - */ -#define CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2ec) -/** CACHE_L2_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L2-Cache. - */ -#define CACHE_L2_CACHE_FAIL_INT_RAW (BIT(5)) -#define CACHE_L2_CACHE_FAIL_INT_RAW_M (CACHE_L2_CACHE_FAIL_INT_RAW_V << CACHE_L2_CACHE_FAIL_INT_RAW_S) -#define CACHE_L2_CACHE_FAIL_INT_RAW_V 0x00000001U -#define CACHE_L2_CACHE_FAIL_INT_RAW_S 5 - -/** CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG register - * Cache Access Fail Interrupt status register - */ -#define CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x2f0) -/** CACHE_L2_CACHE_FAIL_INT_ST : HRO; bitpos: [5]; default: 0; - * The bit indicates the interrupt status of access fail that occurs in L2-Cache due - * to l1 cache accesses L2-Cache. - */ -#define CACHE_L2_CACHE_FAIL_INT_ST (BIT(5)) -#define CACHE_L2_CACHE_FAIL_INT_ST_M (CACHE_L2_CACHE_FAIL_INT_ST_V << CACHE_L2_CACHE_FAIL_INT_ST_S) -#define CACHE_L2_CACHE_FAIL_INT_ST_V 0x00000001U -#define CACHE_L2_CACHE_FAIL_INT_ST_S 5 - -/** CACHE_L2_CACHE_ACS_CNT_CTRL_REG register - * Cache Access Counter enable and clear register - */ -#define CACHE_L2_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x2f4) -/** CACHE_L2_IBUS0_CNT_ENA : HRO; bitpos: [8]; default: 0; - * The bit is used to enable ibus0 counter in L2-Cache. - */ -#define CACHE_L2_IBUS0_CNT_ENA (BIT(8)) -#define CACHE_L2_IBUS0_CNT_ENA_M (CACHE_L2_IBUS0_CNT_ENA_V << CACHE_L2_IBUS0_CNT_ENA_S) -#define CACHE_L2_IBUS0_CNT_ENA_V 0x00000001U -#define CACHE_L2_IBUS0_CNT_ENA_S 8 -/** CACHE_L2_IBUS1_CNT_ENA : HRO; bitpos: [9]; default: 0; - * The bit is used to enable ibus1 counter in L2-Cache. - */ -#define CACHE_L2_IBUS1_CNT_ENA (BIT(9)) -#define CACHE_L2_IBUS1_CNT_ENA_M (CACHE_L2_IBUS1_CNT_ENA_V << CACHE_L2_IBUS1_CNT_ENA_S) -#define CACHE_L2_IBUS1_CNT_ENA_V 0x00000001U -#define CACHE_L2_IBUS1_CNT_ENA_S 9 -/** CACHE_L2_IBUS2_CNT_ENA : HRO; bitpos: [10]; default: 0; - * Reserved - */ -#define CACHE_L2_IBUS2_CNT_ENA (BIT(10)) -#define CACHE_L2_IBUS2_CNT_ENA_M (CACHE_L2_IBUS2_CNT_ENA_V << CACHE_L2_IBUS2_CNT_ENA_S) -#define CACHE_L2_IBUS2_CNT_ENA_V 0x00000001U -#define CACHE_L2_IBUS2_CNT_ENA_S 10 -/** CACHE_L2_IBUS3_CNT_ENA : HRO; bitpos: [11]; default: 0; - * Reserved - */ -#define CACHE_L2_IBUS3_CNT_ENA (BIT(11)) -#define CACHE_L2_IBUS3_CNT_ENA_M (CACHE_L2_IBUS3_CNT_ENA_V << CACHE_L2_IBUS3_CNT_ENA_S) -#define CACHE_L2_IBUS3_CNT_ENA_V 0x00000001U -#define CACHE_L2_IBUS3_CNT_ENA_S 11 -/** CACHE_L2_DBUS0_CNT_ENA : HRO; bitpos: [12]; default: 0; - * The bit is used to enable dbus0 counter in L2-Cache. - */ -#define CACHE_L2_DBUS0_CNT_ENA (BIT(12)) -#define CACHE_L2_DBUS0_CNT_ENA_M (CACHE_L2_DBUS0_CNT_ENA_V << CACHE_L2_DBUS0_CNT_ENA_S) -#define CACHE_L2_DBUS0_CNT_ENA_V 0x00000001U -#define CACHE_L2_DBUS0_CNT_ENA_S 12 -/** CACHE_L2_DBUS1_CNT_ENA : HRO; bitpos: [13]; default: 0; - * The bit is used to enable dbus1 counter in L2-Cache. - */ -#define CACHE_L2_DBUS1_CNT_ENA (BIT(13)) -#define CACHE_L2_DBUS1_CNT_ENA_M (CACHE_L2_DBUS1_CNT_ENA_V << CACHE_L2_DBUS1_CNT_ENA_S) -#define CACHE_L2_DBUS1_CNT_ENA_V 0x00000001U -#define CACHE_L2_DBUS1_CNT_ENA_S 13 -/** CACHE_L2_DBUS2_CNT_ENA : HRO; bitpos: [14]; default: 0; - * Reserved - */ -#define CACHE_L2_DBUS2_CNT_ENA (BIT(14)) -#define CACHE_L2_DBUS2_CNT_ENA_M (CACHE_L2_DBUS2_CNT_ENA_V << CACHE_L2_DBUS2_CNT_ENA_S) -#define CACHE_L2_DBUS2_CNT_ENA_V 0x00000001U -#define CACHE_L2_DBUS2_CNT_ENA_S 14 -/** CACHE_L2_DBUS3_CNT_ENA : HRO; bitpos: [15]; default: 0; - * Reserved - */ -#define CACHE_L2_DBUS3_CNT_ENA (BIT(15)) -#define CACHE_L2_DBUS3_CNT_ENA_M (CACHE_L2_DBUS3_CNT_ENA_V << CACHE_L2_DBUS3_CNT_ENA_S) -#define CACHE_L2_DBUS3_CNT_ENA_V 0x00000001U -#define CACHE_L2_DBUS3_CNT_ENA_S 15 -/** CACHE_L2_IBUS0_CNT_CLR : HRO; bitpos: [24]; default: 0; - * The bit is used to clear ibus0 counter in L2-Cache. - */ -#define CACHE_L2_IBUS0_CNT_CLR (BIT(24)) -#define CACHE_L2_IBUS0_CNT_CLR_M (CACHE_L2_IBUS0_CNT_CLR_V << CACHE_L2_IBUS0_CNT_CLR_S) -#define CACHE_L2_IBUS0_CNT_CLR_V 0x00000001U -#define CACHE_L2_IBUS0_CNT_CLR_S 24 -/** CACHE_L2_IBUS1_CNT_CLR : HRO; bitpos: [25]; default: 0; - * The bit is used to clear ibus1 counter in L2-Cache. - */ -#define CACHE_L2_IBUS1_CNT_CLR (BIT(25)) -#define CACHE_L2_IBUS1_CNT_CLR_M (CACHE_L2_IBUS1_CNT_CLR_V << CACHE_L2_IBUS1_CNT_CLR_S) -#define CACHE_L2_IBUS1_CNT_CLR_V 0x00000001U -#define CACHE_L2_IBUS1_CNT_CLR_S 25 -/** CACHE_L2_IBUS2_CNT_CLR : HRO; bitpos: [26]; default: 0; - * Reserved - */ -#define CACHE_L2_IBUS2_CNT_CLR (BIT(26)) -#define CACHE_L2_IBUS2_CNT_CLR_M (CACHE_L2_IBUS2_CNT_CLR_V << CACHE_L2_IBUS2_CNT_CLR_S) -#define CACHE_L2_IBUS2_CNT_CLR_V 0x00000001U -#define CACHE_L2_IBUS2_CNT_CLR_S 26 -/** CACHE_L2_IBUS3_CNT_CLR : HRO; bitpos: [27]; default: 0; - * Reserved - */ -#define CACHE_L2_IBUS3_CNT_CLR (BIT(27)) -#define CACHE_L2_IBUS3_CNT_CLR_M (CACHE_L2_IBUS3_CNT_CLR_V << CACHE_L2_IBUS3_CNT_CLR_S) -#define CACHE_L2_IBUS3_CNT_CLR_V 0x00000001U -#define CACHE_L2_IBUS3_CNT_CLR_S 27 -/** CACHE_L2_DBUS0_CNT_CLR : HRO; bitpos: [28]; default: 0; - * The bit is used to clear dbus0 counter in L2-Cache. - */ -#define CACHE_L2_DBUS0_CNT_CLR (BIT(28)) -#define CACHE_L2_DBUS0_CNT_CLR_M (CACHE_L2_DBUS0_CNT_CLR_V << CACHE_L2_DBUS0_CNT_CLR_S) -#define CACHE_L2_DBUS0_CNT_CLR_V 0x00000001U -#define CACHE_L2_DBUS0_CNT_CLR_S 28 -/** CACHE_L2_DBUS1_CNT_CLR : HRO; bitpos: [29]; default: 0; - * The bit is used to clear dbus1 counter in L2-Cache. - */ -#define CACHE_L2_DBUS1_CNT_CLR (BIT(29)) -#define CACHE_L2_DBUS1_CNT_CLR_M (CACHE_L2_DBUS1_CNT_CLR_V << CACHE_L2_DBUS1_CNT_CLR_S) -#define CACHE_L2_DBUS1_CNT_CLR_V 0x00000001U -#define CACHE_L2_DBUS1_CNT_CLR_S 29 -/** CACHE_L2_DBUS2_CNT_CLR : HRO; bitpos: [30]; default: 0; - * Reserved - */ -#define CACHE_L2_DBUS2_CNT_CLR (BIT(30)) -#define CACHE_L2_DBUS2_CNT_CLR_M (CACHE_L2_DBUS2_CNT_CLR_V << CACHE_L2_DBUS2_CNT_CLR_S) -#define CACHE_L2_DBUS2_CNT_CLR_V 0x00000001U -#define CACHE_L2_DBUS2_CNT_CLR_S 30 -/** CACHE_L2_DBUS3_CNT_CLR : HRO; bitpos: [31]; default: 0; - * Reserved - */ -#define CACHE_L2_DBUS3_CNT_CLR (BIT(31)) -#define CACHE_L2_DBUS3_CNT_CLR_M (CACHE_L2_DBUS3_CNT_CLR_V << CACHE_L2_DBUS3_CNT_CLR_S) -#define CACHE_L2_DBUS3_CNT_CLR_V 0x00000001U -#define CACHE_L2_DBUS3_CNT_CLR_S 31 - -/** CACHE_L2_IBUS0_ACS_HIT_CNT_REG register - * L2-Cache bus0 Hit-Access Counter register - */ -#define CACHE_L2_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x2f8) -/** CACHE_L2_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-ICache0 accesses L2-Cache due to - * bus0 accessing L1-ICache0. - */ -#define CACHE_L2_IBUS0_HIT_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS0_HIT_CNT_M (CACHE_L2_IBUS0_HIT_CNT_V << CACHE_L2_IBUS0_HIT_CNT_S) -#define CACHE_L2_IBUS0_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS0_HIT_CNT_S 0 - -/** CACHE_L2_IBUS0_ACS_MISS_CNT_REG register - * L2-Cache bus0 Miss-Access Counter register - */ -#define CACHE_L2_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x2fc) -/** CACHE_L2_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-ICache0 accesses L2-Cache due to - * bus0 accessing L1-ICache0. - */ -#define CACHE_L2_IBUS0_MISS_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS0_MISS_CNT_M (CACHE_L2_IBUS0_MISS_CNT_V << CACHE_L2_IBUS0_MISS_CNT_S) -#define CACHE_L2_IBUS0_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS0_MISS_CNT_S 0 - -/** CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG register - * L2-Cache bus0 Conflict-Access Counter register - */ -#define CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x300) -/** CACHE_L2_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-ICache0 accesses - * L2-Cache due to bus0 accessing L1-ICache0. - */ -#define CACHE_L2_IBUS0_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS0_CONFLICT_CNT_M (CACHE_L2_IBUS0_CONFLICT_CNT_V << CACHE_L2_IBUS0_CONFLICT_CNT_S) -#define CACHE_L2_IBUS0_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS0_CONFLICT_CNT_S 0 - -/** CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG register - * L2-Cache bus0 Next-Level-Access Counter register - */ -#define CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x304) -/** CACHE_L2_IBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0. - */ -#define CACHE_L2_IBUS0_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_M (CACHE_L2_IBUS0_NXTLVL_RD_CNT_V << CACHE_L2_IBUS0_NXTLVL_RD_CNT_S) -#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_S 0 - -/** CACHE_L2_IBUS1_ACS_HIT_CNT_REG register - * L2-Cache bus1 Hit-Access Counter register - */ -#define CACHE_L2_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x308) -/** CACHE_L2_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-ICache1 accesses L2-Cache due to - * bus1 accessing L1-ICache1. - */ -#define CACHE_L2_IBUS1_HIT_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS1_HIT_CNT_M (CACHE_L2_IBUS1_HIT_CNT_V << CACHE_L2_IBUS1_HIT_CNT_S) -#define CACHE_L2_IBUS1_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS1_HIT_CNT_S 0 - -/** CACHE_L2_IBUS1_ACS_MISS_CNT_REG register - * L2-Cache bus1 Miss-Access Counter register - */ -#define CACHE_L2_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x30c) -/** CACHE_L2_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-ICache1 accesses L2-Cache due to - * bus1 accessing L1-ICache1. - */ -#define CACHE_L2_IBUS1_MISS_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS1_MISS_CNT_M (CACHE_L2_IBUS1_MISS_CNT_V << CACHE_L2_IBUS1_MISS_CNT_S) -#define CACHE_L2_IBUS1_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS1_MISS_CNT_S 0 - -/** CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG register - * L2-Cache bus1 Conflict-Access Counter register - */ -#define CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x310) -/** CACHE_L2_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-ICache1 accesses - * L2-Cache due to bus1 accessing L1-ICache1. - */ -#define CACHE_L2_IBUS1_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS1_CONFLICT_CNT_M (CACHE_L2_IBUS1_CONFLICT_CNT_V << CACHE_L2_IBUS1_CONFLICT_CNT_S) -#define CACHE_L2_IBUS1_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS1_CONFLICT_CNT_S 0 - -/** CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_REG register - * L2-Cache bus1 Next-Level-Access Counter register - */ -#define CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x314) -/** CACHE_L2_IBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1. - */ -#define CACHE_L2_IBUS1_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_M (CACHE_L2_IBUS1_NXTLVL_RD_CNT_V << CACHE_L2_IBUS1_NXTLVL_RD_CNT_S) -#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_S 0 - -/** CACHE_L2_IBUS2_ACS_HIT_CNT_REG register - * L2-Cache bus2 Hit-Access Counter register - */ -#define CACHE_L2_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x318) -/** CACHE_L2_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-ICache2 accesses L2-Cache due to - * bus2 accessing L1-ICache2. - */ -#define CACHE_L2_IBUS2_HIT_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS2_HIT_CNT_M (CACHE_L2_IBUS2_HIT_CNT_V << CACHE_L2_IBUS2_HIT_CNT_S) -#define CACHE_L2_IBUS2_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS2_HIT_CNT_S 0 - -/** CACHE_L2_IBUS2_ACS_MISS_CNT_REG register - * L2-Cache bus2 Miss-Access Counter register - */ -#define CACHE_L2_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x31c) -/** CACHE_L2_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-ICache2 accesses L2-Cache due to - * bus2 accessing L1-ICache2. - */ -#define CACHE_L2_IBUS2_MISS_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS2_MISS_CNT_M (CACHE_L2_IBUS2_MISS_CNT_V << CACHE_L2_IBUS2_MISS_CNT_S) -#define CACHE_L2_IBUS2_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS2_MISS_CNT_S 0 - -/** CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG register - * L2-Cache bus2 Conflict-Access Counter register - */ -#define CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x320) -/** CACHE_L2_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-ICache2 accesses - * L2-Cache due to bus2 accessing L1-ICache2. - */ -#define CACHE_L2_IBUS2_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS2_CONFLICT_CNT_M (CACHE_L2_IBUS2_CONFLICT_CNT_V << CACHE_L2_IBUS2_CONFLICT_CNT_S) -#define CACHE_L2_IBUS2_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS2_CONFLICT_CNT_S 0 - -/** CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_REG register - * L2-Cache bus2 Next-Level-Access Counter register - */ -#define CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x324) -/** CACHE_L2_IBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2. - */ -#define CACHE_L2_IBUS2_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_M (CACHE_L2_IBUS2_NXTLVL_RD_CNT_V << CACHE_L2_IBUS2_NXTLVL_RD_CNT_S) -#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_S 0 - -/** CACHE_L2_IBUS3_ACS_HIT_CNT_REG register - * L2-Cache bus3 Hit-Access Counter register - */ -#define CACHE_L2_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x328) -/** CACHE_L2_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-ICache3 accesses L2-Cache due to - * bus3 accessing L1-ICache3. - */ -#define CACHE_L2_IBUS3_HIT_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS3_HIT_CNT_M (CACHE_L2_IBUS3_HIT_CNT_V << CACHE_L2_IBUS3_HIT_CNT_S) -#define CACHE_L2_IBUS3_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS3_HIT_CNT_S 0 - -/** CACHE_L2_IBUS3_ACS_MISS_CNT_REG register - * L2-Cache bus3 Miss-Access Counter register - */ -#define CACHE_L2_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x32c) -/** CACHE_L2_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-ICache3 accesses L2-Cache due to - * bus3 accessing L1-ICache3. - */ -#define CACHE_L2_IBUS3_MISS_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS3_MISS_CNT_M (CACHE_L2_IBUS3_MISS_CNT_V << CACHE_L2_IBUS3_MISS_CNT_S) -#define CACHE_L2_IBUS3_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS3_MISS_CNT_S 0 - -/** CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG register - * L2-Cache bus3 Conflict-Access Counter register - */ -#define CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x330) -/** CACHE_L2_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-ICache3 accesses - * L2-Cache due to bus3 accessing L1-ICache3. - */ -#define CACHE_L2_IBUS3_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS3_CONFLICT_CNT_M (CACHE_L2_IBUS3_CONFLICT_CNT_V << CACHE_L2_IBUS3_CONFLICT_CNT_S) -#define CACHE_L2_IBUS3_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS3_CONFLICT_CNT_S 0 - -/** CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_REG register - * L2-Cache bus3 Next-Level-Access Counter register - */ -#define CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x334) -/** CACHE_L2_IBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3. - */ -#define CACHE_L2_IBUS3_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_M (CACHE_L2_IBUS3_NXTLVL_RD_CNT_V << CACHE_L2_IBUS3_NXTLVL_RD_CNT_S) -#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_S 0 - -/** CACHE_L2_DBUS0_ACS_HIT_CNT_REG register - * L2-Cache bus0 Hit-Access Counter register - */ -#define CACHE_L2_DBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x338) -/** CACHE_L2_DBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-DCache accesses L2-Cache due to - * bus0 accessing L1-DCache. - */ -#define CACHE_L2_DBUS0_HIT_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS0_HIT_CNT_M (CACHE_L2_DBUS0_HIT_CNT_V << CACHE_L2_DBUS0_HIT_CNT_S) -#define CACHE_L2_DBUS0_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS0_HIT_CNT_S 0 - -/** CACHE_L2_DBUS0_ACS_MISS_CNT_REG register - * L2-Cache bus0 Miss-Access Counter register - */ -#define CACHE_L2_DBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x33c) -/** CACHE_L2_DBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-DCache accesses L2-Cache due to - * bus0 accessing L1-DCache. - */ -#define CACHE_L2_DBUS0_MISS_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS0_MISS_CNT_M (CACHE_L2_DBUS0_MISS_CNT_V << CACHE_L2_DBUS0_MISS_CNT_S) -#define CACHE_L2_DBUS0_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS0_MISS_CNT_S 0 - -/** CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG register - * L2-Cache bus0 Conflict-Access Counter register - */ -#define CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x340) -/** CACHE_L2_DBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-DCache accesses - * L2-Cache due to bus0 accessing L1-DCache. - */ -#define CACHE_L2_DBUS0_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS0_CONFLICT_CNT_M (CACHE_L2_DBUS0_CONFLICT_CNT_V << CACHE_L2_DBUS0_CONFLICT_CNT_S) -#define CACHE_L2_DBUS0_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS0_CONFLICT_CNT_S 0 - -/** CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG register - * L2-Cache bus0 Next-Level-Access Counter register - */ -#define CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x344) -/** CACHE_L2_DBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache. - */ -#define CACHE_L2_DBUS0_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_M (CACHE_L2_DBUS0_NXTLVL_RD_CNT_V << CACHE_L2_DBUS0_NXTLVL_RD_CNT_S) -#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_S 0 - -/** CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG register - * L2-Cache bus0 WB-Access Counter register - */ -#define CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x348) -/** CACHE_L2_DBUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when L1-DCache accesses L2-Cache due - * to bus0 accessing L1-DCache. - */ -#define CACHE_L2_DBUS0_NXTLVL_WR_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_M (CACHE_L2_DBUS0_NXTLVL_WR_CNT_V << CACHE_L2_DBUS0_NXTLVL_WR_CNT_S) -#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_S 0 - -/** CACHE_L2_DBUS1_ACS_HIT_CNT_REG register - * L2-Cache bus1 Hit-Access Counter register - */ -#define CACHE_L2_DBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x34c) -/** CACHE_L2_DBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-DCache accesses L2-Cache due to - * bus1 accessing L1-DCache. - */ -#define CACHE_L2_DBUS1_HIT_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS1_HIT_CNT_M (CACHE_L2_DBUS1_HIT_CNT_V << CACHE_L2_DBUS1_HIT_CNT_S) -#define CACHE_L2_DBUS1_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS1_HIT_CNT_S 0 - -/** CACHE_L2_DBUS1_ACS_MISS_CNT_REG register - * L2-Cache bus1 Miss-Access Counter register - */ -#define CACHE_L2_DBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x350) -/** CACHE_L2_DBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-DCache accesses L2-Cache due to - * bus1 accessing L1-DCache. - */ -#define CACHE_L2_DBUS1_MISS_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS1_MISS_CNT_M (CACHE_L2_DBUS1_MISS_CNT_V << CACHE_L2_DBUS1_MISS_CNT_S) -#define CACHE_L2_DBUS1_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS1_MISS_CNT_S 0 - -/** CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG register - * L2-Cache bus1 Conflict-Access Counter register - */ -#define CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x354) -/** CACHE_L2_DBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-DCache accesses - * L2-Cache due to bus1 accessing L1-DCache. - */ -#define CACHE_L2_DBUS1_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS1_CONFLICT_CNT_M (CACHE_L2_DBUS1_CONFLICT_CNT_V << CACHE_L2_DBUS1_CONFLICT_CNT_S) -#define CACHE_L2_DBUS1_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS1_CONFLICT_CNT_S 0 - -/** CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_REG register - * L2-Cache bus1 Next-Level-Access Counter register - */ -#define CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x358) -/** CACHE_L2_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache. - */ -#define CACHE_L2_DBUS1_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_M (CACHE_L2_DBUS1_NXTLVL_RD_CNT_V << CACHE_L2_DBUS1_NXTLVL_RD_CNT_S) -#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_S 0 - -/** CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_REG register - * L2-Cache bus1 WB-Access Counter register - */ -#define CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x35c) -/** CACHE_L2_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when L1-DCache accesses L2-Cache due - * to bus1 accessing L1-DCache. - */ -#define CACHE_L2_DBUS1_NXTLVL_WR_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_M (CACHE_L2_DBUS1_NXTLVL_WR_CNT_V << CACHE_L2_DBUS1_NXTLVL_WR_CNT_S) -#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_S 0 - -/** CACHE_L2_DBUS2_ACS_HIT_CNT_REG register - * L2-Cache bus2 Hit-Access Counter register - */ -#define CACHE_L2_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x360) -/** CACHE_L2_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-DCache accesses L2-Cache due to - * bus2 accessing L1-DCache. - */ -#define CACHE_L2_DBUS2_HIT_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS2_HIT_CNT_M (CACHE_L2_DBUS2_HIT_CNT_V << CACHE_L2_DBUS2_HIT_CNT_S) -#define CACHE_L2_DBUS2_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS2_HIT_CNT_S 0 - -/** CACHE_L2_DBUS2_ACS_MISS_CNT_REG register - * L2-Cache bus2 Miss-Access Counter register - */ -#define CACHE_L2_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x364) -/** CACHE_L2_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-DCache accesses L2-Cache due to - * bus2 accessing L1-DCache. - */ -#define CACHE_L2_DBUS2_MISS_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS2_MISS_CNT_M (CACHE_L2_DBUS2_MISS_CNT_V << CACHE_L2_DBUS2_MISS_CNT_S) -#define CACHE_L2_DBUS2_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS2_MISS_CNT_S 0 - -/** CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG register - * L2-Cache bus2 Conflict-Access Counter register - */ -#define CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x368) -/** CACHE_L2_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-DCache accesses - * L2-Cache due to bus2 accessing L1-DCache. - */ -#define CACHE_L2_DBUS2_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS2_CONFLICT_CNT_M (CACHE_L2_DBUS2_CONFLICT_CNT_V << CACHE_L2_DBUS2_CONFLICT_CNT_S) -#define CACHE_L2_DBUS2_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS2_CONFLICT_CNT_S 0 - -/** CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_REG register - * L2-Cache bus2 Next-Level-Access Counter register - */ -#define CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x36c) -/** CACHE_L2_DBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache. - */ -#define CACHE_L2_DBUS2_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_M (CACHE_L2_DBUS2_NXTLVL_RD_CNT_V << CACHE_L2_DBUS2_NXTLVL_RD_CNT_S) -#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_S 0 - -/** CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_REG register - * L2-Cache bus2 WB-Access Counter register - */ -#define CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x370) -/** CACHE_L2_DBUS2_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when L1-DCache accesses L2-Cache due - * to bus2 accessing L1-DCache. - */ -#define CACHE_L2_DBUS2_NXTLVL_WR_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_M (CACHE_L2_DBUS2_NXTLVL_WR_CNT_V << CACHE_L2_DBUS2_NXTLVL_WR_CNT_S) -#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_S 0 - -/** CACHE_L2_DBUS3_ACS_HIT_CNT_REG register - * L2-Cache bus3 Hit-Access Counter register - */ -#define CACHE_L2_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x374) -/** CACHE_L2_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-DCache accesses L2-Cache due to - * bus3 accessing L1-DCache. - */ -#define CACHE_L2_DBUS3_HIT_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS3_HIT_CNT_M (CACHE_L2_DBUS3_HIT_CNT_V << CACHE_L2_DBUS3_HIT_CNT_S) -#define CACHE_L2_DBUS3_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS3_HIT_CNT_S 0 - -/** CACHE_L2_DBUS3_ACS_MISS_CNT_REG register - * L2-Cache bus3 Miss-Access Counter register - */ -#define CACHE_L2_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x378) -/** CACHE_L2_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-DCache accesses L2-Cache due to - * bus3 accessing L1-DCache. - */ -#define CACHE_L2_DBUS3_MISS_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS3_MISS_CNT_M (CACHE_L2_DBUS3_MISS_CNT_V << CACHE_L2_DBUS3_MISS_CNT_S) -#define CACHE_L2_DBUS3_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS3_MISS_CNT_S 0 - -/** CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG register - * L2-Cache bus3 Conflict-Access Counter register - */ -#define CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x37c) -/** CACHE_L2_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-DCache accesses - * L2-Cache due to bus3 accessing L1-DCache. - */ -#define CACHE_L2_DBUS3_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS3_CONFLICT_CNT_M (CACHE_L2_DBUS3_CONFLICT_CNT_V << CACHE_L2_DBUS3_CONFLICT_CNT_S) -#define CACHE_L2_DBUS3_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS3_CONFLICT_CNT_S 0 - -/** CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_REG register - * L2-Cache bus3 Next-Level-Access Counter register - */ -#define CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x380) -/** CACHE_L2_DBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache. - */ -#define CACHE_L2_DBUS3_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_M (CACHE_L2_DBUS3_NXTLVL_RD_CNT_V << CACHE_L2_DBUS3_NXTLVL_RD_CNT_S) -#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_S 0 - -/** CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_REG register - * L2-Cache bus3 WB-Access Counter register - */ -#define CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x384) -/** CACHE_L2_DBUS3_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when L1-DCache accesses L2-Cache due - * to bus3 accessing L1-DCache. - */ -#define CACHE_L2_DBUS3_NXTLVL_WR_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_M (CACHE_L2_DBUS3_NXTLVL_WR_CNT_V << CACHE_L2_DBUS3_NXTLVL_WR_CNT_S) -#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_S 0 - -/** CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG register - * L2-Cache Access Fail ID/attribution information register - */ -#define CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x388) -/** CACHE_L2_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when L1-Cache accesses L2-Cache. - */ -#define CACHE_L2_CACHE_FAIL_ID 0x0000FFFFU -#define CACHE_L2_CACHE_FAIL_ID_M (CACHE_L2_CACHE_FAIL_ID_V << CACHE_L2_CACHE_FAIL_ID_S) -#define CACHE_L2_CACHE_FAIL_ID_V 0x0000FFFFU -#define CACHE_L2_CACHE_FAIL_ID_S 0 -/** CACHE_L2_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when L1-Cache accesses L2-Cache - * due to cache accessing L1-Cache. - */ -#define CACHE_L2_CACHE_FAIL_ATTR 0x0000FFFFU -#define CACHE_L2_CACHE_FAIL_ATTR_M (CACHE_L2_CACHE_FAIL_ATTR_V << CACHE_L2_CACHE_FAIL_ATTR_S) -#define CACHE_L2_CACHE_FAIL_ATTR_V 0x0000FFFFU -#define CACHE_L2_CACHE_FAIL_ATTR_S 16 - -/** CACHE_L2_CACHE_ACS_FAIL_ADDR_REG register - * L2-Cache Access Fail Address information register - */ -#define CACHE_L2_CACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x38c) -/** CACHE_L2_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when L1-Cache accesses L2-Cache. - */ -#define CACHE_L2_CACHE_FAIL_ADDR 0xFFFFFFFFU -#define CACHE_L2_CACHE_FAIL_ADDR_M (CACHE_L2_CACHE_FAIL_ADDR_V << CACHE_L2_CACHE_FAIL_ADDR_S) -#define CACHE_L2_CACHE_FAIL_ADDR_V 0xFFFFFFFFU -#define CACHE_L2_CACHE_FAIL_ADDR_S 0 - -/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG register - * L1-Cache Access Fail Interrupt enable register - */ -#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x390) -/** CACHE_L2_CACHE_PLD_DONE_INT_ENA : HRO; bitpos: [5]; default: 0; - * The bit is used to enable interrupt of L2-Cache preload-operation done. - */ -#define CACHE_L2_CACHE_PLD_DONE_INT_ENA (BIT(5)) -#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_M (CACHE_L2_CACHE_PLD_DONE_INT_ENA_V << CACHE_L2_CACHE_PLD_DONE_INT_ENA_S) -#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_V 0x00000001U -#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_S 5 -/** CACHE_L2_CACHE_PLD_ERR_INT_ENA : HRO; bitpos: [12]; default: 0; - * The bit is used to enable interrupt of L2-Cache preload-operation error. - */ -#define CACHE_L2_CACHE_PLD_ERR_INT_ENA (BIT(12)) -#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_M (CACHE_L2_CACHE_PLD_ERR_INT_ENA_V << CACHE_L2_CACHE_PLD_ERR_INT_ENA_S) -#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_V 0x00000001U -#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_S 12 - -/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG register - * Sync Preload operation Interrupt clear register - */ -#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x394) -/** CACHE_L2_CACHE_PLD_DONE_INT_CLR : HRO; bitpos: [5]; default: 0; - * The bit is used to clear interrupt that occurs only when L2-Cache preload-operation - * is done. - */ -#define CACHE_L2_CACHE_PLD_DONE_INT_CLR (BIT(5)) -#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_M (CACHE_L2_CACHE_PLD_DONE_INT_CLR_V << CACHE_L2_CACHE_PLD_DONE_INT_CLR_S) -#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_V 0x00000001U -#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_S 5 -/** CACHE_L2_CACHE_PLD_ERR_INT_CLR : HRO; bitpos: [12]; default: 0; - * The bit is used to clear interrupt of L2-Cache preload-operation error. - */ -#define CACHE_L2_CACHE_PLD_ERR_INT_CLR (BIT(12)) -#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_M (CACHE_L2_CACHE_PLD_ERR_INT_CLR_V << CACHE_L2_CACHE_PLD_ERR_INT_CLR_S) -#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_V 0x00000001U -#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_S 12 - -/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG register - * Sync Preload operation Interrupt raw register - */ -#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x398) -/** CACHE_L2_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit of the interrupt that occurs only when L2-Cache preload-operation is - * done. - */ -#define CACHE_L2_CACHE_PLD_DONE_INT_RAW (BIT(5)) -#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_M (CACHE_L2_CACHE_PLD_DONE_INT_RAW_V << CACHE_L2_CACHE_PLD_DONE_INT_RAW_S) -#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_V 0x00000001U -#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_S 5 -/** CACHE_L2_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw bit of the interrupt that occurs only when L2-Cache preload-operation error - * occurs. - */ -#define CACHE_L2_CACHE_PLD_ERR_INT_RAW (BIT(12)) -#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_M (CACHE_L2_CACHE_PLD_ERR_INT_RAW_V << CACHE_L2_CACHE_PLD_ERR_INT_RAW_S) -#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_V 0x00000001U -#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_S 12 - -/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG register - * L1-Cache Access Fail Interrupt status register - */ -#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x39c) -/** CACHE_L2_CACHE_PLD_DONE_INT_ST : HRO; bitpos: [5]; default: 0; - * The bit indicates the status of the interrupt that occurs only when L2-Cache - * preload-operation is done. - */ -#define CACHE_L2_CACHE_PLD_DONE_INT_ST (BIT(5)) -#define CACHE_L2_CACHE_PLD_DONE_INT_ST_M (CACHE_L2_CACHE_PLD_DONE_INT_ST_V << CACHE_L2_CACHE_PLD_DONE_INT_ST_S) -#define CACHE_L2_CACHE_PLD_DONE_INT_ST_V 0x00000001U -#define CACHE_L2_CACHE_PLD_DONE_INT_ST_S 5 -/** CACHE_L2_CACHE_PLD_ERR_INT_ST : HRO; bitpos: [12]; default: 0; - * The bit indicates the status of the interrupt of L2-Cache preload-operation error. - */ -#define CACHE_L2_CACHE_PLD_ERR_INT_ST (BIT(12)) -#define CACHE_L2_CACHE_PLD_ERR_INT_ST_M (CACHE_L2_CACHE_PLD_ERR_INT_ST_V << CACHE_L2_CACHE_PLD_ERR_INT_ST_S) -#define CACHE_L2_CACHE_PLD_ERR_INT_ST_V 0x00000001U -#define CACHE_L2_CACHE_PLD_ERR_INT_ST_S 12 - -/** CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG register - * Cache Sync/Preload Operation exception register - */ -#define CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x3a0) -/** CACHE_L2_CACHE_PLD_ERR_CODE : RO; bitpos: [11:10]; default: 0; - * The value 2 is Only available which means preload size is error in L2-Cache. - */ -#define CACHE_L2_CACHE_PLD_ERR_CODE 0x00000003U -#define CACHE_L2_CACHE_PLD_ERR_CODE_M (CACHE_L2_CACHE_PLD_ERR_CODE_V << CACHE_L2_CACHE_PLD_ERR_CODE_S) -#define CACHE_L2_CACHE_PLD_ERR_CODE_V 0x00000003U -#define CACHE_L2_CACHE_PLD_ERR_CODE_S 10 - -/** CACHE_L2_CACHE_SYNC_RST_CTRL_REG register - * Cache Sync Reset control register - */ -#define CACHE_L2_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x3a4) -/** CACHE_L2_CACHE_SYNC_RST : HRO; bitpos: [5]; default: 0; - * set this bit to reset sync-logic inside L2-Cache. Recommend that this should only - * be used to initialize sync-logic when some fatal error of sync-logic occurs. - */ -#define CACHE_L2_CACHE_SYNC_RST (BIT(5)) -#define CACHE_L2_CACHE_SYNC_RST_M (CACHE_L2_CACHE_SYNC_RST_V << CACHE_L2_CACHE_SYNC_RST_S) -#define CACHE_L2_CACHE_SYNC_RST_V 0x00000001U -#define CACHE_L2_CACHE_SYNC_RST_S 5 - -/** CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG register - * Cache Preload Reset control register - */ -#define CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x3a8) -/** CACHE_L2_CACHE_PLD_RST : HRO; bitpos: [5]; default: 0; - * set this bit to reset preload-logic inside L2-Cache. Recommend that this should - * only be used to initialize preload-logic when some fatal error of preload-logic - * occurs. - */ -#define CACHE_L2_CACHE_PLD_RST (BIT(5)) -#define CACHE_L2_CACHE_PLD_RST_M (CACHE_L2_CACHE_PLD_RST_V << CACHE_L2_CACHE_PLD_RST_S) -#define CACHE_L2_CACHE_PLD_RST_V 0x00000001U -#define CACHE_L2_CACHE_PLD_RST_S 5 - -/** CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register - * Cache Autoload buffer clear control register - */ -#define CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x3ac) -/** CACHE_L2_CACHE_ALD_BUF_CLR : HRO; bitpos: [5]; default: 0; - * set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, - * autoload will not work in L2-Cache. This bit should not be active when autoload - * works in L2-Cache. - */ -#define CACHE_L2_CACHE_ALD_BUF_CLR (BIT(5)) -#define CACHE_L2_CACHE_ALD_BUF_CLR_M (CACHE_L2_CACHE_ALD_BUF_CLR_V << CACHE_L2_CACHE_ALD_BUF_CLR_S) -#define CACHE_L2_CACHE_ALD_BUF_CLR_V 0x00000001U -#define CACHE_L2_CACHE_ALD_BUF_CLR_S 5 - -/** CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG register - * Unallocate request buffer clear registers - */ -#define CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x3b0) -/** CACHE_L2_CACHE_UNALLOC_CLR : HRO; bitpos: [5]; default: 0; - * The bit is used to clear the unallocate request buffer of l2 icache where the - * unallocate request is responded but not completed. - */ -#define CACHE_L2_CACHE_UNALLOC_CLR (BIT(5)) -#define CACHE_L2_CACHE_UNALLOC_CLR_M (CACHE_L2_CACHE_UNALLOC_CLR_V << CACHE_L2_CACHE_UNALLOC_CLR_S) -#define CACHE_L2_CACHE_UNALLOC_CLR_V 0x00000001U -#define CACHE_L2_CACHE_UNALLOC_CLR_S 5 - -/** CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG register - * L2 cache access attribute control register - */ -#define CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG (DR_REG_CACHE_BASE + 0x3b4) -/** CACHE_L2_CACHE_ACCESS_FORCE_CC : HRO; bitpos: [0]; default: 1; - * Set this bit to force the request to l2 cache with cacheable attribute, otherwise, - * the attribute is propagated from L1 cache or CPU, it could be one of cacheable and - * non-cacheable. - */ -#define CACHE_L2_CACHE_ACCESS_FORCE_CC (BIT(0)) -#define CACHE_L2_CACHE_ACCESS_FORCE_CC_M (CACHE_L2_CACHE_ACCESS_FORCE_CC_V << CACHE_L2_CACHE_ACCESS_FORCE_CC_S) -#define CACHE_L2_CACHE_ACCESS_FORCE_CC_V 0x00000001U -#define CACHE_L2_CACHE_ACCESS_FORCE_CC_S 0 -/** CACHE_L2_CACHE_ACCESS_FORCE_WB : HRO; bitpos: [1]; default: 1; - * Set this bit to force the request to l2 cache with write-back attribute, otherwise, - * the attribute is propagated from L1 cache or CPU, it could be one of write-back and - * write-through. - */ -#define CACHE_L2_CACHE_ACCESS_FORCE_WB (BIT(1)) -#define CACHE_L2_CACHE_ACCESS_FORCE_WB_M (CACHE_L2_CACHE_ACCESS_FORCE_WB_V << CACHE_L2_CACHE_ACCESS_FORCE_WB_S) -#define CACHE_L2_CACHE_ACCESS_FORCE_WB_V 0x00000001U -#define CACHE_L2_CACHE_ACCESS_FORCE_WB_S 1 -/** CACHE_L2_CACHE_ACCESS_FORCE_WMA : HRO; bitpos: [2]; default: 1; - * Set this bit to force the request to l2 cache with write-miss-allocate attribute, - * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of - * write-miss-allocate and write-miss-no-allocate. - */ -#define CACHE_L2_CACHE_ACCESS_FORCE_WMA (BIT(2)) -#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_M (CACHE_L2_CACHE_ACCESS_FORCE_WMA_V << CACHE_L2_CACHE_ACCESS_FORCE_WMA_S) -#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_V 0x00000001U -#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_S 2 -/** CACHE_L2_CACHE_ACCESS_FORCE_RMA : HRO; bitpos: [3]; default: 1; - * Set this bit to force the request to l2 cache with read-miss-allocate attribute, - * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of - * read-miss-allocate and read-miss-no-allocate. - */ -#define CACHE_L2_CACHE_ACCESS_FORCE_RMA (BIT(3)) -#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_M (CACHE_L2_CACHE_ACCESS_FORCE_RMA_V << CACHE_L2_CACHE_ACCESS_FORCE_RMA_S) -#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_V 0x00000001U -#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_S 3 - -/** CACHE_L2_CACHE_OBJECT_CTRL_REG register - * Cache Tag and Data memory Object control register - */ -#define CACHE_L2_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x3b8) -/** CACHE_L2_CACHE_TAG_OBJECT : HRO; bitpos: [5]; default: 0; - * Set this bit to set L2-Cache tag memory as object. This bit should be onehot with - * the others fields inside this register. - */ -#define CACHE_L2_CACHE_TAG_OBJECT (BIT(5)) -#define CACHE_L2_CACHE_TAG_OBJECT_M (CACHE_L2_CACHE_TAG_OBJECT_V << CACHE_L2_CACHE_TAG_OBJECT_S) -#define CACHE_L2_CACHE_TAG_OBJECT_V 0x00000001U -#define CACHE_L2_CACHE_TAG_OBJECT_S 5 -/** CACHE_L2_CACHE_MEM_OBJECT : HRO; bitpos: [11]; default: 0; - * Set this bit to set L2-Cache data memory as object. This bit should be onehot with - * the others fields inside this register. - */ -#define CACHE_L2_CACHE_MEM_OBJECT (BIT(11)) -#define CACHE_L2_CACHE_MEM_OBJECT_M (CACHE_L2_CACHE_MEM_OBJECT_V << CACHE_L2_CACHE_MEM_OBJECT_S) -#define CACHE_L2_CACHE_MEM_OBJECT_V 0x00000001U -#define CACHE_L2_CACHE_MEM_OBJECT_S 11 - -/** CACHE_L2_CACHE_WAY_OBJECT_REG register - * Cache Tag and Data memory way register - */ -#define CACHE_L2_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x3bc) -/** CACHE_L2_CACHE_WAY_OBJECT : HRO; bitpos: [2:0]; default: 0; - * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: - * way1, 2: way2, 3: way3, ?, 7: way7. - */ -#define CACHE_L2_CACHE_WAY_OBJECT 0x00000007U -#define CACHE_L2_CACHE_WAY_OBJECT_M (CACHE_L2_CACHE_WAY_OBJECT_V << CACHE_L2_CACHE_WAY_OBJECT_S) -#define CACHE_L2_CACHE_WAY_OBJECT_V 0x00000007U -#define CACHE_L2_CACHE_WAY_OBJECT_S 0 - -/** CACHE_L2_CACHE_ADDR_REG register - * Cache address register - */ -#define CACHE_L2_CACHE_ADDR_REG (DR_REG_CACHE_BASE + 0x3c0) -/** CACHE_L2_CACHE_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits stores the address which will decide where inside the specified tag - * memory object will be accessed. - */ -#define CACHE_L2_CACHE_ADDR 0xFFFFFFFFU -#define CACHE_L2_CACHE_ADDR_M (CACHE_L2_CACHE_ADDR_V << CACHE_L2_CACHE_ADDR_S) -#define CACHE_L2_CACHE_ADDR_V 0xFFFFFFFFU -#define CACHE_L2_CACHE_ADDR_S 0 - -/** CACHE_L2_CACHE_DEBUG_BUS_REG register - * Cache Tag/data memory content register - */ -#define CACHE_L2_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x3c4) -/** CACHE_L2_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 964; - * This is a constant place where we can write data to or read data from the tag/data - * memory on the specified cache. - */ -#define CACHE_L2_CACHE_DEBUG_BUS 0xFFFFFFFFU -#define CACHE_L2_CACHE_DEBUG_BUS_M (CACHE_L2_CACHE_DEBUG_BUS_V << CACHE_L2_CACHE_DEBUG_BUS_S) -#define CACHE_L2_CACHE_DEBUG_BUS_V 0xFFFFFFFFU -#define CACHE_L2_CACHE_DEBUG_BUS_S 0 - -/** CACHE_LEVEL_SPLIT1_REG register - * USED TO SPLIT L1 CACHE AND L2 CACHE - */ -#define CACHE_LEVEL_SPLIT1_REG (DR_REG_CACHE_BASE + 0x3c8) -/** CACHE_LEVEL_SPLIT1 : HRO; bitpos: [31:0]; default: 968; - * Reserved - */ -#define CACHE_LEVEL_SPLIT1 0xFFFFFFFFU -#define CACHE_LEVEL_SPLIT1_M (CACHE_LEVEL_SPLIT1_V << CACHE_LEVEL_SPLIT1_S) -#define CACHE_LEVEL_SPLIT1_V 0xFFFFFFFFU -#define CACHE_LEVEL_SPLIT1_S 0 - -/** CACHE_CLOCK_GATE_REG register - * Clock gate control register - */ -#define CACHE_CLOCK_GATE_REG (DR_REG_CACHE_BASE + 0x3cc) -/** CACHE_CLK_EN : R/W; bitpos: [0]; default: 0; - * The bit is used to enable clock gate when access all registers in this module. - */ -#define CACHE_CLK_EN (BIT(0)) -#define CACHE_CLK_EN_M (CACHE_CLK_EN_V << CACHE_CLK_EN_S) -#define CACHE_CLK_EN_V 0x00000001U -#define CACHE_CLK_EN_S 0 - /** CACHE_TRACE_ENA_REG register * Clock gate control register */ @@ -6080,81 +1210,14 @@ extern "C" { #define CACHE_L1_CACHE_TRACE_ENA_M (CACHE_L1_CACHE_TRACE_ENA_V << CACHE_L1_CACHE_TRACE_ENA_S) #define CACHE_L1_CACHE_TRACE_ENA_V 0x00000001U #define CACHE_L1_CACHE_TRACE_ENA_S 0 -/** CACHE_L2_CACHE_TRACE_ENA : HRO; bitpos: [1]; default: 0; - * The bit is used to enable L2-Cache trace for the performance counter and fail tracer - */ -#define CACHE_L2_CACHE_TRACE_ENA (BIT(1)) -#define CACHE_L2_CACHE_TRACE_ENA_M (CACHE_L2_CACHE_TRACE_ENA_V << CACHE_L2_CACHE_TRACE_ENA_S) -#define CACHE_L2_CACHE_TRACE_ENA_V 0x00000001U -#define CACHE_L2_CACHE_TRACE_ENA_S 1 - -/** CACHE_REDUNDANCY_SIG0_REG register - * Cache redundancy signal 0 register - */ -#define CACHE_REDUNDANCY_SIG0_REG (DR_REG_CACHE_BASE + 0x3d4) -/** CACHE_REDCY_SIG0 : R/W; bitpos: [31:0]; default: 0; - * Those bits are prepared for ECO. - */ -#define CACHE_REDCY_SIG0 0xFFFFFFFFU -#define CACHE_REDCY_SIG0_M (CACHE_REDCY_SIG0_V << CACHE_REDCY_SIG0_S) -#define CACHE_REDCY_SIG0_V 0xFFFFFFFFU -#define CACHE_REDCY_SIG0_S 0 - -/** CACHE_REDUNDANCY_SIG1_REG register - * Cache redundancy signal 1 register - */ -#define CACHE_REDUNDANCY_SIG1_REG (DR_REG_CACHE_BASE + 0x3d8) -/** CACHE_REDCY_SIG1 : R/W; bitpos: [31:0]; default: 0; - * Those bits are prepared for ECO. - */ -#define CACHE_REDCY_SIG1 0xFFFFFFFFU -#define CACHE_REDCY_SIG1_M (CACHE_REDCY_SIG1_V << CACHE_REDCY_SIG1_S) -#define CACHE_REDCY_SIG1_V 0xFFFFFFFFU -#define CACHE_REDCY_SIG1_S 0 - -/** CACHE_REDUNDANCY_SIG2_REG register - * Cache redundancy signal 2 register - */ -#define CACHE_REDUNDANCY_SIG2_REG (DR_REG_CACHE_BASE + 0x3dc) -/** CACHE_REDCY_SIG2 : R/W; bitpos: [31:0]; default: 0; - * Those bits are prepared for ECO. - */ -#define CACHE_REDCY_SIG2 0xFFFFFFFFU -#define CACHE_REDCY_SIG2_M (CACHE_REDCY_SIG2_V << CACHE_REDCY_SIG2_S) -#define CACHE_REDCY_SIG2_V 0xFFFFFFFFU -#define CACHE_REDCY_SIG2_S 0 - -/** CACHE_REDUNDANCY_SIG3_REG register - * Cache redundancy signal 3 register - */ -#define CACHE_REDUNDANCY_SIG3_REG (DR_REG_CACHE_BASE + 0x3e0) -/** CACHE_REDCY_SIG3 : R/W; bitpos: [31:0]; default: 0; - * Those bits are prepared for ECO. - */ -#define CACHE_REDCY_SIG3 0xFFFFFFFFU -#define CACHE_REDCY_SIG3_M (CACHE_REDCY_SIG3_V << CACHE_REDCY_SIG3_S) -#define CACHE_REDCY_SIG3_V 0xFFFFFFFFU -#define CACHE_REDCY_SIG3_S 0 - -/** CACHE_REDUNDANCY_SIG4_REG register - * Cache redundancy signal 0 register - */ -#define CACHE_REDUNDANCY_SIG4_REG (DR_REG_CACHE_BASE + 0x3e4) -/** CACHE_REDCY_SIG4 : RO; bitpos: [3:0]; default: 0; - * Those bits are prepared for ECO. - */ -#define CACHE_REDCY_SIG4 0x0000000FU -#define CACHE_REDCY_SIG4_M (CACHE_REDCY_SIG4_V << CACHE_REDCY_SIG4_S) -#define CACHE_REDCY_SIG4_V 0x0000000FU -#define CACHE_REDCY_SIG4_S 0 /** CACHE_DATE_REG register * Version control register */ #define CACHE_DATE_REG (DR_REG_CACHE_BASE + 0x3fc) /** CACHE_DATE : R/W; bitpos: [27:0]; default: 36774432; - * version control register. Note that this default value stored is the latest date - * when the hardware logic was updated. + * Version control register. Note that the default value is the latest date when the + * hardware logic was updated. */ #define CACHE_DATE 0x0FFFFFFFU #define CACHE_DATE_M (CACHE_DATE_V << CACHE_DATE_S) diff --git a/components/soc/esp32c61/register/soc/cache_struct.h b/components/soc/esp32c61/register/soc/cache_struct.h index 408c01c2c7..ed1c69cd68 100644 --- a/components/soc/esp32c61/register/soc/cache_struct.h +++ b/components/soc/esp32c61/register/soc/cache_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,529 +10,69 @@ extern "C" { #endif -/** Group: Control and configuration registers */ -/** Type of l1_icache_ctrl register - * L1 instruction Cache(L1-ICache) control register - */ -typedef union { - struct { - /** l1_icache_shut_ibus0 : R/W; bitpos: [0]; default: 0; - * The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable - */ - uint32_t l1_icache_shut_ibus0:1; - /** l1_icache_shut_ibus1 : R/W; bitpos: [1]; default: 0; - * The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable - */ - uint32_t l1_icache_shut_ibus1:1; - /** l1_icache_shut_ibus2 : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache_shut_ibus2:1; - /** l1_icache_shut_ibus3 : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache_shut_ibus3:1; - uint32_t reserved_4:4; - /** l1_icache_undef_op : R/W; bitpos: [15:8]; default: 0; - * Reserved - */ - uint32_t l1_icache_undef_op:8; - uint32_t reserved_16:16; - }; - uint32_t val; -} cache_l1_icache_ctrl_reg_t; - +/** Group: Control and Configuration Registers */ /** Type of l1_cache_ctrl register - * L1 data Cache(L1-Cache) control register + * L1 data cache (L1 cache) control register */ typedef union { struct { /** l1_cache_shut_bus0 : R/W; bitpos: [0]; default: 0; - * The bit is used to disable core0 bus0 access L1-Cache, 0: enable, 1: disable + * Configures whether to disable BUS0 to access the L1 cache. + * 0: Enable + * 1: Disable */ uint32_t l1_cache_shut_bus0:1; /** l1_cache_shut_bus1 : R/W; bitpos: [1]; default: 0; - * The bit is used to disable core0 bus1 access L1-Cache, 0: enable, 1: disable + * Configures whether to disable BUS1 to access the L1 cache. + * 0: Enable + * 1: Disable */ uint32_t l1_cache_shut_bus1:1; - /** l1_cache_shut_dbus2 : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_cache_shut_dbus2:1; - /** l1_cache_shut_dbus3 : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_cache_shut_dbus3:1; - /** l1_cache_shut_dma : HRO; bitpos: [4]; default: 0; - * The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable - */ - uint32_t l1_cache_shut_dma:1; - uint32_t reserved_5:3; - /** l1_cache_undef_op : R/W; bitpos: [15:8]; default: 0; - * Reserved - */ - uint32_t l1_cache_undef_op:8; - uint32_t reserved_16:16; + uint32_t reserved_2:30; }; uint32_t val; } cache_l1_cache_ctrl_reg_t; -/** Type of l2_cache_ctrl register - * L2 Cache(L2-Cache) control register - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** l2_cache_shut_dma : HRO; bitpos: [4]; default: 0; - * The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable - */ - uint32_t l2_cache_shut_dma:1; - uint32_t reserved_5:3; - /** l2_cache_undef_op : R/W; bitpos: [15:8]; default: 0; - * Reserved - */ - uint32_t l2_cache_undef_op:8; - uint32_t reserved_16:16; - }; - uint32_t val; -} cache_l2_cache_ctrl_reg_t; - - -/** Group: Bypass Cache Control and configuration registers */ -/** Type of l1_bypass_cache_conf register - * Bypass Cache configure register - */ -typedef union { - struct { - /** bypass_l1_icache0_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass. - */ - uint32_t bypass_l1_icache0_en:1; - /** bypass_l1_icache1_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass. - */ - uint32_t bypass_l1_icache1_en:1; - /** bypass_l1_icache2_en : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t bypass_l1_icache2_en:1; - /** bypass_l1_icache3_en : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t bypass_l1_icache3_en:1; - /** bypass_l1_dcache_en : HRO; bitpos: [4]; default: 0; - * The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass. - */ - uint32_t bypass_l1_dcache_en:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} cache_l1_bypass_cache_conf_reg_t; - -/** Type of l2_bypass_cache_conf register - * Bypass Cache configure register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** bypass_l2_cache_en : HRO; bitpos: [5]; default: 0; - * The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass. - */ - uint32_t bypass_l2_cache_en:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_bypass_cache_conf_reg_t; - - -/** Group: Cache Atomic Control and configuration registers */ -/** Type of l1_cache_atomic_conf register - * L1 Cache atomic feature configure register - */ -typedef union { - struct { - /** l1_cache_atomic_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable atomic feature on L1-Cache when multiple cores access - * L1-Cache. 1: disable, 1: enable. - */ - uint32_t l1_cache_atomic_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} cache_l1_cache_atomic_conf_reg_t; - - -/** Group: Cache Mode Control and configuration registers */ -/** Type of l1_icache_cachesize_conf register - * L1 instruction Cache CacheSize mode configure register - */ -typedef union { - struct { - /** l1_icache_cachesize_256 : HRO; bitpos: [0]; default: 0; - * The field is used to configure cachesize of L1-ICache as 256 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_256:1; - /** l1_icache_cachesize_512 : HRO; bitpos: [1]; default: 0; - * The field is used to configure cachesize of L1-ICache as 512 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_512:1; - /** l1_icache_cachesize_1k : HRO; bitpos: [2]; default: 0; - * The field is used to configure cachesize of L1-ICache as 1k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_1k:1; - /** l1_icache_cachesize_2k : HRO; bitpos: [3]; default: 0; - * The field is used to configure cachesize of L1-ICache as 2k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_2k:1; - /** l1_icache_cachesize_4k : HRO; bitpos: [4]; default: 0; - * The field is used to configure cachesize of L1-ICache as 4k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_4k:1; - /** l1_icache_cachesize_8k : HRO; bitpos: [5]; default: 0; - * The field is used to configure cachesize of L1-ICache as 8k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_8k:1; - /** l1_icache_cachesize_16k : HRO; bitpos: [6]; default: 0; - * The field is used to configure cachesize of L1-ICache as 16k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_16k:1; - /** l1_icache_cachesize_32k : HRO; bitpos: [7]; default: 0; - * The field is used to configure cachesize of L1-ICache as 32k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_32k:1; - /** l1_icache_cachesize_64k : HRO; bitpos: [8]; default: 0; - * The field is used to configure cachesize of L1-ICache as 64k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_64k:1; - /** l1_icache_cachesize_128k : HRO; bitpos: [9]; default: 0; - * The field is used to configure cachesize of L1-ICache as 128k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_128k:1; - /** l1_icache_cachesize_256k : HRO; bitpos: [10]; default: 0; - * The field is used to configure cachesize of L1-ICache as 256k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_256k:1; - /** l1_icache_cachesize_512k : HRO; bitpos: [11]; default: 0; - * The field is used to configure cachesize of L1-ICache as 512k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_512k:1; - /** l1_icache_cachesize_1024k : HRO; bitpos: [12]; default: 0; - * The field is used to configure cachesize of L1-ICache as 1024k bytes. This field - * and all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_1024k:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} cache_l1_icache_cachesize_conf_reg_t; - -/** Type of l1_icache_blocksize_conf register - * L1 instruction Cache BlockSize mode configure register - */ -typedef union { - struct { - /** l1_icache_blocksize_8 : HRO; bitpos: [0]; default: 0; - * The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all - * other fields within this register is onehot. - */ - uint32_t l1_icache_blocksize_8:1; - /** l1_icache_blocksize_16 : HRO; bitpos: [1]; default: 0; - * The field is used to configureblocksize of L1-ICache as 16 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_blocksize_16:1; - /** l1_icache_blocksize_32 : HRO; bitpos: [2]; default: 0; - * The field is used to configureblocksize of L1-ICache as 32 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_blocksize_32:1; - /** l1_icache_blocksize_64 : HRO; bitpos: [3]; default: 0; - * The field is used to configureblocksize of L1-ICache as 64 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_blocksize_64:1; - /** l1_icache_blocksize_128 : HRO; bitpos: [4]; default: 0; - * The field is used to configureblocksize of L1-ICache as 128 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_blocksize_128:1; - /** l1_icache_blocksize_256 : HRO; bitpos: [5]; default: 0; - * The field is used to configureblocksize of L1-ICache as 256 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_blocksize_256:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l1_icache_blocksize_conf_reg_t; - /** Type of l1_cache_cachesize_conf register - * L1 data Cache CacheSize mode configure register + * Cache cache size register */ typedef union { struct { - /** l1_cache_cachesize_256 : HRO; bitpos: [0]; default: 0; - * The field is used to configure cachesize of L1-DCache as 256 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_256:1; - /** l1_cache_cachesize_512 : HRO; bitpos: [1]; default: 0; - * The field is used to configure cachesize of L1-DCache as 512 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_512:1; - /** l1_cache_cachesize_1k : HRO; bitpos: [2]; default: 0; - * The field is used to configure cachesize of L1-DCache as 1k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_1k:1; - /** l1_cache_cachesize_2k : HRO; bitpos: [3]; default: 0; - * The field is used to configure cachesize of L1-DCache as 2k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_2k:1; - /** l1_cache_cachesize_4k : HRO; bitpos: [4]; default: 0; - * The field is used to configure cachesize of L1-DCache as 4k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_4k:1; - /** l1_cache_cachesize_8k : HRO; bitpos: [5]; default: 0; - * The field is used to configure cachesize of L1-DCache as 8k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_8k:1; - /** l1_cache_cachesize_16k : HRO; bitpos: [6]; default: 0; - * The field is used to configure cachesize of L1-DCache as 16k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_16k:1; - /** l1_cache_cachesize_32k : HRO; bitpos: [7]; default: 1; - * The field is used to configure cachesize of L1-DCache as 32k bytes. This field and - * all other fields within this register is onehot. + uint32_t reserved_0:7; + /** l1_cache_cachesize_32k : RO; bitpos: [7]; default: 1; + * Indicates that cache size is 32 KB. */ uint32_t l1_cache_cachesize_32k:1; - /** l1_cache_cachesize_64k : HRO; bitpos: [8]; default: 0; - * The field is used to configure cachesize of L1-DCache as 64k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_64k:1; - /** l1_cache_cachesize_128k : HRO; bitpos: [9]; default: 0; - * The field is used to configure cachesize of L1-DCache as 128k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_128k:1; - /** l1_cache_cachesize_256k : HRO; bitpos: [10]; default: 0; - * The field is used to configure cachesize of L1-DCache as 256k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_256k:1; - /** l1_cache_cachesize_512k : HRO; bitpos: [11]; default: 0; - * The field is used to configure cachesize of L1-DCache as 512k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_512k:1; - /** l1_cache_cachesize_1024k : HRO; bitpos: [12]; default: 0; - * The field is used to configure cachesize of L1-DCache as 1024k bytes. This field - * and all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_1024k:1; - uint32_t reserved_13:19; + uint32_t reserved_8:24; }; uint32_t val; } cache_l1_cache_cachesize_conf_reg_t; /** Type of l1_cache_blocksize_conf register - * L1 data Cache BlockSize mode configure register + * Cache block size register */ typedef union { struct { - /** l1_cache_blocksize_8 : HRO; bitpos: [0]; default: 0; - * The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all - * other fields within this register is onehot. - */ - uint32_t l1_cache_blocksize_8:1; - /** l1_cache_blocksize_16 : HRO; bitpos: [1]; default: 0; - * The field is used to configureblocksize of L1-DCache as 16 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_blocksize_16:1; - /** l1_cache_blocksize_32 : HRO; bitpos: [2]; default: 1; - * The field is used to configureblocksize of L1-DCache as 32 bytes. This field and - * all other fields within this register is onehot. + uint32_t reserved_0:2; + /** l1_cache_blocksize_32 : RO; bitpos: [2]; default: 1; + * Indicates that the cache block size is 32 bytes. */ uint32_t l1_cache_blocksize_32:1; - /** l1_cache_blocksize_64 : HRO; bitpos: [3]; default: 0; - * The field is used to configureblocksize of L1-DCache as 64 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_blocksize_64:1; - /** l1_cache_blocksize_128 : HRO; bitpos: [4]; default: 0; - * The field is used to configureblocksize of L1-DCache as 128 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_blocksize_128:1; - /** l1_cache_blocksize_256 : HRO; bitpos: [5]; default: 0; - * The field is used to configureblocksize of L1-DCache as 256 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_blocksize_256:1; - uint32_t reserved_6:26; + uint32_t reserved_3:29; }; uint32_t val; } cache_l1_cache_blocksize_conf_reg_t; -/** Type of l2_cache_cachesize_conf register - * L2 Cache CacheSize mode configure register - */ -typedef union { - struct { - /** l2_cache_cachesize_256 : HRO; bitpos: [0]; default: 0; - * The field is used to configure cachesize of L2-Cache as 256 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_256:1; - /** l2_cache_cachesize_512 : HRO; bitpos: [1]; default: 0; - * The field is used to configure cachesize of L2-Cache as 512 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_512:1; - /** l2_cache_cachesize_1k : HRO; bitpos: [2]; default: 0; - * The field is used to configure cachesize of L2-Cache as 1k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_1k:1; - /** l2_cache_cachesize_2k : HRO; bitpos: [3]; default: 0; - * The field is used to configure cachesize of L2-Cache as 2k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_2k:1; - /** l2_cache_cachesize_4k : HRO; bitpos: [4]; default: 0; - * The field is used to configure cachesize of L2-Cache as 4k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_4k:1; - /** l2_cache_cachesize_8k : HRO; bitpos: [5]; default: 0; - * The field is used to configure cachesize of L2-Cache as 8k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_8k:1; - /** l2_cache_cachesize_16k : HRO; bitpos: [6]; default: 0; - * The field is used to configure cachesize of L2-Cache as 16k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_16k:1; - /** l2_cache_cachesize_32k : HRO; bitpos: [7]; default: 0; - * The field is used to configure cachesize of L2-Cache as 32k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_32k:1; - /** l2_cache_cachesize_64k : HRO; bitpos: [8]; default: 0; - * The field is used to configure cachesize of L2-Cache as 64k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_64k:1; - /** l2_cache_cachesize_128k : HRO; bitpos: [9]; default: 0; - * The field is used to configure cachesize of L2-Cache as 128k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_128k:1; - /** l2_cache_cachesize_256k : HRO; bitpos: [10]; default: 0; - * The field is used to configure cachesize of L2-Cache as 256k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_256k:1; - /** l2_cache_cachesize_512k : HRO; bitpos: [11]; default: 0; - * The field is used to configure cachesize of L2-Cache as 512k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_512k:1; - /** l2_cache_cachesize_1024k : HRO; bitpos: [12]; default: 0; - * The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_1024k:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} cache_l2_cache_cachesize_conf_reg_t; - -/** Type of l2_cache_blocksize_conf register - * L2 Cache BlockSize mode configure register - */ -typedef union { - struct { - /** l2_cache_blocksize_8 : HRO; bitpos: [0]; default: 0; - * The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all - * other fields within this register is onehot. - */ - uint32_t l2_cache_blocksize_8:1; - /** l2_cache_blocksize_16 : HRO; bitpos: [1]; default: 0; - * The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all - * other fields within this register is onehot. - */ - uint32_t l2_cache_blocksize_16:1; - /** l2_cache_blocksize_32 : HRO; bitpos: [2]; default: 0; - * The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all - * other fields within this register is onehot. - */ - uint32_t l2_cache_blocksize_32:1; - /** l2_cache_blocksize_64 : HRO; bitpos: [3]; default: 0; - * The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all - * other fields within this register is onehot. - */ - uint32_t l2_cache_blocksize_64:1; - /** l2_cache_blocksize_128 : HRO; bitpos: [4]; default: 0; - * The field is used to configureblocksize of L2-Cache as 128 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_blocksize_128:1; - /** l2_cache_blocksize_256 : HRO; bitpos: [5]; default: 0; - * The field is used to configureblocksize of L2-Cache as 256 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_blocksize_256:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_blocksize_conf_reg_t; - - -/** Group: Wrap Mode Control and configuration registers */ /** Type of l1_cache_wrap_around_ctrl register - * Cache wrap around control register + * Cache critical word first control register */ typedef union { struct { - /** l1_icache0_wrap : HRO; bitpos: [0]; default: 0; - * Set this bit as 1 to enable L1-ICache0 wrap around mode. - */ - uint32_t l1_icache0_wrap:1; - /** l1_icache1_wrap : HRO; bitpos: [1]; default: 0; - * Set this bit as 1 to enable L1-ICache1 wrap around mode. - */ - uint32_t l1_icache1_wrap:1; - /** l1_icache2_wrap : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_wrap:1; - /** l1_icache3_wrap : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_wrap:1; + uint32_t reserved_0:4; /** l1_cache_wrap : R/W; bitpos: [4]; default: 0; - * Set this bit as 1 to enable L1-DCache wrap around mode. + * Configures whether to enable the critical word first mode for the L1 cache. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_wrap:1; uint32_t reserved_5:27; @@ -540,46 +80,16 @@ typedef union { uint32_t val; } cache_l1_cache_wrap_around_ctrl_reg_t; -/** Type of l2_cache_wrap_around_ctrl register - * Cache wrap around control register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_wrap : HRO; bitpos: [5]; default: 0; - * Set this bit as 1 to enable L2-Cache wrap around mode. - */ - uint32_t l2_cache_wrap:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_wrap_around_ctrl_reg_t; - - -/** Group: Early Restart Control registers */ /** Type of l1_cache_miss_access_ctrl register * Cache wrap around control register */ typedef union { struct { - /** l1_icache0_miss_disable_access : HRO; bitpos: [0]; default: 0; - * Set this bit as 1 to disable early restart of L1-ICache0 - */ - uint32_t l1_icache0_miss_disable_access:1; - /** l1_icache1_miss_disable_access : HRO; bitpos: [1]; default: 0; - * Set this bit as 1 to disable early restart of L1-ICache1 - */ - uint32_t l1_icache1_miss_disable_access:1; - /** l1_icache2_miss_disable_access : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_miss_disable_access:1; - /** l1_icache3_miss_disable_access : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_miss_disable_access:1; + uint32_t reserved_0:4; /** l1_cache_miss_disable_access : R/W; bitpos: [4]; default: 0; - * Set this bit as 1 to disable early restart of L1-DCache + * Configures whether to disable early restart function. + * 0: Enable + * 1: Disable */ uint32_t l1_cache_miss_disable_access:1; uint32_t reserved_5:27; @@ -587,99 +97,31 @@ typedef union { uint32_t val; } cache_l1_cache_miss_access_ctrl_reg_t; -/** Type of l2_cache_miss_access_ctrl register - * Cache wrap around control register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_miss_disable_access : HRO; bitpos: [5]; default: 0; - * Set this bit as 1 to disable early restart of L2-Cache - */ - uint32_t l2_cache_miss_disable_access:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_miss_access_ctrl_reg_t; - -/** Group: Cache Freeze Control registers */ +/** Group: Cache Freeze Control Registers */ /** Type of l1_cache_freeze_ctrl register - * Cache Freeze control register + * Cache freeze control register */ typedef union { struct { - /** l1_icache0_freeze_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable freeze operation on L1-ICache0. It can be cleared by - * software. - */ - uint32_t l1_icache0_freeze_en:1; - /** l1_icache0_freeze_mode : HRO; bitpos: [1]; default: 0; - * The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. - */ - uint32_t l1_icache0_freeze_mode:1; - /** l1_icache0_freeze_done : RO; bitpos: [2]; default: 0; - * The bit is used to indicate whether freeze operation on L1-ICache0 is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l1_icache0_freeze_done:1; - uint32_t reserved_3:1; - /** l1_icache1_freeze_en : HRO; bitpos: [4]; default: 0; - * The bit is used to enable freeze operation on L1-ICache1. It can be cleared by - * software. - */ - uint32_t l1_icache1_freeze_en:1; - /** l1_icache1_freeze_mode : HRO; bitpos: [5]; default: 0; - * The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. - */ - uint32_t l1_icache1_freeze_mode:1; - /** l1_icache1_freeze_done : RO; bitpos: [6]; default: 0; - * The bit is used to indicate whether freeze operation on L1-ICache1 is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l1_icache1_freeze_done:1; - uint32_t reserved_7:1; - /** l1_icache2_freeze_en : HRO; bitpos: [8]; default: 0; - * Reserved - */ - uint32_t l1_icache2_freeze_en:1; - /** l1_icache2_freeze_mode : HRO; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_freeze_mode:1; - /** l1_icache2_freeze_done : RO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l1_icache2_freeze_done:1; - uint32_t reserved_11:1; - /** l1_icache3_freeze_en : HRO; bitpos: [12]; default: 0; - * Reserved - */ - uint32_t l1_icache3_freeze_en:1; - /** l1_icache3_freeze_mode : HRO; bitpos: [13]; default: 0; - * Reserved - */ - uint32_t l1_icache3_freeze_mode:1; - /** l1_icache3_freeze_done : RO; bitpos: [14]; default: 0; - * Reserved - */ - uint32_t l1_icache3_freeze_done:1; - uint32_t reserved_15:1; + uint32_t reserved_0:16; /** l1_cache_freeze_en : R/W; bitpos: [16]; default: 0; - * The bit is used to enable freeze operation on L1-Cache. It can be cleared by + * Configures whether to enable freeze operation in the L1 cache. It can be cleared by * software. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_freeze_en:1; /** l1_cache_freeze_mode : R/W; bitpos: [17]; default: 0; - * The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. + * Configures the freeze mode in the L1 cache. + * 0: Assert busy if a cache miss occurs + * 1: Assert hit if a cache miss occurs */ uint32_t l1_cache_freeze_mode:1; /** l1_cache_freeze_done : RO; bitpos: [18]; default: 0; - * The bit is used to indicate whether freeze operation on L1-Cache is finished or - * not. 0: not finished. 1: finished. + * Represents whether the freeze operation in L1 cache is finished. + * 0: Not finished + * 1: Finished */ uint32_t l1_cache_freeze_done:1; uint32_t reserved_19:13; @@ -687,87 +129,25 @@ typedef union { uint32_t val; } cache_l1_cache_freeze_ctrl_reg_t; -/** Type of l2_cache_freeze_ctrl register - * Cache Freeze control register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** l2_cache_freeze_en : HRO; bitpos: [20]; default: 0; - * The bit is used to enable freeze operation on L2-Cache. It can be cleared by - * software. - */ - uint32_t l2_cache_freeze_en:1; - /** l2_cache_freeze_mode : HRO; bitpos: [21]; default: 0; - * The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. - */ - uint32_t l2_cache_freeze_mode:1; - /** l2_cache_freeze_done : RO; bitpos: [22]; default: 0; - * The bit is used to indicate whether freeze operation on L2-Cache is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l2_cache_freeze_done:1; - uint32_t reserved_23:9; - }; - uint32_t val; -} cache_l2_cache_freeze_ctrl_reg_t; - -/** Group: Cache Data Memory Access Control and Configuration registers */ +/** Group: Cache Data Memory Access Control and Configuration Registers */ /** Type of l1_cache_data_mem_acs_conf register - * Cache data memory access configure register + * Cache data memory access configuration register */ typedef union { struct { - /** l1_icache0_data_mem_rd_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_icache0_data_mem_rd_en:1; - /** l1_icache0_data_mem_wr_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, - * 1: enable. - */ - uint32_t l1_icache0_data_mem_wr_en:1; - uint32_t reserved_2:2; - /** l1_icache1_data_mem_rd_en : HRO; bitpos: [4]; default: 0; - * The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_icache1_data_mem_rd_en:1; - /** l1_icache1_data_mem_wr_en : HRO; bitpos: [5]; default: 0; - * The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, - * 1: enable. - */ - uint32_t l1_icache1_data_mem_wr_en:1; - uint32_t reserved_6:2; - /** l1_icache2_data_mem_rd_en : HRO; bitpos: [8]; default: 0; - * Reserved - */ - uint32_t l1_icache2_data_mem_rd_en:1; - /** l1_icache2_data_mem_wr_en : HRO; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_data_mem_wr_en:1; - uint32_t reserved_10:2; - /** l1_icache3_data_mem_rd_en : HRO; bitpos: [12]; default: 0; - * Reserved - */ - uint32_t l1_icache3_data_mem_rd_en:1; - /** l1_icache3_data_mem_wr_en : HRO; bitpos: [13]; default: 0; - * Reserved - */ - uint32_t l1_icache3_data_mem_wr_en:1; - uint32_t reserved_14:2; + uint32_t reserved_0:16; /** l1_cache_data_mem_rd_en : R/W; bitpos: [16]; default: 0; - * The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: - * enable. + * Configures whether to enable the configuration bus to read the L1 cache data memory. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_data_mem_rd_en:1; /** l1_cache_data_mem_wr_en : R/W; bitpos: [17]; default: 0; - * The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: - * enable. + * Configures whether to enable the configuration bus to write the L1 cache data + * memory. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_data_mem_wr_en:1; uint32_t reserved_18:14; @@ -775,82 +155,22 @@ typedef union { uint32_t val; } cache_l1_cache_data_mem_acs_conf_reg_t; -/** Type of l2_cache_data_mem_acs_conf register - * Cache data memory access configure register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** l2_cache_data_mem_rd_en : HRO; bitpos: [20]; default: 0; - * The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: - * enable. - */ - uint32_t l2_cache_data_mem_rd_en:1; - /** l2_cache_data_mem_wr_en : HRO; bitpos: [21]; default: 0; - * The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: - * enable. - */ - uint32_t l2_cache_data_mem_wr_en:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} cache_l2_cache_data_mem_acs_conf_reg_t; - - -/** Group: Cache Tag Memory Access Control and Configuration registers */ /** Type of l1_cache_tag_mem_acs_conf register - * Cache tag memory access configure register + * Cache tag memory access configuration register */ typedef union { struct { - /** l1_icache0_tag_mem_rd_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_icache0_tag_mem_rd_en:1; - /** l1_icache0_tag_mem_wr_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_icache0_tag_mem_wr_en:1; - uint32_t reserved_2:2; - /** l1_icache1_tag_mem_rd_en : HRO; bitpos: [4]; default: 0; - * The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_icache1_tag_mem_rd_en:1; - /** l1_icache1_tag_mem_wr_en : HRO; bitpos: [5]; default: 0; - * The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_icache1_tag_mem_wr_en:1; - uint32_t reserved_6:2; - /** l1_icache2_tag_mem_rd_en : HRO; bitpos: [8]; default: 0; - * Reserved - */ - uint32_t l1_icache2_tag_mem_rd_en:1; - /** l1_icache2_tag_mem_wr_en : HRO; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_tag_mem_wr_en:1; - uint32_t reserved_10:2; - /** l1_icache3_tag_mem_rd_en : HRO; bitpos: [12]; default: 0; - * Reserved - */ - uint32_t l1_icache3_tag_mem_rd_en:1; - /** l1_icache3_tag_mem_wr_en : HRO; bitpos: [13]; default: 0; - * Reserved - */ - uint32_t l1_icache3_tag_mem_wr_en:1; - uint32_t reserved_14:2; + uint32_t reserved_0:16; /** l1_cache_tag_mem_rd_en : R/W; bitpos: [16]; default: 0; - * The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: - * enable. + * Configures whether to enable the configuration bus to read the L1 cache tag memory. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_tag_mem_rd_en:1; /** l1_cache_tag_mem_wr_en : R/W; bitpos: [17]; default: 0; - * The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1: - * enable. + * Configures whether to enable the configuration bus to write the L1 cache tag memory. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_tag_mem_wr_en:1; uint32_t reserved_18:14; @@ -858,492 +178,123 @@ typedef union { uint32_t val; } cache_l1_cache_tag_mem_acs_conf_reg_t; -/** Type of l2_cache_tag_mem_acs_conf register - * Cache tag memory access configure register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** l2_cache_tag_mem_rd_en : HRO; bitpos: [20]; default: 0; - * The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: - * enable. - */ - uint32_t l2_cache_tag_mem_rd_en:1; - /** l2_cache_tag_mem_wr_en : HRO; bitpos: [21]; default: 0; - * The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: - * enable. - */ - uint32_t l2_cache_tag_mem_wr_en:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} cache_l2_cache_tag_mem_acs_conf_reg_t; - - -/** Group: Prelock Control and configuration registers */ -/** Type of l1_icache0_prelock_conf register - * L1 instruction Cache 0 prelock configure register - */ -typedef union { - struct { - /** l1_icache0_prelock_sct0_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-ICache0. - */ - uint32_t l1_icache0_prelock_sct0_en:1; - /** l1_icache0_prelock_sct1_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-ICache0. - */ - uint32_t l1_icache0_prelock_sct1_en:1; - /** l1_icache0_prelock_rgid : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 icache0 prelock. - */ - uint32_t l1_icache0_prelock_rgid:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l1_icache0_prelock_conf_reg_t; - -/** Type of l1_icache0_prelock_sct0_addr register - * L1 instruction Cache 0 prelock section0 address configure register - */ -typedef union { - struct { - /** l1_icache0_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG - */ - uint32_t l1_icache0_prelock_sct0_addr:32; - }; - uint32_t val; -} cache_l1_icache0_prelock_sct0_addr_reg_t; - -/** Type of l1_icache0_prelock_sct1_addr register - * L1 instruction Cache 0 prelock section1 address configure register - */ -typedef union { - struct { - /** l1_icache0_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG - */ - uint32_t l1_icache0_prelock_sct1_addr:32; - }; - uint32_t val; -} cache_l1_icache0_prelock_sct1_addr_reg_t; - -/** Type of l1_icache0_prelock_sct_size register - * L1 instruction Cache 0 prelock section size configure register - */ -typedef union { - struct { - /** l1_icache0_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG - */ - uint32_t l1_icache0_prelock_sct0_size:14; - uint32_t reserved_14:2; - /** l1_icache0_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG - */ - uint32_t l1_icache0_prelock_sct1_size:14; - uint32_t reserved_30:2; - }; - uint32_t val; -} cache_l1_icache0_prelock_sct_size_reg_t; - -/** Type of l1_icache1_prelock_conf register - * L1 instruction Cache 1 prelock configure register - */ -typedef union { - struct { - /** l1_icache1_prelock_sct0_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-ICache1. - */ - uint32_t l1_icache1_prelock_sct0_en:1; - /** l1_icache1_prelock_sct1_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-ICache1. - */ - uint32_t l1_icache1_prelock_sct1_en:1; - /** l1_icache1_prelock_rgid : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 icache1 prelock. - */ - uint32_t l1_icache1_prelock_rgid:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l1_icache1_prelock_conf_reg_t; - -/** Type of l1_icache1_prelock_sct0_addr register - * L1 instruction Cache 1 prelock section0 address configure register - */ -typedef union { - struct { - /** l1_icache1_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG - */ - uint32_t l1_icache1_prelock_sct0_addr:32; - }; - uint32_t val; -} cache_l1_icache1_prelock_sct0_addr_reg_t; - -/** Type of l1_icache1_prelock_sct1_addr register - * L1 instruction Cache 1 prelock section1 address configure register - */ -typedef union { - struct { - /** l1_icache1_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG - */ - uint32_t l1_icache1_prelock_sct1_addr:32; - }; - uint32_t val; -} cache_l1_icache1_prelock_sct1_addr_reg_t; - -/** Type of l1_icache1_prelock_sct_size register - * L1 instruction Cache 1 prelock section size configure register - */ -typedef union { - struct { - /** l1_icache1_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG - */ - uint32_t l1_icache1_prelock_sct0_size:14; - uint32_t reserved_14:2; - /** l1_icache1_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG - */ - uint32_t l1_icache1_prelock_sct1_size:14; - uint32_t reserved_30:2; - }; - uint32_t val; -} cache_l1_icache1_prelock_sct_size_reg_t; - -/** Type of l1_icache2_prelock_conf register - * L1 instruction Cache 2 prelock configure register - */ -typedef union { - struct { - /** l1_icache2_prelock_sct0_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-ICache2. - */ - uint32_t l1_icache2_prelock_sct0_en:1; - /** l1_icache2_prelock_sct1_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-ICache2. - */ - uint32_t l1_icache2_prelock_sct1_en:1; - /** l1_icache2_prelock_rgid : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 icache2 prelock. - */ - uint32_t l1_icache2_prelock_rgid:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l1_icache2_prelock_conf_reg_t; - -/** Type of l1_icache2_prelock_sct0_addr register - * L1 instruction Cache 2 prelock section0 address configure register - */ -typedef union { - struct { - /** l1_icache2_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG - */ - uint32_t l1_icache2_prelock_sct0_addr:32; - }; - uint32_t val; -} cache_l1_icache2_prelock_sct0_addr_reg_t; - -/** Type of l1_icache2_prelock_sct1_addr register - * L1 instruction Cache 2 prelock section1 address configure register - */ -typedef union { - struct { - /** l1_icache2_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG - */ - uint32_t l1_icache2_prelock_sct1_addr:32; - }; - uint32_t val; -} cache_l1_icache2_prelock_sct1_addr_reg_t; - -/** Type of l1_icache2_prelock_sct_size register - * L1 instruction Cache 2 prelock section size configure register - */ -typedef union { - struct { - /** l1_icache2_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG - */ - uint32_t l1_icache2_prelock_sct0_size:14; - uint32_t reserved_14:2; - /** l1_icache2_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG - */ - uint32_t l1_icache2_prelock_sct1_size:14; - uint32_t reserved_30:2; - }; - uint32_t val; -} cache_l1_icache2_prelock_sct_size_reg_t; - -/** Type of l1_icache3_prelock_conf register - * L1 instruction Cache 3 prelock configure register - */ -typedef union { - struct { - /** l1_icache3_prelock_sct0_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-ICache3. - */ - uint32_t l1_icache3_prelock_sct0_en:1; - /** l1_icache3_prelock_sct1_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-ICache3. - */ - uint32_t l1_icache3_prelock_sct1_en:1; - /** l1_icache3_prelock_rgid : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 icache3 prelock. - */ - uint32_t l1_icache3_prelock_rgid:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l1_icache3_prelock_conf_reg_t; - -/** Type of l1_icache3_prelock_sct0_addr register - * L1 instruction Cache 3 prelock section0 address configure register - */ -typedef union { - struct { - /** l1_icache3_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG - */ - uint32_t l1_icache3_prelock_sct0_addr:32; - }; - uint32_t val; -} cache_l1_icache3_prelock_sct0_addr_reg_t; - -/** Type of l1_icache3_prelock_sct1_addr register - * L1 instruction Cache 3 prelock section1 address configure register - */ -typedef union { - struct { - /** l1_icache3_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG - */ - uint32_t l1_icache3_prelock_sct1_addr:32; - }; - uint32_t val; -} cache_l1_icache3_prelock_sct1_addr_reg_t; - -/** Type of l1_icache3_prelock_sct_size register - * L1 instruction Cache 3 prelock section size configure register - */ -typedef union { - struct { - /** l1_icache3_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG - */ - uint32_t l1_icache3_prelock_sct0_size:14; - uint32_t reserved_14:2; - /** l1_icache3_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG - */ - uint32_t l1_icache3_prelock_sct1_size:14; - uint32_t reserved_30:2; - }; - uint32_t val; -} cache_l1_icache3_prelock_sct_size_reg_t; +/** Group: Prelock Control and Configuration Registers */ /** Type of l1_cache_prelock_conf register * L1 Cache prelock configure register */ typedef union { struct { /** l1_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-Cache. + * Configures whether to enable the prelocking function in Section 0 of the L1 cache. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_prelock_sct0_en:1; /** l1_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-Cache. + * Configures whether to enable the prelocking function in Section 1 of the L1 cache. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_prelock_sct1_en:1; - /** l1_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 cache prelock. - */ - uint32_t l1_cache_prelock_rgid:4; - uint32_t reserved_6:26; + uint32_t reserved_2:30; }; uint32_t val; } cache_l1_cache_prelock_conf_reg_t; /** Type of l1_cache_prelock_sct0_addr register - * L1 Cache prelock section0 address configure register + * L1 cache prelocking Section 0 address configuration register */ typedef union { struct { /** l1_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_SIZE_REG + * Configures the starting virtual address of Section 0 for prelocking in the L1 + * cache. This field should be configured together with + * CACHE_L1_CACHE_PRELOCK_SCT0_SIZE. */ uint32_t l1_cache_prelock_sct0_addr:32; }; uint32_t val; } cache_l1_cache_prelock_sct0_addr_reg_t; -/** Type of l1_dcache_prelock_sct1_addr register - * L1 Cache prelock section1 address configure register +/** Type of l1_cache_prelock_sct1_addr register + * L1 cache prelocking Section 1 address configuration register */ typedef union { struct { /** l1_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_SIZE_REG + * Configures the starting virtual address of Section 1 for prelocking in the L1 + * cache. This field should be configured together with + * CACHE_L1_CACHE_PRELOCK_SCT1_SIZE. */ uint32_t l1_cache_prelock_sct1_addr:32; }; uint32_t val; -} cache_l1_dcache_prelock_sct1_addr_reg_t; +} cache_l1_cache_prelock_sct1_addr_reg_t; -/** Type of l1_dcache_prelock_sct_size register - * L1 Cache prelock section size configure register +/** Type of l1_cache_prelock_sct_size register + * L1 cache prelocking section size configuration register */ typedef union { struct { /** l1_cache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG + * Configures the size of Section 0 for prelocking in the L1 cache. This field should + * be configured together with CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG. */ uint32_t l1_cache_prelock_sct0_size:14; uint32_t reserved_14:2; /** l1_cache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG + * Configures the size of Section 1 for prelocking in the L1 cache. This field should + * be configured together with CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_REG. */ uint32_t l1_cache_prelock_sct1_size:14; uint32_t reserved_30:2; }; uint32_t val; -} cache_l1_dcache_prelock_sct_size_reg_t; - -/** Type of l2_cache_prelock_conf register - * L2 Cache prelock configure register - */ -typedef union { - struct { - /** l2_cache_prelock_sct0_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L2-Cache. - */ - uint32_t l2_cache_prelock_sct0_en:1; - /** l2_cache_prelock_sct1_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L2-Cache. - */ - uint32_t l2_cache_prelock_sct1_en:1; - /** l2_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l2 cache prelock. - */ - uint32_t l2_cache_prelock_rgid:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_prelock_conf_reg_t; - -/** Type of l2_cache_prelock_sct0_addr register - * L2 Cache prelock section0 address configure register - */ -typedef union { - struct { - /** l2_cache_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG - */ - uint32_t l2_cache_prelock_sct0_addr:32; - }; - uint32_t val; -} cache_l2_cache_prelock_sct0_addr_reg_t; - -/** Type of l2_cache_prelock_sct1_addr register - * L2 Cache prelock section1 address configure register - */ -typedef union { - struct { - /** l2_cache_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG - */ - uint32_t l2_cache_prelock_sct1_addr:32; - }; - uint32_t val; -} cache_l2_cache_prelock_sct1_addr_reg_t; - -/** Type of l2_cache_prelock_sct_size register - * L2 Cache prelock section size configure register - */ -typedef union { - struct { - /** l2_cache_prelock_sct0_size : HRO; bitpos: [15:0]; default: 65535; - * Those bits are used to configure the size of the first section of prelock on - * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG - */ - uint32_t l2_cache_prelock_sct0_size:16; - /** l2_cache_prelock_sct1_size : HRO; bitpos: [31:16]; default: 65535; - * Those bits are used to configure the size of the second section of prelock on - * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG - */ - uint32_t l2_cache_prelock_sct1_size:16; - }; - uint32_t val; -} cache_l2_cache_prelock_sct_size_reg_t; +} cache_l1_cache_prelock_sct_size_reg_t; -/** Group: Lock Control and configuration registers */ +/** Group: Lock Control and Configuration Registers */ /** Type of lock_ctrl register - * Lock-class (manual lock) operation control register + * Locking operation control register */ typedef union { struct { /** lock_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable lock operation. It will be cleared by hardware after lock - * operation done + * Configures whether to enable lock operation. It will be cleared by hardware after + * the lock operation is done. + * 0: Disable + * 1: Enable */ uint32_t lock_ena:1; /** unlock_ena : R/W/SC; bitpos: [1]; default: 0; - * The bit is used to enable unlock operation. It will be cleared by hardware after - * unlock operation done + * Configures whether to enable unlock operation. It will be cleared by hardware after + * the unlock operation is done. + * 0: Disable + * 1: Enable */ uint32_t unlock_ena:1; /** lock_done : RO; bitpos: [2]; default: 1; - * The bit is used to indicate whether unlock/lock operation is finished or not. 0: - * not finished. 1: finished. + * Represents whether the unlock or the lock operation is finished. + * 0: Not finished + * 1: Finished */ uint32_t lock_done:1; - /** lock_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of cache lock/unlock. - */ - uint32_t lock_rgid:4; - uint32_t reserved_7:25; + uint32_t reserved_3:29; }; uint32_t val; } cache_lock_ctrl_reg_t; /** Type of lock_map register - * Lock (manual lock) map configure register + * Locking map configuration register */ typedef union { struct { /** lock_map : R/W; bitpos: [5:0]; default: 0; - * Those bits are used to indicate which caches in the two-level cache structure will - * apply this lock/unlock operation. [4]: L1-Cache + * Configures which level of cache in the two-level cache structure to perform the + * locking or the unlocking operation. + * Bit 4: Write 1 to this bit to select the L1 cache + * Other bits: reserved */ uint32_t lock_map:6; uint32_t reserved_6:26; @@ -1352,13 +303,13 @@ typedef union { } cache_lock_map_reg_t; /** Type of lock_addr register - * Lock (manual lock) address configure register + * Locking address configuration register */ typedef union { struct { /** lock_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the lock/unlock operation, - * which should be used together with CACHE_LOCK_SIZE_REG + * Configures the starting virtual address for the locking or unlocking operation. + * This field should be configured together with CACHE_LOCK_SIZE_REG. */ uint32_t lock_addr:32; }; @@ -1366,13 +317,13 @@ typedef union { } cache_lock_addr_reg_t; /** Type of lock_size register - * Lock (manual lock) size configure register + * Locking size configuration register */ typedef union { struct { /** lock_size : R/W; bitpos: [15:0]; default: 0; - * Those bits are used to configure the size of the lock/unlock operation, which - * should be used together with CACHE_LOCK_ADDR_REG + * Configures the size for the locking or unlocking operation. This field should be + * configured together with CACHE_LOCK_ADDR_REG. */ uint32_t lock_size:16; uint32_t reserved_16:16; @@ -1381,63 +332,61 @@ typedef union { } cache_lock_size_reg_t; -/** Group: Sync Control and configuration registers */ +/** Group: Sync Control and Configuration Registers */ /** Type of sync_ctrl register - * Sync-class operation control register + * Sync operation control register */ typedef union { struct { - /** invalidate_ena : R/W/SC; bitpos: [0]; default: 1; - * The bit is used to enable invalidate operation. It will be cleared by hardware - * after invalidate operation done. Note that this bit and the other sync-bits - * (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that - * is, those bits can not be set to 1 at the same time. + /** invalidate_ena : RW; bitpos: [0]; default: 1; + * Configures whether to enable the invalidatation operation. Hardware will clear it + * once the operation has finished. + * 0: Disable + * 1: Enable */ uint32_t invalidate_ena:1; /** clean_ena : R/W/SC; bitpos: [1]; default: 0; - * The bit is used to enable clean operation. It will be cleared by hardware after - * clean operation done. Note that this bit and the other sync-bits (invalidate_ena, - * writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those - * bits can not be set to 1 at the same time. + * Configures whether to enable the clean operation. Hardware will clear it once the + * operation has finished. + * 0: Disable + * 1: Enable */ uint32_t clean_ena:1; /** writeback_ena : R/W/SC; bitpos: [2]; default: 0; - * The bit is used to enable writeback operation. It will be cleared by hardware after - * writeback operation done. Note that this bit and the other sync-bits - * (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that - * is, those bits can not be set to 1 at the same time. + * Configures whether to enable the write-back operation. Hardware will clear it once + * the operation has finished. + * 0: Disable + * 1: Enable */ uint32_t writeback_ena:1; /** writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0; - * The bit is used to enable writeback-invalidate operation. It will be cleared by - * hardware after writeback-invalidate operation done. Note that this bit and the - * other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, - * that is, those bits can not be set to 1 at the same time. + * Configures whether to enable the write-back invalidation operation. Hardware will + * clear it once the operation has finished. + * 0: Disable + * 1: Enable */ uint32_t writeback_invalidate_ena:1; /** sync_done : RO; bitpos: [4]; default: 0; - * The bit is used to indicate whether sync operation (invalidate, clean, writeback, - * writeback_invalidate) is finished or not. 0: not finished. 1: finished. + * Represents whether the synchronization operation is finished. + * 0: Not finished + * 1: Finished */ uint32_t sync_done:1; - /** sync_rgid : HRO; bitpos: [8:5]; default: 0; - * The bit is used to set the gid of cache sync operation (invalidate, clean, - * writeback, writeback_invalidate) - */ - uint32_t sync_rgid:4; - uint32_t reserved_9:23; + uint32_t reserved_5:27; }; uint32_t val; } cache_sync_ctrl_reg_t; /** Type of sync_map register - * Sync map configure register + * Sync map configuration register */ typedef union { struct { /** sync_map : R/W; bitpos: [5:0]; default: 63; - * Those bits are used to indicate which caches in the two-level cache structure will - * apply the sync operation. [4]: L1-Cache + * Configures which caches in the two-level cache structure will apply the sync + * operation. + * Bit 4: Write 1 to this bit to select the L1 cache + * Other bits: Reserved */ uint32_t sync_map:6; uint32_t reserved_6:26; @@ -1446,13 +395,13 @@ typedef union { } cache_sync_map_reg_t; /** Type of sync_addr register - * Sync address configure register + * Sync address configuration register */ typedef union { struct { /** sync_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the sync operation, which - * should be used together with CACHE_SYNC_SIZE_REG + * Configures the starting virtual address for the synchronization operation. This + * field should be configured together with CACHE_SYNC_SIZE_REG. */ uint32_t sync_addr:32; }; @@ -1460,13 +409,13 @@ typedef union { } cache_sync_addr_reg_t; /** Type of sync_size register - * Sync size configure register + * Sync size configuration register */ typedef union { struct { /** sync_size : R/W; bitpos: [24:0]; default: 0; - * Those bits are used to configure the size of the sync operation, which should be - * used together with CACHE_SYNC_ADDR_REG + * Configures the size for the synchronization operation. This field should be + * configured together with CACHE_SYNC_ADDR_REG. */ uint32_t sync_size:25; uint32_t reserved_25:7; @@ -1475,835 +424,127 @@ typedef union { } cache_sync_size_reg_t; -/** Group: Preload Control and configuration registers */ -/** Type of l1_icache0_preload_ctrl register - * L1 instruction Cache 0 preload-operation control register - */ -typedef union { - struct { - /** l1_icache0_preload_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-ICache0. It will be cleared by - * hardware automatically after preload operation is done. - */ - uint32_t l1_icache0_preload_ena:1; - /** l1_icache0_preload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ - uint32_t l1_icache0_preload_done:1; - /** l1_icache0_preload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ - uint32_t l1_icache0_preload_order:1; - /** l1_icache0_preload_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 icache0 preload. - */ - uint32_t l1_icache0_preload_rgid:4; - uint32_t reserved_7:25; - }; - uint32_t val; -} cache_l1_icache0_preload_ctrl_reg_t; - -/** Type of l1_icache0_preload_addr register - * L1 instruction Cache 0 preload address configure register - */ -typedef union { - struct { - /** l1_icache0_preload_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L1-ICache0, which - * should be used together with L1_ICACHE0_PRELOAD_SIZE_REG - */ - uint32_t l1_icache0_preload_addr:32; - }; - uint32_t val; -} cache_l1_icache0_preload_addr_reg_t; - -/** Type of l1_icache0_preload_size register - * L1 instruction Cache 0 preload size configure register - */ -typedef union { - struct { - /** l1_icache0_preload_size : HRO; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG - */ - uint32_t l1_icache0_preload_size:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} cache_l1_icache0_preload_size_reg_t; - -/** Type of l1_icache1_preload_ctrl register - * L1 instruction Cache 1 preload-operation control register - */ -typedef union { - struct { - /** l1_icache1_preload_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-ICache1. It will be cleared by - * hardware automatically after preload operation is done. - */ - uint32_t l1_icache1_preload_ena:1; - /** l1_icache1_preload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ - uint32_t l1_icache1_preload_done:1; - /** l1_icache1_preload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ - uint32_t l1_icache1_preload_order:1; - /** l1_icache1_preload_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 icache1 preload. - */ - uint32_t l1_icache1_preload_rgid:4; - uint32_t reserved_7:25; - }; - uint32_t val; -} cache_l1_icache1_preload_ctrl_reg_t; - -/** Type of l1_icache1_preload_addr register - * L1 instruction Cache 1 preload address configure register - */ -typedef union { - struct { - /** l1_icache1_preload_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L1-ICache1, which - * should be used together with L1_ICACHE1_PRELOAD_SIZE_REG - */ - uint32_t l1_icache1_preload_addr:32; - }; - uint32_t val; -} cache_l1_icache1_preload_addr_reg_t; - -/** Type of l1_icache1_preload_size register - * L1 instruction Cache 1 preload size configure register - */ -typedef union { - struct { - /** l1_icache1_preload_size : HRO; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG - */ - uint32_t l1_icache1_preload_size:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} cache_l1_icache1_preload_size_reg_t; - -/** Type of l1_icache2_preload_ctrl register - * L1 instruction Cache 2 preload-operation control register - */ -typedef union { - struct { - /** l1_icache2_preload_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-ICache2. It will be cleared by - * hardware automatically after preload operation is done. - */ - uint32_t l1_icache2_preload_ena:1; - /** l1_icache2_preload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ - uint32_t l1_icache2_preload_done:1; - /** l1_icache2_preload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ - uint32_t l1_icache2_preload_order:1; - /** l1_icache2_preload_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 icache2 preload. - */ - uint32_t l1_icache2_preload_rgid:4; - uint32_t reserved_7:25; - }; - uint32_t val; -} cache_l1_icache2_preload_ctrl_reg_t; - -/** Type of l1_icache2_preload_addr register - * L1 instruction Cache 2 preload address configure register - */ -typedef union { - struct { - /** l1_icache2_preload_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L1-ICache2, which - * should be used together with L1_ICACHE2_PRELOAD_SIZE_REG - */ - uint32_t l1_icache2_preload_addr:32; - }; - uint32_t val; -} cache_l1_icache2_preload_addr_reg_t; - -/** Type of l1_icache2_preload_size register - * L1 instruction Cache 2 preload size configure register - */ -typedef union { - struct { - /** l1_icache2_preload_size : HRO; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG - */ - uint32_t l1_icache2_preload_size:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} cache_l1_icache2_preload_size_reg_t; - -/** Type of l1_icache3_preload_ctrl register - * L1 instruction Cache 3 preload-operation control register - */ -typedef union { - struct { - /** l1_icache3_preload_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-ICache3. It will be cleared by - * hardware automatically after preload operation is done. - */ - uint32_t l1_icache3_preload_ena:1; - /** l1_icache3_preload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ - uint32_t l1_icache3_preload_done:1; - /** l1_icache3_preload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ - uint32_t l1_icache3_preload_order:1; - /** l1_icache3_preload_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 icache3 preload. - */ - uint32_t l1_icache3_preload_rgid:4; - uint32_t reserved_7:25; - }; - uint32_t val; -} cache_l1_icache3_preload_ctrl_reg_t; - -/** Type of l1_icache3_preload_addr register - * L1 instruction Cache 3 preload address configure register - */ -typedef union { - struct { - /** l1_icache3_preload_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L1-ICache3, which - * should be used together with L1_ICACHE3_PRELOAD_SIZE_REG - */ - uint32_t l1_icache3_preload_addr:32; - }; - uint32_t val; -} cache_l1_icache3_preload_addr_reg_t; - -/** Type of l1_icache3_preload_size register - * L1 instruction Cache 3 preload size configure register - */ -typedef union { - struct { - /** l1_icache3_preload_size : HRO; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG - */ - uint32_t l1_icache3_preload_size:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} cache_l1_icache3_preload_size_reg_t; - +/** Group: Preloading Control and Configuration Registers */ /** Type of l1_cache_preload_ctrl register - * L1 Cache preload-operation control register + * L1 cache preloading operation control register */ typedef union { struct { /** l1_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-Cache. It will be cleared by - * hardware automatically after preload operation is done. + * Configures whether to enable the preloading operation in the L1 cache. It will be + * cleared by hardware automatically after the preloading operation is done. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_preload_ena:1; /** l1_cache_preload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. + * Represents whether the preloading operation is finished. + * 0: Not finished + * 1: Finished */ uint32_t l1_cache_preload_done:1; /** l1_cache_preload_order : R/W; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. + * Configures the direction of the preloading operation. + * 0: Ascending + * 1: Descending */ uint32_t l1_cache_preload_order:1; - /** l1_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 cache preload. - */ - uint32_t l1_cache_preload_rgid:4; - uint32_t reserved_7:25; + uint32_t reserved_3:29; }; uint32_t val; } cache_l1_cache_preload_ctrl_reg_t; -/** Type of l1_dcache_preload_addr register - * L1 Cache preload address configure register +/** Type of l1_cache_preload_addr register + * L1 cache preloading address configuration register */ typedef union { struct { /** l1_cache_preload_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L1-Cache, which - * should be used together with L1_CACHE_PRELOAD_SIZE_REG + * Configures the starting virtual address for the preloading operation in the L1 + * cache. This field should be configured together with + * CACHE_L1_CACHE_PRELOAD_SIZE_REG. */ uint32_t l1_cache_preload_addr:32; }; uint32_t val; -} cache_l1_dcache_preload_addr_reg_t; +} cache_l1_cache_preload_addr_reg_t; -/** Type of l1_dcache_preload_size register - * L1 Cache preload size configure register +/** Type of l1_cache_preload_size register + * L1 cache preloading size configuration register */ typedef union { struct { /** l1_cache_preload_size : R/W; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG + * Configures the size of Section 0 for the preloading operation in the L1 cache. This + * field should be configured together with CACHE_L1_CACHE_PRELOAD_ADDR_REG. */ uint32_t l1_cache_preload_size:14; uint32_t reserved_14:18; }; uint32_t val; -} cache_l1_dcache_preload_size_reg_t; - -/** Type of l2_cache_preload_ctrl register - * L2 Cache preload-operation control register - */ -typedef union { - struct { - /** l2_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L2-Cache. It will be cleared by - * hardware automatically after preload operation is done. - */ - uint32_t l2_cache_preload_ena:1; - /** l2_cache_preload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ - uint32_t l2_cache_preload_done:1; - /** l2_cache_preload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ - uint32_t l2_cache_preload_order:1; - /** l2_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l2 cache preload. - */ - uint32_t l2_cache_preload_rgid:4; - uint32_t reserved_7:25; - }; - uint32_t val; -} cache_l2_cache_preload_ctrl_reg_t; - -/** Type of l2_cache_preload_addr register - * L2 Cache preload address configure register - */ -typedef union { - struct { - /** l2_cache_preload_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L2-Cache, which - * should be used together with L2_CACHE_PRELOAD_SIZE_REG - */ - uint32_t l2_cache_preload_addr:32; - }; - uint32_t val; -} cache_l2_cache_preload_addr_reg_t; - -/** Type of l2_cache_preload_size register - * L2 Cache preload size configure register - */ -typedef union { - struct { - /** l2_cache_preload_size : HRO; bitpos: [15:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG - */ - uint32_t l2_cache_preload_size:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} cache_l2_cache_preload_size_reg_t; +} cache_l1_cache_preload_size_reg_t; -/** Group: Autoload Control and configuration registers */ -/** Type of l1_icache0_autoload_ctrl register - * L1 instruction Cache 0 autoload-operation control register - */ -typedef union { - struct { - /** l1_icache0_autoload_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, - * 0: disable. - */ - uint32_t l1_icache0_autoload_ena:1; - /** l1_icache0_autoload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-ICache0 is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l1_icache0_autoload_done:1; - /** l1_icache0_autoload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-ICache0. 0: - * ascending. 1: descending. - */ - uint32_t l1_icache0_autoload_order:1; - /** l1_icache0_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-ICache0. - * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ - uint32_t l1_icache0_autoload_trigger_mode:2; - uint32_t reserved_5:3; - /** l1_icache0_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-ICache0. - */ - uint32_t l1_icache0_autoload_sct0_ena:1; - /** l1_icache0_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-ICache0. - */ - uint32_t l1_icache0_autoload_sct1_ena:1; - /** l1_icache0_autoload_rgid : HRO; bitpos: [13:10]; default: 0; - * The bit is used to set the gid of l1 icache0 autoload. - */ - uint32_t l1_icache0_autoload_rgid:4; - uint32_t reserved_14:18; - }; - uint32_t val; -} cache_l1_icache0_autoload_ctrl_reg_t; - -/** Type of l1_icache0_autoload_sct0_addr register - * L1 instruction Cache 0 autoload section 0 address configure register - */ -typedef union { - struct { - /** l1_icache0_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L1-ICache0. Note that it should be used together with - * L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache0_autoload_sct0_addr:32; - }; - uint32_t val; -} cache_l1_icache0_autoload_sct0_addr_reg_t; - -/** Type of l1_icache0_autoload_sct0_size register - * L1 instruction Cache 0 autoload section 0 size configure register - */ -typedef union { - struct { - /** l1_icache0_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-ICache0. Note that it should be used together with - * L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache0_autoload_sct0_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l1_icache0_autoload_sct0_size_reg_t; - -/** Type of l1_icache0_autoload_sct1_addr register - * L1 instruction Cache 0 autoload section 1 address configure register - */ -typedef union { - struct { - /** l1_icache0_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L1-ICache0. Note that it should be used together with - * L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache0_autoload_sct1_addr:32; - }; - uint32_t val; -} cache_l1_icache0_autoload_sct1_addr_reg_t; - -/** Type of l1_icache0_autoload_sct1_size register - * L1 instruction Cache 0 autoload section 1 size configure register - */ -typedef union { - struct { - /** l1_icache0_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L1-ICache0. Note that it should be used together with - * L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache0_autoload_sct1_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l1_icache0_autoload_sct1_size_reg_t; - -/** Type of l1_icache1_autoload_ctrl register - * L1 instruction Cache 1 autoload-operation control register - */ -typedef union { - struct { - /** l1_icache1_autoload_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, - * 0: disable. - */ - uint32_t l1_icache1_autoload_ena:1; - /** l1_icache1_autoload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-ICache1 is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l1_icache1_autoload_done:1; - /** l1_icache1_autoload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-ICache1. 0: - * ascending. 1: descending. - */ - uint32_t l1_icache1_autoload_order:1; - /** l1_icache1_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-ICache1. - * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ - uint32_t l1_icache1_autoload_trigger_mode:2; - uint32_t reserved_5:3; - /** l1_icache1_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-ICache1. - */ - uint32_t l1_icache1_autoload_sct0_ena:1; - /** l1_icache1_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-ICache1. - */ - uint32_t l1_icache1_autoload_sct1_ena:1; - /** l1_icache1_autoload_rgid : HRO; bitpos: [13:10]; default: 0; - * The bit is used to set the gid of l1 icache1 autoload. - */ - uint32_t l1_icache1_autoload_rgid:4; - uint32_t reserved_14:18; - }; - uint32_t val; -} cache_l1_icache1_autoload_ctrl_reg_t; - -/** Type of l1_icache1_autoload_sct0_addr register - * L1 instruction Cache 1 autoload section 0 address configure register - */ -typedef union { - struct { - /** l1_icache1_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L1-ICache1. Note that it should be used together with - * L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache1_autoload_sct0_addr:32; - }; - uint32_t val; -} cache_l1_icache1_autoload_sct0_addr_reg_t; - -/** Type of l1_icache1_autoload_sct0_size register - * L1 instruction Cache 1 autoload section 0 size configure register - */ -typedef union { - struct { - /** l1_icache1_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-ICache1. Note that it should be used together with - * L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache1_autoload_sct0_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l1_icache1_autoload_sct0_size_reg_t; - -/** Type of l1_icache1_autoload_sct1_addr register - * L1 instruction Cache 1 autoload section 1 address configure register - */ -typedef union { - struct { - /** l1_icache1_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L1-ICache1. Note that it should be used together with - * L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache1_autoload_sct1_addr:32; - }; - uint32_t val; -} cache_l1_icache1_autoload_sct1_addr_reg_t; - -/** Type of l1_icache1_autoload_sct1_size register - * L1 instruction Cache 1 autoload section 1 size configure register - */ -typedef union { - struct { - /** l1_icache1_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L1-ICache1. Note that it should be used together with - * L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache1_autoload_sct1_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l1_icache1_autoload_sct1_size_reg_t; - -/** Type of l1_icache2_autoload_ctrl register - * L1 instruction Cache 2 autoload-operation control register - */ -typedef union { - struct { - /** l1_icache2_autoload_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, - * 0: disable. - */ - uint32_t l1_icache2_autoload_ena:1; - /** l1_icache2_autoload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-ICache2 is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l1_icache2_autoload_done:1; - /** l1_icache2_autoload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-ICache2. 0: - * ascending. 1: descending. - */ - uint32_t l1_icache2_autoload_order:1; - /** l1_icache2_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-ICache2. - * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ - uint32_t l1_icache2_autoload_trigger_mode:2; - uint32_t reserved_5:3; - /** l1_icache2_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-ICache2. - */ - uint32_t l1_icache2_autoload_sct0_ena:1; - /** l1_icache2_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-ICache2. - */ - uint32_t l1_icache2_autoload_sct1_ena:1; - /** l1_icache2_autoload_rgid : HRO; bitpos: [13:10]; default: 0; - * The bit is used to set the gid of l1 icache2 autoload. - */ - uint32_t l1_icache2_autoload_rgid:4; - uint32_t reserved_14:18; - }; - uint32_t val; -} cache_l1_icache2_autoload_ctrl_reg_t; - -/** Type of l1_icache2_autoload_sct0_addr register - * L1 instruction Cache 2 autoload section 0 address configure register - */ -typedef union { - struct { - /** l1_icache2_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L1-ICache2. Note that it should be used together with - * L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache2_autoload_sct0_addr:32; - }; - uint32_t val; -} cache_l1_icache2_autoload_sct0_addr_reg_t; - -/** Type of l1_icache2_autoload_sct0_size register - * L1 instruction Cache 2 autoload section 0 size configure register - */ -typedef union { - struct { - /** l1_icache2_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-ICache2. Note that it should be used together with - * L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache2_autoload_sct0_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l1_icache2_autoload_sct0_size_reg_t; - -/** Type of l1_icache2_autoload_sct1_addr register - * L1 instruction Cache 2 autoload section 1 address configure register - */ -typedef union { - struct { - /** l1_icache2_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L1-ICache2. Note that it should be used together with - * L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache2_autoload_sct1_addr:32; - }; - uint32_t val; -} cache_l1_icache2_autoload_sct1_addr_reg_t; - -/** Type of l1_icache2_autoload_sct1_size register - * L1 instruction Cache 2 autoload section 1 size configure register - */ -typedef union { - struct { - /** l1_icache2_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L1-ICache2. Note that it should be used together with - * L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache2_autoload_sct1_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l1_icache2_autoload_sct1_size_reg_t; - -/** Type of l1_icache3_autoload_ctrl register - * L1 instruction Cache 3 autoload-operation control register - */ -typedef union { - struct { - /** l1_icache3_autoload_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, - * 0: disable. - */ - uint32_t l1_icache3_autoload_ena:1; - /** l1_icache3_autoload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-ICache3 is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l1_icache3_autoload_done:1; - /** l1_icache3_autoload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-ICache3. 0: - * ascending. 1: descending. - */ - uint32_t l1_icache3_autoload_order:1; - /** l1_icache3_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-ICache3. - * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ - uint32_t l1_icache3_autoload_trigger_mode:2; - uint32_t reserved_5:3; - /** l1_icache3_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-ICache3. - */ - uint32_t l1_icache3_autoload_sct0_ena:1; - /** l1_icache3_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-ICache3. - */ - uint32_t l1_icache3_autoload_sct1_ena:1; - /** l1_icache3_autoload_rgid : HRO; bitpos: [13:10]; default: 0; - * The bit is used to set the gid of l1 icache3 autoload. - */ - uint32_t l1_icache3_autoload_rgid:4; - uint32_t reserved_14:18; - }; - uint32_t val; -} cache_l1_icache3_autoload_ctrl_reg_t; - -/** Type of l1_icache3_autoload_sct0_addr register - * L1 instruction Cache 3 autoload section 0 address configure register - */ -typedef union { - struct { - /** l1_icache3_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L1-ICache3. Note that it should be used together with - * L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache3_autoload_sct0_addr:32; - }; - uint32_t val; -} cache_l1_icache3_autoload_sct0_addr_reg_t; - -/** Type of l1_icache3_autoload_sct0_size register - * L1 instruction Cache 3 autoload section 0 size configure register - */ -typedef union { - struct { - /** l1_icache3_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-ICache3. Note that it should be used together with - * L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache3_autoload_sct0_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l1_icache3_autoload_sct0_size_reg_t; - -/** Type of l1_icache3_autoload_sct1_addr register - * L1 instruction Cache 3 autoload section 1 address configure register - */ -typedef union { - struct { - /** l1_icache3_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L1-ICache3. Note that it should be used together with - * L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache3_autoload_sct1_addr:32; - }; - uint32_t val; -} cache_l1_icache3_autoload_sct1_addr_reg_t; - -/** Type of l1_icache3_autoload_sct1_size register - * L1 instruction Cache 3 autoload section 1 size configure register - */ -typedef union { - struct { - /** l1_icache3_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; - * Reserved - */ - uint32_t l1_icache3_autoload_sct1_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l1_icache3_autoload_sct1_size_reg_t; - +/** Group: Autoloading Control and Configuration Registers */ /** Type of l1_cache_autoload_ctrl register - * L1 Cache autoload-operation control register + * L1 cache autoloading operation control register */ typedef union { struct { /** l1_cache_autoload_ena : R/W; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-Cache. 1: enable, - * 0: disable. + * Configures whether to enable the autoloading operation in the L1 cache. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_autoload_ena:1; /** l1_cache_autoload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-Cache is finished or - * not. 0: not finished. 1: finished. + * Represents whether the autoloading operation in the L1 cache is finished. + * 0: Not finished + * 1: Finished */ uint32_t l1_cache_autoload_done:1; /** l1_cache_autoload_order : R/W; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-Cache. 0: - * ascending. 1: descending. + * Configures the direction of the autoloading operation in the L1 cache. + * 0: Ascending + * 1: Descending */ uint32_t l1_cache_autoload_order:1; /** l1_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3: - * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + * Configures the trigger mode of the autoloading operation in the L1 cache. + * 0/3: Triggered by misses + * 1: Triggered by hits + * 2: Triggered by misses or hits */ uint32_t l1_cache_autoload_trigger_mode:2; uint32_t reserved_5:3; /** l1_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-Cache. + * Configures whether to enable Section 0 for the autoloading operation in the L1 + * cache. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_autoload_sct0_ena:1; /** l1_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-Cache. + * Configures whether to enable Section 1 for the autoloading operation in the L1 + * cache. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_autoload_sct1_ena:1; - /** l1_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0; - * The bit is used to enable the third section for autoload operation on L1-Cache. - */ - uint32_t l1_cache_autoload_sct2_ena:1; - /** l1_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0; - * The bit is used to enable the fourth section for autoload operation on L1-Cache. - */ - uint32_t l1_cache_autoload_sct3_ena:1; - /** l1_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0; - * The bit is used to set the gid of l1 cache autoload. - */ - uint32_t l1_cache_autoload_rgid:4; - uint32_t reserved_16:16; + uint32_t reserved_10:22; }; uint32_t val; } cache_l1_cache_autoload_ctrl_reg_t; /** Type of l1_cache_autoload_sct0_addr register - * L1 Cache autoload section 0 address configure register + * L1 cache autoloading Section 0 address configuration register */ typedef union { struct { /** l1_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA. + * Configures the starting virtual address of Section 0 for the autoloading operation + * in the L1 cache. Note that it should be used together with + * CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE and CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA. */ uint32_t l1_cache_autoload_sct0_addr:32; }; @@ -2311,14 +552,14 @@ typedef union { } cache_l1_cache_autoload_sct0_addr_reg_t; /** Type of l1_cache_autoload_sct0_size register - * L1 Cache autoload section 0 size configure register + * L1 cache autoloading Section 0 size configuration register */ typedef union { struct { /** l1_cache_autoload_sct0_size : R/W; bitpos: [24:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA. + * Configures the size of Section 0 for the autoloading operation in the L1 cache. + * Note that it should be used together with CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR and + * CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA. */ uint32_t l1_cache_autoload_sct0_size:25; uint32_t reserved_25:7; @@ -2327,14 +568,14 @@ typedef union { } cache_l1_cache_autoload_sct0_size_reg_t; /** Type of l1_cache_autoload_sct1_addr register - * L1 Cache autoload section 1 address configure register + * L1 cache autoloading Section 1 address configuration register */ typedef union { struct { /** l1_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA. + * Configures the starting virtual address of Section 1 for the autoloading operation + * in the L1 cache. Note that it should be used together with + * CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE and CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA. */ uint32_t l1_cache_autoload_sct1_addr:32; }; @@ -2342,14 +583,14 @@ typedef union { } cache_l1_cache_autoload_sct1_addr_reg_t; /** Type of l1_cache_autoload_sct1_size register - * L1 Cache autoload section 1 size configure register + * L1 cache autoloading Section 1 size configuration register */ typedef union { struct { /** l1_cache_autoload_sct1_size : R/W; bitpos: [24:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA. + * Configures the size of Section 1 for the autoloading operation in the L1 cache. + * Note that it should be used together with CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR and + * CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA. */ uint32_t l1_cache_autoload_sct1_size:25; uint32_t reserved_25:7; @@ -2357,459 +598,110 @@ typedef union { uint32_t val; } cache_l1_cache_autoload_sct1_size_reg_t; -/** Type of l1_cache_autoload_sct2_addr register - * L1 Cache autoload section 2 address configure register - */ -typedef union { - struct { - /** l1_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the third section for - * autoload operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA. - */ - uint32_t l1_cache_autoload_sct2_addr:32; - }; - uint32_t val; -} cache_l1_cache_autoload_sct2_addr_reg_t; -/** Type of l1_cache_autoload_sct2_size register - * L1 Cache autoload section 2 size configure register - */ -typedef union { - struct { - /** l1_cache_autoload_sct2_size : HRO; bitpos: [24:0]; default: 0; - * Those bits are used to configure the size of the third section for autoload - * operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA. - */ - uint32_t l1_cache_autoload_sct2_size:25; - uint32_t reserved_25:7; - }; - uint32_t val; -} cache_l1_cache_autoload_sct2_size_reg_t; - -/** Type of l1_cache_autoload_sct3_addr register - * L1 Cache autoload section 1 address configure register - */ -typedef union { - struct { - /** l1_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the fourth section for - * autoload operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA. - */ - uint32_t l1_cache_autoload_sct3_addr:32; - }; - uint32_t val; -} cache_l1_cache_autoload_sct3_addr_reg_t; - -/** Type of l1_cache_autoload_sct3_size register - * L1 Cache autoload section 1 size configure register - */ -typedef union { - struct { - /** l1_cache_autoload_sct3_size : HRO; bitpos: [24:0]; default: 0; - * Those bits are used to configure the size of the fourth section for autoload - * operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA. - */ - uint32_t l1_cache_autoload_sct3_size:25; - uint32_t reserved_25:7; - }; - uint32_t val; -} cache_l1_cache_autoload_sct3_size_reg_t; - -/** Type of l2_cache_autoload_ctrl register - * L2 Cache autoload-operation control register - */ -typedef union { - struct { - /** l2_cache_autoload_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, - * 0: disable. - */ - uint32_t l2_cache_autoload_ena:1; - /** l2_cache_autoload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L2-Cache is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l2_cache_autoload_done:1; - /** l2_cache_autoload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L2-Cache. 0: - * ascending. 1: descending. - */ - uint32_t l2_cache_autoload_order:1; - /** l2_cache_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: - * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ - uint32_t l2_cache_autoload_trigger_mode:2; - uint32_t reserved_5:3; - /** l2_cache_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L2-Cache. - */ - uint32_t l2_cache_autoload_sct0_ena:1; - /** l2_cache_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L2-Cache. - */ - uint32_t l2_cache_autoload_sct1_ena:1; - /** l2_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0; - * The bit is used to enable the third section for autoload operation on L2-Cache. - */ - uint32_t l2_cache_autoload_sct2_ena:1; - /** l2_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0; - * The bit is used to enable the fourth section for autoload operation on L2-Cache. - */ - uint32_t l2_cache_autoload_sct3_ena:1; - /** l2_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0; - * The bit is used to set the gid of l2 cache autoload. - */ - uint32_t l2_cache_autoload_rgid:4; - uint32_t reserved_16:16; - }; - uint32_t val; -} cache_l2_cache_autoload_ctrl_reg_t; - -/** Type of l2_cache_autoload_sct0_addr register - * L2 Cache autoload section 0 address configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l2_cache_autoload_sct0_addr:32; - }; - uint32_t val; -} cache_l2_cache_autoload_sct0_addr_reg_t; - -/** Type of l2_cache_autoload_sct0_size register - * L2 Cache autoload section 0 size configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l2_cache_autoload_sct0_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l2_cache_autoload_sct0_size_reg_t; - -/** Type of l2_cache_autoload_sct1_addr register - * L2 Cache autoload section 1 address configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l2_cache_autoload_sct1_addr:32; - }; - uint32_t val; -} cache_l2_cache_autoload_sct1_addr_reg_t; - -/** Type of l2_cache_autoload_sct1_size register - * L2 Cache autoload section 1 size configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l2_cache_autoload_sct1_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l2_cache_autoload_sct1_size_reg_t; - -/** Type of l2_cache_autoload_sct2_addr register - * L2 Cache autoload section 2 address configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the third section for - * autoload operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA. - */ - uint32_t l2_cache_autoload_sct2_addr:32; - }; - uint32_t val; -} cache_l2_cache_autoload_sct2_addr_reg_t; - -/** Type of l2_cache_autoload_sct2_size register - * L2 Cache autoload section 2 size configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the third section for autoload - * operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA. - */ - uint32_t l2_cache_autoload_sct2_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l2_cache_autoload_sct2_size_reg_t; - -/** Type of l2_cache_autoload_sct3_addr register - * L2 Cache autoload section 3 address configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the fourth section for - * autoload operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA. - */ - uint32_t l2_cache_autoload_sct3_addr:32; - }; - uint32_t val; -} cache_l2_cache_autoload_sct3_addr_reg_t; - -/** Type of l2_cache_autoload_sct3_size register - * L2 Cache autoload section 3 size configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the fourth section for autoload - * operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA. - */ - uint32_t l2_cache_autoload_sct3_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l2_cache_autoload_sct3_size_reg_t; - - -/** Group: Interrupt registers */ +/** Group: Interrupt Registers */ /** Type of l1_cache_acs_cnt_int_ena register - * Cache Access Counter Interrupt enable register + * Cache access counter interrupt enable register */ typedef union { struct { - /** l1_ibus0_ovf_int_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L1-ICache0 due to bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_ovf_int_ena:1; - /** l1_ibus1_ovf_int_ena : HRO; bitpos: [1]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L1-ICache1 due to bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_ovf_int_ena:1; - /** l1_ibus2_ovf_int_ena : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_ibus2_ovf_int_ena:1; - /** l1_ibus3_ovf_int_ena : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_ibus3_ovf_int_ena:1; + uint32_t reserved_0:4; /** l1_bus0_ovf_int_ena : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L1-DCache due to bus0 accesses L1-DCache. + * Write 1 to enable L1_BUS0_OVF_INT. */ uint32_t l1_bus0_ovf_int_ena:1; /** l1_bus1_ovf_int_ena : R/W; bitpos: [5]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L1-DCache due to bus1 accesses L1-DCache. + * Write 1 to enable L1_BUS1_OVF_INT. */ uint32_t l1_bus1_ovf_int_ena:1; - /** l1_dbus2_ovf_int_ena : HRO; bitpos: [6]; default: 0; - * Reserved - */ - uint32_t l1_dbus2_ovf_int_ena:1; - /** l1_dbus3_ovf_int_ena : HRO; bitpos: [7]; default: 0; - * Reserved - */ - uint32_t l1_dbus3_ovf_int_ena:1; - uint32_t reserved_8:24; + uint32_t reserved_6:26; }; uint32_t val; } cache_l1_cache_acs_cnt_int_ena_reg_t; /** Type of l1_cache_acs_cnt_int_clr register - * Cache Access Counter Interrupt clear register + * Cache access counter interrupt clear register */ typedef union { struct { - /** l1_ibus0_ovf_int_clr : HRO; bitpos: [0]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due - * to bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_ovf_int_clr:1; - /** l1_ibus1_ovf_int_clr : HRO; bitpos: [1]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due - * to bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_ovf_int_clr:1; - /** l1_ibus2_ovf_int_clr : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_ibus2_ovf_int_clr:1; - /** l1_ibus3_ovf_int_clr : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_ibus3_ovf_int_clr:1; + uint32_t reserved_0:4; /** l1_bus0_ovf_int_clr : WT; bitpos: [4]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L1-DCache due - * to bus0 accesses L1-DCache. + * Write 1 to clear L1_BUS0_OVF_INT. */ uint32_t l1_bus0_ovf_int_clr:1; /** l1_bus1_ovf_int_clr : WT; bitpos: [5]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L1-DCache due - * to bus1 accesses L1-DCache. + * Write 1 to clear L1_BUS1_OVF_INT. */ uint32_t l1_bus1_ovf_int_clr:1; - /** l1_dbus2_ovf_int_clr : R/W; bitpos: [6]; default: 0; - * Reserved - */ - uint32_t l1_dbus2_ovf_int_clr:1; - /** l1_dbus3_ovf_int_clr : R/W; bitpos: [7]; default: 0; - * Reserved - */ - uint32_t l1_dbus3_ovf_int_clr:1; - uint32_t reserved_8:24; + uint32_t reserved_6:26; }; uint32_t val; } cache_l1_cache_acs_cnt_int_clr_reg_t; /** Type of l1_cache_acs_cnt_int_raw register - * Cache Access Counter Interrupt raw register + * Cache access counter interrupt raw register */ typedef union { struct { - /** l1_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 - * due to bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_ovf_int_raw:1; - /** l1_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 - * due to bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_ovf_int_raw:1; - /** l1_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 - * due to bus2 accesses L1-ICache2. - */ - uint32_t l1_ibus2_ovf_int_raw:1; - /** l1_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 - * due to bus3 accesses L1-ICache3. - */ - uint32_t l1_ibus3_ovf_int_raw:1; + uint32_t reserved_0:4; /** l1_bus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache - * due to bus0 accesses L1-DCache. + * The raw interrupt status of L1_BUS0_OVF_INT. */ uint32_t l1_bus0_ovf_int_raw:1; /** l1_bus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache - * due to bus1 accesses L1-DCache. + * The raw interrupt status of L1_BUS1_OVF_INT. */ uint32_t l1_bus1_ovf_int_raw:1; - /** l1_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache - * due to bus2 accesses L1-DCache. - */ - uint32_t l1_dbus2_ovf_int_raw:1; - /** l1_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache - * due to bus3 accesses L1-DCache. - */ - uint32_t l1_dbus3_ovf_int_raw:1; - uint32_t reserved_8:24; + uint32_t reserved_6:26; }; uint32_t val; } cache_l1_cache_acs_cnt_int_raw_reg_t; /** Type of l1_cache_acs_cnt_int_st register - * Cache Access Counter Interrupt status register + * Cache access counter interrupt status register */ typedef union { struct { - /** l1_ibus0_ovf_int_st : HRO; bitpos: [0]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L1-ICache0 due to bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_ovf_int_st:1; - /** l1_ibus1_ovf_int_st : RO; bitpos: [1]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L1-ICache1 due to bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_ovf_int_st:1; - /** l1_ibus2_ovf_int_st : RO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_ibus2_ovf_int_st:1; - /** l1_ibus3_ovf_int_st : RO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_ibus3_ovf_int_st:1; + uint32_t reserved_0:4; /** l1_bus0_ovf_int_st : RO; bitpos: [4]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L1-DCache due to bus0 accesses L1-DCache. + * The masked interrupt status of L1_BUS0_OVF_INT. */ uint32_t l1_bus0_ovf_int_st:1; /** l1_bus1_ovf_int_st : RO; bitpos: [5]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L1-DCache due to bus1 accesses L1-DCache. + * The masked interrupt status of L1_BUS1_OVF_INT. */ uint32_t l1_bus1_ovf_int_st:1; - /** l1_dbus2_ovf_int_st : RO; bitpos: [6]; default: 0; - * Reserved - */ - uint32_t l1_dbus2_ovf_int_st:1; - /** l1_dbus3_ovf_int_st : RO; bitpos: [7]; default: 0; - * Reserved - */ - uint32_t l1_dbus3_ovf_int_st:1; - uint32_t reserved_8:24; + uint32_t reserved_6:26; }; uint32_t val; } cache_l1_cache_acs_cnt_int_st_reg_t; -/** Type of l1_cache_acs_fail_int_ena register - * Cache Access Fail Interrupt enable register +/** Type of l1_cache_acs_fail_ctrl register + * Cache access failed interrupt configuration register */ typedef union { struct { - /** l1_icache0_fail_int_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to - * cpu accesses L1-ICache0. + uint32_t reserved_0:4; + /** l1_cache_acs_fail_check_mode : R/W; bitpos: [4]; default: 0; + * Configures whether to pass the exception of cache accessing lower-level memory to + * the upper-level device. + * 0: Do not pass to the upper-level device + * 1: Pass to the upper-level device */ - uint32_t l1_icache0_fail_int_ena:1; - /** l1_icache1_fail_int_ena : HRO; bitpos: [1]; default: 0; - * The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to - * cpu accesses L1-ICache1. - */ - uint32_t l1_icache1_fail_int_ena:1; - /** l1_icache2_fail_int_ena : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_fail_int_ena:1; - /** l1_icache3_fail_int_ena : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_fail_int_ena:1; + uint32_t l1_cache_acs_fail_check_mode:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_ctrl_reg_t; + +/** Type of l1_cache_acs_fail_int_ena register + * Cache access failed interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:4; /** l1_cache_fail_int_ena : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt of access fail that occurs in L1-DCache due to - * cpu accesses L1-DCache. + * Write 1 to enable L1_CACHE_FAIL_INT. */ uint32_t l1_cache_fail_int_ena:1; uint32_t reserved_5:27; @@ -2818,31 +710,13 @@ typedef union { } cache_l1_cache_acs_fail_int_ena_reg_t; /** Type of l1_cache_acs_fail_int_clr register - * L1-Cache Access Fail Interrupt clear register + * L1 cache access failed interrupt clear register */ typedef union { struct { - /** l1_icache0_fail_int_clr : WT; bitpos: [0]; default: 0; - * The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to - * cpu accesses L1-ICache0. - */ - uint32_t l1_icache0_fail_int_clr:1; - /** l1_icache1_fail_int_clr : WT; bitpos: [1]; default: 0; - * The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to - * cpu accesses L1-ICache1. - */ - uint32_t l1_icache1_fail_int_clr:1; - /** l1_icache2_fail_int_clr : WT; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_fail_int_clr:1; - /** l1_icache3_fail_int_clr : WT; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_fail_int_clr:1; + uint32_t reserved_0:4; /** l1_cache_fail_int_clr : WT; bitpos: [4]; default: 0; - * The bit is used to clear interrupt of access fail that occurs in L1-DCache due to - * cpu accesses L1-DCache. + * Write 1 to clear L1_CACHE_FAIL_INT. */ uint32_t l1_cache_fail_int_clr:1; uint32_t reserved_5:27; @@ -2851,28 +725,13 @@ typedef union { } cache_l1_cache_acs_fail_int_clr_reg_t; /** Type of l1_cache_acs_fail_int_raw register - * Cache Access Fail Interrupt raw register + * Cache access failed interrupt raw register */ typedef union { struct { - /** l1_icache0_fail_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-ICache0. - */ - uint32_t l1_icache0_fail_int_raw:1; - /** l1_icache1_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-ICache1. - */ - uint32_t l1_icache1_fail_int_raw:1; - /** l1_icache2_fail_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-ICache2. - */ - uint32_t l1_icache2_fail_int_raw:1; - /** l1_icache3_fail_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-ICache3. - */ - uint32_t l1_icache3_fail_int_raw:1; + uint32_t reserved_0:4; /** l1_cache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-DCache. + * The raw interrupt status of L1_CACHE_FAIL_INT. */ uint32_t l1_cache_fail_int_raw:1; uint32_t reserved_5:27; @@ -2881,31 +740,13 @@ typedef union { } cache_l1_cache_acs_fail_int_raw_reg_t; /** Type of l1_cache_acs_fail_int_st register - * Cache Access Fail Interrupt status register + * Cache access failed interrupt status register */ typedef union { struct { - /** l1_icache0_fail_int_st : RO; bitpos: [0]; default: 0; - * The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due - * to cpu accesses L1-ICache. - */ - uint32_t l1_icache0_fail_int_st:1; - /** l1_icache1_fail_int_st : RO; bitpos: [1]; default: 0; - * The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due - * to cpu accesses L1-ICache. - */ - uint32_t l1_icache1_fail_int_st:1; - /** l1_icache2_fail_int_st : RO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_fail_int_st:1; - /** l1_icache3_fail_int_st : RO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_fail_int_st:1; + uint32_t reserved_0:4; /** l1_cache_fail_int_st : RO; bitpos: [4]; default: 0; - * The bit indicates the interrupt status of access fail that occurs in L1-DCache due - * to cpu accesses L1-DCache. + * The masked interrupt status of L1_CACHE_FAIL_INT. */ uint32_t l1_cache_fail_int_st:1; uint32_t reserved_5:27; @@ -2914,61 +755,28 @@ typedef union { } cache_l1_cache_acs_fail_int_st_reg_t; /** Type of l1_cache_sync_preload_int_ena register - * L1-Cache Access Fail Interrupt enable register + * Sync and preloading operation interrupt enable register */ typedef union { struct { - /** l1_icache0_pld_done_int_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload - * operation is done, interrupt occurs. - */ - uint32_t l1_icache0_pld_done_int_ena:1; - /** l1_icache1_pld_done_int_ena : HRO; bitpos: [1]; default: 0; - * The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload - * operation is done, interrupt occurs. - */ - uint32_t l1_icache1_pld_done_int_ena:1; - /** l1_icache2_pld_done_int_ena : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_done_int_ena:1; - /** l1_icache3_pld_done_int_ena : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_done_int_ena:1; + uint32_t reserved_0:4; /** l1_cache_pld_done_int_ena : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt of L1-Cache preload-operation. If preload - * operation is done, interrupt occurs. + * Write 1 to enable L1_CACHE_PLD_DONE_INT. */ uint32_t l1_cache_pld_done_int_ena:1; uint32_t reserved_5:1; /** sync_done_int_ena : R/W; bitpos: [6]; default: 0; - * The bit is used to enable interrupt of Cache sync-operation done. + * Write 1 to enable CACHE_SYNC_DONE_INT. */ uint32_t sync_done_int_ena:1; - /** l1_icache0_pld_err_int_ena : HRO; bitpos: [7]; default: 0; - * The bit is used to enable interrupt of L1-ICache0 preload-operation error. - */ - uint32_t l1_icache0_pld_err_int_ena:1; - /** l1_icache1_pld_err_int_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable interrupt of L1-ICache1 preload-operation error. - */ - uint32_t l1_icache1_pld_err_int_ena:1; - /** l1_icache2_pld_err_int_ena : HRO; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_err_int_ena:1; - /** l1_icache3_pld_err_int_ena : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_err_int_ena:1; + uint32_t reserved_7:4; /** l1_cache_pld_err_int_ena : R/W; bitpos: [11]; default: 0; - * The bit is used to enable interrupt of L1-Cache preload-operation error. + * Write 1 to enable CACHE_PLD_ERR_INT. */ uint32_t l1_cache_pld_err_int_ena:1; uint32_t reserved_12:1; /** sync_err_int_ena : R/W; bitpos: [13]; default: 0; - * The bit is used to enable interrupt of Cache sync-operation error. + * Write 1 to enable CACHE_SYNC_ERR_INT. */ uint32_t sync_err_int_ena:1; uint32_t reserved_14:18; @@ -2977,62 +785,28 @@ typedef union { } cache_l1_cache_sync_preload_int_ena_reg_t; /** Type of l1_cache_sync_preload_int_clr register - * Sync Preload operation Interrupt clear register + * Sync and preloading operation interrupt clear register */ typedef union { struct { - /** l1_icache0_pld_done_int_clr : HRO; bitpos: [0]; default: 0; - * The bit is used to clear interrupt that occurs only when L1-ICache0 - * preload-operation is done. - */ - uint32_t l1_icache0_pld_done_int_clr:1; - /** l1_icache1_pld_done_int_clr : HRO; bitpos: [1]; default: 0; - * The bit is used to clear interrupt that occurs only when L1-ICache1 - * preload-operation is done. - */ - uint32_t l1_icache1_pld_done_int_clr:1; - /** l1_icache2_pld_done_int_clr : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_done_int_clr:1; - /** l1_icache3_pld_done_int_clr : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_done_int_clr:1; + uint32_t reserved_0:4; /** l1_cache_pld_done_int_clr : WT; bitpos: [4]; default: 0; - * The bit is used to clear interrupt that occurs only when L1-Cache preload-operation - * is done. + * Write 1 to clear L1_CACHE_PLD_DONE_INT. */ uint32_t l1_cache_pld_done_int_clr:1; uint32_t reserved_5:1; /** sync_done_int_clr : WT; bitpos: [6]; default: 0; - * The bit is used to clear interrupt that occurs only when Cache sync-operation is - * done. + * Write 1 to clear CACHE_SYNC_DONE_INT. */ uint32_t sync_done_int_clr:1; - /** l1_icache0_pld_err_int_clr : HRO; bitpos: [7]; default: 0; - * The bit is used to clear interrupt of L1-ICache0 preload-operation error. - */ - uint32_t l1_icache0_pld_err_int_clr:1; - /** l1_icache1_pld_err_int_clr : HRO; bitpos: [8]; default: 0; - * The bit is used to clear interrupt of L1-ICache1 preload-operation error. - */ - uint32_t l1_icache1_pld_err_int_clr:1; - /** l1_icache2_pld_err_int_clr : HRO; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_err_int_clr:1; - /** l1_icache3_pld_err_int_clr : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_err_int_clr:1; + uint32_t reserved_7:4; /** l1_cache_pld_err_int_clr : WT; bitpos: [11]; default: 0; - * The bit is used to clear interrupt of L1-Cache preload-operation error. + * Write 1 to clear L1_CACHE_PLD_ERR_INT. */ uint32_t l1_cache_pld_err_int_clr:1; uint32_t reserved_12:1; /** sync_err_int_clr : WT; bitpos: [13]; default: 0; - * The bit is used to clear interrupt of Cache sync-operation error. + * Write 1 to clear CACHE_SYNC_ERR_INT. */ uint32_t sync_err_int_clr:1; uint32_t reserved_14:18; @@ -3041,65 +815,28 @@ typedef union { } cache_l1_cache_sync_preload_int_clr_reg_t; /** Type of l1_cache_sync_preload_int_raw register - * Sync Preload operation Interrupt raw register + * Sync and preloading operation interrupt raw register */ typedef union { struct { - /** l1_icache0_pld_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is - * done. - */ - uint32_t l1_icache0_pld_done_int_raw:1; - /** l1_icache1_pld_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is - * done. - */ - uint32_t l1_icache1_pld_done_int_raw:1; - /** l1_icache2_pld_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_done_int_raw:1; - /** l1_icache3_pld_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_done_int_raw:1; + uint32_t reserved_0:4; /** l1_cache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit of the interrupt that occurs only when L1-Cache preload-operation is - * done. + * The raw interrupt status of L1_CACHE_PLD_DONE_INT. */ uint32_t l1_cache_pld_done_int_raw:1; uint32_t reserved_5:1; /** sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit of the interrupt that occurs only when Cache sync-operation is done. + * The raw interrupt status of CACHE_SYNC_DONE_INT. */ uint32_t sync_done_int_raw:1; - /** l1_icache0_pld_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation - * error occurs. - */ - uint32_t l1_icache0_pld_err_int_raw:1; - /** l1_icache1_pld_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation - * error occurs. - */ - uint32_t l1_icache1_pld_err_int_raw:1; - /** l1_icache2_pld_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_err_int_raw:1; - /** l1_icache3_pld_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_err_int_raw:1; + uint32_t reserved_7:4; /** l1_cache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * The raw bit of the interrupt that occurs only when L1-Cache preload-operation error - * occurs. + * The raw interrupt status of L1_CACHE_PLD_ERR_INT. */ uint32_t l1_cache_pld_err_int_raw:1; uint32_t reserved_12:1; /** sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * The raw bit of the interrupt that occurs only when Cache sync-operation error - * occurs. + * The raw interrupt status of CACHE_SYNC_ERR_INT. */ uint32_t sync_err_int_raw:1; uint32_t reserved_14:18; @@ -3108,62 +845,28 @@ typedef union { } cache_l1_cache_sync_preload_int_raw_reg_t; /** Type of l1_cache_sync_preload_int_st register - * L1-Cache Access Fail Interrupt status register + * Sync and preloading operation interrupt status register */ typedef union { struct { - /** l1_icache0_pld_done_int_st : HRO; bitpos: [0]; default: 0; - * The bit indicates the status of the interrupt that occurs only when L1-ICache0 - * preload-operation is done. - */ - uint32_t l1_icache0_pld_done_int_st:1; - /** l1_icache1_pld_done_int_st : HRO; bitpos: [1]; default: 0; - * The bit indicates the status of the interrupt that occurs only when L1-ICache1 - * preload-operation is done. - */ - uint32_t l1_icache1_pld_done_int_st:1; - /** l1_icache2_pld_done_int_st : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_done_int_st:1; - /** l1_icache3_pld_done_int_st : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_done_int_st:1; + uint32_t reserved_0:4; /** l1_cache_pld_done_int_st : RO; bitpos: [4]; default: 0; - * The bit indicates the status of the interrupt that occurs only when L1-Cache - * preload-operation is done. + * The masked interrupt status of L1_CACHE_PLD_DONE_INT. */ uint32_t l1_cache_pld_done_int_st:1; uint32_t reserved_5:1; /** sync_done_int_st : RO; bitpos: [6]; default: 0; - * The bit indicates the status of the interrupt that occurs only when Cache - * sync-operation is done. + * The masked interrupt status of CACHE_SYNC_DONE_INT. */ uint32_t sync_done_int_st:1; - /** l1_icache0_pld_err_int_st : HRO; bitpos: [7]; default: 0; - * The bit indicates the status of the interrupt of L1-ICache0 preload-operation error. - */ - uint32_t l1_icache0_pld_err_int_st:1; - /** l1_icache1_pld_err_int_st : HRO; bitpos: [8]; default: 0; - * The bit indicates the status of the interrupt of L1-ICache1 preload-operation error. - */ - uint32_t l1_icache1_pld_err_int_st:1; - /** l1_icache2_pld_err_int_st : HRO; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_err_int_st:1; - /** l1_icache3_pld_err_int_st : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_err_int_st:1; + uint32_t reserved_7:4; /** l1_cache_pld_err_int_st : RO; bitpos: [11]; default: 0; - * The bit indicates the status of the interrupt of L1-Cache preload-operation error. + * The masked interrupt status of L1_CACHE_PLD_ERR_INT. */ uint32_t l1_cache_pld_err_int_st:1; uint32_t reserved_12:1; /** sync_err_int_st : RO; bitpos: [13]; default: 0; - * The bit indicates the status of the interrupt of Cache sync-operation error. + * The masked interrupt status of CACHE_SYNC_ERR_INT. */ uint32_t sync_err_int_st:1; uint32_t reserved_14:18; @@ -3171,693 +874,53 @@ typedef union { uint32_t val; } cache_l1_cache_sync_preload_int_st_reg_t; -/** Type of l2_cache_acs_cnt_int_ena register - * Cache Access Counter Interrupt enable register - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** l2_ibus0_ovf_int_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L2-Cache due to bus0 accesses L2-Cache. - */ - uint32_t l2_ibus0_ovf_int_ena:1; - /** l2_ibus1_ovf_int_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L2-Cache due to bus1 accesses L2-Cache. - */ - uint32_t l2_ibus1_ovf_int_ena:1; - /** l2_ibus2_ovf_int_ena : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l2_ibus2_ovf_int_ena:1; - /** l2_ibus3_ovf_int_ena : HRO; bitpos: [11]; default: 0; - * Reserved - */ - uint32_t l2_ibus3_ovf_int_ena:1; - /** l2_dbus0_ovf_int_ena : HRO; bitpos: [12]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L2-Cache due to bus0 accesses L2-Cache. - */ - uint32_t l2_dbus0_ovf_int_ena:1; - /** l2_dbus1_ovf_int_ena : HRO; bitpos: [13]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L2-Cache due to bus1 accesses L2-Cache. - */ - uint32_t l2_dbus1_ovf_int_ena:1; - /** l2_dbus2_ovf_int_ena : HRO; bitpos: [14]; default: 0; - * Reserved - */ - uint32_t l2_dbus2_ovf_int_ena:1; - /** l2_dbus3_ovf_int_ena : HRO; bitpos: [15]; default: 0; - * Reserved - */ - uint32_t l2_dbus3_ovf_int_ena:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} cache_l2_cache_acs_cnt_int_ena_reg_t; -/** Type of l2_cache_acs_cnt_int_clr register - * Cache Access Counter Interrupt clear register - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** l2_ibus0_ovf_int_clr : HRO; bitpos: [8]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L2-Cache due - * to bus0 accesses L2-Cache. - */ - uint32_t l2_ibus0_ovf_int_clr:1; - /** l2_ibus1_ovf_int_clr : HRO; bitpos: [9]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L2-Cache due - * to bus1 accesses L2-Cache. - */ - uint32_t l2_ibus1_ovf_int_clr:1; - /** l2_ibus2_ovf_int_clr : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l2_ibus2_ovf_int_clr:1; - /** l2_ibus3_ovf_int_clr : HRO; bitpos: [11]; default: 0; - * Reserved - */ - uint32_t l2_ibus3_ovf_int_clr:1; - /** l2_dbus0_ovf_int_clr : HRO; bitpos: [12]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L2-Cache due - * to bus0 accesses L2-Cache. - */ - uint32_t l2_dbus0_ovf_int_clr:1; - /** l2_dbus1_ovf_int_clr : HRO; bitpos: [13]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L2-Cache due - * to bus1 accesses L2-Cache. - */ - uint32_t l2_dbus1_ovf_int_clr:1; - /** l2_dbus2_ovf_int_clr : HRO; bitpos: [14]; default: 0; - * Reserved - */ - uint32_t l2_dbus2_ovf_int_clr:1; - /** l2_dbus3_ovf_int_clr : HRO; bitpos: [15]; default: 0; - * Reserved - */ - uint32_t l2_dbus3_ovf_int_clr:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} cache_l2_cache_acs_cnt_int_clr_reg_t; - -/** Type of l2_cache_acs_cnt_int_raw register - * Cache Access Counter Interrupt raw register - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** l2_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus0 accesses L2-ICache0. - */ - uint32_t l2_ibus0_ovf_int_raw:1; - /** l2_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus1 accesses L2-ICache1. - */ - uint32_t l2_ibus1_ovf_int_raw:1; - /** l2_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus2 accesses L2-ICache2. - */ - uint32_t l2_ibus2_ovf_int_raw:1; - /** l2_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus3 accesses L2-ICache3. - */ - uint32_t l2_ibus3_ovf_int_raw:1; - /** l2_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus0 accesses L2-DCache. - */ - uint32_t l2_dbus0_ovf_int_raw:1; - /** l2_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus1 accesses L2-DCache. - */ - uint32_t l2_dbus1_ovf_int_raw:1; - /** l2_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus2 accesses L2-DCache. - */ - uint32_t l2_dbus2_ovf_int_raw:1; - /** l2_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus3 accesses L2-DCache. - */ - uint32_t l2_dbus3_ovf_int_raw:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} cache_l2_cache_acs_cnt_int_raw_reg_t; - -/** Type of l2_cache_acs_cnt_int_st register - * Cache Access Counter Interrupt status register - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** l2_ibus0_ovf_int_st : HRO; bitpos: [8]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L2-Cache due to bus0 accesses L2-Cache. - */ - uint32_t l2_ibus0_ovf_int_st:1; - /** l2_ibus1_ovf_int_st : HRO; bitpos: [9]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L2-Cache due to bus1 accesses L2-Cache. - */ - uint32_t l2_ibus1_ovf_int_st:1; - /** l2_ibus2_ovf_int_st : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l2_ibus2_ovf_int_st:1; - /** l2_ibus3_ovf_int_st : HRO; bitpos: [11]; default: 0; - * Reserved - */ - uint32_t l2_ibus3_ovf_int_st:1; - /** l2_dbus0_ovf_int_st : HRO; bitpos: [12]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L2-Cache due to bus0 accesses L2-Cache. - */ - uint32_t l2_dbus0_ovf_int_st:1; - /** l2_dbus1_ovf_int_st : HRO; bitpos: [13]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L2-Cache due to bus1 accesses L2-Cache. - */ - uint32_t l2_dbus1_ovf_int_st:1; - /** l2_dbus2_ovf_int_st : HRO; bitpos: [14]; default: 0; - * Reserved - */ - uint32_t l2_dbus2_ovf_int_st:1; - /** l2_dbus3_ovf_int_st : HRO; bitpos: [15]; default: 0; - * Reserved - */ - uint32_t l2_dbus3_ovf_int_st:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} cache_l2_cache_acs_cnt_int_st_reg_t; - -/** Type of l2_cache_acs_fail_int_ena register - * Cache Access Fail Interrupt enable register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_fail_int_ena : HRO; bitpos: [5]; default: 0; - * The bit is used to enable interrupt of access fail that occurs in L2-Cache due to - * l1 cache accesses L2-Cache. - */ - uint32_t l2_cache_fail_int_ena:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_acs_fail_int_ena_reg_t; - -/** Type of l2_cache_acs_fail_int_clr register - * L1-Cache Access Fail Interrupt clear register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_fail_int_clr : HRO; bitpos: [5]; default: 0; - * The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 - * cache accesses L2-Cache. - */ - uint32_t l2_cache_fail_int_clr:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_acs_fail_int_clr_reg_t; - -/** Type of l2_cache_acs_fail_int_raw register - * Cache Access Fail Interrupt raw register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_fail_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L2-Cache. - */ - uint32_t l2_cache_fail_int_raw:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_acs_fail_int_raw_reg_t; - -/** Type of l2_cache_acs_fail_int_st register - * Cache Access Fail Interrupt status register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_fail_int_st : HRO; bitpos: [5]; default: 0; - * The bit indicates the interrupt status of access fail that occurs in L2-Cache due - * to l1 cache accesses L2-Cache. - */ - uint32_t l2_cache_fail_int_st:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_acs_fail_int_st_reg_t; - -/** Type of l2_cache_sync_preload_int_ena register - * L1-Cache Access Fail Interrupt enable register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_pld_done_int_ena : HRO; bitpos: [5]; default: 0; - * The bit is used to enable interrupt of L2-Cache preload-operation done. - */ - uint32_t l2_cache_pld_done_int_ena:1; - uint32_t reserved_6:6; - /** l2_cache_pld_err_int_ena : HRO; bitpos: [12]; default: 0; - * The bit is used to enable interrupt of L2-Cache preload-operation error. - */ - uint32_t l2_cache_pld_err_int_ena:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} cache_l2_cache_sync_preload_int_ena_reg_t; - -/** Type of l2_cache_sync_preload_int_clr register - * Sync Preload operation Interrupt clear register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_pld_done_int_clr : HRO; bitpos: [5]; default: 0; - * The bit is used to clear interrupt that occurs only when L2-Cache preload-operation - * is done. - */ - uint32_t l2_cache_pld_done_int_clr:1; - uint32_t reserved_6:6; - /** l2_cache_pld_err_int_clr : HRO; bitpos: [12]; default: 0; - * The bit is used to clear interrupt of L2-Cache preload-operation error. - */ - uint32_t l2_cache_pld_err_int_clr:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} cache_l2_cache_sync_preload_int_clr_reg_t; - -/** Type of l2_cache_sync_preload_int_raw register - * Sync Preload operation Interrupt raw register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_pld_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit of the interrupt that occurs only when L2-Cache preload-operation is - * done. - */ - uint32_t l2_cache_pld_done_int_raw:1; - uint32_t reserved_6:6; - /** l2_cache_pld_err_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * The raw bit of the interrupt that occurs only when L2-Cache preload-operation error - * occurs. - */ - uint32_t l2_cache_pld_err_int_raw:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} cache_l2_cache_sync_preload_int_raw_reg_t; - -/** Type of l2_cache_sync_preload_int_st register - * L1-Cache Access Fail Interrupt status register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_pld_done_int_st : HRO; bitpos: [5]; default: 0; - * The bit indicates the status of the interrupt that occurs only when L2-Cache - * preload-operation is done. - */ - uint32_t l2_cache_pld_done_int_st:1; - uint32_t reserved_6:6; - /** l2_cache_pld_err_int_st : HRO; bitpos: [12]; default: 0; - * The bit indicates the status of the interrupt of L2-Cache preload-operation error. - */ - uint32_t l2_cache_pld_err_int_st:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} cache_l2_cache_sync_preload_int_st_reg_t; - - -/** Group: Cache Access Fail Configuration register */ -/** Type of l1_cache_acs_fail_ctrl register - * Cache Access Fail Configuration register - */ -typedef union { - struct { - /** l1_icache0_acs_fail_check_mode : HRO; bitpos: [0]; default: 0; - * The bit is used to configure l1 icache0 access fail check mode. 0: the access fail - * is not propagated to the request, 1: the access fail is propagated to the request - */ - uint32_t l1_icache0_acs_fail_check_mode:1; - /** l1_icache1_acs_fail_check_mode : HRO; bitpos: [1]; default: 0; - * The bit is used to configure l1 icache1 access fail check mode. 0: the access fail - * is not propagated to the request, 1: the access fail is propagated to the request - */ - uint32_t l1_icache1_acs_fail_check_mode:1; - /** l1_icache2_acs_fail_check_mode : HRO; bitpos: [2]; default: 0; - * The bit is used to configure l1 icache2 access fail check mode. 0: the access fail - * is not propagated to the request, 1: the access fail is propagated to the request - */ - uint32_t l1_icache2_acs_fail_check_mode:1; - /** l1_icache3_acs_fail_check_mode : HRO; bitpos: [3]; default: 0; - * The bit is used to configure l1 icache3 access fail check mode. 0: the access fail - * is not propagated to the request, 1: the access fail is propagated to the request - */ - uint32_t l1_icache3_acs_fail_check_mode:1; - /** l1_cache_acs_fail_check_mode : R/W; bitpos: [4]; default: 0; - * The bit is used to configure l1 cache access fail check mode. 0: the access fail is - * not propagated to the request, 1: the access fail is propagated to the request - */ - uint32_t l1_cache_acs_fail_check_mode:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} cache_l1_cache_acs_fail_ctrl_reg_t; - -/** Type of l2_cache_acs_fail_ctrl register - * Cache Access Fail Configuration register - */ -typedef union { - struct { - /** l2_cache_acs_fail_check_mode : HRO; bitpos: [0]; default: 0; - * The bit is used to configure l2 cache access fail check mode. 0: the access fail is - * not propagated to the request, 1: the access fail is propagated to the request - */ - uint32_t l2_cache_acs_fail_check_mode:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} cache_l2_cache_acs_fail_ctrl_reg_t; - - -/** Group: Access Statistics registers */ +/** Group: Access Statistics Registers */ /** Type of l1_cache_acs_cnt_ctrl register - * Cache Access Counter enable and clear register + * Cache access counter enable and clear register */ typedef union { struct { - /** l1_ibus0_cnt_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable ibus0 counter in L1-ICache0. - */ - uint32_t l1_ibus0_cnt_ena:1; - /** l1_ibus1_cnt_ena : HRO; bitpos: [1]; default: 0; - * The bit is used to enable ibus1 counter in L1-ICache1. - */ - uint32_t l1_ibus1_cnt_ena:1; - /** l1_ibus2_cnt_ena : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_ibus2_cnt_ena:1; - /** l1_ibus3_cnt_ena : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_ibus3_cnt_ena:1; + uint32_t reserved_0:4; /** l1_bus0_cnt_ena : R/W; bitpos: [4]; default: 0; - * The bit is used to enable dbus0 counter in L1-DCache. + * Configures whether to enable the BUS0 counters in the L1 cache. + * 0: Disable + * 1: Enable */ uint32_t l1_bus0_cnt_ena:1; /** l1_bus1_cnt_ena : R/W; bitpos: [5]; default: 0; - * The bit is used to enable dbus1 counter in L1-DCache. + * Configures whether to enable the BUS1 counters in the L1 cache. + * 0: Disable + * 1: Enable */ uint32_t l1_bus1_cnt_ena:1; - /** l1_dbus2_cnt_ena : HRO; bitpos: [6]; default: 0; - * Reserved - */ - uint32_t l1_dbus2_cnt_ena:1; - /** l1_dbus3_cnt_ena : HRO; bitpos: [7]; default: 0; - * Reserved - */ - uint32_t l1_dbus3_cnt_ena:1; - uint32_t reserved_8:8; - /** l1_ibus0_cnt_clr : WT; bitpos: [16]; default: 0; - * The bit is used to clear ibus0 counter in L1-ICache0. - */ - uint32_t l1_ibus0_cnt_clr:1; - /** l1_ibus1_cnt_clr : WT; bitpos: [17]; default: 0; - * The bit is used to clear ibus1 counter in L1-ICache1. - */ - uint32_t l1_ibus1_cnt_clr:1; - /** l1_ibus2_cnt_clr : WT; bitpos: [18]; default: 0; - * Reserved - */ - uint32_t l1_ibus2_cnt_clr:1; - /** l1_ibus3_cnt_clr : WT; bitpos: [19]; default: 0; - * Reserved - */ - uint32_t l1_ibus3_cnt_clr:1; + uint32_t reserved_6:14; /** l1_bus0_cnt_clr : WT; bitpos: [20]; default: 0; - * The bit is used to clear dbus0 counter in L1-DCache. + * Configures whether to clear the BUS0 counters in the L1 cache. + * 0: Not clear + * 1: Clear */ uint32_t l1_bus0_cnt_clr:1; /** l1_bus1_cnt_clr : WT; bitpos: [21]; default: 0; - * The bit is used to clear dbus1 counter in L1-DCache. + * Configures whether to clear the BUS1 counters in the L1 cache. + * 0: Not clear + * 1: Clear */ uint32_t l1_bus1_cnt_clr:1; - /** l1_dbus2_cnt_clr : HRO; bitpos: [22]; default: 0; - * Reserved - */ - uint32_t l1_dbus2_cnt_clr:1; - /** l1_dbus3_cnt_clr : HRO; bitpos: [23]; default: 0; - * Reserved - */ - uint32_t l1_dbus3_cnt_clr:1; - uint32_t reserved_24:8; + uint32_t reserved_22:10; }; uint32_t val; } cache_l1_cache_acs_cnt_ctrl_reg_t; -/** Type of l1_ibus0_acs_hit_cnt register - * L1-ICache bus0 Hit-Access Counter register - */ -typedef union { - struct { - /** l1_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_hit_cnt:32; - }; - uint32_t val; -} cache_l1_ibus0_acs_hit_cnt_reg_t; - -/** Type of l1_ibus0_acs_miss_cnt register - * L1-ICache bus0 Miss-Access Counter register - */ -typedef union { - struct { - /** l1_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_miss_cnt:32; - }; - uint32_t val; -} cache_l1_ibus0_acs_miss_cnt_reg_t; - -/** Type of l1_ibus0_acs_conflict_cnt register - * L1-ICache bus0 Conflict-Access Counter register - */ -typedef union { - struct { - /** l1_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_conflict_cnt:32; - }; - uint32_t val; -} cache_l1_ibus0_acs_conflict_cnt_reg_t; - -/** Type of l1_ibus0_acs_nxtlvl_rd_cnt register - * L1-ICache bus0 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l1_ibus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-ICache accesses L2-Cache due to - * bus0 accessing L1-ICache0. - */ - uint32_t l1_ibus0_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l1_ibus0_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l1_ibus1_acs_hit_cnt register - * L1-ICache bus1 Hit-Access Counter register - */ -typedef union { - struct { - /** l1_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_hit_cnt:32; - }; - uint32_t val; -} cache_l1_ibus1_acs_hit_cnt_reg_t; - -/** Type of l1_ibus1_acs_miss_cnt register - * L1-ICache bus1 Miss-Access Counter register - */ -typedef union { - struct { - /** l1_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_miss_cnt:32; - }; - uint32_t val; -} cache_l1_ibus1_acs_miss_cnt_reg_t; - -/** Type of l1_ibus1_acs_conflict_cnt register - * L1-ICache bus1 Conflict-Access Counter register - */ -typedef union { - struct { - /** l1_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_conflict_cnt:32; - }; - uint32_t val; -} cache_l1_ibus1_acs_conflict_cnt_reg_t; - -/** Type of l1_ibus1_acs_nxtlvl_rd_cnt register - * L1-ICache bus1 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l1_ibus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-ICache accesses L2-Cache due to - * bus1 accessing L1-ICache1. - */ - uint32_t l1_ibus1_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l1_ibus1_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l1_ibus2_acs_hit_cnt register - * L1-ICache bus2 Hit-Access Counter register - */ -typedef union { - struct { - /** l1_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus2 accesses L1-ICache2. - */ - uint32_t l1_ibus2_hit_cnt:32; - }; - uint32_t val; -} cache_l1_ibus2_acs_hit_cnt_reg_t; - -/** Type of l1_ibus2_acs_miss_cnt register - * L1-ICache bus2 Miss-Access Counter register - */ -typedef union { - struct { - /** l1_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus2 accesses L1-ICache2. - */ - uint32_t l1_ibus2_miss_cnt:32; - }; - uint32_t val; -} cache_l1_ibus2_acs_miss_cnt_reg_t; - -/** Type of l1_ibus2_acs_conflict_cnt register - * L1-ICache bus2 Conflict-Access Counter register - */ -typedef union { - struct { - /** l1_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus2 accesses L1-ICache2. - */ - uint32_t l1_ibus2_conflict_cnt:32; - }; - uint32_t val; -} cache_l1_ibus2_acs_conflict_cnt_reg_t; - -/** Type of l1_ibus2_acs_nxtlvl_rd_cnt register - * L1-ICache bus2 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l1_ibus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-ICache accesses L2-Cache due to - * bus2 accessing L1-ICache2. - */ - uint32_t l1_ibus2_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l1_ibus2_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l1_ibus3_acs_hit_cnt register - * L1-ICache bus3 Hit-Access Counter register - */ -typedef union { - struct { - /** l1_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus3 accesses L1-ICache3. - */ - uint32_t l1_ibus3_hit_cnt:32; - }; - uint32_t val; -} cache_l1_ibus3_acs_hit_cnt_reg_t; - -/** Type of l1_ibus3_acs_miss_cnt register - * L1-ICache bus3 Miss-Access Counter register - */ -typedef union { - struct { - /** l1_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus3 accesses L1-ICache3. - */ - uint32_t l1_ibus3_miss_cnt:32; - }; - uint32_t val; -} cache_l1_ibus3_acs_miss_cnt_reg_t; - -/** Type of l1_ibus3_acs_conflict_cnt register - * L1-ICache bus3 Conflict-Access Counter register - */ -typedef union { - struct { - /** l1_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus3 accesses L1-ICache3. - */ - uint32_t l1_ibus3_conflict_cnt:32; - }; - uint32_t val; -} cache_l1_ibus3_acs_conflict_cnt_reg_t; - -/** Type of l1_ibus3_acs_nxtlvl_rd_cnt register - * L1-ICache bus3 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l1_ibus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-ICache accesses L2-Cache due to - * bus3 accessing L1-ICache3. - */ - uint32_t l1_ibus3_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l1_ibus3_acs_nxtlvl_rd_cnt_reg_t; +/** Group: Access Statistics registers */ /** Type of l1_bus0_acs_hit_cnt register - * L1-Cache bus0 Hit-Access Counter register + * L1 cache BUS0 hit-access counter register */ typedef union { struct { /** l1_bus0_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus0 accesses L1-Cache. + * Represents the number of hits when BUS0 accesses the L1 cache. */ uint32_t l1_bus0_hit_cnt:32; }; @@ -3865,12 +928,12 @@ typedef union { } cache_l1_bus0_acs_hit_cnt_reg_t; /** Type of l1_bus0_acs_miss_cnt register - * L1-Cache bus0 Miss-Access Counter register + * L1 cache BUS0 missed-access counter register */ typedef union { struct { /** l1_bus0_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus0 accesses L1-Cache. + * Represents the number of misses when BUS0 accesses the L1 cache. */ uint32_t l1_bus0_miss_cnt:32; }; @@ -3878,52 +941,53 @@ typedef union { } cache_l1_bus0_acs_miss_cnt_reg_t; /** Type of l1_bus0_acs_conflict_cnt register - * L1-Cache bus0 Conflict-Access Counter register + * L1 cache BUS0 conflicting-access Counter register */ typedef union { struct { - /** l1_bus0_conflict_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus0 accesses L1-Cache. + /** l1_bus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * Represents the number of access conflicts when BUS0 accesses the L1 cache. */ - uint32_t l1_bus0_conflict_rd_cnt:32; + uint32_t l1_bus0_conflict_cnt:32; }; uint32_t val; } cache_l1_bus0_acs_conflict_cnt_reg_t; -/** Type of l1_dbus0_acs_nxtlvl_rd_cnt register - * L1-Cache bus0 Next-Level-Access Counter register +/** Type of l1_bus0_acs_nxtlvl_rd_cnt register + * L1 cache BUS0 reads the lower-level memory */ typedef union { struct { /** l1_bus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-Cache accesses L2-Cache due to - * bus0 accessing L1-Cache. + * Represents the number of times that the cache accesses its lower-level module due + * to BUS0's read access. */ uint32_t l1_bus0_nxtlvl_rd_cnt:32; }; uint32_t val; -} cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t; +} cache_l1_bus0_acs_nxtlvl_rd_cnt_reg_t; -/** Type of l1_dbus0_acs_nxtlvl_wr_cnt register - * L1-DCache bus0 WB-Access Counter register +/** Type of l1_bus0_acs_nxtlvl_wr_cnt register + * L1 cache BUS0 writes the lower-level memory */ typedef union { struct { /** l1_bus0_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when bus0 accesses L1-Cache. + * Represents the number of times that the cache accesses its lower-level module due + * to BUS0's write access. */ uint32_t l1_bus0_nxtlvl_wr_cnt:32; }; uint32_t val; -} cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t; +} cache_l1_bus0_acs_nxtlvl_wr_cnt_reg_t; /** Type of l1_bus1_acs_hit_cnt register - * L1-Cache bus1 Hit-Access Counter register + * L1 cache BUS1 hit-access counter register */ typedef union { struct { /** l1_bus1_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus1 accesses L1-Cache. + * Represents the number of hits when BUS1 accesses the L1 cache. */ uint32_t l1_bus1_hit_cnt:32; }; @@ -3931,12 +995,12 @@ typedef union { } cache_l1_bus1_acs_hit_cnt_reg_t; /** Type of l1_bus1_acs_miss_cnt register - * L1-Cache bus1 Miss-Access Counter register + * L1 cache BUS1 missed-access counter register */ typedef union { struct { /** l1_bus1_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus1 accesses L1-Cache. + * Represents the number of misses when BUS1 accesses the L1 cache. */ uint32_t l1_bus1_miss_cnt:32; }; @@ -3944,12 +1008,12 @@ typedef union { } cache_l1_bus1_acs_miss_cnt_reg_t; /** Type of l1_bus1_acs_conflict_cnt register - * L1-Cache bus1 Conflict-Access Counter register + * L1 cache BUS1 conflicting-access counter register */ typedef union { struct { /** l1_bus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus1 accesses L1-Cache. + * Represents the number of access conflicts when BUS1 accesses the L1 cache. */ uint32_t l1_bus1_conflict_cnt:32; }; @@ -3957,957 +1021,93 @@ typedef union { } cache_l1_bus1_acs_conflict_cnt_reg_t; /** Type of l1_dbus1_acs_nxtlvl_rd_cnt register - * L1-DCache bus1 Next-Level-Access Counter register + * L1 cache BUS1 reads the lower-level memory */ typedef union { struct { - /** l1_dbus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-Cache accesses L2-Cache due to - * bus1 accessing L1-Cache. + /** l1_bus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * Represents the number of times that the cache accesses its lower-level module due + * to BUS1's read access. */ - uint32_t l1_dbus1_nxtlvl_rd_cnt:32; + uint32_t l1_bus1_nxtlvl_rd_cnt:32; }; uint32_t val; } cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t; /** Type of l1_dbus1_acs_nxtlvl_wr_cnt register - * L1-DCache bus1 WB-Access Counter register + * L1 cache BUS1 writes the lower-level memory */ typedef union { struct { - /** l1_dbus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when bus1 accesses L1-Cache. + /** l1_bus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; + * Represents the number of times that the cache accesses its lower-level module due + * to BUS1's write access. */ - uint32_t l1_dbus1_nxtlvl_wr_cnt:32; + uint32_t l1_bus1_nxtlvl_wr_cnt:32; }; uint32_t val; } cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t; -/** Type of l1_dbus2_acs_hit_cnt register - * L1-DCache bus2 Hit-Access Counter register - */ -typedef union { - struct { - /** l1_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus2 accesses L1-DCache. - */ - uint32_t l1_dbus2_hit_cnt:32; - }; - uint32_t val; -} cache_l1_dbus2_acs_hit_cnt_reg_t; - -/** Type of l1_dbus2_acs_miss_cnt register - * L1-DCache bus2 Miss-Access Counter register - */ -typedef union { - struct { - /** l1_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus2 accesses L1-DCache. - */ - uint32_t l1_dbus2_miss_cnt:32; - }; - uint32_t val; -} cache_l1_dbus2_acs_miss_cnt_reg_t; - -/** Type of l1_dbus2_acs_conflict_cnt register - * L1-DCache bus2 Conflict-Access Counter register - */ -typedef union { - struct { - /** l1_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus2 accesses L1-DCache. - */ - uint32_t l1_dbus2_conflict_cnt:32; - }; - uint32_t val; -} cache_l1_dbus2_acs_conflict_cnt_reg_t; - -/** Type of l1_dbus2_acs_nxtlvl_rd_cnt register - * L1-DCache bus2 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l1_dbus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-Cache accesses L2-Cache due to - * bus2 accessing L1-Cache. - */ - uint32_t l1_dbus2_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l1_dbus2_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l1_dbus2_acs_nxtlvl_wr_cnt register - * L1-DCache bus2 WB-Access Counter register - */ -typedef union { - struct { - /** l1_dbus2_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when bus2 accesses L1-Cache. - */ - uint32_t l1_dbus2_nxtlvl_wr_cnt:32; - }; - uint32_t val; -} cache_l1_dbus2_acs_nxtlvl_wr_cnt_reg_t; - -/** Type of l1_dbus3_acs_hit_cnt register - * L1-DCache bus3 Hit-Access Counter register - */ -typedef union { - struct { - /** l1_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus3 accesses L1-DCache. - */ - uint32_t l1_dbus3_hit_cnt:32; - }; - uint32_t val; -} cache_l1_dbus3_acs_hit_cnt_reg_t; - -/** Type of l1_dbus3_acs_miss_cnt register - * L1-DCache bus3 Miss-Access Counter register - */ -typedef union { - struct { - /** l1_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus3 accesses L1-DCache. - */ - uint32_t l1_dbus3_miss_cnt:32; - }; - uint32_t val; -} cache_l1_dbus3_acs_miss_cnt_reg_t; - -/** Type of l1_dbus3_acs_conflict_cnt register - * L1-DCache bus3 Conflict-Access Counter register - */ -typedef union { - struct { - /** l1_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus3 accesses L1-DCache. - */ - uint32_t l1_dbus3_conflict_cnt:32; - }; - uint32_t val; -} cache_l1_dbus3_acs_conflict_cnt_reg_t; - -/** Type of l1_dbus3_acs_nxtlvl_rd_cnt register - * L1-DCache bus3 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l1_dbus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-Cache accesses L2-Cache due to - * bus3 accessing L1-Cache. - */ - uint32_t l1_dbus3_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l1_dbus3_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l1_dbus3_acs_nxtlvl_wr_cnt register - * L1-DCache bus3 WB-Access Counter register - */ -typedef union { - struct { - /** l1_dbus3_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when bus0 accesses L1-Cache. - */ - uint32_t l1_dbus3_nxtlvl_wr_cnt:32; - }; - uint32_t val; -} cache_l1_dbus3_acs_nxtlvl_wr_cnt_reg_t; - -/** Type of l2_cache_acs_cnt_ctrl register - * Cache Access Counter enable and clear register - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** l2_ibus0_cnt_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable ibus0 counter in L2-Cache. - */ - uint32_t l2_ibus0_cnt_ena:1; - /** l2_ibus1_cnt_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable ibus1 counter in L2-Cache. - */ - uint32_t l2_ibus1_cnt_ena:1; - /** l2_ibus2_cnt_ena : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l2_ibus2_cnt_ena:1; - /** l2_ibus3_cnt_ena : HRO; bitpos: [11]; default: 0; - * Reserved - */ - uint32_t l2_ibus3_cnt_ena:1; - /** l2_dbus0_cnt_ena : HRO; bitpos: [12]; default: 0; - * The bit is used to enable dbus0 counter in L2-Cache. - */ - uint32_t l2_dbus0_cnt_ena:1; - /** l2_dbus1_cnt_ena : HRO; bitpos: [13]; default: 0; - * The bit is used to enable dbus1 counter in L2-Cache. - */ - uint32_t l2_dbus1_cnt_ena:1; - /** l2_dbus2_cnt_ena : HRO; bitpos: [14]; default: 0; - * Reserved - */ - uint32_t l2_dbus2_cnt_ena:1; - /** l2_dbus3_cnt_ena : HRO; bitpos: [15]; default: 0; - * Reserved - */ - uint32_t l2_dbus3_cnt_ena:1; - uint32_t reserved_16:8; - /** l2_ibus0_cnt_clr : HRO; bitpos: [24]; default: 0; - * The bit is used to clear ibus0 counter in L2-Cache. - */ - uint32_t l2_ibus0_cnt_clr:1; - /** l2_ibus1_cnt_clr : HRO; bitpos: [25]; default: 0; - * The bit is used to clear ibus1 counter in L2-Cache. - */ - uint32_t l2_ibus1_cnt_clr:1; - /** l2_ibus2_cnt_clr : HRO; bitpos: [26]; default: 0; - * Reserved - */ - uint32_t l2_ibus2_cnt_clr:1; - /** l2_ibus3_cnt_clr : HRO; bitpos: [27]; default: 0; - * Reserved - */ - uint32_t l2_ibus3_cnt_clr:1; - /** l2_dbus0_cnt_clr : HRO; bitpos: [28]; default: 0; - * The bit is used to clear dbus0 counter in L2-Cache. - */ - uint32_t l2_dbus0_cnt_clr:1; - /** l2_dbus1_cnt_clr : HRO; bitpos: [29]; default: 0; - * The bit is used to clear dbus1 counter in L2-Cache. - */ - uint32_t l2_dbus1_cnt_clr:1; - /** l2_dbus2_cnt_clr : HRO; bitpos: [30]; default: 0; - * Reserved - */ - uint32_t l2_dbus2_cnt_clr:1; - /** l2_dbus3_cnt_clr : HRO; bitpos: [31]; default: 0; - * Reserved - */ - uint32_t l2_dbus3_cnt_clr:1; - }; - uint32_t val; -} cache_l2_cache_acs_cnt_ctrl_reg_t; - -/** Type of l2_ibus0_acs_hit_cnt register - * L2-Cache bus0 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-ICache0 accesses L2-Cache due to - * bus0 accessing L1-ICache0. - */ - uint32_t l2_ibus0_hit_cnt:32; - }; - uint32_t val; -} cache_l2_ibus0_acs_hit_cnt_reg_t; - -/** Type of l2_ibus0_acs_miss_cnt register - * L2-Cache bus0 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-ICache0 accesses L2-Cache due to - * bus0 accessing L1-ICache0. - */ - uint32_t l2_ibus0_miss_cnt:32; - }; - uint32_t val; -} cache_l2_ibus0_acs_miss_cnt_reg_t; - -/** Type of l2_ibus0_acs_conflict_cnt register - * L2-Cache bus0 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-ICache0 accesses - * L2-Cache due to bus0 accessing L1-ICache0. - */ - uint32_t l2_ibus0_conflict_cnt:32; - }; - uint32_t val; -} cache_l2_ibus0_acs_conflict_cnt_reg_t; - -/** Type of l2_ibus0_acs_nxtlvl_rd_cnt register - * L2-Cache bus0 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_ibus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0. - */ - uint32_t l2_ibus0_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l2_ibus0_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l2_ibus1_acs_hit_cnt register - * L2-Cache bus1 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-ICache1 accesses L2-Cache due to - * bus1 accessing L1-ICache1. - */ - uint32_t l2_ibus1_hit_cnt:32; - }; - uint32_t val; -} cache_l2_ibus1_acs_hit_cnt_reg_t; - -/** Type of l2_ibus1_acs_miss_cnt register - * L2-Cache bus1 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-ICache1 accesses L2-Cache due to - * bus1 accessing L1-ICache1. - */ - uint32_t l2_ibus1_miss_cnt:32; - }; - uint32_t val; -} cache_l2_ibus1_acs_miss_cnt_reg_t; - -/** Type of l2_ibus1_acs_conflict_cnt register - * L2-Cache bus1 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-ICache1 accesses - * L2-Cache due to bus1 accessing L1-ICache1. - */ - uint32_t l2_ibus1_conflict_cnt:32; - }; - uint32_t val; -} cache_l2_ibus1_acs_conflict_cnt_reg_t; - -/** Type of l2_ibus1_acs_nxtlvl_rd_cnt register - * L2-Cache bus1 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_ibus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1. - */ - uint32_t l2_ibus1_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l2_ibus1_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l2_ibus2_acs_hit_cnt register - * L2-Cache bus2 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-ICache2 accesses L2-Cache due to - * bus2 accessing L1-ICache2. - */ - uint32_t l2_ibus2_hit_cnt:32; - }; - uint32_t val; -} cache_l2_ibus2_acs_hit_cnt_reg_t; - -/** Type of l2_ibus2_acs_miss_cnt register - * L2-Cache bus2 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-ICache2 accesses L2-Cache due to - * bus2 accessing L1-ICache2. - */ - uint32_t l2_ibus2_miss_cnt:32; - }; - uint32_t val; -} cache_l2_ibus2_acs_miss_cnt_reg_t; - -/** Type of l2_ibus2_acs_conflict_cnt register - * L2-Cache bus2 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-ICache2 accesses - * L2-Cache due to bus2 accessing L1-ICache2. - */ - uint32_t l2_ibus2_conflict_cnt:32; - }; - uint32_t val; -} cache_l2_ibus2_acs_conflict_cnt_reg_t; - -/** Type of l2_ibus2_acs_nxtlvl_rd_cnt register - * L2-Cache bus2 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_ibus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2. - */ - uint32_t l2_ibus2_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l2_ibus2_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l2_ibus3_acs_hit_cnt register - * L2-Cache bus3 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-ICache3 accesses L2-Cache due to - * bus3 accessing L1-ICache3. - */ - uint32_t l2_ibus3_hit_cnt:32; - }; - uint32_t val; -} cache_l2_ibus3_acs_hit_cnt_reg_t; - -/** Type of l2_ibus3_acs_miss_cnt register - * L2-Cache bus3 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-ICache3 accesses L2-Cache due to - * bus3 accessing L1-ICache3. - */ - uint32_t l2_ibus3_miss_cnt:32; - }; - uint32_t val; -} cache_l2_ibus3_acs_miss_cnt_reg_t; - -/** Type of l2_ibus3_acs_conflict_cnt register - * L2-Cache bus3 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-ICache3 accesses - * L2-Cache due to bus3 accessing L1-ICache3. - */ - uint32_t l2_ibus3_conflict_cnt:32; - }; - uint32_t val; -} cache_l2_ibus3_acs_conflict_cnt_reg_t; - -/** Type of l2_ibus3_acs_nxtlvl_rd_cnt register - * L2-Cache bus3 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_ibus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3. - */ - uint32_t l2_ibus3_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l2_ibus3_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l2_dbus0_acs_hit_cnt register - * L2-Cache bus0 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-DCache accesses L2-Cache due to - * bus0 accessing L1-DCache. - */ - uint32_t l2_dbus0_hit_cnt:32; - }; - uint32_t val; -} cache_l2_dbus0_acs_hit_cnt_reg_t; - -/** Type of l2_dbus0_acs_miss_cnt register - * L2-Cache bus0 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-DCache accesses L2-Cache due to - * bus0 accessing L1-DCache. - */ - uint32_t l2_dbus0_miss_cnt:32; - }; - uint32_t val; -} cache_l2_dbus0_acs_miss_cnt_reg_t; - -/** Type of l2_dbus0_acs_conflict_cnt register - * L2-Cache bus0 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-DCache accesses - * L2-Cache due to bus0 accessing L1-DCache. - */ - uint32_t l2_dbus0_conflict_cnt:32; - }; - uint32_t val; -} cache_l2_dbus0_acs_conflict_cnt_reg_t; - -/** Type of l2_dbus0_acs_nxtlvl_rd_cnt register - * L2-Cache bus0 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_dbus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache. - */ - uint32_t l2_dbus0_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l2_dbus0_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l2_dbus0_acs_nxtlvl_wr_cnt register - * L2-Cache bus0 WB-Access Counter register - */ -typedef union { - struct { - /** l2_dbus0_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when L1-DCache accesses L2-Cache due - * to bus0 accessing L1-DCache. - */ - uint32_t l2_dbus0_nxtlvl_wr_cnt:32; - }; - uint32_t val; -} cache_l2_dbus0_acs_nxtlvl_wr_cnt_reg_t; - -/** Type of l2_dbus1_acs_hit_cnt register - * L2-Cache bus1 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-DCache accesses L2-Cache due to - * bus1 accessing L1-DCache. - */ - uint32_t l2_dbus1_hit_cnt:32; - }; - uint32_t val; -} cache_l2_dbus1_acs_hit_cnt_reg_t; - -/** Type of l2_dbus1_acs_miss_cnt register - * L2-Cache bus1 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-DCache accesses L2-Cache due to - * bus1 accessing L1-DCache. - */ - uint32_t l2_dbus1_miss_cnt:32; - }; - uint32_t val; -} cache_l2_dbus1_acs_miss_cnt_reg_t; - -/** Type of l2_dbus1_acs_conflict_cnt register - * L2-Cache bus1 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-DCache accesses - * L2-Cache due to bus1 accessing L1-DCache. - */ - uint32_t l2_dbus1_conflict_cnt:32; - }; - uint32_t val; -} cache_l2_dbus1_acs_conflict_cnt_reg_t; - -/** Type of l2_dbus1_acs_nxtlvl_rd_cnt register - * L2-Cache bus1 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_dbus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache. - */ - uint32_t l2_dbus1_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l2_dbus1_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l2_dbus1_acs_nxtlvl_wr_cnt register - * L2-Cache bus1 WB-Access Counter register - */ -typedef union { - struct { - /** l2_dbus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when L1-DCache accesses L2-Cache due - * to bus1 accessing L1-DCache. - */ - uint32_t l2_dbus1_nxtlvl_wr_cnt:32; - }; - uint32_t val; -} cache_l2_dbus1_acs_nxtlvl_wr_cnt_reg_t; - -/** Type of l2_dbus2_acs_hit_cnt register - * L2-Cache bus2 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-DCache accesses L2-Cache due to - * bus2 accessing L1-DCache. - */ - uint32_t l2_dbus2_hit_cnt:32; - }; - uint32_t val; -} cache_l2_dbus2_acs_hit_cnt_reg_t; - -/** Type of l2_dbus2_acs_miss_cnt register - * L2-Cache bus2 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-DCache accesses L2-Cache due to - * bus2 accessing L1-DCache. - */ - uint32_t l2_dbus2_miss_cnt:32; - }; - uint32_t val; -} cache_l2_dbus2_acs_miss_cnt_reg_t; - -/** Type of l2_dbus2_acs_conflict_cnt register - * L2-Cache bus2 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-DCache accesses - * L2-Cache due to bus2 accessing L1-DCache. - */ - uint32_t l2_dbus2_conflict_cnt:32; - }; - uint32_t val; -} cache_l2_dbus2_acs_conflict_cnt_reg_t; - -/** Type of l2_dbus2_acs_nxtlvl_rd_cnt register - * L2-Cache bus2 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_dbus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache. - */ - uint32_t l2_dbus2_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l2_dbus2_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l2_dbus2_acs_nxtlvl_wr_cnt register - * L2-Cache bus2 WB-Access Counter register - */ -typedef union { - struct { - /** l2_dbus2_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when L1-DCache accesses L2-Cache due - * to bus2 accessing L1-DCache. - */ - uint32_t l2_dbus2_nxtlvl_wr_cnt:32; - }; - uint32_t val; -} cache_l2_dbus2_acs_nxtlvl_wr_cnt_reg_t; - -/** Type of l2_dbus3_acs_hit_cnt register - * L2-Cache bus3 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-DCache accesses L2-Cache due to - * bus3 accessing L1-DCache. - */ - uint32_t l2_dbus3_hit_cnt:32; - }; - uint32_t val; -} cache_l2_dbus3_acs_hit_cnt_reg_t; - -/** Type of l2_dbus3_acs_miss_cnt register - * L2-Cache bus3 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-DCache accesses L2-Cache due to - * bus3 accessing L1-DCache. - */ - uint32_t l2_dbus3_miss_cnt:32; - }; - uint32_t val; -} cache_l2_dbus3_acs_miss_cnt_reg_t; - -/** Type of l2_dbus3_acs_conflict_cnt register - * L2-Cache bus3 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-DCache accesses - * L2-Cache due to bus3 accessing L1-DCache. - */ - uint32_t l2_dbus3_conflict_cnt:32; - }; - uint32_t val; -} cache_l2_dbus3_acs_conflict_cnt_reg_t; - -/** Type of l2_dbus3_acs_nxtlvl_rd_cnt register - * L2-Cache bus3 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_dbus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache. - */ - uint32_t l2_dbus3_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l2_dbus3_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l2_dbus3_acs_nxtlvl_wr_cnt register - * L2-Cache bus3 WB-Access Counter register - */ -typedef union { - struct { - /** l2_dbus3_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when L1-DCache accesses L2-Cache due - * to bus3 accessing L1-DCache. - */ - uint32_t l2_dbus3_nxtlvl_wr_cnt:32; - }; - uint32_t val; -} cache_l2_dbus3_acs_nxtlvl_wr_cnt_reg_t; - /** Group: Access Fail Debug registers */ -/** Type of l1_icache0_acs_fail_id_attr register - * L1-ICache0 Access Fail ID/attribution information register - */ -typedef union { - struct { - /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache0 accesses L1-ICache. - */ - uint32_t l1_icache0_fail_id:16; - /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache0 accesses L1-ICache. - */ - uint32_t l1_icache0_fail_attr:16; - }; - uint32_t val; -} cache_l1_icache0_acs_fail_id_attr_reg_t; - -/** Type of l1_icache0_acs_fail_addr register - * L1-ICache0 Access Fail Address information register - */ -typedef union { - struct { - /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache0 accesses L1-ICache. - */ - uint32_t l1_icache0_fail_addr:32; - }; - uint32_t val; -} cache_l1_icache0_acs_fail_addr_reg_t; - -/** Type of l1_icache1_acs_fail_id_attr register - * L1-ICache0 Access Fail ID/attribution information register - */ -typedef union { - struct { - /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache1 accesses L1-ICache. - */ - uint32_t l1_icache1_fail_id:16; - /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache1 accesses L1-ICache. - */ - uint32_t l1_icache1_fail_attr:16; - }; - uint32_t val; -} cache_l1_icache1_acs_fail_id_attr_reg_t; - -/** Type of l1_icache1_acs_fail_addr register - * L1-ICache0 Access Fail Address information register - */ -typedef union { - struct { - /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache1 accesses L1-ICache. - */ - uint32_t l1_icache1_fail_addr:32; - }; - uint32_t val; -} cache_l1_icache1_acs_fail_addr_reg_t; - -/** Type of l1_icache2_acs_fail_id_attr register - * L1-ICache0 Access Fail ID/attribution information register - */ -typedef union { - struct { - /** l1_icache2_fail_id : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache2 accesses L1-ICache. - */ - uint32_t l1_icache2_fail_id:16; - /** l1_icache2_fail_attr : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache2 accesses L1-ICache. - */ - uint32_t l1_icache2_fail_attr:16; - }; - uint32_t val; -} cache_l1_icache2_acs_fail_id_attr_reg_t; - -/** Type of l1_icache2_acs_fail_addr register - * L1-ICache0 Access Fail Address information register - */ -typedef union { - struct { - /** l1_icache2_fail_addr : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache2 accesses L1-ICache. - */ - uint32_t l1_icache2_fail_addr:32; - }; - uint32_t val; -} cache_l1_icache2_acs_fail_addr_reg_t; - -/** Type of l1_icache3_acs_fail_id_attr register - * L1-ICache0 Access Fail ID/attribution information register - */ -typedef union { - struct { - /** l1_icache3_fail_id : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache3 accesses L1-ICache. - */ - uint32_t l1_icache3_fail_id:16; - /** l1_icache3_fail_attr : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache3 accesses L1-ICache. - */ - uint32_t l1_icache3_fail_attr:16; - }; - uint32_t val; -} cache_l1_icache3_acs_fail_id_attr_reg_t; - -/** Type of l1_icache3_acs_fail_addr register - * L1-ICache0 Access Fail Address information register - */ -typedef union { - struct { - /** l1_icache3_fail_addr : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache3 accesses L1-ICache. - */ - uint32_t l1_icache3_fail_addr:32; - }; - uint32_t val; -} cache_l1_icache3_acs_fail_addr_reg_t; - -/** Type of l1_dcache_acs_fail_id_attr register - * L1-Cache Access Fail ID/attribution information register +/** Type of l1_cache_acs_fail_id_attr register + * L1 cache access failed ID and attribution recording register */ typedef union { struct { /** l1_cache_fail_id : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache accesses L1-Cache. + * Represents the ID of the failed access to the L1 cache. + * Bit 4: BUS0 + * Bit 5: BUS1 + * Others: reserved */ uint32_t l1_cache_fail_id:16; /** l1_cache_fail_attr : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache accesses L1-Cache. + * Represents the attribute of the failed access to the L1 cache. + * Bit 0: Fetching instructions + * Bit 1: Reading data + * Bit 7: non-cacheable + * Others: reserved */ uint32_t l1_cache_fail_attr:16; }; uint32_t val; -} cache_l1_dcache_acs_fail_id_attr_reg_t; +} cache_l1_cache_acs_fail_id_attr_reg_t; -/** Type of l1_dcache_acs_fail_addr register - * L1-Cache Access Fail Address information register +/** Type of l1_cache_acs_fail_addr register + * L1 cache access failed address information register */ typedef union { struct { /** l1_cache_fail_addr : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache accesses L1-Cache. + * Represents the address of the failed access to the L1 cache. */ uint32_t l1_cache_fail_addr:32; }; uint32_t val; -} cache_l1_dcache_acs_fail_addr_reg_t; - -/** Type of l2_cache_acs_fail_id_attr register - * L2-Cache Access Fail ID/attribution information register - */ -typedef union { - struct { - /** l2_cache_fail_id : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when L1-Cache accesses L2-Cache. - */ - uint32_t l2_cache_fail_id:16; - /** l2_cache_fail_attr : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when L1-Cache accesses L2-Cache - * due to cache accessing L1-Cache. - */ - uint32_t l2_cache_fail_attr:16; - }; - uint32_t val; -} cache_l2_cache_acs_fail_id_attr_reg_t; - -/** Type of l2_cache_acs_fail_addr register - * L2-Cache Access Fail Address information register - */ -typedef union { - struct { - /** l2_cache_fail_addr : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when L1-Cache accesses L2-Cache. - */ - uint32_t l2_cache_fail_addr:32; - }; - uint32_t val; -} cache_l2_cache_acs_fail_addr_reg_t; +} cache_l1_cache_acs_fail_addr_reg_t; -/** Group: Operation Exception registers */ +/** Group: Access Fail Debug Registers */ /** Type of l1_cache_sync_preload_exception register - * Cache Sync/Preload Operation exception register + * Cache sync and preloading operation exception register */ typedef union { struct { - /** l1_icache0_pld_err_code : RO; bitpos: [1:0]; default: 0; - * The value 2 is Only available which means preload size is error in L1-ICache0. - */ - uint32_t l1_icache0_pld_err_code:2; - /** l1_icache1_pld_err_code : RO; bitpos: [3:2]; default: 0; - * The value 2 is Only available which means preload size is error in L1-ICache1. - */ - uint32_t l1_icache1_pld_err_code:2; - /** l1_icache2_pld_err_code : RO; bitpos: [5:4]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_err_code:2; - /** l1_icache3_pld_err_code : RO; bitpos: [7:6]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_err_code:2; + uint32_t reserved_0:8; /** l1_cache_pld_err_code : RO; bitpos: [9:8]; default: 0; - * The value 2 is Only available which means preload size is error in L1-Cache. + * Represents the error code for the failed preloading operation. + * 2: The preloading size in the L1 cache is wrong + * Other values: reserved */ uint32_t l1_cache_pld_err_code:2; uint32_t reserved_10:2; /** sync_err_code : RO; bitpos: [13:12]; default: 0; - * The values 0-2 are available which means sync map, command conflict and size are - * error in Cache System. + * Represents the error code for the failed synchronization operation. + * 0: Incorrect synchronization map + * 1: Synchronization command conflict + * 2: Incorrect synchronization size + * 3: Reserved */ uint32_t sync_err_code:2; uint32_t reserved_14:18; @@ -4915,49 +1115,20 @@ typedef union { uint32_t val; } cache_l1_cache_sync_preload_exception_reg_t; -/** Type of l2_cache_sync_preload_exception register - * Cache Sync/Preload Operation exception register - */ -typedef union { - struct { - uint32_t reserved_0:10; - /** l2_cache_pld_err_code : RO; bitpos: [11:10]; default: 0; - * The value 2 is Only available which means preload size is error in L2-Cache. - */ - uint32_t l2_cache_pld_err_code:2; - uint32_t reserved_12:20; - }; - uint32_t val; -} cache_l2_cache_sync_preload_exception_reg_t; - -/** Group: Sync Reset control and configuration registers */ +/** Group: Sync Reset Control and Configuration Registers */ /** Type of l1_cache_sync_rst_ctrl register - * Cache Sync Reset control register + * Cache sync reset control register */ typedef union { struct { - /** l1_icache0_sync_rst : HRO; bitpos: [0]; default: 0; - * set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only - * be used to initialize sync-logic when some fatal error of sync-logic occurs. - */ - uint32_t l1_icache0_sync_rst:1; - /** l1_icache1_sync_rst : HRO; bitpos: [1]; default: 0; - * set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only - * be used to initialize sync-logic when some fatal error of sync-logic occurs. - */ - uint32_t l1_icache1_sync_rst:1; - /** l1_icache2_sync_rst : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_sync_rst:1; - /** l1_icache3_sync_rst : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_sync_rst:1; + uint32_t reserved_0:4; /** l1_cache_sync_rst : R/W; bitpos: [4]; default: 0; - * set this bit to reset sync-logic inside L1-Cache. Recommend that this should only - * be used to initialize sync-logic when some fatal error of sync-logic occurs. + * Configures whether to reset the synchronization logic inside the L1 cache. + * 0: Not reset + * 1: Reset + * It is recommended that this field should only be used when a fatal error of the + * synchronization logic occurs. */ uint32_t l1_cache_sync_rst:1; uint32_t reserved_5:27; @@ -4965,53 +1136,18 @@ typedef union { uint32_t val; } cache_l1_cache_sync_rst_ctrl_reg_t; -/** Type of l2_cache_sync_rst_ctrl register - * Cache Sync Reset control register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_sync_rst : HRO; bitpos: [5]; default: 0; - * set this bit to reset sync-logic inside L2-Cache. Recommend that this should only - * be used to initialize sync-logic when some fatal error of sync-logic occurs. - */ - uint32_t l2_cache_sync_rst:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_sync_rst_ctrl_reg_t; - - -/** Group: Preload Reset control and configuration registers */ /** Type of l1_cache_preload_rst_ctrl register - * Cache Preload Reset control register + * Cache preloading reset control register */ typedef union { struct { - /** l1_icache0_pld_rst : HRO; bitpos: [0]; default: 0; - * set this bit to reset preload-logic inside L1-ICache0. Recommend that this should - * only be used to initialize preload-logic when some fatal error of preload-logic - * occurs. - */ - uint32_t l1_icache0_pld_rst:1; - /** l1_icache1_pld_rst : HRO; bitpos: [1]; default: 0; - * set this bit to reset preload-logic inside L1-ICache1. Recommend that this should - * only be used to initialize preload-logic when some fatal error of preload-logic - * occurs. - */ - uint32_t l1_icache1_pld_rst:1; - /** l1_icache2_pld_rst : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_rst:1; - /** l1_icache3_pld_rst : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_rst:1; + uint32_t reserved_0:4; /** l1_cache_pld_rst : R/W; bitpos: [4]; default: 0; - * set this bit to reset preload-logic inside L1-Cache. Recommend that this should - * only be used to initialize preload-logic when some fatal error of preload-logic - * occurs. + * Configures whether to reset the preloading logic inside the L1 cache. + * 0: Not reset + * 1: Reset + * It is recommended that this field should only be used when a fatal error of the + * preloading logic occurs. */ uint32_t l1_cache_pld_rst:1; uint32_t reserved_5:27; @@ -5019,54 +1155,18 @@ typedef union { uint32_t val; } cache_l1_cache_preload_rst_ctrl_reg_t; -/** Type of l2_cache_preload_rst_ctrl register - * Cache Preload Reset control register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_pld_rst : HRO; bitpos: [5]; default: 0; - * set this bit to reset preload-logic inside L2-Cache. Recommend that this should - * only be used to initialize preload-logic when some fatal error of preload-logic - * occurs. - */ - uint32_t l2_cache_pld_rst:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_preload_rst_ctrl_reg_t; - -/** Group: Autoload buffer clear control and configuration registers */ +/** Group: Autoloading Buffer Clear Control and Configuration Registers */ /** Type of l1_cache_autoload_buf_clr_ctrl register - * Cache Autoload buffer clear control register + * Cache autoloading buffer clear control register */ typedef union { struct { - /** l1_icache0_ald_buf_clr : HRO; bitpos: [0]; default: 0; - * set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, - * autoload will not work in L1-ICache0. This bit should not be active when autoload - * works in L1-ICache0. - */ - uint32_t l1_icache0_ald_buf_clr:1; - /** l1_icache1_ald_buf_clr : HRO; bitpos: [1]; default: 0; - * set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, - * autoload will not work in L1-ICache1. This bit should not be active when autoload - * works in L1-ICache1. - */ - uint32_t l1_icache1_ald_buf_clr:1; - /** l1_icache2_ald_buf_clr : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_ald_buf_clr:1; - /** l1_icache3_ald_buf_clr : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_ald_buf_clr:1; + uint32_t reserved_0:4; /** l1_cache_ald_buf_clr : R/W; bitpos: [4]; default: 0; - * set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, - * autoload will not work in L1-Cache. This bit should not be active when autoload - * works in L1-Cache. + * Configures whether to clear the autoloading buffer inside the L1 cache. + * 0: Not clear the buffer. Recommended when autoloading of L1 cache is used. + * 1: Clear the buffer. Once set, autoloading of L1 cache will stop working. */ uint32_t l1_cache_ald_buf_clr:1; uint32_t reserved_5:27; @@ -5074,126 +1174,29 @@ typedef union { uint32_t val; } cache_l1_cache_autoload_buf_clr_ctrl_reg_t; -/** Type of l2_cache_autoload_buf_clr_ctrl register - * Cache Autoload buffer clear control register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_ald_buf_clr : HRO; bitpos: [5]; default: 0; - * set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, - * autoload will not work in L2-Cache. This bit should not be active when autoload - * works in L2-Cache. - */ - uint32_t l2_cache_ald_buf_clr:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_autoload_buf_clr_ctrl_reg_t; - -/** Group: Unallocate request buffer clear registers */ -/** Type of l1_unallocate_buffer_clear register - * Unallocate request buffer clear registers - */ -typedef union { - struct { - /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0; - * The bit is used to clear the unallocate request buffer of l1 icache0 where the - * unallocate request is responded but not completed. - */ - uint32_t l1_icache0_unalloc_clr:1; - /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0; - * The bit is used to clear the unallocate request buffer of l1 icache1 where the - * unallocate request is responded but not completed. - */ - uint32_t l1_icache1_unalloc_clr:1; - /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_unalloc_clr:1; - /** l1_icache3_unalloc_clr : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_unalloc_clr:1; - /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0; - * The bit is used to clear the unallocate request buffer of l1 cache where the - * unallocate request is responded but not completed. - */ - uint32_t l1_cache_unalloc_clr:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} cache_l1_unallocate_buffer_clear_reg_t; - -/** Type of l2_unallocate_buffer_clear register - * Unallocate request buffer clear registers - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0; - * The bit is used to clear the unallocate request buffer of l2 icache where the - * unallocate request is responded but not completed. - */ - uint32_t l2_cache_unalloc_clr:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_unallocate_buffer_clear_reg_t; - - -/** Group: Tag and Data Memory Access Control and configuration register */ +/** Group: Tag and Data Memory Access Control and Configuration Registers */ /** Type of l1_cache_object_ctrl register - * Cache Tag and Data memory Object control register + * Cache tag and data memory object control register */ typedef union { struct { - /** l1_icache0_tag_object : R/W; bitpos: [0]; default: 0; - * Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with - * the others fields inside this register. - */ - uint32_t l1_icache0_tag_object:1; - /** l1_icache1_tag_object : R/W; bitpos: [1]; default: 0; - * Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with - * the others fields inside this register. - */ - uint32_t l1_icache1_tag_object:1; - /** l1_icache2_tag_object : R/W; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_tag_object:1; - /** l1_icache3_tag_object : R/W; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_tag_object:1; + uint32_t reserved_0:4; /** l1_cache_tag_object : R/W; bitpos: [4]; default: 0; - * Set this bit to set L1-Cache tag memory as object. This bit should be onehot with - * the others fields inside this register. + * Configure whether to set the L1 cache tag memory as an object. + * 0: Not set + * 1: Set + * This register uses "one-hot encoding," which means that at any time, only one field + * can be valid in conjunction with other fields. */ uint32_t l1_cache_tag_object:1; - uint32_t reserved_5:1; - /** l1_icache0_mem_object : R/W; bitpos: [6]; default: 0; - * Set this bit to set L1-ICache0 data memory as object. This bit should be onehot - * with the others fields inside this register. - */ - uint32_t l1_icache0_mem_object:1; - /** l1_icache1_mem_object : R/W; bitpos: [7]; default: 0; - * Set this bit to set L1-ICache1 data memory as object. This bit should be onehot - * with the others fields inside this register. - */ - uint32_t l1_icache1_mem_object:1; - /** l1_icache2_mem_object : R/W; bitpos: [8]; default: 0; - * Reserved - */ - uint32_t l1_icache2_mem_object:1; - /** l1_icache3_mem_object : R/W; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache3_mem_object:1; + uint32_t reserved_5:5; /** l1_cache_mem_object : R/W; bitpos: [10]; default: 0; - * Set this bit to set L1-Cache data memory as object. This bit should be onehot with - * the others fields inside this register. + * Configure whether to set the L1 cache data memory as an object. + * 0: Not set + * 1: Set + * This register uses "one-hot encoding," which means that at any time, only one field + * can be valid in conjunction with other fields. */ uint32_t l1_cache_mem_object:1; uint32_t reserved_11:21; @@ -5202,13 +1205,16 @@ typedef union { } cache_l1_cache_object_ctrl_reg_t; /** Type of l1_cache_way_object register - * Cache Tag and Data memory way register + * Cache tag and data memory way register */ typedef union { struct { /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0; - * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: - * way1, 2: way2, 3: way3, ?, 7: way7. + * Configures which way in the tag memory or the data memory to access. + * 0: Way 0 + * 1: Way 1 + * 2: Way 2 + * 3: Way 3 */ uint32_t l1_cache_way_object:3; uint32_t reserved_3:29; @@ -5216,178 +1222,34 @@ typedef union { uint32_t val; } cache_l1_cache_way_object_reg_t; -/** Type of l1_cache_addr register - * Cache address register - */ -typedef union { - struct { - /** l1_cache_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits stores the address which will decide where inside the specified tag - * memory object will be accessed. - */ - uint32_t l1_cache_addr:32; - }; - uint32_t val; -} cache_l1_cache_addr_reg_t; - /** Type of l1_cache_debug_bus register - * Cache Tag/data memory content register + * Cache tag and data memory content register */ typedef union { struct { /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 612; - * This is a constant place where we can write data to or read data from the tag/data - * memory on the specified cache. + * Configures the data to write to or the data to read from the tag memory or the data + * memory. */ uint32_t l1_cache_debug_bus:32; }; uint32_t val; } cache_l1_cache_debug_bus_reg_t; -/** Type of l2_cache_object_ctrl register - * Cache Tag and Data memory Object control register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_tag_object : HRO; bitpos: [5]; default: 0; - * Set this bit to set L2-Cache tag memory as object. This bit should be onehot with - * the others fields inside this register. - */ - uint32_t l2_cache_tag_object:1; - uint32_t reserved_6:5; - /** l2_cache_mem_object : HRO; bitpos: [11]; default: 0; - * Set this bit to set L2-Cache data memory as object. This bit should be onehot with - * the others fields inside this register. - */ - uint32_t l2_cache_mem_object:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} cache_l2_cache_object_ctrl_reg_t; -/** Type of l2_cache_way_object register - * Cache Tag and Data memory way register - */ -typedef union { - struct { - /** l2_cache_way_object : HRO; bitpos: [2:0]; default: 0; - * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: - * way1, 2: way2, 3: way3, ?, 7: way7. - */ - uint32_t l2_cache_way_object:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} cache_l2_cache_way_object_reg_t; - -/** Type of l2_cache_addr register +/** Group: Tag and Data Memory Access Control and configuration register */ +/** Type of l1_cache_addr register * Cache address register */ typedef union { struct { - /** l2_cache_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits stores the address which will decide where inside the specified tag - * memory object will be accessed. + /** l1_cache_addr : R/W; bitpos: [31:0]; default: 0; + * Configures the virtual address inside the tag memory or data memory to access. */ - uint32_t l2_cache_addr:32; + uint32_t l1_cache_addr:32; }; uint32_t val; -} cache_l2_cache_addr_reg_t; - -/** Type of l2_cache_debug_bus register - * Cache Tag/data memory content register - */ -typedef union { - struct { - /** l2_cache_debug_bus : R/W; bitpos: [31:0]; default: 964; - * This is a constant place where we can write data to or read data from the tag/data - * memory on the specified cache. - */ - uint32_t l2_cache_debug_bus:32; - }; - uint32_t val; -} cache_l2_cache_debug_bus_reg_t; - - -/** Group: Split L1 and L2 registers */ -/** Type of level_split0 register - * USED TO SPLIT L1 CACHE AND L2 CACHE - */ -typedef union { - struct { - /** level_split0 : HRO; bitpos: [31:0]; default: 616; - * Reserved - */ - uint32_t level_split0:32; - }; - uint32_t val; -} cache_level_split0_reg_t; - -/** Type of level_split1 register - * USED TO SPLIT L1 CACHE AND L2 CACHE - */ -typedef union { - struct { - /** level_split1 : HRO; bitpos: [31:0]; default: 968; - * Reserved - */ - uint32_t level_split1:32; - }; - uint32_t val; -} cache_level_split1_reg_t; - - -/** Group: L2 cache access attribute control register */ -/** Type of l2_cache_access_attr_ctrl register - * L2 cache access attribute control register - */ -typedef union { - struct { - /** l2_cache_access_force_cc : HRO; bitpos: [0]; default: 1; - * Set this bit to force the request to l2 cache with cacheable attribute, otherwise, - * the attribute is propagated from L1 cache or CPU, it could be one of cacheable and - * non-cacheable. - */ - uint32_t l2_cache_access_force_cc:1; - /** l2_cache_access_force_wb : HRO; bitpos: [1]; default: 1; - * Set this bit to force the request to l2 cache with write-back attribute, otherwise, - * the attribute is propagated from L1 cache or CPU, it could be one of write-back and - * write-through. - */ - uint32_t l2_cache_access_force_wb:1; - /** l2_cache_access_force_wma : HRO; bitpos: [2]; default: 1; - * Set this bit to force the request to l2 cache with write-miss-allocate attribute, - * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of - * write-miss-allocate and write-miss-no-allocate. - */ - uint32_t l2_cache_access_force_wma:1; - /** l2_cache_access_force_rma : HRO; bitpos: [3]; default: 1; - * Set this bit to force the request to l2 cache with read-miss-allocate attribute, - * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of - * read-miss-allocate and read-miss-no-allocate. - */ - uint32_t l2_cache_access_force_rma:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} cache_l2_cache_access_attr_ctrl_reg_t; - - -/** Group: Clock Gate Control and configuration register */ -/** Type of clock_gate register - * Clock gate control register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * The bit is used to enable clock gate when access all registers in this module. - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} cache_clock_gate_reg_t; +} cache_l1_cache_addr_reg_t; /** Group: Cache Trace Control register */ @@ -5400,93 +1262,21 @@ typedef union { * The bit is used to enable L1-Cache trace for the performance counter and fail tracer */ uint32_t l1_cache_trace_ena:1; - /** l2_cache_trace_ena : HRO; bitpos: [1]; default: 0; - * The bit is used to enable L2-Cache trace for the performance counter and fail tracer - */ - uint32_t l2_cache_trace_ena:1; - uint32_t reserved_2:30; + uint32_t reserved_1:31; }; uint32_t val; } cache_trace_ena_reg_t; -/** Group: Redundancy register (Prepare for ECO) */ -/** Type of redundancy_sig0 register - * Cache redundancy signal 0 register - */ -typedef union { - struct { - /** redcy_sig0 : R/W; bitpos: [31:0]; default: 0; - * Those bits are prepared for ECO. - */ - uint32_t redcy_sig0:32; - }; - uint32_t val; -} cache_redundancy_sig0_reg_t; - -/** Type of redundancy_sig1 register - * Cache redundancy signal 1 register - */ -typedef union { - struct { - /** redcy_sig1 : R/W; bitpos: [31:0]; default: 0; - * Those bits are prepared for ECO. - */ - uint32_t redcy_sig1:32; - }; - uint32_t val; -} cache_redundancy_sig1_reg_t; - -/** Type of redundancy_sig2 register - * Cache redundancy signal 2 register - */ -typedef union { - struct { - /** redcy_sig2 : R/W; bitpos: [31:0]; default: 0; - * Those bits are prepared for ECO. - */ - uint32_t redcy_sig2:32; - }; - uint32_t val; -} cache_redundancy_sig2_reg_t; - -/** Type of redundancy_sig3 register - * Cache redundancy signal 3 register - */ -typedef union { - struct { - /** redcy_sig3 : R/W; bitpos: [31:0]; default: 0; - * Those bits are prepared for ECO. - */ - uint32_t redcy_sig3:32; - }; - uint32_t val; -} cache_redundancy_sig3_reg_t; - -/** Type of redundancy_sig4 register - * Cache redundancy signal 0 register - */ -typedef union { - struct { - /** redcy_sig4 : RO; bitpos: [3:0]; default: 0; - * Those bits are prepared for ECO. - */ - uint32_t redcy_sig4:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} cache_redundancy_sig4_reg_t; - - -/** Group: Version register */ +/** Group: Version Control Registers */ /** Type of date register * Version control register */ typedef union { struct { /** date : R/W; bitpos: [27:0]; default: 36774432; - * version control register. Note that this default value stored is the latest date - * when the hardware logic was updated. + * Version control register. Note that the default value is the latest date when the + * hardware logic was updated. */ uint32_t date:28; uint32_t reserved_28:4; @@ -5496,12 +1286,9 @@ typedef union { typedef struct { - volatile cache_l1_icache_ctrl_reg_t l1_icache_ctrl; + uint32_t reserved_000; volatile cache_l1_cache_ctrl_reg_t l1_cache_ctrl; - volatile cache_l1_bypass_cache_conf_reg_t l1_bypass_cache_conf; - volatile cache_l1_cache_atomic_conf_reg_t l1_cache_atomic_conf; - volatile cache_l1_icache_cachesize_conf_reg_t l1_icache_cachesize_conf; - volatile cache_l1_icache_blocksize_conf_reg_t l1_icache_blocksize_conf; + uint32_t reserved_008[4]; volatile cache_l1_cache_cachesize_conf_reg_t l1_cache_cachesize_conf; volatile cache_l1_cache_blocksize_conf_reg_t l1_cache_blocksize_conf; volatile cache_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl; @@ -5509,26 +1296,11 @@ typedef struct { volatile cache_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl; volatile cache_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf; volatile cache_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf; - volatile cache_l1_icache0_prelock_conf_reg_t l1_icache0_prelock_conf; - volatile cache_l1_icache0_prelock_sct0_addr_reg_t l1_icache0_prelock_sct0_addr; - volatile cache_l1_icache0_prelock_sct1_addr_reg_t l1_icache0_prelock_sct1_addr; - volatile cache_l1_icache0_prelock_sct_size_reg_t l1_icache0_prelock_sct_size; - volatile cache_l1_icache1_prelock_conf_reg_t l1_icache1_prelock_conf; - volatile cache_l1_icache1_prelock_sct0_addr_reg_t l1_icache1_prelock_sct0_addr; - volatile cache_l1_icache1_prelock_sct1_addr_reg_t l1_icache1_prelock_sct1_addr; - volatile cache_l1_icache1_prelock_sct_size_reg_t l1_icache1_prelock_sct_size; - volatile cache_l1_icache2_prelock_conf_reg_t l1_icache2_prelock_conf; - volatile cache_l1_icache2_prelock_sct0_addr_reg_t l1_icache2_prelock_sct0_addr; - volatile cache_l1_icache2_prelock_sct1_addr_reg_t l1_icache2_prelock_sct1_addr; - volatile cache_l1_icache2_prelock_sct_size_reg_t l1_icache2_prelock_sct_size; - volatile cache_l1_icache3_prelock_conf_reg_t l1_icache3_prelock_conf; - volatile cache_l1_icache3_prelock_sct0_addr_reg_t l1_icache3_prelock_sct0_addr; - volatile cache_l1_icache3_prelock_sct1_addr_reg_t l1_icache3_prelock_sct1_addr; - volatile cache_l1_icache3_prelock_sct_size_reg_t l1_icache3_prelock_sct_size; + uint32_t reserved_034[16]; volatile cache_l1_cache_prelock_conf_reg_t l1_cache_prelock_conf; volatile cache_l1_cache_prelock_sct0_addr_reg_t l1_cache_prelock_sct0_addr; - volatile cache_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr; - volatile cache_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size; + volatile cache_l1_cache_prelock_sct1_addr_reg_t l1_cache_prelock_sct1_addr; + volatile cache_l1_cache_prelock_sct_size_reg_t l1_cache_prelock_sct_size; volatile cache_lock_ctrl_reg_t lock_ctrl; volatile cache_lock_map_reg_t lock_map; volatile cache_lock_addr_reg_t lock_addr; @@ -5537,50 +1309,17 @@ typedef struct { volatile cache_sync_map_reg_t sync_map; volatile cache_sync_addr_reg_t sync_addr; volatile cache_sync_size_reg_t sync_size; - volatile cache_l1_icache0_preload_ctrl_reg_t l1_icache0_preload_ctrl; - volatile cache_l1_icache0_preload_addr_reg_t l1_icache0_preload_addr; - volatile cache_l1_icache0_preload_size_reg_t l1_icache0_preload_size; - volatile cache_l1_icache1_preload_ctrl_reg_t l1_icache1_preload_ctrl; - volatile cache_l1_icache1_preload_addr_reg_t l1_icache1_preload_addr; - volatile cache_l1_icache1_preload_size_reg_t l1_icache1_preload_size; - volatile cache_l1_icache2_preload_ctrl_reg_t l1_icache2_preload_ctrl; - volatile cache_l1_icache2_preload_addr_reg_t l1_icache2_preload_addr; - volatile cache_l1_icache2_preload_size_reg_t l1_icache2_preload_size; - volatile cache_l1_icache3_preload_ctrl_reg_t l1_icache3_preload_ctrl; - volatile cache_l1_icache3_preload_addr_reg_t l1_icache3_preload_addr; - volatile cache_l1_icache3_preload_size_reg_t l1_icache3_preload_size; + uint32_t reserved_0a4[12]; volatile cache_l1_cache_preload_ctrl_reg_t l1_cache_preload_ctrl; - volatile cache_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr; - volatile cache_l1_dcache_preload_size_reg_t l1_dcache_preload_size; - volatile cache_l1_icache0_autoload_ctrl_reg_t l1_icache0_autoload_ctrl; - volatile cache_l1_icache0_autoload_sct0_addr_reg_t l1_icache0_autoload_sct0_addr; - volatile cache_l1_icache0_autoload_sct0_size_reg_t l1_icache0_autoload_sct0_size; - volatile cache_l1_icache0_autoload_sct1_addr_reg_t l1_icache0_autoload_sct1_addr; - volatile cache_l1_icache0_autoload_sct1_size_reg_t l1_icache0_autoload_sct1_size; - volatile cache_l1_icache1_autoload_ctrl_reg_t l1_icache1_autoload_ctrl; - volatile cache_l1_icache1_autoload_sct0_addr_reg_t l1_icache1_autoload_sct0_addr; - volatile cache_l1_icache1_autoload_sct0_size_reg_t l1_icache1_autoload_sct0_size; - volatile cache_l1_icache1_autoload_sct1_addr_reg_t l1_icache1_autoload_sct1_addr; - volatile cache_l1_icache1_autoload_sct1_size_reg_t l1_icache1_autoload_sct1_size; - volatile cache_l1_icache2_autoload_ctrl_reg_t l1_icache2_autoload_ctrl; - volatile cache_l1_icache2_autoload_sct0_addr_reg_t l1_icache2_autoload_sct0_addr; - volatile cache_l1_icache2_autoload_sct0_size_reg_t l1_icache2_autoload_sct0_size; - volatile cache_l1_icache2_autoload_sct1_addr_reg_t l1_icache2_autoload_sct1_addr; - volatile cache_l1_icache2_autoload_sct1_size_reg_t l1_icache2_autoload_sct1_size; - volatile cache_l1_icache3_autoload_ctrl_reg_t l1_icache3_autoload_ctrl; - volatile cache_l1_icache3_autoload_sct0_addr_reg_t l1_icache3_autoload_sct0_addr; - volatile cache_l1_icache3_autoload_sct0_size_reg_t l1_icache3_autoload_sct0_size; - volatile cache_l1_icache3_autoload_sct1_addr_reg_t l1_icache3_autoload_sct1_addr; - volatile cache_l1_icache3_autoload_sct1_size_reg_t l1_icache3_autoload_sct1_size; + volatile cache_l1_cache_preload_addr_reg_t l1_cache_preload_addr; + volatile cache_l1_cache_preload_size_reg_t l1_cache_preload_size; + uint32_t reserved_0e0[20]; volatile cache_l1_cache_autoload_ctrl_reg_t l1_cache_autoload_ctrl; volatile cache_l1_cache_autoload_sct0_addr_reg_t l1_cache_autoload_sct0_addr; volatile cache_l1_cache_autoload_sct0_size_reg_t l1_cache_autoload_sct0_size; volatile cache_l1_cache_autoload_sct1_addr_reg_t l1_cache_autoload_sct1_addr; volatile cache_l1_cache_autoload_sct1_size_reg_t l1_cache_autoload_sct1_size; - volatile cache_l1_cache_autoload_sct2_addr_reg_t l1_cache_autoload_sct2_addr; - volatile cache_l1_cache_autoload_sct2_size_reg_t l1_cache_autoload_sct2_size; - volatile cache_l1_cache_autoload_sct3_addr_reg_t l1_cache_autoload_sct3_addr; - volatile cache_l1_cache_autoload_sct3_size_reg_t l1_cache_autoload_sct3_size; + uint32_t reserved_144[4]; volatile cache_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena; volatile cache_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr; volatile cache_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw; @@ -5591,52 +1330,20 @@ typedef struct { volatile cache_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw; volatile cache_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st; volatile cache_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl; - volatile cache_l1_ibus0_acs_hit_cnt_reg_t l1_ibus0_acs_hit_cnt; - volatile cache_l1_ibus0_acs_miss_cnt_reg_t l1_ibus0_acs_miss_cnt; - volatile cache_l1_ibus0_acs_conflict_cnt_reg_t l1_ibus0_acs_conflict_cnt; - volatile cache_l1_ibus0_acs_nxtlvl_rd_cnt_reg_t l1_ibus0_acs_nxtlvl_rd_cnt; - volatile cache_l1_ibus1_acs_hit_cnt_reg_t l1_ibus1_acs_hit_cnt; - volatile cache_l1_ibus1_acs_miss_cnt_reg_t l1_ibus1_acs_miss_cnt; - volatile cache_l1_ibus1_acs_conflict_cnt_reg_t l1_ibus1_acs_conflict_cnt; - volatile cache_l1_ibus1_acs_nxtlvl_rd_cnt_reg_t l1_ibus1_acs_nxtlvl_rd_cnt; - volatile cache_l1_ibus2_acs_hit_cnt_reg_t l1_ibus2_acs_hit_cnt; - volatile cache_l1_ibus2_acs_miss_cnt_reg_t l1_ibus2_acs_miss_cnt; - volatile cache_l1_ibus2_acs_conflict_cnt_reg_t l1_ibus2_acs_conflict_cnt; - volatile cache_l1_ibus2_acs_nxtlvl_rd_cnt_reg_t l1_ibus2_acs_nxtlvl_rd_cnt; - volatile cache_l1_ibus3_acs_hit_cnt_reg_t l1_ibus3_acs_hit_cnt; - volatile cache_l1_ibus3_acs_miss_cnt_reg_t l1_ibus3_acs_miss_cnt; - volatile cache_l1_ibus3_acs_conflict_cnt_reg_t l1_ibus3_acs_conflict_cnt; - volatile cache_l1_ibus3_acs_nxtlvl_rd_cnt_reg_t l1_ibus3_acs_nxtlvl_rd_cnt; + uint32_t reserved_17c[16]; volatile cache_l1_bus0_acs_hit_cnt_reg_t l1_bus0_acs_hit_cnt; volatile cache_l1_bus0_acs_miss_cnt_reg_t l1_bus0_acs_miss_cnt; volatile cache_l1_bus0_acs_conflict_cnt_reg_t l1_bus0_acs_conflict_cnt; - volatile cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t l1_dbus0_acs_nxtlvl_rd_cnt; - volatile cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t l1_dbus0_acs_nxtlvl_wr_cnt; + volatile cache_l1_bus0_acs_nxtlvl_rd_cnt_reg_t l1_bus0_acs_nxtlvl_rd_cnt; + volatile cache_l1_bus0_acs_nxtlvl_wr_cnt_reg_t l1_bus0_acs_nxtlvl_wr_cnt; volatile cache_l1_bus1_acs_hit_cnt_reg_t l1_bus1_acs_hit_cnt; volatile cache_l1_bus1_acs_miss_cnt_reg_t l1_bus1_acs_miss_cnt; volatile cache_l1_bus1_acs_conflict_cnt_reg_t l1_bus1_acs_conflict_cnt; volatile cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t l1_dbus1_acs_nxtlvl_rd_cnt; volatile cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t l1_dbus1_acs_nxtlvl_wr_cnt; - volatile cache_l1_dbus2_acs_hit_cnt_reg_t l1_dbus2_acs_hit_cnt; - volatile cache_l1_dbus2_acs_miss_cnt_reg_t l1_dbus2_acs_miss_cnt; - volatile cache_l1_dbus2_acs_conflict_cnt_reg_t l1_dbus2_acs_conflict_cnt; - volatile cache_l1_dbus2_acs_nxtlvl_rd_cnt_reg_t l1_dbus2_acs_nxtlvl_rd_cnt; - volatile cache_l1_dbus2_acs_nxtlvl_wr_cnt_reg_t l1_dbus2_acs_nxtlvl_wr_cnt; - volatile cache_l1_dbus3_acs_hit_cnt_reg_t l1_dbus3_acs_hit_cnt; - volatile cache_l1_dbus3_acs_miss_cnt_reg_t l1_dbus3_acs_miss_cnt; - volatile cache_l1_dbus3_acs_conflict_cnt_reg_t l1_dbus3_acs_conflict_cnt; - volatile cache_l1_dbus3_acs_nxtlvl_rd_cnt_reg_t l1_dbus3_acs_nxtlvl_rd_cnt; - volatile cache_l1_dbus3_acs_nxtlvl_wr_cnt_reg_t l1_dbus3_acs_nxtlvl_wr_cnt; - volatile cache_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr; - volatile cache_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr; - volatile cache_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr; - volatile cache_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr; - volatile cache_l1_icache2_acs_fail_id_attr_reg_t l1_icache2_acs_fail_id_attr; - volatile cache_l1_icache2_acs_fail_addr_reg_t l1_icache2_acs_fail_addr; - volatile cache_l1_icache3_acs_fail_id_attr_reg_t l1_icache3_acs_fail_id_attr; - volatile cache_l1_icache3_acs_fail_addr_reg_t l1_icache3_acs_fail_addr; - volatile cache_l1_dcache_acs_fail_id_attr_reg_t l1_dcache_acs_fail_id_attr; - volatile cache_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr; + uint32_t reserved_1e4[18]; + volatile cache_l1_cache_acs_fail_id_attr_reg_t l1_cache_acs_fail_id_attr; + volatile cache_l1_cache_acs_fail_addr_reg_t l1_cache_acs_fail_addr; volatile cache_l1_cache_sync_preload_int_ena_reg_t l1_cache_sync_preload_int_ena; volatile cache_l1_cache_sync_preload_int_clr_reg_t l1_cache_sync_preload_int_clr; volatile cache_l1_cache_sync_preload_int_raw_reg_t l1_cache_sync_preload_int_raw; @@ -5645,108 +1352,14 @@ typedef struct { volatile cache_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl; volatile cache_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl; volatile cache_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl; - volatile cache_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear; + uint32_t reserved_254; volatile cache_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl; volatile cache_l1_cache_way_object_reg_t l1_cache_way_object; volatile cache_l1_cache_addr_reg_t l1_cache_addr; volatile cache_l1_cache_debug_bus_reg_t l1_cache_debug_bus; - volatile cache_level_split0_reg_t level_split0; - volatile cache_l2_cache_ctrl_reg_t l2_cache_ctrl; - volatile cache_l2_bypass_cache_conf_reg_t l2_bypass_cache_conf; - volatile cache_l2_cache_cachesize_conf_reg_t l2_cache_cachesize_conf; - volatile cache_l2_cache_blocksize_conf_reg_t l2_cache_blocksize_conf; - volatile cache_l2_cache_wrap_around_ctrl_reg_t l2_cache_wrap_around_ctrl; - volatile cache_l2_cache_miss_access_ctrl_reg_t l2_cache_miss_access_ctrl; - volatile cache_l2_cache_freeze_ctrl_reg_t l2_cache_freeze_ctrl; - volatile cache_l2_cache_data_mem_acs_conf_reg_t l2_cache_data_mem_acs_conf; - volatile cache_l2_cache_tag_mem_acs_conf_reg_t l2_cache_tag_mem_acs_conf; - volatile cache_l2_cache_prelock_conf_reg_t l2_cache_prelock_conf; - volatile cache_l2_cache_prelock_sct0_addr_reg_t l2_cache_prelock_sct0_addr; - volatile cache_l2_cache_prelock_sct1_addr_reg_t l2_cache_prelock_sct1_addr; - volatile cache_l2_cache_prelock_sct_size_reg_t l2_cache_prelock_sct_size; - volatile cache_l2_cache_preload_ctrl_reg_t l2_cache_preload_ctrl; - volatile cache_l2_cache_preload_addr_reg_t l2_cache_preload_addr; - volatile cache_l2_cache_preload_size_reg_t l2_cache_preload_size; - volatile cache_l2_cache_autoload_ctrl_reg_t l2_cache_autoload_ctrl; - volatile cache_l2_cache_autoload_sct0_addr_reg_t l2_cache_autoload_sct0_addr; - volatile cache_l2_cache_autoload_sct0_size_reg_t l2_cache_autoload_sct0_size; - volatile cache_l2_cache_autoload_sct1_addr_reg_t l2_cache_autoload_sct1_addr; - volatile cache_l2_cache_autoload_sct1_size_reg_t l2_cache_autoload_sct1_size; - volatile cache_l2_cache_autoload_sct2_addr_reg_t l2_cache_autoload_sct2_addr; - volatile cache_l2_cache_autoload_sct2_size_reg_t l2_cache_autoload_sct2_size; - volatile cache_l2_cache_autoload_sct3_addr_reg_t l2_cache_autoload_sct3_addr; - volatile cache_l2_cache_autoload_sct3_size_reg_t l2_cache_autoload_sct3_size; - volatile cache_l2_cache_acs_cnt_int_ena_reg_t l2_cache_acs_cnt_int_ena; - volatile cache_l2_cache_acs_cnt_int_clr_reg_t l2_cache_acs_cnt_int_clr; - volatile cache_l2_cache_acs_cnt_int_raw_reg_t l2_cache_acs_cnt_int_raw; - volatile cache_l2_cache_acs_cnt_int_st_reg_t l2_cache_acs_cnt_int_st; - volatile cache_l2_cache_acs_fail_ctrl_reg_t l2_cache_acs_fail_ctrl; - volatile cache_l2_cache_acs_fail_int_ena_reg_t l2_cache_acs_fail_int_ena; - volatile cache_l2_cache_acs_fail_int_clr_reg_t l2_cache_acs_fail_int_clr; - volatile cache_l2_cache_acs_fail_int_raw_reg_t l2_cache_acs_fail_int_raw; - volatile cache_l2_cache_acs_fail_int_st_reg_t l2_cache_acs_fail_int_st; - volatile cache_l2_cache_acs_cnt_ctrl_reg_t l2_cache_acs_cnt_ctrl; - volatile cache_l2_ibus0_acs_hit_cnt_reg_t l2_ibus0_acs_hit_cnt; - volatile cache_l2_ibus0_acs_miss_cnt_reg_t l2_ibus0_acs_miss_cnt; - volatile cache_l2_ibus0_acs_conflict_cnt_reg_t l2_ibus0_acs_conflict_cnt; - volatile cache_l2_ibus0_acs_nxtlvl_rd_cnt_reg_t l2_ibus0_acs_nxtlvl_rd_cnt; - volatile cache_l2_ibus1_acs_hit_cnt_reg_t l2_ibus1_acs_hit_cnt; - volatile cache_l2_ibus1_acs_miss_cnt_reg_t l2_ibus1_acs_miss_cnt; - volatile cache_l2_ibus1_acs_conflict_cnt_reg_t l2_ibus1_acs_conflict_cnt; - volatile cache_l2_ibus1_acs_nxtlvl_rd_cnt_reg_t l2_ibus1_acs_nxtlvl_rd_cnt; - volatile cache_l2_ibus2_acs_hit_cnt_reg_t l2_ibus2_acs_hit_cnt; - volatile cache_l2_ibus2_acs_miss_cnt_reg_t l2_ibus2_acs_miss_cnt; - volatile cache_l2_ibus2_acs_conflict_cnt_reg_t l2_ibus2_acs_conflict_cnt; - volatile cache_l2_ibus2_acs_nxtlvl_rd_cnt_reg_t l2_ibus2_acs_nxtlvl_rd_cnt; - volatile cache_l2_ibus3_acs_hit_cnt_reg_t l2_ibus3_acs_hit_cnt; - volatile cache_l2_ibus3_acs_miss_cnt_reg_t l2_ibus3_acs_miss_cnt; - volatile cache_l2_ibus3_acs_conflict_cnt_reg_t l2_ibus3_acs_conflict_cnt; - volatile cache_l2_ibus3_acs_nxtlvl_rd_cnt_reg_t l2_ibus3_acs_nxtlvl_rd_cnt; - volatile cache_l2_dbus0_acs_hit_cnt_reg_t l2_dbus0_acs_hit_cnt; - volatile cache_l2_dbus0_acs_miss_cnt_reg_t l2_dbus0_acs_miss_cnt; - volatile cache_l2_dbus0_acs_conflict_cnt_reg_t l2_dbus0_acs_conflict_cnt; - volatile cache_l2_dbus0_acs_nxtlvl_rd_cnt_reg_t l2_dbus0_acs_nxtlvl_rd_cnt; - volatile cache_l2_dbus0_acs_nxtlvl_wr_cnt_reg_t l2_dbus0_acs_nxtlvl_wr_cnt; - volatile cache_l2_dbus1_acs_hit_cnt_reg_t l2_dbus1_acs_hit_cnt; - volatile cache_l2_dbus1_acs_miss_cnt_reg_t l2_dbus1_acs_miss_cnt; - volatile cache_l2_dbus1_acs_conflict_cnt_reg_t l2_dbus1_acs_conflict_cnt; - volatile cache_l2_dbus1_acs_nxtlvl_rd_cnt_reg_t l2_dbus1_acs_nxtlvl_rd_cnt; - volatile cache_l2_dbus1_acs_nxtlvl_wr_cnt_reg_t l2_dbus1_acs_nxtlvl_wr_cnt; - volatile cache_l2_dbus2_acs_hit_cnt_reg_t l2_dbus2_acs_hit_cnt; - volatile cache_l2_dbus2_acs_miss_cnt_reg_t l2_dbus2_acs_miss_cnt; - volatile cache_l2_dbus2_acs_conflict_cnt_reg_t l2_dbus2_acs_conflict_cnt; - volatile cache_l2_dbus2_acs_nxtlvl_rd_cnt_reg_t l2_dbus2_acs_nxtlvl_rd_cnt; - volatile cache_l2_dbus2_acs_nxtlvl_wr_cnt_reg_t l2_dbus2_acs_nxtlvl_wr_cnt; - volatile cache_l2_dbus3_acs_hit_cnt_reg_t l2_dbus3_acs_hit_cnt; - volatile cache_l2_dbus3_acs_miss_cnt_reg_t l2_dbus3_acs_miss_cnt; - volatile cache_l2_dbus3_acs_conflict_cnt_reg_t l2_dbus3_acs_conflict_cnt; - volatile cache_l2_dbus3_acs_nxtlvl_rd_cnt_reg_t l2_dbus3_acs_nxtlvl_rd_cnt; - volatile cache_l2_dbus3_acs_nxtlvl_wr_cnt_reg_t l2_dbus3_acs_nxtlvl_wr_cnt; - volatile cache_l2_cache_acs_fail_id_attr_reg_t l2_cache_acs_fail_id_attr; - volatile cache_l2_cache_acs_fail_addr_reg_t l2_cache_acs_fail_addr; - volatile cache_l2_cache_sync_preload_int_ena_reg_t l2_cache_sync_preload_int_ena; - volatile cache_l2_cache_sync_preload_int_clr_reg_t l2_cache_sync_preload_int_clr; - volatile cache_l2_cache_sync_preload_int_raw_reg_t l2_cache_sync_preload_int_raw; - volatile cache_l2_cache_sync_preload_int_st_reg_t l2_cache_sync_preload_int_st; - volatile cache_l2_cache_sync_preload_exception_reg_t l2_cache_sync_preload_exception; - volatile cache_l2_cache_sync_rst_ctrl_reg_t l2_cache_sync_rst_ctrl; - volatile cache_l2_cache_preload_rst_ctrl_reg_t l2_cache_preload_rst_ctrl; - volatile cache_l2_cache_autoload_buf_clr_ctrl_reg_t l2_cache_autoload_buf_clr_ctrl; - volatile cache_l2_unallocate_buffer_clear_reg_t l2_unallocate_buffer_clear; - volatile cache_l2_cache_access_attr_ctrl_reg_t l2_cache_access_attr_ctrl; - volatile cache_l2_cache_object_ctrl_reg_t l2_cache_object_ctrl; - volatile cache_l2_cache_way_object_reg_t l2_cache_way_object; - volatile cache_l2_cache_addr_reg_t l2_cache_addr; - volatile cache_l2_cache_debug_bus_reg_t l2_cache_debug_bus; - volatile cache_level_split1_reg_t level_split1; - volatile cache_clock_gate_reg_t clock_gate; + uint32_t reserved_268[90]; volatile cache_trace_ena_reg_t trace_ena; - volatile cache_redundancy_sig0_reg_t redundancy_sig0; - volatile cache_redundancy_sig1_reg_t redundancy_sig1; - volatile cache_redundancy_sig2_reg_t redundancy_sig2; - volatile cache_redundancy_sig3_reg_t redundancy_sig3; - volatile cache_redundancy_sig4_reg_t redundancy_sig4; - uint32_t reserved_3e8[5]; + uint32_t reserved_3d4[10]; volatile cache_date_reg_t date; } cache_dev_t;