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change(pms): update pms soc headers of p4

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This commit is contained in:
laokaiyao
2025-05-27 16:57:42 +08:00
parent f5748246ea
commit 7f2d5939b5
6 changed files with 82 additions and 246 deletions
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68
components/soc/esp32p4/register/soc/dma_pms_reg.h
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@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -1555,65 +1555,35 @@ extern "C" {
#define PMS_DMA_L2MEM_MON_W_PMS_V 0xFFFFFFFFU #define PMS_DMA_L2MEM_MON_W_PMS_V 0xFFFFFFFFU
#define PMS_DMA_L2MEM_MON_W_PMS_S 0 #define PMS_DMA_L2MEM_MON_W_PMS_S 0
/** PMS_DMA_TCM_MON_PMS_R_REG register /** PMS_DMA_SPM_MON_PMS_R_REG register
* TCM Monitor read permission control register * SPM Monitor read permission control register
*/ */
#define PMS_DMA_TCM_MON_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1e4) #define PMS_DMA_SPM_MON_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1e4)
/** PMS_DMA_TCM_MON_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; /** PMS_DMA_SPM_MON_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
* Configures read permission for TCM MON. Each bit corresponds to a region. Bit 0 * Configures read permission for SPM MON. Each bit corresponds to a region. Bit 0
* corresponds to region0, and so on. * corresponds to region0, and so on.
* 0: Disable read permission. * 0: Disable read permission.
* 1: Enable read permission. * 1: Enable read permission.
*/ */
#define PMS_DMA_TCM_MON_R_PMS 0xFFFFFFFFU #define PMS_DMA_SPM_MON_R_PMS 0xFFFFFFFFU
#define PMS_DMA_TCM_MON_R_PMS_M (PMS_DMA_TCM_MON_R_PMS_V << PMS_DMA_TCM_MON_R_PMS_S) #define PMS_DMA_SPM_MON_R_PMS_M (PMS_DMA_SPM_MON_R_PMS_V << PMS_DMA_SPM_MON_R_PMS_S)
#define PMS_DMA_TCM_MON_R_PMS_V 0xFFFFFFFFU #define PMS_DMA_SPM_MON_R_PMS_V 0xFFFFFFFFU
#define PMS_DMA_TCM_MON_R_PMS_S 0 #define PMS_DMA_SPM_MON_R_PMS_S 0
/** PMS_DMA_TCM_MON_PMS_W_REG register /** PMS_DMA_SPM_MON_PMS_W_REG register
* TCM Monitor write permission control register * SPM Monitor write permission control register
*/ */
#define PMS_DMA_TCM_MON_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1e8) #define PMS_DMA_SPM_MON_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1e8)
/** PMS_DMA_TCM_MON_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; /** PMS_DMA_SPM_MON_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
* Configures write permission for TCM monitor to access 32 address ranges. Bit 0 * Configures write permission for SPM monitor to access 32 address ranges. Bit 0
* corresponds to region0, and so on. * corresponds to region0, and so on.
* 0: Disable write permission. * 0: Disable write permission.
* 1: Enable write permission. * 1: Enable write permission.
*/ */
#define PMS_DMA_TCM_MON_W_PMS 0xFFFFFFFFU #define PMS_DMA_SPM_MON_W_PMS 0xFFFFFFFFU
#define PMS_DMA_TCM_MON_W_PMS_M (PMS_DMA_TCM_MON_W_PMS_V << PMS_DMA_TCM_MON_W_PMS_S) #define PMS_DMA_SPM_MON_W_PMS_M (PMS_DMA_SPM_MON_W_PMS_V << PMS_DMA_SPM_MON_W_PMS_S)
#define PMS_DMA_TCM_MON_W_PMS_V 0xFFFFFFFFU #define PMS_DMA_SPM_MON_W_PMS_V 0xFFFFFFFFU
#define PMS_DMA_TCM_MON_W_PMS_S 0 #define PMS_DMA_SPM_MON_W_PMS_S 0
/** PMS_DMA_REGDMA_PMS_R_REG register
* REGDMA read permission control register
*/
#define PMS_DMA_REGDMA_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1ec)
/** PMS_DMA_REGDMA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
* Configures read permission for REGDMA. Each bit corresponds to a region. Bit 0
* corresponds to region0, and so on.
* 0: Disable read permission.
* 1: Enable read permission.
*/
#define PMS_DMA_REGDMA_R_PMS 0xFFFFFFFFU
#define PMS_DMA_REGDMA_R_PMS_M (PMS_DMA_REGDMA_R_PMS_V << PMS_DMA_REGDMA_R_PMS_S)
#define PMS_DMA_REGDMA_R_PMS_V 0xFFFFFFFFU
#define PMS_DMA_REGDMA_R_PMS_S 0
/** PMS_DMA_REGDMA_PMS_W_REG register
* REGDMA write permission control register
*/
#define PMS_DMA_REGDMA_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1f0)
/** PMS_DMA_REGDMA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
* Configures write permission for REGDMA. Each bit corresponds to a region. Bit 0
* corresponds to region0, and so on.
* 0: Disable write permission.
* 1: Enable write permission.
*/
#define PMS_DMA_REGDMA_W_PMS 0xFFFFFFFFU
#define PMS_DMA_REGDMA_W_PMS_M (PMS_DMA_REGDMA_W_PMS_V << PMS_DMA_REGDMA_W_PMS_S)
#define PMS_DMA_REGDMA_W_PMS_V 0xFFFFFFFFU
#define PMS_DMA_REGDMA_W_PMS_S 0
/** PMS_DMA_H264_PMS_R_REG register /** PMS_DMA_H264_PMS_R_REG register
* H264 DMA read permission control register * H264 DMA read permission control register

66
components/soc/esp32p4/register/soc/dma_pms_struct.h
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@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -778,69 +778,37 @@ typedef union {
uint32_t val; uint32_t val;
} pms_dma_l2mem_mon_pms_w_reg_t; } pms_dma_l2mem_mon_pms_w_reg_t;
/** Type of tcm_mon_pms_r register /** Type of spm_mon_pms_r register
* TCM Monitor read permission control register * SPM Monitor read permission control register
*/ */
typedef union { typedef union {
struct { struct {
/** tcm_mon_r_pms : R/W; bitpos: [31:0]; default: 4294967295; /** spm_mon_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
* Configures read permission for TCM MON. Each bit corresponds to a region. Bit 0 * Configures read permission for SPM MON. Each bit corresponds to a region. Bit 0
* corresponds to region0, and so on. * corresponds to region0, and so on.
* 0: Disable read permission. * 0: Disable read permission.
* 1: Enable read permission. * 1: Enable read permission.
*/ */
uint32_t tcm_mon_r_pms:32; uint32_t spm_mon_r_pms:32;
}; };
uint32_t val; uint32_t val;
} pms_dma_tcm_mon_pms_r_reg_t; } pms_dma_spm_mon_pms_r_reg_t;
/** Type of tcm_mon_pms_w register /** Type of spm_mon_pms_w register
* TCM Monitor write permission control register * SPM Monitor write permission control register
*/ */
typedef union { typedef union {
struct { struct {
/** tcm_mon_w_pms : R/W; bitpos: [31:0]; default: 4294967295; /** spm_mon_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
* Configures write permission for TCM monitor to access 32 address ranges. Bit 0 * Configures write permission for SPM monitor to access 32 address ranges. Bit 0
* corresponds to region0, and so on. * corresponds to region0, and so on.
* 0: Disable write permission. * 0: Disable write permission.
* 1: Enable write permission. * 1: Enable write permission.
*/ */
uint32_t tcm_mon_w_pms:32; uint32_t spm_mon_w_pms:32;
}; };
uint32_t val; uint32_t val;
} pms_dma_tcm_mon_pms_w_reg_t; } pms_dma_spm_mon_pms_w_reg_t;
/** Type of regdma_pms_r register
* REGDMA read permission control register
*/
typedef union {
struct {
/** regdma_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
* Configures read permission for REGDMA. Each bit corresponds to a region. Bit 0
* corresponds to region0, and so on.
* 0: Disable read permission.
* 1: Enable read permission.
*/
uint32_t regdma_r_pms:32;
};
uint32_t val;
} pms_dma_regdma_pms_r_reg_t;
/** Type of regdma_pms_w register
* REGDMA write permission control register
*/
typedef union {
struct {
/** regdma_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
* Configures write permission for REGDMA. Each bit corresponds to a region. Bit 0
* corresponds to region0, and so on.
* 0: Disable write permission.
* 1: Enable write permission.
*/
uint32_t regdma_w_pms:32;
};
uint32_t val;
} pms_dma_regdma_pms_w_reg_t;
/** Type of h264_pms_r register /** Type of h264_pms_r register
* H264 DMA read permission control register * H264 DMA read permission control register
@ -1121,11 +1089,9 @@ typedef struct {
volatile pms_dma_trace1_pms_w_reg_t trace1_pms_w; volatile pms_dma_trace1_pms_w_reg_t trace1_pms_w;
volatile pms_dma_l2mem_mon_pms_r_reg_t l2mem_mon_pms_r; volatile pms_dma_l2mem_mon_pms_r_reg_t l2mem_mon_pms_r;
volatile pms_dma_l2mem_mon_pms_w_reg_t l2mem_mon_pms_w; volatile pms_dma_l2mem_mon_pms_w_reg_t l2mem_mon_pms_w;
volatile pms_dma_tcm_mon_pms_r_reg_t tcm_mon_pms_r; volatile pms_dma_spm_mon_pms_r_reg_t spm_mon_pms_r;
volatile pms_dma_tcm_mon_pms_w_reg_t tcm_mon_pms_w; volatile pms_dma_spm_mon_pms_w_reg_t spm_mon_pms_w;
volatile pms_dma_regdma_pms_r_reg_t regdma_pms_r; uint32_t reserved_1ec[4];
volatile pms_dma_regdma_pms_w_reg_t regdma_pms_w;
uint32_t reserved_1f4[2];
volatile pms_dma_h264_pms_r_reg_t h264_pms_r; volatile pms_dma_h264_pms_r_reg_t h264_pms_r;
volatile pms_dma_h264_pms_w_reg_t h264_pms_w; volatile pms_dma_h264_pms_w_reg_t h264_pms_w;
volatile pms_dma_dma2d_ppa_pms_r_reg_t dma2d_ppa_pms_r; volatile pms_dma_dma2d_ppa_pms_r_reg_t dma2d_ppa_pms_r;

103
components/soc/esp32p4/register/soc/hp_peri_pms_reg.h
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@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -118,15 +118,15 @@ extern "C" {
#define PMS_CORE0_MM_L2MEM_MON_ALLOW_M (PMS_CORE0_MM_L2MEM_MON_ALLOW_V << PMS_CORE0_MM_L2MEM_MON_ALLOW_S) #define PMS_CORE0_MM_L2MEM_MON_ALLOW_M (PMS_CORE0_MM_L2MEM_MON_ALLOW_V << PMS_CORE0_MM_L2MEM_MON_ALLOW_S)
#define PMS_CORE0_MM_L2MEM_MON_ALLOW_V 0x00000001U #define PMS_CORE0_MM_L2MEM_MON_ALLOW_V 0x00000001U
#define PMS_CORE0_MM_L2MEM_MON_ALLOW_S 9 #define PMS_CORE0_MM_L2MEM_MON_ALLOW_S 9
/** PMS_CORE0_MM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1; /** PMS_CORE0_MM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access TCM monitor. * Configures whether HP CPU0 in machine mode has permission to access SPM monitor.
* 0: Not allowed * 0: Not allowed
* 1: Allowed * 1: Allowed
*/ */
#define PMS_CORE0_MM_TCM_MON_ALLOW (BIT(10)) #define PMS_CORE0_MM_SPM_MON_ALLOW (BIT(10))
#define PMS_CORE0_MM_TCM_MON_ALLOW_M (PMS_CORE0_MM_TCM_MON_ALLOW_V << PMS_CORE0_MM_TCM_MON_ALLOW_S) #define PMS_CORE0_MM_SPM_MON_ALLOW_M (PMS_CORE0_MM_SPM_MON_ALLOW_V << PMS_CORE0_MM_SPM_MON_ALLOW_S)
#define PMS_CORE0_MM_TCM_MON_ALLOW_V 0x00000001U #define PMS_CORE0_MM_SPM_MON_ALLOW_V 0x00000001U
#define PMS_CORE0_MM_TCM_MON_ALLOW_S 10 #define PMS_CORE0_MM_SPM_MON_ALLOW_S 10
/** PMS_CORE0_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1; /** PMS_CORE0_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access cache. * Configures whether HP CPU0 in machine mode has permission to access cache.
* 0: Not allowed * 0: Not allowed
@ -180,16 +180,6 @@ extern "C" {
#define PMS_CORE0_MM_HP_GDMA_ALLOW_M (PMS_CORE0_MM_HP_GDMA_ALLOW_V << PMS_CORE0_MM_HP_GDMA_ALLOW_S) #define PMS_CORE0_MM_HP_GDMA_ALLOW_M (PMS_CORE0_MM_HP_GDMA_ALLOW_V << PMS_CORE0_MM_HP_GDMA_ALLOW_S)
#define PMS_CORE0_MM_HP_GDMA_ALLOW_V 0x00000001U #define PMS_CORE0_MM_HP_GDMA_ALLOW_V 0x00000001U
#define PMS_CORE0_MM_HP_GDMA_ALLOW_S 3 #define PMS_CORE0_MM_HP_GDMA_ALLOW_S 3
/** PMS_CORE0_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access HP GDMA (DW
* GDMA).
* 0: Not allowed
* 1: Allow
*/
#define PMS_CORE0_MM_HP_REGDMA_ALLOW (BIT(4))
#define PMS_CORE0_MM_HP_REGDMA_ALLOW_M (PMS_CORE0_MM_HP_REGDMA_ALLOW_V << PMS_CORE0_MM_HP_REGDMA_ALLOW_S)
#define PMS_CORE0_MM_HP_REGDMA_ALLOW_V 0x00000001U
#define PMS_CORE0_MM_HP_REGDMA_ALLOW_S 4
/** PMS_CORE0_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; /** PMS_CORE0_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access HP SDMMC. * Configures whether HP CPU0 in machine mode has permission to access HP SDMMC.
* 0: Not allowed * 0: Not allowed
@ -831,15 +821,15 @@ extern "C" {
#define PMS_CORE0_UM_L2MEM_MON_ALLOW_M (PMS_CORE0_UM_L2MEM_MON_ALLOW_V << PMS_CORE0_UM_L2MEM_MON_ALLOW_S) #define PMS_CORE0_UM_L2MEM_MON_ALLOW_M (PMS_CORE0_UM_L2MEM_MON_ALLOW_V << PMS_CORE0_UM_L2MEM_MON_ALLOW_S)
#define PMS_CORE0_UM_L2MEM_MON_ALLOW_V 0x00000001U #define PMS_CORE0_UM_L2MEM_MON_ALLOW_V 0x00000001U
#define PMS_CORE0_UM_L2MEM_MON_ALLOW_S 9 #define PMS_CORE0_UM_L2MEM_MON_ALLOW_S 9
/** PMS_CORE0_UM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1; /** PMS_CORE0_UM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access TCM monitor. * Configures whether HP CPU0 in user mode has permission to access SPM monitor.
* 0: Not allowed * 0: Not allowed
* 1: Allowed * 1: Allowed
*/ */
#define PMS_CORE0_UM_TCM_MON_ALLOW (BIT(10)) #define PMS_CORE0_UM_SPM_MON_ALLOW (BIT(10))
#define PMS_CORE0_UM_TCM_MON_ALLOW_M (PMS_CORE0_UM_TCM_MON_ALLOW_V << PMS_CORE0_UM_TCM_MON_ALLOW_S) #define PMS_CORE0_UM_SPM_MON_ALLOW_M (PMS_CORE0_UM_SPM_MON_ALLOW_V << PMS_CORE0_UM_SPM_MON_ALLOW_S)
#define PMS_CORE0_UM_TCM_MON_ALLOW_V 0x00000001U #define PMS_CORE0_UM_SPM_MON_ALLOW_V 0x00000001U
#define PMS_CORE0_UM_TCM_MON_ALLOW_S 10 #define PMS_CORE0_UM_SPM_MON_ALLOW_S 10
/** PMS_CORE0_UM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1; /** PMS_CORE0_UM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access cache. * Configures whether HP CPU0 in user mode has permission to access cache.
* 0: Not allowed * 0: Not allowed
@ -895,15 +885,6 @@ extern "C" {
#define PMS_CORE0_UM_HP_GDMA_ALLOW_M (PMS_CORE0_UM_HP_GDMA_ALLOW_V << PMS_CORE0_UM_HP_GDMA_ALLOW_S) #define PMS_CORE0_UM_HP_GDMA_ALLOW_M (PMS_CORE0_UM_HP_GDMA_ALLOW_V << PMS_CORE0_UM_HP_GDMA_ALLOW_S)
#define PMS_CORE0_UM_HP_GDMA_ALLOW_V 0x00000001U #define PMS_CORE0_UM_HP_GDMA_ALLOW_V 0x00000001U
#define PMS_CORE0_UM_HP_GDMA_ALLOW_S 3 #define PMS_CORE0_UM_HP_GDMA_ALLOW_S 3
/** PMS_CORE0_UM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access HP regdma.
* 0: Not allowed
* 1: Allow
*/
#define PMS_CORE0_UM_HP_REGDMA_ALLOW (BIT(4))
#define PMS_CORE0_UM_HP_REGDMA_ALLOW_M (PMS_CORE0_UM_HP_REGDMA_ALLOW_V << PMS_CORE0_UM_HP_REGDMA_ALLOW_S)
#define PMS_CORE0_UM_HP_REGDMA_ALLOW_V 0x00000001U
#define PMS_CORE0_UM_HP_REGDMA_ALLOW_S 4
/** PMS_CORE0_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; /** PMS_CORE0_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access HP SDMMC. * Configures whether HP CPU0 in user mode has permission to access HP SDMMC.
* 0: Not allowed * 0: Not allowed
@ -1536,15 +1517,15 @@ extern "C" {
#define PMS_CORE1_MM_L2MEM_MON_ALLOW_M (PMS_CORE1_MM_L2MEM_MON_ALLOW_V << PMS_CORE1_MM_L2MEM_MON_ALLOW_S) #define PMS_CORE1_MM_L2MEM_MON_ALLOW_M (PMS_CORE1_MM_L2MEM_MON_ALLOW_V << PMS_CORE1_MM_L2MEM_MON_ALLOW_S)
#define PMS_CORE1_MM_L2MEM_MON_ALLOW_V 0x00000001U #define PMS_CORE1_MM_L2MEM_MON_ALLOW_V 0x00000001U
#define PMS_CORE1_MM_L2MEM_MON_ALLOW_S 9 #define PMS_CORE1_MM_L2MEM_MON_ALLOW_S 9
/** PMS_CORE1_MM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1; /** PMS_CORE1_MM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access TCM monitor. * Configures whether HP CPU1 in machine mode has permission to access SPM monitor.
* 0: Not allowed * 0: Not allowed
* 1: Allowed * 1: Allowed
*/ */
#define PMS_CORE1_MM_TCM_MON_ALLOW (BIT(10)) #define PMS_CORE1_MM_SPM_MON_ALLOW (BIT(10))
#define PMS_CORE1_MM_TCM_MON_ALLOW_M (PMS_CORE1_MM_TCM_MON_ALLOW_V << PMS_CORE1_MM_TCM_MON_ALLOW_S) #define PMS_CORE1_MM_SPM_MON_ALLOW_M (PMS_CORE1_MM_SPM_MON_ALLOW_V << PMS_CORE1_MM_SPM_MON_ALLOW_S)
#define PMS_CORE1_MM_TCM_MON_ALLOW_V 0x00000001U #define PMS_CORE1_MM_SPM_MON_ALLOW_V 0x00000001U
#define PMS_CORE1_MM_TCM_MON_ALLOW_S 10 #define PMS_CORE1_MM_SPM_MON_ALLOW_S 10
/** PMS_CORE1_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1; /** PMS_CORE1_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access cache. * Configures whether HP CPU1 in machine mode has permission to access cache.
* 0: Not allowed * 0: Not allowed
@ -1598,16 +1579,6 @@ extern "C" {
#define PMS_CORE1_MM_HP_GDMA_ALLOW_M (PMS_CORE1_MM_HP_GDMA_ALLOW_V << PMS_CORE1_MM_HP_GDMA_ALLOW_S) #define PMS_CORE1_MM_HP_GDMA_ALLOW_M (PMS_CORE1_MM_HP_GDMA_ALLOW_V << PMS_CORE1_MM_HP_GDMA_ALLOW_S)
#define PMS_CORE1_MM_HP_GDMA_ALLOW_V 0x00000001U #define PMS_CORE1_MM_HP_GDMA_ALLOW_V 0x00000001U
#define PMS_CORE1_MM_HP_GDMA_ALLOW_S 3 #define PMS_CORE1_MM_HP_GDMA_ALLOW_S 3
/** PMS_CORE1_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access HP GDMA (DW
* GDMA).
* 0: Not allowed
* 1: Allow
*/
#define PMS_CORE1_MM_HP_REGDMA_ALLOW (BIT(4))
#define PMS_CORE1_MM_HP_REGDMA_ALLOW_M (PMS_CORE1_MM_HP_REGDMA_ALLOW_V << PMS_CORE1_MM_HP_REGDMA_ALLOW_S)
#define PMS_CORE1_MM_HP_REGDMA_ALLOW_V 0x00000001U
#define PMS_CORE1_MM_HP_REGDMA_ALLOW_S 4
/** PMS_CORE1_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; /** PMS_CORE1_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access HP SDMMC. * Configures whether HP CPU1 in machine mode has permission to access HP SDMMC.
* 0: Not allowed * 0: Not allowed
@ -2249,15 +2220,15 @@ extern "C" {
#define PMS_CORE1_UM_L2MEM_MON_ALLOW_M (PMS_CORE1_UM_L2MEM_MON_ALLOW_V << PMS_CORE1_UM_L2MEM_MON_ALLOW_S) #define PMS_CORE1_UM_L2MEM_MON_ALLOW_M (PMS_CORE1_UM_L2MEM_MON_ALLOW_V << PMS_CORE1_UM_L2MEM_MON_ALLOW_S)
#define PMS_CORE1_UM_L2MEM_MON_ALLOW_V 0x00000001U #define PMS_CORE1_UM_L2MEM_MON_ALLOW_V 0x00000001U
#define PMS_CORE1_UM_L2MEM_MON_ALLOW_S 9 #define PMS_CORE1_UM_L2MEM_MON_ALLOW_S 9
/** PMS_CORE1_UM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1; /** PMS_CORE1_UM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access TCM monitor. * Configures whether HP CPU1 in user mode has permission to access SPM monitor.
* 0: Not allowed * 0: Not allowed
* 1: Allowed * 1: Allowed
*/ */
#define PMS_CORE1_UM_TCM_MON_ALLOW (BIT(10)) #define PMS_CORE1_UM_SPM_MON_ALLOW (BIT(10))
#define PMS_CORE1_UM_TCM_MON_ALLOW_M (PMS_CORE1_UM_TCM_MON_ALLOW_V << PMS_CORE1_UM_TCM_MON_ALLOW_S) #define PMS_CORE1_UM_SPM_MON_ALLOW_M (PMS_CORE1_UM_SPM_MON_ALLOW_V << PMS_CORE1_UM_SPM_MON_ALLOW_S)
#define PMS_CORE1_UM_TCM_MON_ALLOW_V 0x00000001U #define PMS_CORE1_UM_SPM_MON_ALLOW_V 0x00000001U
#define PMS_CORE1_UM_TCM_MON_ALLOW_S 10 #define PMS_CORE1_UM_SPM_MON_ALLOW_S 10
/** PMS_CORE1_UM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1; /** PMS_CORE1_UM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access cache. * Configures whether HP CPU1 in user mode has permission to access cache.
* 0: Not allowed * 0: Not allowed
@ -2313,15 +2284,6 @@ extern "C" {
#define PMS_CORE1_UM_HP_GDMA_ALLOW_M (PMS_CORE1_UM_HP_GDMA_ALLOW_V << PMS_CORE1_UM_HP_GDMA_ALLOW_S) #define PMS_CORE1_UM_HP_GDMA_ALLOW_M (PMS_CORE1_UM_HP_GDMA_ALLOW_V << PMS_CORE1_UM_HP_GDMA_ALLOW_S)
#define PMS_CORE1_UM_HP_GDMA_ALLOW_V 0x00000001U #define PMS_CORE1_UM_HP_GDMA_ALLOW_V 0x00000001U
#define PMS_CORE1_UM_HP_GDMA_ALLOW_S 3 #define PMS_CORE1_UM_HP_GDMA_ALLOW_S 3
/** PMS_CORE1_UM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access HP regdma.
* 0: Not allowed
* 1: Allow
*/
#define PMS_CORE1_UM_HP_REGDMA_ALLOW (BIT(4))
#define PMS_CORE1_UM_HP_REGDMA_ALLOW_M (PMS_CORE1_UM_HP_REGDMA_ALLOW_V << PMS_CORE1_UM_HP_REGDMA_ALLOW_S)
#define PMS_CORE1_UM_HP_REGDMA_ALLOW_V 0x00000001U
#define PMS_CORE1_UM_HP_REGDMA_ALLOW_S 4
/** PMS_CORE1_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; /** PMS_CORE1_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access HP SDMMC. * Configures whether HP CPU1 in user mode has permission to access HP SDMMC.
* 0: Not allowed * 0: Not allowed
@ -2873,21 +2835,6 @@ extern "C" {
#define PMS_CORE1_UM_HP_CLKRST_ALLOW_V 0x00000001U #define PMS_CORE1_UM_HP_CLKRST_ALLOW_V 0x00000001U
#define PMS_CORE1_UM_HP_CLKRST_ALLOW_S 4 #define PMS_CORE1_UM_HP_CLKRST_ALLOW_S 4
/** PMS_REGDMA_PERI_PMS_REG register
* Permission register for REGDMA
*/
#define PMS_REGDMA_PERI_PMS_REG (DR_REG_HP_PERI_PMS_BASE + 0x48)
/** PMS_REGDMA_PERI_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether REGDMA has permission to access all HP peripheral (including CPU
* peripherals).
* 0: Not allowed
* 1: Allow
*/
#define PMS_REGDMA_PERI_ALLOW (BIT(0))
#define PMS_REGDMA_PERI_ALLOW_M (PMS_REGDMA_PERI_ALLOW_V << PMS_REGDMA_PERI_ALLOW_S)
#define PMS_REGDMA_PERI_ALLOW_V 0x00000001U
#define PMS_REGDMA_PERI_ALLOW_S 0
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

51
components/soc/esp32p4/register/soc/hp_peri_pms_struct.h
View File

@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -103,12 +103,12 @@ typedef union {
* 1: Allowed * 1: Allowed
*/ */
uint32_t coren_mm_l2mem_mon_allow:1; uint32_t coren_mm_l2mem_mon_allow:1;
/** coren_mm_tcm_mon_allow : R/W; bitpos: [10]; default: 1; /** coren_mm_spm_mon_allow : R/W; bitpos: [10]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access TCM monitor. * Configures whether HP CPUn in machine mode has permission to access SPM monitor.
* 0: Not allowed * 0: Not allowed
* 1: Allowed * 1: Allowed
*/ */
uint32_t coren_mm_tcm_mon_allow:1; uint32_t coren_mm_spm_mon_allow:1;
/** coren_mm_cache_allow : R/W; bitpos: [11]; default: 1; /** coren_mm_cache_allow : R/W; bitpos: [11]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access cache. * Configures whether HP CPUn in machine mode has permission to access cache.
* 0: Not allowed * 0: Not allowed
@ -152,13 +152,7 @@ typedef union {
* 1: Allowed * 1: Allowed
*/ */
uint32_t coren_mm_hp_gdma_allow:1; uint32_t coren_mm_hp_gdma_allow:1;
/** coren_mm_hp_regdma_allow : R/W; bitpos: [4]; default: 1; uint32_t reserved_4:1;
* Configures whether HP CPUn in machine mode has permission to access HP GDMA (DW
* GDMA).
* 0: Not allowed
* 1: Allow
*/
uint32_t coren_mm_hp_regdma_allow:1;
/** coren_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1; /** coren_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access HP SDMMC. * Configures whether HP CPUn in machine mode has permission to access HP SDMMC.
* 0: Not allowed * 0: Not allowed
@ -616,12 +610,12 @@ typedef union {
* 1: Allowed * 1: Allowed
*/ */
uint32_t coren_um_l2mem_mon_allow:1; uint32_t coren_um_l2mem_mon_allow:1;
/** coren_um_tcm_mon_allow : R/W; bitpos: [10]; default: 1; /** coren_um_spm_mon_allow : R/W; bitpos: [10]; default: 1;
* Configures whether HP CPUn in user mode has permission to access TCM monitor. * Configures whether HP CPUn in user mode has permission to access SPM monitor.
* 0: Not allowed * 0: Not allowed
* 1: Allowed * 1: Allowed
*/ */
uint32_t coren_um_tcm_mon_allow:1; uint32_t coren_um_spm_mon_allow:1;
/** coren_um_cache_allow : R/W; bitpos: [11]; default: 1; /** coren_um_cache_allow : R/W; bitpos: [11]; default: 1;
* Configures whether HP CPUn in user mode has permission to access cache. * Configures whether HP CPUn in user mode has permission to access cache.
* 0: Not allowed * 0: Not allowed
@ -667,12 +661,7 @@ typedef union {
* 1: Allowed * 1: Allowed
*/ */
uint32_t coren_um_hp_gdma_allow:1; uint32_t coren_um_hp_gdma_allow:1;
/** coren_um_hp_regdma_allow : R/W; bitpos: [4]; default: 1; uint32_t reserved_4:1;
* Configures whether HP CPUn in user mode has permission to access HP regdma.
* 0: Not allowed
* 1: Allow
*/
uint32_t coren_um_hp_regdma_allow:1;
/** coren_um_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1; /** coren_um_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPUn in user mode has permission to access HP SDMMC. * Configures whether HP CPUn in user mode has permission to access HP SDMMC.
* 0: Not allowed * 0: Not allowed
@ -1063,25 +1052,6 @@ typedef union {
} pms_coren_um_hp_peri_pms_reg3_reg_t; } pms_coren_um_hp_peri_pms_reg3_reg_t;
/** Group: TEE Peripheral Permission Control Registers */
/** Type of regdma_peri_pms register
* Permission register for REGDMA
*/
typedef union {
struct {
/** regdma_peri_allow : R/W; bitpos: [0]; default: 1;
* Configures whether REGDMA has permission to access all HP peripheral (including CPU
* peripherals).
* 0: Not allowed
* 1: Allow
*/
uint32_t regdma_peri_allow:1;
uint32_t reserved_1:31;
};
uint32_t val;
} pms_regdma_peri_pms_reg_t;
typedef struct { typedef struct {
volatile pms_hp_peri_pms_date_reg_t hp_peri_pms_date; volatile pms_hp_peri_pms_date_reg_t hp_peri_pms_date;
volatile pms_hp_peri_pms_clk_en_reg_t hp_peri_pms_clk_en; volatile pms_hp_peri_pms_clk_en_reg_t hp_peri_pms_clk_en;
@ -1101,13 +1071,12 @@ typedef struct {
volatile pms_coren_um_hp_peri_pms_reg1_reg_t core1_um_hp_peri_pms_reg1; volatile pms_coren_um_hp_peri_pms_reg1_reg_t core1_um_hp_peri_pms_reg1;
volatile pms_coren_um_hp_peri_pms_reg2_reg_t core1_um_hp_peri_pms_reg2; volatile pms_coren_um_hp_peri_pms_reg2_reg_t core1_um_hp_peri_pms_reg2;
volatile pms_coren_um_hp_peri_pms_reg3_reg_t core1_um_hp_peri_pms_reg3; volatile pms_coren_um_hp_peri_pms_reg3_reg_t core1_um_hp_peri_pms_reg3;
volatile pms_regdma_peri_pms_reg_t regdma_peri_pms;
} hp_peri_pms_dev_t; } hp_peri_pms_dev_t;
extern hp_peri_pms_dev_t HP_PERI_PMS; extern hp_peri_pms_dev_t HP_PERI_PMS;
#ifndef __cplusplus #ifndef __cplusplus
_Static_assert(sizeof(hp_peri_pms_dev_t) == 0x4c, "Invalid size of hp_peri_pms_dev_t structure"); _Static_assert(sizeof(hp_peri_pms_dev_t) == 0x48, "Invalid size of hp_peri_pms_dev_t structure");
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus

24
components/soc/esp32p4/register/soc/lp2hp_peri_pms_reg.h
View File

@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -119,15 +119,15 @@ extern "C" {
#define PMS_LP_MM_L2MEM_MON_ALLOW_M (PMS_LP_MM_L2MEM_MON_ALLOW_V << PMS_LP_MM_L2MEM_MON_ALLOW_S) #define PMS_LP_MM_L2MEM_MON_ALLOW_M (PMS_LP_MM_L2MEM_MON_ALLOW_V << PMS_LP_MM_L2MEM_MON_ALLOW_S)
#define PMS_LP_MM_L2MEM_MON_ALLOW_V 0x00000001U #define PMS_LP_MM_L2MEM_MON_ALLOW_V 0x00000001U
#define PMS_LP_MM_L2MEM_MON_ALLOW_S 9 #define PMS_LP_MM_L2MEM_MON_ALLOW_S 9
/** PMS_LP_MM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1; /** PMS_LP_MM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access TCM monitor. * Configures whether the LP CPU in machine mode has permission to access SPM monitor.
* 0: Not allowed * 0: Not allowed
* 1: Allowed * 1: Allowed
*/ */
#define PMS_LP_MM_TCM_MON_ALLOW (BIT(10)) #define PMS_LP_MM_SPM_MON_ALLOW (BIT(10))
#define PMS_LP_MM_TCM_MON_ALLOW_M (PMS_LP_MM_TCM_MON_ALLOW_V << PMS_LP_MM_TCM_MON_ALLOW_S) #define PMS_LP_MM_SPM_MON_ALLOW_M (PMS_LP_MM_SPM_MON_ALLOW_V << PMS_LP_MM_SPM_MON_ALLOW_S)
#define PMS_LP_MM_TCM_MON_ALLOW_V 0x00000001U #define PMS_LP_MM_SPM_MON_ALLOW_V 0x00000001U
#define PMS_LP_MM_TCM_MON_ALLOW_S 10 #define PMS_LP_MM_SPM_MON_ALLOW_S 10
/** PMS_LP_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1; /** PMS_LP_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access cache. * Configures whether the LP CPU in machine mode has permission to access cache.
* 0: Not allowed * 0: Not allowed
@ -181,16 +181,6 @@ extern "C" {
#define PMS_LP_MM_HP_GDMA_ALLOW_M (PMS_LP_MM_HP_GDMA_ALLOW_V << PMS_LP_MM_HP_GDMA_ALLOW_S) #define PMS_LP_MM_HP_GDMA_ALLOW_M (PMS_LP_MM_HP_GDMA_ALLOW_V << PMS_LP_MM_HP_GDMA_ALLOW_S)
#define PMS_LP_MM_HP_GDMA_ALLOW_V 0x00000001U #define PMS_LP_MM_HP_GDMA_ALLOW_V 0x00000001U
#define PMS_LP_MM_HP_GDMA_ALLOW_S 3 #define PMS_LP_MM_HP_GDMA_ALLOW_S 3
/** PMS_LP_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP GDMA (DW
* GDMA).
* 0: Not allowed
* 1: Allow
*/
#define PMS_LP_MM_HP_REGDMA_ALLOW (BIT(4))
#define PMS_LP_MM_HP_REGDMA_ALLOW_M (PMS_LP_MM_HP_REGDMA_ALLOW_V << PMS_LP_MM_HP_REGDMA_ALLOW_S)
#define PMS_LP_MM_HP_REGDMA_ALLOW_V 0x00000001U
#define PMS_LP_MM_HP_REGDMA_ALLOW_S 4
/** PMS_LP_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; /** PMS_LP_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP SDMMC. * Configures whether the LP CPU in machine mode has permission to access HP SDMMC.
* 0: Not allowed * 0: Not allowed

16
components/soc/esp32p4/register/soc/lp2hp_peri_pms_struct.h
View File

@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -104,12 +104,12 @@ typedef union {
* 1: Allowed * 1: Allowed
*/ */
uint32_t lp_mm_l2mem_mon_allow:1; uint32_t lp_mm_l2mem_mon_allow:1;
/** lp_mm_tcm_mon_allow : R/W; bitpos: [10]; default: 1; /** lp_mm_spm_mon_allow : R/W; bitpos: [10]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access TCM monitor. * Configures whether the LP CPU in machine mode has permission to access SPM monitor.
* 0: Not allowed * 0: Not allowed
* 1: Allowed * 1: Allowed
*/ */
uint32_t lp_mm_tcm_mon_allow:1; uint32_t lp_mm_spm_mon_allow:1;
/** lp_mm_cache_allow : R/W; bitpos: [11]; default: 1; /** lp_mm_cache_allow : R/W; bitpos: [11]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access cache. * Configures whether the LP CPU in machine mode has permission to access cache.
* 0: Not allowed * 0: Not allowed
@ -153,13 +153,7 @@ typedef union {
* 1: Allowed * 1: Allowed
*/ */
uint32_t lp_mm_hp_gdma_allow:1; uint32_t lp_mm_hp_gdma_allow:1;
/** lp_mm_hp_regdma_allow : R/W; bitpos: [4]; default: 1; uint32_t reserved_4:1;
* Configures whether the LP CPU in machine mode has permission to access HP GDMA (DW
* GDMA).
* 0: Not allowed
* 1: Allow
*/
uint32_t lp_mm_hp_regdma_allow:1;
/** lp_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1; /** lp_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP SDMMC. * Configures whether the LP CPU in machine mode has permission to access HP SDMMC.
* 0: Not allowed * 0: Not allowed